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From: Bart V. A. <bva...@ac...> - 2015-04-22 10:20:10
|
On 04/21/15 23:02, Philippe Waroquiers wrote: > On Mon, 2015-04-20 at 23:46 +0200, Florian Krohm wrote: >> On 20.04.2015 23:28, Philippe Waroquiers wrote: >>> Nice cleanup. >>> One small comment: wouldn't the description of VG_(sr_as_string)() >>> better be put in the .h rather than in the .c file ? >>> The fact that the memory is static (or must be freed by the caller) >>> is better described there ? >> >> I tend to favour small comments in header files and put noteworthy >> details next to the implementation. But I have no strong feelings and we >> don't have a policy for this either. So if you want to change it please >> feel free. > Done as revision 15127. > > At work, we have a convention/guideline that to know how to use a > module, it is/should be sufficient to read the 'spec' (i.e. the .h) > of the module. > This allows to limit the reading to what is needed. > E.g. allows to skip internal functions/comments/internal data structures > and so on. > > So, information for the caller such as > 'you must free the returned pointer' > or > 'returns a static buffer, overwritten on next invocation' > is better placed in the .h, following this convention. > > I think many modules of Valgrind already follows > this approach. > > Maybe we could be more systematic in that approach ? There might be good reasons to add documentation for Valgrind functions in Valgrind header files. But I think it's worth mentioning here that there is a strict policy in the Linux kernel is to add such documentation in the .c files only. The rationale behind this policy is that it is easy to forget to update a header file when modifying the implementation. That's why in the Linux kernel the documentation is kept close to the implementation. Bart. |
|
From: <sv...@va...> - 2015-04-22 09:43:00
|
Author: bart
Date: Wed Apr 22 09:07:35 2015
New Revision: 15130
Log:
NEWS: Add entry for bug #346416 / trunk r15123
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Apr 22 09:07:35 2015
@@ -161,6 +161,7 @@
entries on ppc.
346267 Fix compiler warning about casting arguments, ppc64.
346324 Add support for the ppc instructions lbarx, lharx, stbcs, sthcs
+346416 Add support for LL_IOC_PATH2FID and LL_IOC_GETPARENT Lustre ioctls
Release 3.10.1 (25 November 2014)
|
|
From: <sv...@va...> - 2015-04-21 22:05:02
|
Author: philippe
Date: Tue Apr 21 23:04:55 2015
New Revision: 15129
Log:
Announce in NEWS the optimisation done for helgrind big applications
full history level
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Apr 21 23:04:55 2015
@@ -16,6 +16,8 @@
taken so far.
* Helgrind:
+ Memory and speed improvement for --history-level=full for big applications
+ accessing a lot of memory with many different stacktraces.
* Callgrind:
|
|
From: <sv...@va...> - 2015-04-21 21:58:22
|
Author: philippe
Date: Tue Apr 21 22:58:14 2015
New Revision: 15128
Log:
Add some stats to helgrind stats:
* nr of client malloc-ed blocks
* how many OldRef helgrind has, and the distribution
of these OldRef according to the nr of accs they have
Modified:
trunk/helgrind/hg_main.c
trunk/helgrind/libhb_core.c
Modified: trunk/helgrind/hg_main.c
==============================================================================
--- trunk/helgrind/hg_main.c (original)
+++ trunk/helgrind/hg_main.c Tue Apr 21 22:58:14 2015
@@ -5359,6 +5359,9 @@
HG_(stats__LockN_to_P_queries),
HG_(stats__LockN_to_P_get_map_size)() );
+ VG_(printf)("client malloc-ed blocks: %'8d\n",
+ VG_(HT_count_nodes)(hg_mallocmeta_table));
+
VG_(printf)("string table map: %'8llu queries (%llu map size)\n",
HG_(stats__string_table_queries),
HG_(stats__string_table_get_map_size)() );
Modified: trunk/helgrind/libhb_core.c
==============================================================================
--- trunk/helgrind/libhb_core.c (original)
+++ trunk/helgrind/libhb_core.c Tue Apr 21 22:58:14 2015
@@ -6120,6 +6120,33 @@
}
VG_(printf)("%s","\n");
+ {
+ UWord OldRef_accs_n[N_OLDREF_ACCS+1];
+ UInt accs_n;
+ UWord OldRef_n;
+ UInt i;
+
+ OldRef_n = 0;
+ for (i = 0; i <= N_OLDREF_ACCS; i++)
+ OldRef_accs_n[i] = 0;
+
+ for (OldRef* o = mru.prev; o != &lru; o = o->prev) {
+ OldRef_n++;
+ accs_n = 0;
+ for (i = 0; i < N_OLDREF_ACCS; i++) {
+ if (o->accs[i].thrid != 0)
+ accs_n++;
+ }
+ OldRef_accs_n[accs_n]++;
+ }
+
+ tl_assert(OldRef_n == oldrefTreeN);
+ VG_(printf)( " libhb: oldrefTreeN %lu ", oldrefTreeN);
+ VG_(printf)( "( ");
+ for (i = 0; i <= N_OLDREF_ACCS; i++)
+ VG_(printf)( "accs[%d]=%lu ", i, OldRef_accs_n[i]);
+ VG_(printf)( ")\n");
+ }
VG_(printf)( " libhb: ctxt__rcdec: 1=%lu(%lu eq), 2=%lu, 3=%lu\n",
stats__ctxt_rcdec1, stats__ctxt_rcdec1_eq,
stats__ctxt_rcdec2,
|
|
From: Philippe W. <phi...@sk...> - 2015-04-21 21:01:51
|
On Mon, 2015-04-20 at 23:46 +0200, Florian Krohm wrote: > On 20.04.2015 23:28, Philippe Waroquiers wrote: > > Nice cleanup. > > One small comment: wouldn't the description of VG_(sr_as_string)() > > better be put in the .h rather than in the .c file ? > > The fact that the memory is static (or must be freed by the caller) > > is better described there ? > > I tend to favour small comments in header files and put noteworthy > details next to the implementation. But I have no strong feelings and we > don't have a policy for this either. So if you want to change it please > feel free. Done as revision 15127. At work, we have a convention/guideline that to know how to use a module, it is/should be sufficient to read the 'spec' (i.e. the .h) of the module. This allows to limit the reading to what is needed. E.g. allows to skip internal functions/comments/internal data structures and so on. So, information for the caller such as 'you must free the returned pointer' or 'returns a static buffer, overwritten on next invocation' is better placed in the .h, following this convention. I think many modules of Valgrind already follows this approach. Maybe we could be more systematic in that approach ? Philippe |
|
From: <sv...@va...> - 2015-04-21 20:56:55
|
Author: philippe
Date: Tue Apr 21 21:56:49 2015
New Revision: 15127
Log:
Move a comment useful to the caller to the .h, rather than keeping it
in the .c
Modified:
trunk/coregrind/m_libcprint.c
trunk/include/pub_tool_libcprint.h
Modified: trunk/coregrind/m_libcprint.c
==============================================================================
--- trunk/coregrind/m_libcprint.c (original)
+++ trunk/coregrind/m_libcprint.c Tue Apr 21 21:56:49 2015
@@ -647,9 +647,6 @@
VG_(sr_as_string)()
------------------------------------------------------------------ */
-/* Return a textual representation of a SysRes value in a statically
- allocated buffer. The buffer will be overwritten with the next
- invocation. */
#if defined(VGO_linux)
// FIXME: Does this function need to be adjusted for MIPS's _valEx ?
const HChar *VG_(sr_as_string) ( SysRes sr )
Modified: trunk/include/pub_tool_libcprint.h
==============================================================================
--- trunk/include/pub_tool_libcprint.h (original)
+++ trunk/include/pub_tool_libcprint.h Tue Apr 21 21:56:49 2015
@@ -154,7 +154,9 @@
/* Flush any output cached by previous calls to VG_(message) et al. */
extern void VG_(message_flush) ( void );
-/* Return a SysRes value as a character string. */
+/* Return a textual representation of a SysRes value in a statically
+ allocated buffer. The buffer will be overwritten with the next
+ invocation. */
extern const HChar *VG_(sr_as_string) ( SysRes sr );
#endif // __PUB_TOOL_LIBCPRINT_H
|
|
From: <sv...@va...> - 2015-04-21 20:55:47
|
Author: philippe
Date: Tue Apr 21 21:55:40 2015
New Revision: 15126
Log:
Do RCEC_GC when approaching the max nr of RCEC, not when reaching it.
Otherwise, long running applications still see the max nr of RCEC
slowly growing, which increases the memory usage and
makes the (fixed) contextTab hash table slower to search.
Without this margin, the max could increase as the GC code
is not called at exactly the moment we reach the previous max,
but rather when a thread has run a bunch of basic blocks.
Modified:
trunk/helgrind/libhb_core.c
Modified: trunk/helgrind/libhb_core.c
==============================================================================
--- trunk/helgrind/libhb_core.c (original)
+++ trunk/helgrind/libhb_core.c Tue Apr 21 21:55:40 2015
@@ -6416,13 +6416,19 @@
void libhb_maybe_GC ( void )
{
/* GC the unreferenced (zero rc) RCECs when
- (1) reaching a significant nr of RCECs (to avoid scanning a contextTab
- with mostly NULL ptr)
- and (2) reaching at least the max nr of RCEC (as we have in any case
- at least that amount of RCEC in the pool allocator)
- and (3) the nr of referenced RCECs is less than 75% than total nr RCECs. */
+ (1) reaching a significant nr of RCECs (to avoid scanning a contextTab
+ with mostly NULL ptr)
+ and (2) approaching the max nr of RCEC (as we have in any case
+ at least that amount of RCEC in the pool allocator)
+ Note: the margin allows to avoid a small but constant increase
+ of the max nr of RCEC due to the fact that libhb_maybe_GC is
+ not called when the current nr of RCEC exactly reaches the max.
+ and (3) the nr of referenced RCECs is less than 75% than total nr RCECs.
+ Avoid growing too much the nr of RCEC keeps the memory use low,
+ and avoids to have too many elements in the (fixed) contextTab hashtable.
+ */
if (UNLIKELY(stats__ctxt_tab_curr > N_RCEC_TAB/2
- && stats__ctxt_tab_curr >= stats__ctxt_tab_max
+ && stats__ctxt_tab_curr + 1000 >= stats__ctxt_tab_max
&& stats__ctxt_tab_curr * 0.75 > RCEC_referenced))
do_RCEC_GC();
|
|
From: <sv...@va...> - 2015-04-21 20:13:34
|
Author: carll
Date: Tue Apr 21 21:13:27 2015
New Revision: 15125
Log:
Update the NEWS file with the fixes for bugzillas 345695, 346267, and 346324.
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Apr 21 21:13:27 2015
@@ -155,6 +155,10 @@
n-i-bz Old STABS code is still being compiled, but never used. Remove it.
n-i-bz Fix compilation on distros with glibc < 2.5
n-i-bz (vex 3098) Avoid generation of Neon insns on non-Neon hosts
+345695 Add support for the auxvex entries AT_DCHCEBSIZE and AT_HWCAP2
+ entries on ppc.
+346267 Fix compiler warning about casting arguments, ppc64.
+346324 Add support for the ppc instructions lbarx, lharx, stbcs, sthcs
Release 3.10.1 (25 November 2014)
|
|
From: <sv...@va...> - 2015-04-21 20:06:20
|
Author: carll
Date: Tue Apr 21 21:06:13 2015
New Revision: 15124
Log:
Update the expected output file none/tests/ppc64/jm_int_isa_2_07.stdout.exp
for PPC64 big endian.
Modified:
trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
Modified: trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp Tue Apr 21 21:06:13 2015
@@ -1 +1,17 @@
-NO ISA 2.07 SUPPORT
+stq abcdef0123456789,1133557722446688, 0 => abcdef0123456789,1133557722446688)
+
+lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+
+lbarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x00000000000000aa, 0x0000000000000000)
+
+lharx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x000000000000aacc, 0x0000000000000000)
+
+lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+
+stbcx. abefcd0145236789,1155337744226688 => 8900000000000000,0000000000000001; CR=20000000
+
+sthcx. abefcd0145236789,1155337744226688 => 6789000000000000,0000000000000001; CR=20000000
+
+stqcx. abefcd0145236789,1155337744226688 => abefcd0145236789,1155337744226688; CR=20000000
+
+All done. Tested 8 different instructions
|
|
From: Julian S. <js...@ac...> - 2015-04-21 18:56:00
|
Hi Carl, On 21/04/15 20:29, Carl E. Love wrote: > instructions. I found that I need to increase the #define value of > MAX_REG_WRITE_SIZE from 1696 to 1712. The value must be as large as the > the biggest guest state. The value 1712 is the minimum value that is > required with the new PPC64 TEXASRU register to meet the requirement. Yes, that's fine. No problem. J |
|
From: Carl E. L. <ce...@us...> - 2015-04-21 18:29:10
|
Julian: I received a request to add support for the PPC64 TEXASRU register, (https://bugzilla.linux.ibm.com/show_bug.cgi?id=124179). It is one of the registers used to hold information on the transactional memory instructions. I found that I need to increase the #define value of MAX_REG_WRITE_SIZE from 1696 to 1712. The value must be as large as the the biggest guest state. The value 1712 is the minimum value that is required with the new PPC64 TEXASRU register to meet the requirement. Since I am outside of the PPC code space, I am asking for permission to make this change. The full patch is given below for your review. Carl Love ----------------------------------------------------------------------- PPC64, add support for the TEXASRU register. The TEXASRU register is a 32-bit register that holds the upper 32 bits of the Transaction EXception And Summary Register (TEXASR). --- VEX/priv/guest_ppc_toIR.c | 22 +++++++++++++++++++--- VEX/pub/libvex_guest_ppc32.h | 3 ++- VEX/pub/libvex_guest_ppc64.h | 6 ++++++ memcheck/mc_main.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 6a29c47..b1326da 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -286,6 +286,7 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f ) #define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2) #define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR) #define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR) +#define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU) #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) @@ -436,6 +437,7 @@ typedef enum { PPC_GST_TFHAR, // Transactional Failure Handler Address Register PPC_GST_TFIAR, // Transactional Failure Instruction Address Register PPC_GST_TEXASR, // Transactional EXception And Summary Register + PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper PPC_GST_MAX } PPC_GST; @@ -2739,6 +2741,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) case PPC_GST_TEXASR: return IRExpr_Get( OFFB_TEXASR, ty ); + case PPC_GST_TEXASRU: + return IRExpr_Get( OFFB_TEXASRU, ty ); + case PPC_GST_TFIAR: return IRExpr_Get( OFFB_TFIAR, ty ); @@ -2907,6 +2912,12 @@ static void putGST ( PPC_GST reg, IRExpr* src ) vassert( ty_src == Ity_I64 ); stmt( IRStmt_Put( OFFB_TEXASR, src ) ); break; + + case PPC_GST_TEXASRU: + vassert( ty_src == Ity_I32 ); + stmt( IRStmt_Put( OFFB_TEXASRU, src ) ); + break; + case PPC_GST_TFIAR: vassert( ty_src == Ity_I64 ); stmt( IRStmt_Put( OFFB_TFIAR, src ) ); @@ -3337,9 +3348,10 @@ static ULong generate_TMreason( UInt failure_code, static void storeTMfailure( Addr64 err_address, ULong tm_reason, Addr64 handler_address ) { - putGST( PPC_GST_TFIAR, mkU64( err_address ) ); - putGST( PPC_GST_TEXASR, mkU64( tm_reason ) ); - putGST( PPC_GST_TFHAR, mkU64( handler_address ) ); + putGST( PPC_GST_TFIAR, mkU64( err_address ) ); + putGST( PPC_GST_TEXASR, mkU64( tm_reason ) ); + putGST( PPC_GST_TEXASRU, mkU32( 0 ) ); + putGST( PPC_GST_TFHAR, mkU64( handler_address ) ); } /*------------------------------------------------------------*/ @@ -7115,6 +7127,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) DIP("mfspr r%u (TEXASR)\n", rD_addr); putIReg( rD_addr, getGST( PPC_GST_TEXASR) ); break; + case 0x83: // 131 + DIP("mfspr r%u (TEXASRU)\n", rD_addr); + putIReg( rD_addr, getGST( PPC_GST_TEXASRU) ); + break; case 0x100: DIP("mfvrsave r%u\n", rD_addr); putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ), diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h index 35dd318..3c2fd9e 100644 --- a/VEX/pub/libvex_guest_ppc32.h +++ b/VEX/pub/libvex_guest_ppc32.h @@ -241,9 +241,10 @@ typedef /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register + /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper /* Padding to make it have an 16-aligned size */ - /* 1384 */ UInt padding2; + /* 1388 */ UInt padding2; } VexGuestPPC32State; diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h index 9a4caed..13a3540 100644 --- a/VEX/pub/libvex_guest_ppc64.h +++ b/VEX/pub/libvex_guest_ppc64.h @@ -282,6 +282,12 @@ typedef /* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register /* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register /* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register + /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + + /* Padding to make it have an 16-aligned size */ + /* 1684 */ UInt padding1; + /* 1688 */ UInt padding2; + /* 1692 */ UInt padding3; } VexGuestPPC64State; diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 5cd2414..1fc1561 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -4142,7 +4142,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid, static void mc_post_reg_write ( CorePart part, ThreadId tid, PtrdiffT offset, SizeT size) { -# define MAX_REG_WRITE_SIZE 1696 +# define MAX_REG_WRITE_SIZE 1712 UChar area[MAX_REG_WRITE_SIZE]; tl_assert(size <= MAX_REG_WRITE_SIZE); VG_(memset)(area, V_BITS8_DEFINED, size); -- 1.8.3.1 |
|
From: <sv...@va...> - 2015-04-21 17:46:59
|
Author: bart
Date: Tue Apr 21 18:46:52 2015
New Revision: 15123
Log:
Add support for LL_IOC_PATH2FID and LL_IOC_GETPARENT Lustre ioctls
From: Frank Zago <fz...@cr...>
Modified:
trunk/coregrind/m_syswrap/syswrap-linux.c
trunk/include/vki/vki-linux.h
Modified: trunk/coregrind/m_syswrap/syswrap-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-linux.c Tue Apr 21 18:46:52 2015
@@ -7321,11 +7321,28 @@
break;
#endif
- /* To do: figure out which software layer extends the sign of 'request' */
- case VKI_OBD_IOC_FID2PATH:
- PRE_MEM_READ("VKI_OBD_IOC_FID2PATH(args)", ARG3,
- sizeof(struct vki_getinfo_fid2path));
+ /* Lustre */
+ case VKI_OBD_IOC_FID2PATH: {
+ struct vki_getinfo_fid2path *gf = (struct vki_getinfo_fid2path *)ARG3;
+ PRE_MEM_READ("VKI_OBD_IOC_FID2PATH(args)", ARG3, sizeof(struct vki_getinfo_fid2path));
+ PRE_FIELD_WRITE("VKI_OBD_IOC_FID2PATH(args).gf_recno", gf->gf_recno);
+ PRE_FIELD_WRITE("VKI_OBD_IOC_FID2PATH(args).gf_linkno", gf->gf_linkno);
+ PRE_MEM_WRITE("VKI_OBD_IOC_FID2PATH(args)", (Addr)gf->gf_path, gf->gf_pathlen);
+ break;
+ }
+
+ case VKI_LL_IOC_PATH2FID:
+ PRE_MEM_WRITE("ioctl(VKI_LL_IOC_PATH2FID)", ARG3, sizeof(struct vki_lu_fid));
+ break;
+
+ case VKI_LL_IOC_GETPARENT: {
+ struct vki_getparent *gp = (struct vki_getparent *)ARG3;
+ PRE_FIELD_READ("ioctl(VKI_LL_IOC_GETPARENT).gp_linkno", gp->gp_linkno);
+ PRE_FIELD_READ("ioctl(VKI_LL_IOC_GETPARENT).gp_name_size", gp->gp_name_size);
+ PRE_FIELD_WRITE("ioctl(VKI_LL_IOC_GETPARENT).gp_fid", gp->gp_fid);
+ PRE_MEM_WRITE("ioctl(VKI_LL_IOC_GETPARENT).gp_name", (Addr)gp->gp_name, gp->gp_name_size);
break;
+ }
/* V4L2 */
case VKI_V4L2_QUERYCAP: {
@@ -9636,13 +9653,26 @@
break;
#endif
- /* To do: figure out which software layer extends the sign of 'request' */
+ /* Lustre */
case VKI_OBD_IOC_FID2PATH: {
struct vki_getinfo_fid2path *args = (void *)(ARG3);
- POST_MEM_WRITE((Addr)args->gf_path, args->gf_pathlen);
+ POST_FIELD_WRITE(args->gf_recno);
+ POST_FIELD_WRITE(args->gf_linkno);
+ POST_MEM_WRITE((Addr)args->gf_path, VG_(strlen)(args->gf_path)+1);
+ break;
}
+
+ case VKI_LL_IOC_PATH2FID:
+ POST_MEM_WRITE(ARG3, sizeof(struct vki_lu_fid));
break;
+ case VKI_LL_IOC_GETPARENT: {
+ struct vki_getparent *gp = (struct vki_getparent *)ARG3;
+ POST_FIELD_WRITE(gp->gp_fid);
+ POST_MEM_WRITE((Addr)gp->gp_name, VG_(strlen)(gp->gp_name)+1);
+ break;
+ }
+
/* V4L2 */
case VKI_V4L2_S_FMT:
case VKI_V4L2_TRY_FMT:
Modified: trunk/include/vki/vki-linux.h
==============================================================================
--- trunk/include/vki/vki-linux.h (original)
+++ trunk/include/vki/vki-linux.h Tue Apr 21 18:46:52 2015
@@ -3658,6 +3658,26 @@
#define VKI_OBD_IOC_FID2PATH \
_VKI_IOWR ('f', 150, VKI_OBD_IOC_DATA_TYPE)
+#define VKI_LL_IOC_PATH2FID \
+ _VKI_IOR ('f', 173, long)
+
+//----------------------------------------------------------------------
+// From lustre/include/lustre/lustre_idl.h
+//----------------------------------------------------------------------
+
+struct vki_getparent {
+ struct vki_lu_fid gp_fid;
+ __vki_u32 gp_linkno;
+ __vki_u32 gp_name_size;
+ char gp_name[0];
+} __attribute__((packed));
+
+//----------------------------------------------------------------------
+// From Lustre's lustre/include/lustre/lustre_user.h
+//----------------------------------------------------------------------
+#define VKI_LL_IOC_GETPARENT \
+ _VKI_IOWR('f', 249, struct vki_getparent)
+
struct vki_v4l2_rect {
__vki_s32 left;
|
|
From: Carl E. L. <ce...@us...> - 2015-04-21 15:45:54
|
On Sun, 2015-04-19 at 07:57 -0700, Patrick J. LoPresti wrote: > On Sat, Apr 18, 2015 at 3:47 AM, Florian Krohm <fl...@ei...> wrote: > > > > What you describe would work but require additional configury. And that > > is something I would like to avoid. We already have 3000 lines of it. > > If will be less work to simply modify the test to not pass these values > > as function arguments. > > Assuming that is possible, I agree. Although even that demands > cluttering the source with a long comment if the needed approach is > unnatural. > > When it is impossible or inconvenient to modify the source, the > approach I have seen is to place all such warning suppressions in one > header file. And then dispatch on the compiler version in that header > (not in the configure script). Something like > <http://stackoverflow.com/a/18463996/768469>. > > This approach keeps the source uncluttered, and it adds little to the > testing burden since (a) it is simple enough to get right every time > and (b) these are just warning suppressions. > > This is part of the cost of keeping everything "-Wall clean" across > multiple platforms. But it is not a large cost compared to the > benefits. > > - Pat > The test code follows a basic structure which is used across a wide range of tests. I will take a look at the code and see if I can put the arguments into a struct and pass the struct without adding too much confusion to the code. I think that would be preferable to messing around with the configuration file for the compile. Carl Love |
|
From: Carl E. L. <ce...@us...> - 2015-04-21 15:32:01
|
On Tue, 2015-04-21 at 12:20 +0000,
val...@li... wrote:
> Message: 4
> Date: Tue, 21 Apr 2015 10:58:00 +0200
> From: Thomas Huth <th...@re...>
> Subject: [Valgrind-developers] unhandled ppc64be-linux syscall: 175
> To: val...@li...
> Message-ID: <20150421105800.7ef1bb82@thh440s>
> Content-Type: text/plain; charset=US-ASCII
>
>
> Hi all!
>
> While trying to run qemu with valgrind on a ppc64 host, I've
> encountered the following warning message from valgrind:
>
> --11641-- WARNING: unhandled ppc64be-linux syscall: 175
>
> valgrind then stops execution, so this was rather an error message
> than
> a warning message, I guess ;-)
>
> The following patch seems to fix this issue for me, however since I am
> not very experienced with valgrind yet, could somebody please have a
> closer look whether this is the right way to deal with this missing
> syscall?
>
> Thanks,
> Thomas
> diff -u a/coregrind/m_syswrap/syswrap-ppc64-linux.c
> b/coregrind/m_syswrap/syswrap-ppc64-linux.c
> --- a/coregrind/m_syswrap/syswrap-ppc64-linux.c 2015-04-21
> 10:51:45.450216797 +0200
> +++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c 2015-04-21
> 10:27:34.916665631 +0200
> @@ -988,7 +988,7 @@
> LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 173
> LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 174
>
> -// _____(__NR_rt_sigpending, sys_rt_sigpending), // 175
> + LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 175
> LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 176
> LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 177
> LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 178
Thomas:
I will look into this with you. Can you send me directly
(ce...@us...) your test case. I will see about testing your patch
and getting a fix committed. Thanks.
Carl Love
|
|
From: <sv...@va...> - 2015-04-21 15:00:05
|
Author: sewardj
Date: Tue Apr 21 15:59:58 2015
New Revision: 3142
Log:
Whitespace only change (fix indentation)
Modified:
branches/NCODE/priv/host_generic_regs.c
branches/NCODE/priv/host_generic_regs.h
Modified: branches/NCODE/priv/host_generic_regs.c
==============================================================================
--- branches/NCODE/priv/host_generic_regs.c (original)
+++ branches/NCODE/priv/host_generic_regs.c Tue Apr 21 15:59:58 2015
@@ -772,9 +772,9 @@
This function is required to generate <= 1024 bytes of code.
Returns True if OK, False if not enough buffer space.
*/
-Bool HInstrNCode__emit ( /*MOD*/AssemblyBuffer* ab_hot,
- /*MOD*/AssemblyBuffer* ab_cold,
- /*MOD*/RelocationBuffer* rb,
+Bool HInstrNCode__emit ( /*MOD*/AssemblyBuffer* ab_hot,
+ /*MOD*/AssemblyBuffer* ab_cold,
+ /*MOD*/RelocationBuffer* rb,
const HInstrNCode* details,
Bool verbose,
void (*emit_OneNInstr) (
Modified: branches/NCODE/priv/host_generic_regs.h
==============================================================================
--- branches/NCODE/priv/host_generic_regs.h (original)
+++ branches/NCODE/priv/host_generic_regs.h Tue Apr 21 15:59:58 2015
@@ -821,9 +821,9 @@
Returns True if OK, False if not enough buffer space.
*/
extern
-Bool HInstrNCode__emit ( /*MOD*/AssemblyBuffer* ab_hot,
- /*MOD*/AssemblyBuffer* ab_cold,
- /*MOD*/RelocationBuffer* rb,
+Bool HInstrNCode__emit ( /*MOD*/AssemblyBuffer* ab_hot,
+ /*MOD*/AssemblyBuffer* ab_cold,
+ /*MOD*/RelocationBuffer* rb,
const HInstrNCode* details,
Bool verbose,
void (*emit_OneNInstr) (
|
|
From: <sv...@va...> - 2015-04-21 14:59:31
|
Author: sewardj
Date: Tue Apr 21 15:59:24 2015
New Revision: 3141
Log:
arm32 back end: add support for NCode artefacts created by valgrind r15122.
Modified:
branches/NCODE/priv/host_arm_defs.c
branches/NCODE/priv/ir_defs.c
branches/NCODE/pub/libvex_ir.h
Modified: branches/NCODE/priv/host_arm_defs.c
==============================================================================
--- branches/NCODE/priv/host_arm_defs.c (original)
+++ branches/NCODE/priv/host_arm_defs.c Tue Apr 21 15:59:24 2015
@@ -2962,6 +2962,14 @@
*p++ = imm32;
}
#else
+
+ if (imm32 == 0xFFFFFFFF) {
+ /* Generate mvn rD, #0 */
+ instr = XXXXXXXX(0xE, 0x3, 0xE, 0x0, rD, 0, 0, 0);
+ PUT(ab, instr);
+ return;
+ }
+
if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
/* Generate movw rD, #low16. Then, if the high 16 are
nonzero, generate movt rD, #high16. */
@@ -3299,6 +3307,15 @@
else vassert(0); // ill-constructed insn
} else {
// RR case
+ HReg rN = am->ARMam2.RR.base;
+ HReg rM = am->ARMam2.RR.index;
+ if (bL == 1 && bS == 0) {
+ // ldrh
+ UInt instr = XXXXXXXX(cc, X0001, X1001, iregEnc(rN),
+ iregEnc(rD), X0000, X1011, iregEnc(rM));
+ PUT(ab, instr);
+ goto done;
+ }
goto bad;
}
}
@@ -4889,7 +4906,7 @@
case Nin_Branch: {
/* We are going to generate an ARM branch insn, which naturally
- can be conditional if neeed. It will be of the form
+ can be conditional if necessary. It will be of the form
cond:4 1010 simm:24
We need to generate both the instruction and a relocation
record that describes how to fix up the offset (simm:24)
@@ -4912,12 +4929,12 @@
= mkRelocWhere(niLabel.zone, AssemblyBuffer__getNext(ab)+0);
RelocDst dst
= mkRelocDst_from_NLabel(ni->Nin.Branch.dst);
- /* Bias is 8 because we've set |where| to be the start of the
+ /* Bias is -8 because we've set |where| to be the start of the
branch insn. The processor however expects the offset to
be relative to the start of 8 bytes past the insn (ARM
ancient history) which means that a naive "dst - where"
value will give an offset that is 8 too large. Hence the
- bias of 8. */
+ bias of -8. */
Relocation reloc
= mkRelocation(where, 0, 23, dst, /*bias*/-8, /*rshift*/2);
vassert(RelocationBuffer__getRemainingSize(rb) > 0);
@@ -4974,29 +4991,64 @@
vassert(slotNo == n_to_preserve);
/* Marshall args for the call, do the call, marshal the result */
- /* Case: 1 arg reg, 1 result reg */
UInt nArgRegs = nregVecLen(ni->Nin.Call.argRegs);
+ HReg r0 = hregARM_R0();
+ HReg r1 = hregARM_R1();
+ HReg r12 = hregARM_R12();
if (nArgRegs == 1
&& isNRegINVALID(ni->Nin.Call.resHi)
&& !isNRegINVALID(ni->Nin.Call.resLo)) {
-
+ /* Case: 1 arg reg, 1 result reg */
HReg arg1 = mapNReg(nregMap, ni->Nin.Call.argRegs[0]);
HReg res1 = mapNReg(nregMap, ni->Nin.Call.resLo);
- HReg r0 = hregARM_R0();
if (!sameHReg(r0, arg1))
HI( mk_iMOVds_RR_ARM(r0, arg1) );
- HReg r12 = hregARM_R12();
HI( ARMInstr_Imm32(r12, (UInt)(HWord)ni->Nin.Call.entry) );
HI( ARMInstr_NC_CallR12() );
if (!sameHReg(res1, r0))
- HI( mk_iMOVds_RR_ARM(res1, r0) );
- } else {
- goto unhandled;
+ HI( mk_iMOVds_RR_ARM(res1, r0) );
}
+ else
+ if (nArgRegs == 1
+ && !isNRegINVALID(ni->Nin.Call.resHi)
+ && !isNRegINVALID(ni->Nin.Call.resLo)) {
+ /* Case: 1 arg reg, 2 result res */
+ HReg arg1 = mapNReg(nregMap, ni->Nin.Call.argRegs[0]);
+ HReg resLo = mapNReg(nregMap, ni->Nin.Call.resLo);
+ HReg resHi = mapNReg(nregMap, ni->Nin.Call.resHi);
+ if (!sameHReg(r0, arg1))
+ HI( mk_iMOVds_RR_ARM(r0, arg1) );
+
+ HI( ARMInstr_Imm32(r12, (UInt)(HWord)ni->Nin.Call.entry) );
+ HI( ARMInstr_NC_CallR12() );
+
+ /* Need to do "resHi:resLo = r1:r0". There's various fancy
+ ways to do this, but we'll keep it simple and do this:
+ if all 4 registers are disjoint:
+ resLo = r0
+ resHi = r1
+ else
+ r12 = r0
+ resHi = r1
+ resLo = r12
+ */
+ vassert(!sameHReg(resLo, resHi));
+ if (!sameHReg(resLo, r0) && !sameHReg(resLo, r1) &&
+ !sameHReg(resHi, r0) && !sameHReg(resHi, r1)) {
+ HI( mk_iMOVds_RR_ARM(resLo, r0) );
+ HI( mk_iMOVds_RR_ARM(resHi, r1) );
+ } else {
+ HI( mk_iMOVds_RR_ARM(r12, r0) );
+ HI( mk_iMOVds_RR_ARM(resHi, r1) );
+ HI( mk_iMOVds_RR_ARM(resLo, r12) );
+ }
+ }
+ else
+ goto unhandled;
/* Restore live regs */
RRegSetIterator__init(iter, &to_preserve);
@@ -5074,8 +5126,14 @@
HI( ARMInstr_CmpOrTst(False/*!isCmp*/, reg, ARMRI84_I84(imm,0)) );
break;
}
- if (ni->Nin.SetFlagsWri.how == Nsf_CMP && imm <= 0xFF) {
- HI( ARMInstr_CmpOrTst(True/*isCmp*/, reg, ARMRI84_I84(imm,0)) );
+ if (ni->Nin.SetFlagsWri.how == Nsf_CMP) {
+ if (imm <= 0xFF) {
+ HI( ARMInstr_CmpOrTst(True/*isCmp*/, reg, ARMRI84_I84(imm,0)) );
+ } else {
+ HReg r12 = hregARM_R12();
+ HI( ARMInstr_Imm32(r12, imm) );
+ HI( ARMInstr_CmpOrTst(True/*isCmp*/, reg, ARMRI84_R(r12)) );
+ }
break;
}
goto unhandled;
@@ -5092,9 +5150,9 @@
HReg dstR = mapNReg(nregMap, ni->Nin.LoadU.dst);
NEA* addr = ni->Nin.LoadU.addr;
UChar szB = ni->Nin.LoadU.szB;
- /* The Nea_IRS case is a kludge. It would be better to
- generate a single instruction, but that requires a new
- AMDAMode_IRS, which doesn't currently exist. */
+ /* The Nea_IRS case is a bit ugly, since we have to
+ synthesise a 32 bit immediate, but there's no way around
+ that. */
if (addr->tag == Nea_IRS && !fitsIn12bits((UInt)addr->Nea.IRS.base)) {
UInt imm = (UInt)addr->Nea.IRS.base;
HReg indexR = mapNReg(nregMap, addr->Nea.IRS.index);
@@ -5118,6 +5176,14 @@
ARMAMode1_RRS(baseR, indexR, shift)) );
break;
}
+ if (szB == 2 && shift > 0 && shift <= 3) {
+ HReg r12 = hregARM_R12();
+ HI( ARMInstr_Shift(ARMsh_SHL, r12, indexR, ARMRI5_I5(shift)) );
+ HI( ARMInstr_LdSt16(ARMcc_AL, True/*isLoad*/,
+ False/*!signedLoad*/, dstR,
+ ARMAMode2_RR(baseR, r12)) );
+ break;
+ }
}
goto unhandled;
}
Modified: branches/NCODE/priv/ir_defs.c
==============================================================================
--- branches/NCODE/priv/ir_defs.c (original)
+++ branches/NCODE/priv/ir_defs.c Tue Apr 21 15:59:24 2015
@@ -374,12 +374,20 @@
}
IRTemp* mkIRTempVec_1 ( IRTemp tmp1 ) {
- IRTemp* vec = LibVEX_Alloc(2 * sizeof(IRTemp*));
+ IRTemp* vec = LibVEX_Alloc_inline(2 * sizeof(IRTemp*));
vec[0] = tmp1;
vec[1] = IRTemp_INVALID;
return vec;
}
+IRTemp* mkIRTempVec_2 ( IRTemp tmp1, IRTemp tmp2 ) {
+ IRTemp* vec = LibVEX_Alloc_inline(3 * sizeof(IRTemp*));
+ vec[0] = tmp1;
+ vec[1] = tmp2;
+ vec[2] = IRTemp_INVALID;
+ return vec;
+}
+
void ppIROp ( IROp op )
{
const HChar* str = NULL;
Modified: branches/NCODE/pub/libvex_ir.h
==============================================================================
--- branches/NCODE/pub/libvex_ir.h (original)
+++ branches/NCODE/pub/libvex_ir.h Tue Apr 21 15:59:24 2015
@@ -401,6 +401,7 @@
/* IRTemp_INVALID-terminated IRTemp vector constructors. */
extern IRTemp* mkIRTempVec_1 ( IRTemp );
+extern IRTemp* mkIRTempVec_2 ( IRTemp, IRTemp );
/* --------------- Primops (arity 1,2,3 and 4) --------------- */
|
|
From: <sv...@va...> - 2015-04-21 14:57:08
|
Author: sewardj
Date: Tue Apr 21 15:57:01 2015
New Revision: 15122
Log:
Create a new NCode template, for 64 bit loads on 32 bit targets (LOADV64le_on_32).
Modified:
branches/NCODE/memcheck/mc_include.h
branches/NCODE/memcheck/mc_main.c
branches/NCODE/memcheck/mc_translate.c
Modified: branches/NCODE/memcheck/mc_include.h
==============================================================================
--- branches/NCODE/memcheck/mc_include.h (original)
+++ branches/NCODE/memcheck/mc_include.h Tue Apr 21 15:57:01 2015
@@ -605,6 +605,7 @@
extern NCodeTemplate* MC_(tmpl__LOADV16le_on_64);
extern NCodeTemplate* MC_(tmpl__LOADV8_on_64);
+extern NCodeTemplate* MC_(tmpl__LOADV64le_on_32);
extern NCodeTemplate* MC_(tmpl__LOADV32le_on_32);
Modified: branches/NCODE/memcheck/mc_main.c
==============================================================================
--- branches/NCODE/memcheck/mc_main.c (original)
+++ branches/NCODE/memcheck/mc_main.c Tue Apr 21 15:57:01 2015
@@ -4279,6 +4279,7 @@
VG_REGPARM(1) static ULong mc_LOADV16le_on_64_slow ( Addr a );
VG_REGPARM(1) static ULong mc_LOADV8_on_64_slow ( Addr a );
+VG_REGPARM(1) static ULong mc_LOADV64le_on_32_slow ( Addr a );
VG_REGPARM(1) static UInt mc_LOADV32le_on_32_slow ( Addr a );
static void* ncode_alloc ( UInt n ) {
@@ -4301,6 +4302,7 @@
NCodeTemplate* MC_(tmpl__LOADV16le_on_64) = NULL;
NCodeTemplate* MC_(tmpl__LOADV8_on_64) = NULL;
+NCodeTemplate* MC_(tmpl__LOADV64le_on_32) = NULL;
NCodeTemplate* MC_(tmpl__LOADV32le_on_32) = NULL;
static NCodeTemplate* mk_tmpl__LOADV64le_on_64 ( NAlloc na )
@@ -4613,6 +4615,71 @@
return tmpl;
}
+static NCodeTemplate* mk_tmpl__LOADV64le_on_32 ( NAlloc na )
+{
+ NInstr** hot = na((12+1) * sizeof(NInstr*));
+ NInstr** cold = na((7+1) * sizeof(NInstr*));
+
+ NReg rHi = mkNReg(Nrr_Result, 0);
+ NReg rLo = mkNReg(Nrr_Result, 1);
+ NReg a0 = mkNReg(Nrr_Argument, 0);
+ NReg s0 = mkNReg(Nrr_Scratch, 0);
+
+ /* NCode [rHi,rLo] = "LOADV64le_on_32" [a0] s0 {
+ hot:
+ 0 tst.w a0, #7 misaligned?
+ 1 bnz cold.5 yes, goto slow path
+ 2 shr.w s0, a0, #16 s0 = pri-map-ix
+ 3 ld.32 s0, [&pri_map[0] + s0 << #2] s0 = sec-map
+ 4 and.w rLo, a0, #0xFFFF rLo = sec-map-offB
+ 5 shr.w rLo, rLo, #3 rLo = sec-map-ix
+ 6 ld.16 rLo, [s0 + rLo << 1] rLo = sec-map-VABITS16
+ 7 cmp.w rLo, #0xAAAA rLo == VABITS16_DEFINED?
+ 8 bnz cold.0 no, goto cold.0
+ 9 imm.w rHi, #0x0 VBITS32_DEFINED
+ 10 imm.w rLo, #0x0 VBITS32_DEFINED
+ 11 nop continue
+ cold:
+ 0 mov.w s0, rLo s0 = sec-map-VABITS16
+ 1 imm.w rHi, #0xFFFFFFFF VBITS32_UNDEFINED
+ 2 imm.w rLo, #0xFFFFFFFF VBITS32_UNDEFINED
+ 3 cmp.w s0, #0x5555 s0 == VABITS16_UNDEFINED?
+ 4 bz hot.11 yes, continue
+ 5 call rHi,rLo = mc_LOADV64le_on_32_slow[..](a0) call helper
+ 6 b hot.11 continue
+ }
+ */
+ hot[0] = NInstr_SetFlagsWri (na, Nsf_TEST, a0, MASK(8));
+ hot[1] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 5));
+ hot[2] = NInstr_ShiftWri (na, Nsh_SHR, s0, a0, 16);
+ hot[3] = NInstr_LoadU (na, 4, s0, NEA_IRS(na, (HWord)&primary_map[0],
+ s0, 2));
+ hot[4] = NInstr_AluWri (na, Nalu_AND, rLo, a0, 0xFFFF);
+ hot[5] = NInstr_ShiftWri (na, Nsh_SHR, rLo, rLo, 3);
+ hot[6] = NInstr_LoadU (na, 2, rLo, NEA_RRS(na, s0, rLo, 1));
+ hot[7] = NInstr_SetFlagsWri (na, Nsf_CMP, rLo, VA_BITS16_DEFINED);
+ hot[8] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 0));
+ hot[9] = NInstr_ImmW (na, rHi, V_BITS32_DEFINED);
+ hot[10] = NInstr_ImmW (na, rLo, V_BITS32_DEFINED);
+ hot[11] = NInstr_Nop (na);
+
+ cold[0] = NInstr_MovW (na, s0, rLo);
+ cold[1] = NInstr_ImmW (na, rHi, V_BITS32_UNDEFINED);
+ cold[2] = NInstr_ImmW (na, rLo, V_BITS32_UNDEFINED);
+ cold[3] = NInstr_SetFlagsWri (na, Nsf_CMP, s0, VA_BITS16_UNDEFINED);
+ cold[4] = NInstr_Branch (na, Ncc_Z, mkNLabel(Nlz_Hot, 11));
+ cold[5] = NInstr_Call (na, rHi, rLo, mkNRegVec1(na, a0),
+ (void*)& mc_LOADV64le_on_32_slow,
+ "mc_LOADV64le_on_32_slow");
+ cold[6] = NInstr_Branch (na, Ncc_ALWAYS, mkNLabel(Nlz_Hot, 11));
+
+ hot[12] = cold[7] = NULL;
+ NCodeTemplate* tmpl
+ = mkNCodeTemplate(na,"LOADV64le_on_32",
+ /*res, parms, scratch*/2, 1, 1, hot, cold);
+ return tmpl;
+}
+
static NCodeTemplate* mk_tmpl__LOADV32le_on_32 ( NAlloc na )
{
NInstr** hot = na((11+1) * sizeof(NInstr*));
@@ -4626,7 +4693,7 @@
/* NCode [r0] = "LOADV32le_on_32" [a0] s0 {
hot:
- 0 tst.w a0, #3 high?
+ 0 tst.w a0, #3 misaligned?
1 bnz cold.4 yes, goto slow path
2 shr.w s0, a0, #16 s0 = pri-map-ix
3 ld.32 s0, [&pri_map[0] + s0 << #2] s0 = sec-map
@@ -4687,7 +4754,9 @@
MC_(tmpl__LOADV16le_on_64) = mk_tmpl__LOADV16le_on_64(ncode_alloc);
MC_(tmpl__LOADV8_on_64) = mk_tmpl__LOADV8_on_64(ncode_alloc);
+ tl_assert(MC_(tmpl__LOADV64le_on_32) == NULL);
tl_assert(MC_(tmpl__LOADV32le_on_32) == NULL);
+ MC_(tmpl__LOADV64le_on_32) = mk_tmpl__LOADV64le_on_32(ncode_alloc);
MC_(tmpl__LOADV32le_on_32) = mk_tmpl__LOADV32le_on_32(ncode_alloc);
}
@@ -4827,6 +4896,11 @@
{
return mc_LOADVn_slow( a, 64, False/*!isBigEndian*/ );
}
+VG_REGPARM(1) static ULong mc_LOADV64le_on_32_slow ( Addr a )
+{
+ return mc_LOADVn_slow( a, 64, False/*!isBigEndian*/ );
+}
+
static INLINE
void mc_STOREV64 ( Addr a, ULong vbits64, Bool isBigEndian )
Modified: branches/NCODE/memcheck/mc_translate.c
==============================================================================
--- branches/NCODE/memcheck/mc_translate.c (original)
+++ branches/NCODE/memcheck/mc_translate.c Tue Apr 21 15:57:01 2015
@@ -4688,6 +4688,21 @@
/* NCode load cases for 32 bit hosts */
if (guardIsAlwaysTrue(guard) && mce->hWordTy == Ity_I32 && end == Iend_LE) {
switch (ty) {
+ case Ity_I64: {
+ /* Unconditional LOAD64le on 32 bit host. Generate inline code. */
+ IRTemp datavbitsLO = newTemp(mce, Ity_I32, VSh);
+ IRTemp datavbitsHI = newTemp(mce, Ity_I32, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV64le_on_32);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_2( datavbitsHI,
+ datavbitsLO );
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ IRAtom* datavbits64
+ = assignNew('V', mce, Ity_I64,
+ binop(Iop_32HLto64, mkexpr(datavbitsHI),
+ mkexpr(datavbitsLO)));
+ return datavbits64;
+ }
case Ity_I32: {
/* Unconditional LOAD32le on 32 bit host. Generate inline code. */
IRTemp datavbits32 = newTemp(mce, Ity_I32, VSh);
|
|
From: <sv...@va...> - 2015-04-21 14:55:05
|
Author: sewardj
Date: Tue Apr 21 15:54:56 2015
New Revision: 3140
Log:
Merge, from trunk, r3139
(Add spec rules for EQ, MI, PL, GT and LE after COPY.)
Modified:
branches/NCODE/priv/guest_arm_helpers.c
Modified: branches/NCODE/priv/guest_arm_helpers.c
==============================================================================
--- branches/NCODE/priv/guest_arm_helpers.c (original)
+++ branches/NCODE/priv/guest_arm_helpers.c Tue Apr 21 15:54:56 2015
@@ -700,6 +700,14 @@
/*---------------- COPY ----------------*/
+ /* --- 0,1 --- */
+ if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_COPY)) {
+ /* EQ after COPY --> (cc_dep1 >> ARMG_CC_SHIFT_Z) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_Z)),
+ mkU32(1));
+ }
if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_COPY)) {
/* NE after COPY --> ((cc_dep1 >> ARMG_CC_SHIFT_Z) ^ 1) & 1 */
return binop(Iop_And32,
@@ -710,6 +718,48 @@
mkU32(1));
}
+ /* --- 4,5 --- */
+ if (isU32(cond_n_op, (ARMCondMI << 4) | ARMG_CC_OP_COPY)) {
+ /* MI after COPY --> (cc_dep1 >> ARMG_CC_SHIFT_N) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_N)),
+ mkU32(1));
+ }
+ if (isU32(cond_n_op, (ARMCondPL << 4) | ARMG_CC_OP_COPY)) {
+ /* PL after COPY --> ((cc_dep1 >> ARMG_CC_SHIFT_N) ^ 1) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Xor32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_N)),
+ mkU32(1)),
+ mkU32(1));
+ }
+
+ /* --- 12,13 --- */
+ if (isU32(cond_n_op, (ARMCondGT << 4) | ARMG_CC_OP_COPY)) {
+ /* GT after COPY --> ((z | (n^v)) & 1) ^ 1 */
+ IRExpr* n = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_N));
+ IRExpr* v = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_V));
+ IRExpr* z = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_Z));
+ return binop(Iop_Xor32,
+ binop(Iop_And32,
+ binop(Iop_Or32, z, binop(Iop_Xor32, n, v)),
+ mkU32(1)),
+ mkU32(1));
+ }
+ if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_COPY)) {
+ /* LE after COPY --> ((z | (n^v)) & 1) ^ 0 */
+ IRExpr* n = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_N));
+ IRExpr* v = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_V));
+ IRExpr* z = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_Z));
+ return binop(Iop_Xor32,
+ binop(Iop_And32,
+ binop(Iop_Or32, z, binop(Iop_Xor32, n, v)),
+ mkU32(1)),
+ mkU32(0));
+ }
+
/*----------------- AL -----------------*/
/* A critically important case for Thumb code.
|
|
From: <sv...@va...> - 2015-04-21 14:51:11
|
Author: sewardj
Date: Tue Apr 21 15:51:02 2015
New Revision: 3139
Log:
Add spec rules for EQ, MI, PL, GT and LE after COPY. These result
from floating point comparisons.
Modified:
trunk/priv/guest_arm_helpers.c
Modified: trunk/priv/guest_arm_helpers.c
==============================================================================
--- trunk/priv/guest_arm_helpers.c (original)
+++ trunk/priv/guest_arm_helpers.c Tue Apr 21 15:51:02 2015
@@ -700,6 +700,14 @@
/*---------------- COPY ----------------*/
+ /* --- 0,1 --- */
+ if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_COPY)) {
+ /* EQ after COPY --> (cc_dep1 >> ARMG_CC_SHIFT_Z) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_Z)),
+ mkU32(1));
+ }
if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_COPY)) {
/* NE after COPY --> ((cc_dep1 >> ARMG_CC_SHIFT_Z) ^ 1) & 1 */
return binop(Iop_And32,
@@ -710,6 +718,48 @@
mkU32(1));
}
+ /* --- 4,5 --- */
+ if (isU32(cond_n_op, (ARMCondMI << 4) | ARMG_CC_OP_COPY)) {
+ /* MI after COPY --> (cc_dep1 >> ARMG_CC_SHIFT_N) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_N)),
+ mkU32(1));
+ }
+ if (isU32(cond_n_op, (ARMCondPL << 4) | ARMG_CC_OP_COPY)) {
+ /* PL after COPY --> ((cc_dep1 >> ARMG_CC_SHIFT_N) ^ 1) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Xor32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_N)),
+ mkU32(1)),
+ mkU32(1));
+ }
+
+ /* --- 12,13 --- */
+ if (isU32(cond_n_op, (ARMCondGT << 4) | ARMG_CC_OP_COPY)) {
+ /* GT after COPY --> ((z | (n^v)) & 1) ^ 1 */
+ IRExpr* n = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_N));
+ IRExpr* v = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_V));
+ IRExpr* z = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_Z));
+ return binop(Iop_Xor32,
+ binop(Iop_And32,
+ binop(Iop_Or32, z, binop(Iop_Xor32, n, v)),
+ mkU32(1)),
+ mkU32(1));
+ }
+ if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_COPY)) {
+ /* LE after COPY --> ((z | (n^v)) & 1) ^ 0 */
+ IRExpr* n = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_N));
+ IRExpr* v = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_V));
+ IRExpr* z = binop(Iop_Shr32, cc_dep1, mkU8(ARMG_CC_SHIFT_Z));
+ return binop(Iop_Xor32,
+ binop(Iop_And32,
+ binop(Iop_Or32, z, binop(Iop_Xor32, n, v)),
+ mkU32(1)),
+ mkU32(0));
+ }
+
/*----------------- AL -----------------*/
/* A critically important case for Thumb code.
|
|
From: <sv...@va...> - 2015-04-21 12:27:17
|
Author: cborntra
Date: Tue Apr 21 13:27:09 2015
New Revision: 15121
Log:
increase function size even more (see r15095). On s390 this testcase
might use a relative load (e.g. via load address relative long(larl)
for the address) into the literal pool for some constants. 1280 seems
to be enough that the r/o data is copied along the function.
Modified:
trunk/perf/bigcode.c
Modified: trunk/perf/bigcode.c
==============================================================================
--- trunk/perf/bigcode.c (original)
+++ trunk/perf/bigcode.c Tue Apr 21 13:27:09 2015
@@ -20,7 +20,8 @@
#endif
#include "tests/sys_mman.h"
-#define FN_SIZE 1024 // Must be big enough to hold the compiled f()
+#define FN_SIZE 1280 // Must be big enough to hold the compiled f()
+ // and any literal pool that might be used
#define N_LOOPS 20000 // Should be divisible by four
#define RATIO 4 // Ratio of code sizes between the two modes
|
|
From: Florian K. <fl...@ei...> - 2015-04-21 12:20:07
|
On 21.04.2015 11:09, Christian Borntraeger wrote: > Several ways of fixing this > (a) using -march=z9-109 or later avoids literal pool (this system introduced extended immidiate values). This will happen anyway on recent distros (z9 was introduced 10 years ago, so most distros > have a default compiler option for z9 or later) > > (b) further increase func size. Increasing FN_SIZE sounds better than fiddling with compiler options. > Now: This actually shows, that the mmap PROT_WRITE | PROT_EXEC is wrong. Strictly > speaking we __need__ PROT_READ as well. It just does not matter as PROT_EXEC implies > PROT_READ on a page table level. You cannot execute an instruction without reading it first from somewhere. So, to me, specifying PROT_READ in addition to PROT_EXEC is redundant. We should leave the prot bits as is because they gave rise to r15075. In other words, this is a testcase for that change. Florian |
|
From: Christian B. <bor...@de...> - 2015-04-21 09:09:38
|
Am 21.04.2015 um 04:20 schrieb Christian Borntraeger:
> none/tests/bigcode (stdout)
> none/tests/bigcode (stderr)
[...]
> --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old
> -- Running tests in perf ----------------------------------------------
> -- bigcode1 --
> bigcode1 valgrind-new:0.22s no:
> *** Command returned non-zero (2816)
> *** See perf.{cmd,stdout,stderr} to determine what went wrong.
I looked into these bugs and the problem is that the gcc on SLES11 compiles for z900 which
only has instructions with small immediates. So gcc thinks that f should load some values
from the literal pool with a relative instruction:
00000000800007b4 <f>:
800007b4: e3 d0 f0 68 00 24 stg %r13,104(%r15)
800007ba: c0 d0 00 00 02 3f larl %r13,80000c38 <------ relative load (2*0x23f bytes)
800007c0: b9 04 00 02 lgr %r0,%r2
800007c4: b9 04 00 23 lgr %r2,%r3
800007c8: 18 10 lr %r1,%r0
800007ca: 54 10 d0 04 n %r1,4(%r13)
800007ce: 12 11 ltr %r1,%r1
800007d0: a7 a4 00 08 jhe 800007e0 <f+0x2c>
800007d4: a7 1a ff ff ahi %r1,-1
[...]
This of course fails miserably as soon as the function is copied (wrong values
even without values, crashes with valgrind) and the literal is not.
Several ways of fixing this
(a) using -march=z9-109 or later avoids literal pool (this system introduced extended immidiate values). This will happen anyway on recent distros (z9 was introduced 10 years ago, so most distros
have a default compiler option for z9 or later)
(b) further increase func size.
I guess the tilegx fix r15095 recently fixes the same issue - the code can not be that big. ZhiGang,
can you double check if your fix was also actually a literal pool value and not code?
In our case we are beyond 1024 bytes, see above: 7ba ---> c38 is 1150 bytes
Now this patch fixes the issue:
Index: perf/bigcode.c
===================================================================
--- perf/bigcode.c (revision 15120)
+++ perf/bigcode.c (working copy)
@@ -20,7 +20,8 @@
#endif
#include "tests/sys_mman.h"
-#define FN_SIZE 1024 // Must be big enough to hold the compiled f()
+#define FN_SIZE 1280 // Must be big enough to hold the compiled f()
+ // and any literal pool that might be used
#define N_LOOPS 20000 // Should be divisible by four
#define RATIO 4 // Ratio of code sizes between the two modes
So I am tempted to check in aboves patch.
Now: This actually shows, that the mmap PROT_WRITE | PROT_EXEC is wrong. Strictly
speaking we __need__ PROT_READ as well. It just does not matter as PROT_EXEC implies
PROT_READ on a page table level.
Opinions?
Christian
|
|
From: Thomas H. <th...@re...> - 2015-04-21 08:58:16
|
Hi all!
While trying to run qemu with valgrind on a ppc64 host, I've
encountered the following warning message from valgrind:
--11641-- WARNING: unhandled ppc64be-linux syscall: 175
valgrind then stops execution, so this was rather an error message than
a warning message, I guess ;-)
The following patch seems to fix this issue for me, however since I am
not very experienced with valgrind yet, could somebody please have a
closer look whether this is the right way to deal with this missing
syscall?
Thanks,
Thomas
diff -u a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c 2015-04-21 10:51:45.450216797 +0200
+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c 2015-04-21 10:27:34.916665631 +0200
@@ -988,7 +988,7 @@
LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 173
LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 174
-// _____(__NR_rt_sigpending, sys_rt_sigpending), // 175
+ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 175
LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 176
LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 177
LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 178
|
Author: carll
Date: Tue Apr 21 00:38:33 2015
New Revision: 15120
Log:
Add support for the lbarx, lharx, stbcx and sthcs instructions.
One of the expect files was missing. Also found that there
was a bug in the stq, stqcx, lq and lqarx instructions for LE.
The VEX commit for the instruction fix was 3138.
This commit updates the expect files for the corrected instructions
and adds the missing expect files.
The bugzilla for the orginal issue of the missing instructions
is 346324.
Added:
trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp-LE
Removed:
trunk/memcheck/tests/ppc32/power_ISA2_07.stdout.exp-LE
Modified:
trunk/memcheck/tests/ppc32/Makefile.am
trunk/none/tests/ppc32/Makefile.am
trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
Modified: trunk/memcheck/tests/ppc32/Makefile.am
==============================================================================
--- trunk/memcheck/tests/ppc32/Makefile.am (original)
+++ trunk/memcheck/tests/ppc32/Makefile.am Tue Apr 21 00:38:33 2015
@@ -6,7 +6,7 @@
EXTRA_DIST = $(noinst_SCRIPTS) \
power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
power_ISA2_05.stdout.exp_Without_FPPO \
- power_ISA2_07.stdout.exp power_ISA2_07.stdout.exp-LE \
+ power_ISA2_07.stdout.exp \
power_ISA2_07.stderr.exp power_ISA2_07.vgtest
check_PROGRAMS = \
@@ -16,11 +16,11 @@
-I$(top_srcdir)/include @FLAG_M32@
if HAS_ISA_2_07
- BUILD_FLAGS_ISA_2_07 = -mhtm -mcpu=power8
- ISA_2_07_FLAG = -DHAS_ISA_2_07
+BUILD_FLAGS_ISA_2_07 = -mhtm -mcpu=power8
+ISA_2_07_FLAG = -DHAS_ISA_2_07
else
- BUILD_FLAGS_ISA_2_07 =
- ISA_2_07_FLAG =
+BUILD_FLAGS_ISA_2_07 =
+ISA_2_07_FLAG =
endif
power_ISA2_07_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
Removed: trunk/memcheck/tests/ppc32/power_ISA2_07.stdout.exp-LE
==============================================================================
--- trunk/memcheck/tests/ppc32/power_ISA2_07.stdout.exp-LE (original)
+++ trunk/memcheck/tests/ppc32/power_ISA2_07.stdout.exp-LE (removed)
@@ -1,2 +0,0 @@
-lbarx => 0x77
-lharx => 0xbeef
Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Tue Apr 21 00:38:33 2015
@@ -40,7 +40,7 @@
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
- jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.stdout.exp-LE \
+ jm_int_isa_2_07.stdout.exp \
jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
Modified: trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp Tue Apr 21 00:38:33 2015
@@ -1,17 +1 @@
-stq abcdef0123456789,1133557722446688, 0 => abcdef0123456789,1133557722446688)
-
-lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
-
-lbarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x00000000000000aa, 0x0000000000000000)
-
-lharx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x000000000000aacc, 0x0000000000000000)
-
-lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
-
-stbcx. abefcd0145236789,1155337744226688 => 8900000000000000,0000000000000001; CR=20000000
-
-sthcx. abefcd0145236789,1155337744226688 => 6789000000000000,0000000000000001; CR=20000000
-
-stqcx. abefcd0145236789,1155337744226688 => abefcd0145236789,1155337744226688; CR=20000000
-
-All done. Tested 8 different instructions
+NO ISA 2.07 SUPPORT
Added: trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp-LE
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp-LE (added)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp-LE Tue Apr 21 00:38:33 2015
@@ -0,0 +1,17 @@
+stq abcdef0123456789,1133557722446688, 0 => 1133557722446688,abcdef0123456789)
+
+lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xabcdef0123456789, 0xaaccee0011335577)
+
+lbarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x0000000000000077, 0x0000000000000000)
+
+lharx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x0000000000005577, 0x0000000000000000)
+
+lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xabcdef0123456789, 0xaaccee0011335577)
+
+stbcx. abefcd0145236789,1155337744226688 => 0000000000000089,0000000000000001; CR=20000000
+
+sthcx. abefcd0145236789,1155337744226688 => 0000000000006789,0000000000000001; CR=20000000
+
+stqcx. abefcd0145236789,1155337744226688 => 1155337744226688,abefcd0145236789; CR=20000000
+
+All done. Tested 8 different instructions
|
|
From: <sv...@va...> - 2015-04-20 23:34:41
|
Author: carll
Date: Tue Apr 21 00:34:33 2015
New Revision: 3138
Log:
Fix for an error in the stq, stqcx, lqarx and lq instructions with LE.
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Apr 21 00:34:33 2015
@@ -5125,10 +5125,17 @@
*/
// trap if EA misaligned on 16 byte address
if (mode64) {
- assign(high, load(ty, mkexpr( EA ) ) );
- assign(low, load(ty, binop( Iop_Add64,
- mkexpr( EA ),
- mkU64( 8 ) ) ) );
+ if (host_endness == VexEndnessBE) {
+ assign(high, load(ty, mkexpr( EA ) ) );
+ assign(low, load(ty, binop( Iop_Add64,
+ mkexpr( EA ),
+ mkU64( 8 ) ) ) );
+ } else {
+ assign(low, load(ty, mkexpr( EA ) ) );
+ assign(high, load(ty, binop( Iop_Add64,
+ mkexpr( EA ),
+ mkU64( 8 ) ) ) );
+ }
} else {
assign(high, load(ty, binop( Iop_Add32,
mkexpr( EA ),
@@ -5336,11 +5343,20 @@
DIP("stq r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
if (mode64) {
- /* upper 64-bits */
- assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+ if (host_endness == VexEndnessBE) {
+
+ /* upper 64-bits */
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
- /* lower 64-bits */
- assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) );
+ /* lower 64-bits */
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) );
+ } else {
+ /* upper 64-bits */
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+8 ) );
+
+ /* lower 64-bits */
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16 ) );
+ }
} else {
/* upper half of upper 64-bits */
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+4 ) );
@@ -6535,11 +6551,19 @@
// and actually do the load
if (mode64) {
- stmt( stmt_load( res_hi,
- mkexpr(EA), NULL/*this is a load*/) );
- stmt( stmt_load( res_lo,
- binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
- NULL/*this is a load*/) );
+ if (host_endness == VexEndnessBE) {
+ stmt( stmt_load( res_hi,
+ mkexpr(EA), NULL/*this is a load*/) );
+ stmt( stmt_load( res_lo,
+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+ NULL/*this is a load*/) );
+ } else {
+ stmt( stmt_load( res_lo,
+ mkexpr(EA), NULL/*this is a load*/) );
+ stmt( stmt_load( res_hi,
+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+ NULL/*this is a load*/) );
+ }
} else {
stmt( stmt_load( res_hi,
binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
@@ -6575,8 +6599,15 @@
resSC = newTemp(Ity_I1);
if (mode64) {
- stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) );
- store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
+ if (host_endness == VexEndnessBE) {
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ),
+ mkexpr(rS_lo) );
+ } else {
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_lo) ) );
+ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ),
+ mkexpr(rS_hi) );
+ }
} else {
stmt( stmt_load( resSC, binop( Iop_Add32,
mkexpr(EA),
|