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From: <sv...@va...> - 2014-06-04 23:22:45
|
Author: sewardj
Date: Wed Jun 4 23:22:29 2014
New Revision: 13997
Log:
Enable sys_fchmodat.
Modified:
trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-arm64-linux.c Wed Jun 4 23:22:29 2014
@@ -920,6 +920,7 @@
LINX_(__NR_fallocate, sys_fallocate), // 47
LINX_(__NR_faccessat, sys_faccessat), // 48
GENX_(__NR_chdir, sys_chdir), // 49
+ LINX_(__NR_fchmodat, sys_fchmodat), // 53
LINXY(__NR_openat, sys_openat), // 56
GENXY(__NR_close, sys_close), // 57
LINXY(__NR_pipe2, sys_pipe2), // 59
@@ -1360,7 +1361,6 @@
//ZZ LINX_(__NR_renameat, sys_renameat), // 302
//ZZ LINX_(__NR_symlinkat, sys_symlinkat), // 304
//ZZ
-//ZZ LINX_(__NR_fchmodat, sys_fchmodat), //
//ZZ LINX_(__NR_shmget, sys_shmget), //307
//ZZ // LINX_(__NR_pselect6, sys_pselect6), //
//ZZ
|
|
From: <sv...@va...> - 2014-06-04 21:55:25
|
Author: sewardj
Date: Wed Jun 4 21:55:16 2014
New Revision: 13996
Log:
Fix out-of-range constants for some 32 bit insns, presumably tolerated
by older assembler versions but not newer ones.
Modified:
trunk/none/tests/arm64/integer.c
Modified: trunk/none/tests/arm64/integer.c
==============================================================================
--- trunk/none/tests/arm64/integer.c (original)
+++ trunk/none/tests/arm64/integer.c Wed Jun 4 21:55:16 2014
@@ -576,8 +576,8 @@
TESTINST2("ands x3,x4, #0x8080808080808080", 0xF070707070707070, x3, x4, 0);
TESTINST2("and w3,w4, #0xF", ALL5s, x3, x4, 0);
-TESTINST2("and w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0);
-TESTINST2("and w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
+TESTINST2("and w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
+TESTINST2("and w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
TESTINST2("ands w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
TESTINST2("ands w3,w4, #0x80808080", 0x143fdf810277796e, x3, x4, 0);
@@ -592,8 +592,8 @@
TESTINST2("orr x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
TESTINST2("orr w3,w4, #0xF", ALL5s, x3, x4, 0);
-TESTINST2("orr w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0);
-TESTINST2("orr w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
+TESTINST2("orr w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
+TESTINST2("orr w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
////////////////////////////////////////////////////////////////
printf("EOR(imm)\n");
@@ -602,8 +602,8 @@
TESTINST2("eor x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
TESTINST2("eor w3,w4, #0xF", ALL5s, x3, x4, 0);
-TESTINST2("eor w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0);
-TESTINST2("eor w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
+TESTINST2("eor w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
+TESTINST2("eor w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
////////////////////////////////////////////////////////////////
printf("MOVZ\n");
|
|
From: <sv...@va...> - 2014-06-04 13:13:18
|
Author: sewardj
Date: Wed Jun 4 13:13:05 2014
New Revision: 13995
Log:
Add test cases for ADC/ADCS/SBC/SBCS. Pertains to #335496.
Modified:
trunk/none/tests/arm64/integer.c
Modified: trunk/none/tests/arm64/integer.c
==============================================================================
--- trunk/none/tests/arm64/integer.c (original)
+++ trunk/none/tests/arm64/integer.c Wed Jun 4 13:13:05 2014
@@ -1,6 +1,6 @@
/* To compile:
- aarch64-linux-gnu-gcc -Wall -g -O0 -o test_arm64_int test_arm64_int.c \
+ aarch64-linux-gnu-gcc -Wall -g -O0 -o integer none/tests/arm64/integer.c \
-DTEST_BFM=1 # (or 0)
The ubfm/sbfm/bfm tests are huge and take ages to compile and run.
Set TEST_BFM to 0 to skip them.
@@ -243,6 +243,163 @@
TESTINST3("add x3, x4, x5", 12345, 6789, x3, x4, x5, 0);
TESTINST3("add w3, w4, w5", 12345, 6789, x3, x4, x5, 0);
+
+TESTINST3("adc x3, x4, x5", 12345, 6789, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 12345, 6789, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adc x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adc x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+
+TESTINST3("adc w3, w4, w5", 12345, 6789, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 12345, 6789, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 1);
+TESTINST3("adc w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("adc w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 1);
+
+
+TESTINST3("adcs x3, x4, x5", 12345, 6789, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 12345, 6789, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+TESTINST3("adcs x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("adcs x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+
+TESTINST3("adcs w3, w4, w5", 12345, 6789, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 12345, 6789, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 1);
+TESTINST3("adcs w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("adcs w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 1);
+
+
+TESTINST3("sbc x3, x4, x5", 12345, 6789, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 12345, 6789, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbc x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbc x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+
+TESTINST3("sbc w3, w4, w5", 12345, 6789, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 12345, 6789, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 1);
+TESTINST3("sbc w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("sbc w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 1);
+
+
+TESTINST3("sbcs x3, x4, x5", 12345, 6789, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 12345, 6789, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0, 0xffffffffffffffffULL, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x31415927ULL<<32, 0x27181728ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x00000001ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x00000001ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x80000000ULL<<32, 0x00000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x00000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+TESTINST3("sbcs x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,0);
+TESTINST3("sbcs x3, x4, x5", 0x80000000ULL<<32, 0x80000000ULL<<32, x3,x4,x5,1);
+
+TESTINST3("sbcs w3, w4, w5", 12345, 6789, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 12345, 6789, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0, 0xffffffffULL, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x31415927, 0x27181728, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x00000001, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x00000001, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x80000000, 0x00000000, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x00000000, 0x80000000, x3,x4,x5, 1);
+TESTINST3("sbcs w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 0);
+TESTINST3("sbcs w3, w4, w5", 0x80000000, 0x80000000, x3,x4,x5, 1);
+
+
TESTINST2("bfm x2, x4, #0, #63", 0x5555555555555555, x2, x4, 0);
TESTINST2("bfm x2, x4, #0, #63", 0xaaaaaaaaaaaaaaaa, x2, x4, 0);
|
|
From: <sv...@va...> - 2014-06-04 13:09:56
|
Author: sewardj
Date: Wed Jun 4 13:09:44 2014
New Revision: 2868
Log:
Support ADC/ADCS/SBC/SBCS. Fixes #335496. (di...@go...)
Modified:
trunk/priv/guest_arm64_defs.h
trunk/priv/guest_arm64_helpers.c
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_defs.h
==============================================================================
--- trunk/priv/guest_arm64_defs.h (original)
+++ trunk/priv/guest_arm64_defs.h Wed Jun 4 13:09:44 2014
@@ -83,12 +83,12 @@
ULong arm64g_calculate_flags_nzcv ( ULong cc_op, ULong cc_dep1,
ULong cc_dep2, ULong cc_dep3 );
-//ZZ /* Calculate the C flag from the thunk components, in the lowest bit
-//ZZ of the word (bit 0). */
-//ZZ extern
-//ZZ UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1,
-//ZZ UInt cc_dep2, UInt cc_dep3 );
-//ZZ
+/* Calculate the C flag from the thunk components, in the lowest bit
+ of the word (bit 0). */
+extern
+ULong arm64g_calculate_flag_c ( ULong cc_op, ULong cc_dep1,
+ ULong cc_dep2, ULong cc_dep3 );
+
//ZZ /* Calculate the V flag from the thunk components, in the lowest bit
//ZZ of the word (bit 0). */
//ZZ extern
@@ -159,8 +159,10 @@
OP_ADD64 argL argR unused
OP_SUB32 argL argR unused
OP_SUB64 argL argR unused
-//ZZ OP_ADC argL argR 31x0:old_C
-//ZZ OP_SBB argL argR 31x0:old_C
+ OP_ADC32 argL argR 63x0:old_C
+ OP_ADC64 argL argR 63x0:old_C
+ OP_SBC32 argL argR 63x0:old_C
+ OP_SBC64 argL argR 63x0:old_C
OP_LOGIC32 result unused unused
OP_LOGIC64 result unused unused
//ZZ OP_MUL result unused 30x0:old_C:old_V
@@ -183,11 +185,17 @@
ARM64G_CC_OP_SUB64, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op),
DEP3 = 0 */
-//ZZ ARMG_CC_OP_ADC, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
-//ZZ DEP3 = oldC (in LSB) */
-//ZZ
-//ZZ ARMG_CC_OP_SBB, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
-//ZZ DEP3 = oldC (in LSB) */
+ ARM64G_CC_OP_ADC32, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
+ DEP3 = oldC (in LSB) */
+
+ ARM64G_CC_OP_ADC64, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
+ DEP3 = oldC (in LSB) */
+
+ ARM64G_CC_OP_SBC32, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
+ DEP3 = oldC (in LSB) */
+
+ ARM64G_CC_OP_SBC64, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
+ DEP3 = oldC (in LSB) */
ARM64G_CC_OP_LOGIC32, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */
ARM64G_CC_OP_LOGIC64, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */
Modified: trunk/priv/guest_arm64_helpers.c
==============================================================================
--- trunk/priv/guest_arm64_helpers.c (original)
+++ trunk/priv/guest_arm64_helpers.c Wed Jun 4 13:09:44 2014
@@ -153,26 +153,46 @@
ULong nf = res >> 63;
return nf;
}
-//ZZ case ARMG_CC_OP_ADC: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL + argR + oldC;
-//ZZ UInt nf = res >> 31;
-//ZZ return nf;
-//ZZ }
-//ZZ case ARMG_CC_OP_SBB: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL - argR - (oldC ^ 1);
-//ZZ UInt nf = res >> 31;
-//ZZ return nf;
-//ZZ }
+ case ARM64G_CC_OP_ADC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL + argR + oldC;
+ ULong nf = (ULong)(res >> 31);
+ return nf;
+ }
+ case ARM64G_CC_OP_ADC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL + argR + oldC;
+ ULong nf = res >> 63;
+ return nf;
+ }
+ case ARM64G_CC_OP_SBC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL - argR - (oldC ^ 1);
+ ULong nf = (ULong)(res >> 31);
+ return nf;
+ }
+ case ARM64G_CC_OP_SBC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL - argR - (oldC ^ 1);
+ ULong nf = res >> 63;
+ return nf;
+ }
case ARM64G_CC_OP_LOGIC32: {
/* (res, unused, unused) */
UInt res = (UInt)cc_dep1;
@@ -251,26 +271,46 @@
ULong zf = res == 0;
return zf;
}
-//ZZ case ARMG_CC_OP_ADC: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL + argR + oldC;
-//ZZ UInt zf = res == 0;
-//ZZ return zf;
-//ZZ }
-//ZZ case ARMG_CC_OP_SBB: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL - argR - (oldC ^ 1);
-//ZZ UInt zf = res == 0;
-//ZZ return zf;
-//ZZ }
+ case ARM64G_CC_OP_ADC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL + argR + oldC;
+ ULong zf = res == 0;
+ return zf;
+ }
+ case ARM64G_CC_OP_ADC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL + argR + oldC;
+ ULong zf = res == 0;
+ return zf;
+ }
+ case ARM64G_CC_OP_SBC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL - argR - (oldC ^ 1);
+ ULong zf = res == 0;
+ return zf;
+ }
+ case ARM64G_CC_OP_SBC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL - argR - (oldC ^ 1);
+ ULong zf = res == 0;
+ return zf;
+ }
case ARM64G_CC_OP_LOGIC32: {
/* (res, unused, unused) */
UInt res = (UInt)cc_dep1;
@@ -309,7 +349,6 @@
/* CALLED FROM GENERATED CODE: CLEAN HELPER */
/* Calculate the C flag from the supplied thunk components, in the
least significant bit of the word. Returned bits 63:1 are zero. */
-static
ULong arm64g_calculate_flag_c ( ULong cc_op, ULong cc_dep1,
ULong cc_dep2, ULong cc_dep3 )
{
@@ -349,25 +388,44 @@
ULong cf = argL >= argR;
return cf;
}
-//ZZ case ARMG_CC_OP_ADC: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL + argR + oldC;
-//ZZ UInt cf = oldC ? (res <= argL) : (res < argL);
-//ZZ return cf;
-//ZZ }
-//ZZ case ARMG_CC_OP_SBB: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt cf = oldC ? (argL >= argR) : (argL > argR);
-//ZZ return cf;
-//ZZ }
+ case ARM64G_CC_OP_ADC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL + argR + oldC;
+ ULong cf = oldC ? (res <= argL) : (res < argL);
+ return cf;
+ }
+ case ARM64G_CC_OP_ADC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL + argR + oldC;
+ ULong cf = oldC ? (res <= argL) : (res < argL);
+ return cf;
+ }
+ case ARM64G_CC_OP_SBC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong cf = oldC ? (argL >= argR) : (argL > argR);
+ return cf;
+ }
+ case ARM64G_CC_OP_SBC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong cf = oldC ? (argL >= argR) : (argL > argR);
+ return cf;
+ }
case ARM64G_CC_OP_LOGIC32:
case ARM64G_CC_OP_LOGIC64: {
/* (res, unused, unused) */
@@ -442,26 +500,46 @@
ULong vf = (((argL ^ argR) & (argL ^ res))) >> 63;
return vf;
}
-//ZZ case ARMG_CC_OP_ADC: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL + argR + oldC;
-//ZZ UInt vf = ((res ^ argL) & (res ^ argR)) >> 31;
-//ZZ return vf;
-//ZZ }
-//ZZ case ARMG_CC_OP_SBB: {
-//ZZ /* (argL, argR, oldC) */
-//ZZ UInt argL = cc_dep1;
-//ZZ UInt argR = cc_dep2;
-//ZZ UInt oldC = cc_dep3;
-//ZZ vassert((oldC & ~1) == 0);
-//ZZ UInt res = argL - argR - (oldC ^ 1);
-//ZZ UInt vf = ((argL ^ argR) & (argL ^ res)) >> 31;
-//ZZ return vf;
-//ZZ }
+ case ARM64G_CC_OP_ADC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL + argR + oldC;
+ ULong vf = (ULong)(((res ^ argL) & (res ^ argR)) >> 31);
+ return vf;
+ }
+ case ARM64G_CC_OP_ADC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL + argR + oldC;
+ ULong vf = ((res ^ argL) & (res ^ argR)) >> 63;
+ return vf;
+ }
+ case ARM64G_CC_OP_SBC32: {
+ /* (argL, argR, oldC) */
+ UInt argL = cc_dep1;
+ UInt argR = cc_dep2;
+ UInt oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ UInt res = argL - argR - (oldC ^ 1);
+ ULong vf = (ULong)(((argL ^ argR) & (argL ^ res)) >> 31);
+ return vf;
+ }
+ case ARM64G_CC_OP_SBC64: {
+ /* (argL, argR, oldC) */
+ ULong argL = cc_dep1;
+ ULong argR = cc_dep2;
+ ULong oldC = cc_dep3;
+ vassert((oldC & ~1) == 0);
+ ULong res = argL - argR - (oldC ^ 1);
+ ULong vf = ((argL ^ argR) & (argL ^ res)) >> 63;
+ return vf;
+ }
case ARM64G_CC_OP_LOGIC32:
case ARM64G_CC_OP_LOGIC64: {
/* (res, unused, unused) */
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Wed Jun 4 13:09:44 2014
@@ -1316,30 +1316,30 @@
}
-//ZZ /* Build IR to calculate just the carry flag from stored
-//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression ::
-//ZZ Ity_I32. */
-//ZZ static IRExpr* mk_armg_calculate_flag_c ( void )
-//ZZ {
-//ZZ IRExpr** args
-//ZZ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32),
-//ZZ IRExpr_Get(OFFB_CC_DEP1, Ity_I32),
-//ZZ IRExpr_Get(OFFB_CC_DEP2, Ity_I32),
-//ZZ IRExpr_Get(OFFB_CC_NDEP, Ity_I32) );
-//ZZ IRExpr* call
-//ZZ = mkIRExprCCall(
-//ZZ Ity_I32,
-//ZZ 0/*regparm*/,
-//ZZ "armg_calculate_flag_c", &armg_calculate_flag_c,
-//ZZ args
-//ZZ );
-//ZZ /* Exclude OP and NDEP from definedness checking. We're only
-//ZZ interested in DEP1 and DEP2. */
-//ZZ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3);
-//ZZ return call;
-//ZZ }
-//ZZ
-//ZZ
+/* Build IR to calculate just the carry flag from stored
+ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression ::
+ Ity_I64. */
+static IRExpr* mk_arm64g_calculate_flag_c ( void )
+{
+ IRExpr** args
+ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I64),
+ IRExpr_Get(OFFB_CC_DEP1, Ity_I64),
+ IRExpr_Get(OFFB_CC_DEP2, Ity_I64),
+ IRExpr_Get(OFFB_CC_NDEP, Ity_I64) );
+ IRExpr* call
+ = mkIRExprCCall(
+ Ity_I64,
+ 0/*regparm*/,
+ "arm64g_calculate_flag_c", &arm64g_calculate_flag_c,
+ args
+ );
+ /* Exclude OP and NDEP from definedness checking. We're only
+ interested in DEP1 and DEP2. */
+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3);
+ return call;
+}
+
+
//ZZ /* Build IR to calculate just the overflow flag from stored
//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression ::
//ZZ Ity_I32. */
@@ -1428,6 +1428,35 @@
setFlags_D1_D2_ND(cc_op, argL64, argR64, z64);
}
+/* Build IR to set the flags thunk after ADC or SBC. */
+static
+void setFlags_ADC_SBC ( Bool is64, Bool isSBC,
+ IRTemp argL, IRTemp argR, IRTemp oldC )
+{
+ IRTemp argL64 = IRTemp_INVALID;
+ IRTemp argR64 = IRTemp_INVALID;
+ IRTemp oldC64 = IRTemp_INVALID;
+ if (is64) {
+ argL64 = argL;
+ argR64 = argR;
+ oldC64 = oldC;
+ } else {
+ argL64 = newTemp(Ity_I64);
+ argR64 = newTemp(Ity_I64);
+ oldC64 = newTemp(Ity_I64);
+ assign(argL64, unop(Iop_32Uto64, mkexpr(argL)));
+ assign(argR64, unop(Iop_32Uto64, mkexpr(argR)));
+ assign(oldC64, unop(Iop_32Uto64, mkexpr(oldC)));
+ }
+ UInt cc_op = ARM64G_CC_OP_NUMBER;
+ /**/ if ( isSBC && is64) { cc_op = ARM64G_CC_OP_SBC64; }
+ else if ( isSBC && !is64) { cc_op = ARM64G_CC_OP_SBC32; }
+ else if (!isSBC && is64) { cc_op = ARM64G_CC_OP_ADC64; }
+ else if (!isSBC && !is64) { cc_op = ARM64G_CC_OP_ADC32; }
+ else { vassert(0); }
+ setFlags_D1_D2_ND(cc_op, argL64, argR64, oldC64);
+}
+
/* Build IR to set the flags thunk after ADD or SUB, if the given
condition evaluates to True at run time. If not, the flags are set
to the specified NZCV value. */
@@ -2308,6 +2337,68 @@
}
}
+ /* ------------------- ADC/SBC(reg) ------------------- */
+ /* x==0 => 32 bit op x==1 => 64 bit op
+
+ 31 30 29 28 23 21 20 15 9 4
+ | | | | | | | | | |
+ x 0 0 11010 00 0 Rm 000000 Rn Rd ADC Rd,Rn,Rm
+ x 0 1 11010 00 0 Rm 000000 Rn Rd ADCS Rd,Rn,Rm
+ x 1 0 11010 00 0 Rm 000000 Rn Rd SBC Rd,Rn,Rm
+ x 1 1 11010 00 0 Rm 000000 Rn Rd SBCS Rd,Rn,Rm
+ */
+
+ if (INSN(28,21) == BITS8(1,1,0,1,0,0,0,0) && INSN(15,10) == 0 ) {
+ UInt bX = INSN(31,31);
+ UInt bOP = INSN(30,30); /* 0: ADC, 1: SBC */
+ UInt bS = INSN(29,29); /* set flags */
+ UInt rM = INSN(20,16);
+ UInt rN = INSN(9,5);
+ UInt rD = INSN(4,0);
+
+ Bool isSUB = bOP == 1;
+ Bool is64 = bX == 1;
+ IRType ty = is64 ? Ity_I64 : Ity_I32;
+
+ IRTemp oldC = newTemp(ty);
+ assign(oldC,
+ is64 ? mk_arm64g_calculate_flag_c()
+ : unop(Iop_64to32, mk_arm64g_calculate_flag_c()) );
+
+ IRTemp argL = newTemp(ty);
+ assign(argL, getIRegOrZR(is64, rN));
+ IRTemp argR = newTemp(ty);
+ assign(argR, getIRegOrZR(is64, rM));
+
+ IROp op = isSUB ? mkSUB(ty) : mkADD(ty);
+ IRTemp res = newTemp(ty);
+ if (isSUB) {
+ IRExpr* one = is64 ? mkU64(1) : mkU32(1);
+ IROp xorOp = is64 ? Iop_Xor64 : Iop_Xor32;
+ assign(res,
+ binop(op,
+ binop(op, mkexpr(argL), mkexpr(argR)),
+ binop(xorOp, mkexpr(oldC), one)));
+ } else {
+ assign(res,
+ binop(op,
+ binop(op, mkexpr(argL), mkexpr(argR)),
+ mkexpr(oldC)));
+ }
+
+ if (rD != 31) putIRegOrZR(is64, rD, mkexpr(res));
+
+ if (bS) {
+ setFlags_ADC_SBC(is64, isSUB, argL, argR, oldC);
+ }
+
+ DIP("%s%s %s, %s, %s\n",
+ bOP ? "sbc" : "adc", bS ? "s" : "",
+ nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN),
+ nameIRegOrZR(is64, rM));
+ return True;
+ }
+
/* -------------------- LOGIC(reg) -------------------- */
/* x==0 => 32 bit op x==1 => 64 bit op
N==0 => inv? is no-op (no inversion)
|
|
From: <sv...@va...> - 2014-06-04 11:44:51
|
Author: sewardj
Date: Wed Jun 4 11:44:45 2014
New Revision: 2867
Log:
Support the "ishst" variant of "dmb". Fixes #335263. (di...@go...)
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Wed Jun 4 11:44:45 2014
@@ -4731,6 +4731,11 @@
DIP("dmb ish\n");
return True;
}
+ if (INSN(31,0) == 0xD5033ABF) {
+ stmt(IRStmt_MBE(Imbe_Fence));
+ DIP("dmb ishst\n");
+ return True;
+ }
if (INSN(31,0) == 0xD5033B9F) {
stmt(IRStmt_MBE(Imbe_Fence));
DIP("dsb ish\n");
|
|
From: <sv...@va...> - 2014-06-04 11:37:01
|
Author: sewardj
Date: Wed Jun 4 11:36:54 2014
New Revision: 2866
Log:
Support movi_{16b,8b}_#imm8. Fixes #335262. (di...@go...)
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Wed Jun 4 11:36:54 2014
@@ -5398,7 +5398,7 @@
MOV Vd.2d #imm (q=1)
Allowable op:cmode
FMOV = 1:1111
- MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, 11110
+ MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110
*/
if (INSN(31,31) == 0
&& INSN(28,19) == BITS10(0,1,1,1,1,0,0,0,0,0)
@@ -5418,7 +5418,7 @@
case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00
case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0
case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x
- case BITS5(1,1,1,1,0): // 1:1110
+ case BITS5(1,1,1,1,0): case BITS5(0,1,1,1,0): // x:1110
ok = True; break;
default:
break;
|
|
From: <sv...@va...> - 2014-06-04 11:36:35
|
Author: dejanj
Date: Wed Jun 4 11:36:21 2014
New Revision: 13994
Log:
mips64: Tests for Cavium MIPS Octeon Atomic and Count Instructions.
Tests for instructions:
baddu, pop, dpop, saa, saad, laa, laad, lai, laid, lad, ladd, law, lawd,
las, lasd, lac, lacd
Added:
trunk/none/tests/mips64/cvm_atomic.c
trunk/none/tests/mips64/cvm_atomic.stderr.exp
trunk/none/tests/mips64/cvm_atomic.stdout.exp-LE
trunk/none/tests/mips64/cvm_atomic.stdout.exp-non-octeon
trunk/none/tests/mips64/cvm_atomic.vgtest
trunk/none/tests/mips64/cvm_atomic_thread.c
trunk/none/tests/mips64/cvm_atomic_thread.stderr.exp
trunk/none/tests/mips64/cvm_atomic_thread.stdout.exp-LE
trunk/none/tests/mips64/cvm_atomic_thread.stdout.exp-non-octeon
trunk/none/tests/mips64/cvm_atomic_thread.vgtest
Modified:
trunk/NEWS
trunk/docs/internals/3_9_BUGSTATUS.txt
trunk/none/tests/mips64/ (props changed)
trunk/none/tests/mips64/Makefile.am
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Jun 4 11:36:21 2014
@@ -90,6 +90,7 @@
326921 coregrind fails to compile m_trampoline.S with MIPS/Linux port of V
326983 Clear direction flag after tests on amd64.
327212 Do not prepend the current directory to absolute path names.
+327223 Support for Cavium MIPS Octeon Atomic and Count Instructions
327238 Callgrind Assertion 'passed <= last_bb->cjmp_count' failed
327284 s390x: Fix translation of the risbg instruction
327639 vex amd64->IR pcmpestri SSE4.2 instruction is unsupported 0x34
Modified: trunk/docs/internals/3_9_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_9_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_9_BUGSTATUS.txt Wed Jun 4 11:36:21 2014
@@ -38,7 +38,6 @@
=== VEX/mips ===========================================================
-327223 Support for Cavium MIPS Octeon Atomic and Count Instructions
328147 vex mips->IR: unhandled instruction bytes: 0x0 0x0 0x0 0xE
=== VEX/ppc ============================================================
Modified: trunk/none/tests/mips64/Makefile.am
==============================================================================
--- trunk/none/tests/mips64/Makefile.am (original)
+++ trunk/none/tests/mips64/Makefile.am Wed Jun 4 11:36:21 2014
@@ -15,6 +15,10 @@
cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \
cvm_lx_ins.stdout.exp-non-octeon \
cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \
+ cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-non-octeon \
+ cvm_atomic.stderr.exp cvm_atomic.vgtest \
+ cvm_atomic_thread.stdout.exp-LE cvm_atomic_thread.stdout.exp-non-octeon \
+ cvm_atomic_thread.stderr.exp cvm_atomic_thread.vgtest \
extract_insert_bit_field.stdout.exp-mips64 \
extract_insert_bit_field.stdout.exp-mips64r2 \
extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \
@@ -61,6 +65,8 @@
branches \
cvm_ins \
cvm_lx_ins \
+ cvm_atomic \
+ cvm_atomic_thread \
extract_insert_bit_field \
fpu_arithmetic \
fpu_branches \
@@ -89,6 +95,8 @@
cvm_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@
cvm_lx_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+cvm_atomic_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+cvm_atomic_thread_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
load_indexed_instructions_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
fpu_arithmetic_CFLAGS = $(AM_CFLAGS) -lm
Added: trunk/none/tests/mips64/cvm_atomic.c
==============================================================================
--- trunk/none/tests/mips64/cvm_atomic.c (added)
+++ trunk/none/tests/mips64/cvm_atomic.c Wed Jun 4 11:36:21 2014
@@ -0,0 +1,298 @@
+#include <stdio.h>
+
+#define N 256
+
+unsigned long long reg_val_double[N];
+
+void init_reg_val_double()
+{
+ unsigned long c = 19650218UL;
+ int i;
+ reg_val_double[0]= c & 0xffffffffUL;
+ for (i = 1; i < N; i++) {
+ reg_val_double[i] = (1812433253UL * (reg_val_double[i - 1] ^
+ (reg_val_double[i - 1] >> 30)) + i);
+ }
+}
+
+
+/* Make a copy of original array to prevent the unexpected changes by Atomic Add
+ Instructions */
+unsigned long long reg_val_double_copy[N];
+
+void copy_reg_val_double()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ reg_val_double_copy[i] = reg_val_double[i];
+ }
+}
+
+/* TEST1_32/64 macro is used in load atomic increment/decrement/set/clear
+ instructions. After executing each instruction we must check both memory
+ location and register value.
+
+ 1: Move arguments (offset and base address) to registers
+ 2: Add offset and base address to make absolute address
+ 3: Execute instruction
+ 4: Move result from register ($t3)
+ 5: Load memory data ('lw' for 32bit instruction and 'ld' for 64bit addresses)
+*/
+#define TEST1_32(instruction, offset,mem) \
+{ \
+ unsigned long out = 0; \
+ unsigned long res_mem = 0; \
+ __asm__ volatile( \
+ "move $t0, %2" "\n\t" \
+ "move $t1, %3" "\n\t" \
+ "daddu $t0, $t1, $t0" "\n\t" \
+ instruction " $t3, ($t0)" "\n\t" \
+ "move %0, $t3" "\n\t" \
+ "lw %1, 0($t0)" "\n\t" \
+ : "=&r" (out), "=&r"(res_mem) \
+ : "r" (mem) , "r" (offset) \
+ : "$12", "$13", "cc", "memory" \
+ ); \
+ printf("%s :: offset: 0x%x, out: 0x%lx, result:0x%lx\n", \
+ instruction, offset, out, res_mem); \
+}
+
+#define TEST1_64(instruction, offset,mem) \
+{ \
+ unsigned long out = 0; \
+ unsigned long res_mem = 0; \
+ __asm__ volatile( \
+ "move $t0, %2" "\n\t" \
+ "move $t1, %3" "\n\t" \
+ "daddu $t0, $t1, $t0" "\n\t" \
+ instruction " $t3, ($t0)" "\n\t" \
+ "move %0, $t3" "\n\t" \
+ "ld %1, 0($t0)" "\n\t" \
+ : "=&r" (out), "=&r"(res_mem) \
+ : "r" (mem) , "r" (offset) \
+ : "$12", "$13", "cc", "memory" \
+ ); \
+ printf("%s :: offset: 0x%x, out: 0x%lx, result: 0x%lx\n", \
+ instruction, offset, out, res_mem); \
+}
+
+/* Test 2 macro is used for pop/dpop/baddu instructions. After executing each
+ instructions the macro performs following operations:
+
+ 1: Move arguments to registers
+ 2: Execute instruction
+ 3: Move result to register ($t3)
+*/
+#define TEST2(instruction, RSVal, RTVal) \
+{ \
+ unsigned long out; \
+ __asm__ volatile( \
+ "move $t1, %1" "\n\t" \
+ "move $t2, %2" "\n\t" \
+ instruction "\n\t" \
+ "move %0, $t3" "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSVal), "r" (RTVal) \
+ : "$12", "$13", "cc", "memory" \
+ ); \
+ printf("%s :: rd 0x%lx, rs 0x%llx, rt 0x%llx\n", \
+ instruction, out, (long long) RSVal, (long long) RTVal); \
+}
+
+/* TEST3 macro is used for store atomic add and store atomic add doubleword
+ instructions. Following operations are performed by the test macro:
+
+ 1: Move arguments to the register
+ 2: Add offset and base address to make absolute address
+ 3: Execute instruction
+ 4: Load memory data
+*/
+#define TEST3(instruction, offset, mem, value) \
+{ \
+ unsigned long out = 0; \
+ unsigned long outPre = 0; \
+ __asm__ volatile( \
+ "move $t0, %2" "\n\t" \
+ "move $t1, %3" "\n\t" \
+ "daddu $t0, $t1, $t0" "\n\t" \
+ "ld %1, 0($t0)" "\n\t" \
+ "move $t2, %4" "\n\t" \
+ instruction " $t2, ($t0)" "\n\t" \
+ "ld %0, 0($t0)" "\n\t" \
+ : "=&r" (out), "=&r" (outPre) \
+ : "r" (mem) , "r" (offset), "r" (value) \
+ : "$12", "$13", "$14", "cc", "memory" \
+ ); \
+ printf("%s :: value: 0x%llx, memPre: 0x%lx, mem: 0x%lx\n", \
+ instruction, value, outPre, out); \
+}
+
+/* TEST4_32/64 is used for load atomic add/swap instructions. Following
+ operations are performed by macro after execution of each instruction:
+
+ 1: Move arguments to register.
+ 2: Add offset and base address to make absolute address.
+ 3: Execute instruction.
+ 4: Move result to register.
+ 5: Load memory data ('lw' for 32bit instruction and 'ld' for 64bit).
+*/
+#define TEST4_32(instruction, offset, mem) \
+{ \
+ unsigned long out = 0; \
+ unsigned long res_mem = 0; \
+ __asm__ volatile( \
+ "move $t0, %2" "\n\t" \
+ "move $t1, %3" "\n\t" \
+ "daddu $t0, $t0, $t1" "\n\t" \
+ instruction " $t3, ($t0), $t1" "\n\t" \
+ "move %0, $t3" "\n\t" \
+ "lw %1, 0($t0)" "\n\t" \
+ : "=&r" (out), "=&r"(res_mem) \
+ : "r" (mem) , "r" (offset) \
+ : "$12", "$13", "cc", "memory" \
+ ); \
+ printf("%s :: offset: 0x%x, out: 0x%lx, result:0x%lx\n", \
+ instruction, offset, out, res_mem); \
+}
+
+#define TEST4_64(instruction, offset, mem) \
+{ \
+ unsigned long out = 0; \
+ unsigned long res_mem = 0; \
+ __asm__ volatile( \
+ "move $t0, %2" "\n\t" \
+ "move $t1, %3" "\n\t" \
+ "daddu $t0, $t0, $t1" "\n\t" \
+ instruction " $t3, ($t0), $t1" "\n\t" \
+ "move %0, $t3" "\n\t" \
+ "ld %1, 0($t0)" "\n\t" \
+ : "=&r" (out), "=&r"(res_mem) \
+ : "r" (mem) , "r" (offset) \
+ : "$12", "$13", "cc", "memory" \
+ ); \
+ printf("%s :: offset: 0x%x, out: 0x%lx, result: 0x%lx\n", \
+ instruction, offset, out, res_mem); \
+}
+
+typedef enum {
+ BADDU, POP, DPOP, SAA, SAAD, LAA, LAAD, LAW, LAWD, LAI, LAID, LAD, LADD,
+ LAS, LASD, LAC, LACD
+} cvm_op;
+
+int main()
+{
+#if (_MIPS_ARCH_OCTEON2)
+ init_reg_val_double();
+ int i,j;
+ cvm_op op;
+ for (op = BADDU; op <= LACD; op++) {
+ switch(op){
+ /* Unsigned Byte Add - BADDU rd, rs, rt; Cavium OCTEON */
+ case BADDU: {
+ for(i = 4; i < N; i += 4)
+ for(j = 4; j < N; j += 4)
+ TEST2("baddu $t3, $t1, $t2", reg_val_double[i],
+ reg_val_double[j]);
+ break;
+ }
+ case POP: { /* Count Ones in a Word - POP */
+ for(j = 4; j < N; j += 4)
+ TEST2("pop $t3, $t1", reg_val_double[j], 0);
+ break;
+ }
+ case DPOP: { /* Count Ones in a Doubleword - DPOP */
+ for(j = 8; j < N; j += 8)
+ TEST2("dpop $t3, $t1", reg_val_double[j], 0);
+ break;
+ }
+ case SAA: { /* Atomic Add Word - saa rt, (base). */
+ copy_reg_val_double();
+ for(j = 4; j < N; j += 4)
+ TEST3("saa", j, reg_val_double_copy, reg_val_double[j]);
+ break;
+ }
+ case SAAD: { /* Atomic Add Double - saad rt, (base). */
+ copy_reg_val_double();
+ for(j = 8; j < N; j += 8)
+ TEST3("saad", j, reg_val_double_copy, reg_val_double[j]);
+ break;
+ }
+ case LAA: { /* Load Atomic Add Word - laa rd, (base), rt. */
+ copy_reg_val_double();
+ for(j = 4; j < N; j += 4)
+ TEST4_32("laa", j, reg_val_double_copy);
+ break;
+ }
+ case LAAD: { /* Load Atomic Add Double - laad rd, (base), rt */
+ copy_reg_val_double();
+ for(j = 8; j < N; j += 8)
+ TEST4_64("laad ", j, reg_val_double_copy);
+ break;
+ }
+ case LAW: { /* Load Atomic Swap Word - law rd, (base), rt */
+ copy_reg_val_double();
+ for(j = 4; j < N; j += 4)
+ TEST4_32("law", j, reg_val_double_copy);
+ break;
+ }
+ case LAWD: { /* Load Atomic Swap Double - lawd rd, (base), rt */
+ copy_reg_val_double();
+ for(j = 8; j < N; j += 8)
+ TEST4_64("lawd", j, reg_val_double_copy);
+ break;
+ }
+ case LAI: { /* Load Atomic Increment Word - lai rd, (base) */
+ copy_reg_val_double();
+ for(i = 4; i < N; i += 4)
+ TEST1_32("lai", i, reg_val_double_copy);
+ break;
+ }
+ case LAID: { /* Load Atomic Increment Double - laid rd, (base) */
+ copy_reg_val_double();
+ for(i = 8; i < N; i += 8)
+ TEST1_64("laid ", i, reg_val_double_copy);
+ break;
+ }
+ case LAD: { /* Load Atomic Decrement Word - lad rd, (base) */
+ copy_reg_val_double();
+ for(i = 4; i < N; i += 4)
+ TEST1_32("lad", i, reg_val_double_copy);
+ break;
+ }
+ case LADD: { /* Load Atomic Decrement Double - ladd rd, (base) */
+ copy_reg_val_double();
+ for(i = 8; i < N; i += 8)
+ TEST1_64("ladd",i, reg_val_double_copy);
+ break;
+ }
+ case LAS:{ /* Load Atomic Set Word - las rd, (base) */
+ copy_reg_val_double();
+ for(i = 4; i < N; i += 4)
+ TEST1_32("las",i, reg_val_double_copy);
+ break;
+ }
+ case LASD:{ /* Load Atomic Set Word - lasd rd, (base) */
+ copy_reg_val_double();
+ for(i = 8; i < N; i += 8)
+ TEST1_64("lasd",i, reg_val_double_copy);
+ break;
+ }
+ case LAC: { /* Load Atomic Clear Word - lac rd, (base) */
+ copy_reg_val_double();
+ for(i = 4; i < N; i += 4)
+ TEST1_32("lac",i, reg_val_double_copy);
+ break;
+ }
+ case LACD: { /* Load Atomic Clear Double - lacd rd, (base) */
+ copy_reg_val_double();
+ for(i = 8; i < N; i += 8)
+ TEST1_64("lacd",i, reg_val_double_copy);
+ break;
+ }
+ default:
+ printf("Nothing to be executed \n");
+ }
+ }
+#endif
+ return 0;
+}
Added: trunk/none/tests/mips64/cvm_atomic.stderr.exp
==============================================================================
(empty)
Added: trunk/none/tests/mips64/cvm_atomic.stdout.exp-LE
==============================================================================
--- trunk/none/tests/mips64/cvm_atomic.stdout.exp-LE (added)
+++ trunk/none/tests/mips64/cvm_atomic.stdout.exp-LE Wed Jun 4 11:36:21 2014
@@ -0,0 +1,4721 @@
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x42b0c0a28677b502, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x42b0c0a28677b502, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x42b0c0a28677b502, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x42b0c0a28677b502, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x42b0c0a28677b502, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x42b0c0a28677b502, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42b0c0a28677b502, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42b0c0a28677b502, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x42b0c0a28677b502, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x42b0c0a28677b502, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x42b0c0a28677b502, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x42b0c0a28677b502, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x42b0c0a28677b502, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x42b0c0a28677b502, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x42b0c0a28677b502, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x42b0c0a28677b502, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x42b0c0a28677b502, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x42b0c0a28677b502, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x42b0c0a28677b502, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x42b0c0a28677b502, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x42b0c0a28677b502, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x42b0c0a28677b502, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x42b0c0a28677b502, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x42b0c0a28677b502, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x42b0c0a28677b502, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x42b0c0a28677b502, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x42b0c0a28677b502, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x42b0c0a28677b502, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x42b0c0a28677b502, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x42b0c0a28677b502, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0x42b0c0a28677b502, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x42b0c0a28677b502, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x42b0c0a28677b502, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x42b0c0a28677b502, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x42b0c0a28677b502, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x42b0c0a28677b502, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x42b0c0a28677b502, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x42b0c0a28677b502, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x42b0c0a28677b502, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x42b0c0a28677b502, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x42b0c0a28677b502, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x42b0c0a28677b502, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x42b0c0a28677b502, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x42b0c0a28677b502, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x42b0c0a28677b502, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x42b0c0a28677b502, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x42b0c0a28677b502, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x42b0c0a28677b502, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x42b0c0a28677b502, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x42b0c0a28677b502, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x42b0c0a28677b502, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x42b0c0a28677b502, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x42b0c0a28677b502, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x42b0c0a28677b502, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x42b0c0a28677b502, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x42b0c0a28677b502, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x9e705cc51ad8dca0, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x9e705cc51ad8dca0, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x9e705cc51ad8dca0, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x9e705cc51ad8dca0, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9e705cc51ad8dca0, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x9e705cc51ad8dca0, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x9e705cc51ad8dca0, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x9e705cc51ad8dca0, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x9e705cc51ad8dca0, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x9e705cc51ad8dca0, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x9e705cc51ad8dca0, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x9e705cc51ad8dca0, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0x9e705cc51ad8dca0, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x9e705cc51ad8dca0, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x9e705cc51ad8dca0, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x9e705cc51ad8dca0, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x9e705cc51ad8dca0, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x9e705cc51ad8dca0, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x9e705cc51ad8dca0, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x9e705cc51ad8dca0, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x9e705cc51ad8dca0, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x9e705cc51ad8dca0, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x9e705cc51ad8dca0, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x9e705cc51ad8dca0, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x9e705cc51ad8dca0, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x9e705cc51ad8dca0, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x9e705cc51ad8dca0, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x9e705cc51ad8dca0, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x9e705cc51ad8dca0, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x9e705cc51ad8dca0, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x9e705cc51ad8dca0, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x9e705cc51ad8dca0, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x9e705cc51ad8dca0, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x9e705cc51ad8dca0, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x9e705cc51ad8dca0, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x9e705cc51ad8dca0, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x9e705cc51ad8dca0, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x9e705cc51ad8dca0, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x9e705cc51ad8dca0, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x9e705cc51ad8dca0, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x9e705cc51ad8dca0, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x9e705cc51ad8dca0, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x9e705cc51ad8dca0, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x9e705cc51ad8dca0, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x9e705cc51ad8dca0, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x9e705cc51ad8dca0, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x9e705cc51ad8dca0, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x9e705cc51ad8dca0, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x9e705cc51ad8dca0, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x9e705cc51ad8dca0, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x9e705cc51ad8dca0, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x9e705cc51ad8dca0, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x9e705cc51ad8dca0, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x9e705cc51ad8dca0, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x9e705cc51ad8dca0, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x9e705cc51ad8dca0, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x9e705cc51ad8dca0, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x9e705cc51ad8dca0, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x9e705cc51ad8dca0, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x9e705cc51ad8dca0, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x47f505569a08a180, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x47f505569a08a180, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x47f505569a08a180, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x47f505569a08a180, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x47f505569a08a180, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x47f505569a08a180, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x47f505569a08a180, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x47f505569a08a180, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x47f505569a08a180, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x47f505569a08a180, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x47f505569a08a180, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x47f505569a08a180, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x47f505569a08a180, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x47f505569a08a180, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x47f505569a08a180, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x47f505569a08a180, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x47f505569a08a180, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x47f505569a08a180, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x47f505569a08a180, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x47f505569a08a180, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x47f505569a08a180, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x47f505569a08a180, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x47f505569a08a180, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x47f505569a08a180, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x47f505569a08a180, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x47f505569a08a180, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0x47f505569a08a180, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x47f505569a08a180, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x47f505569a08a180, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x47f505569a08a180, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x47f505569a08a180, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x47f505569a08a180, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x47f505569a08a180, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x47f505569a08a180, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x47f505569a08a180, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x47f505569a08a180, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x47f505569a08a180, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x47f505569a08a180, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x47f505569a08a180, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x47f505569a08a180, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x47f505569a08a180, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x47f505569a08a180, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x47f505569a08a180, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x47f505569a08a180, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x47f505569a08a180, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x47f505569a08a180, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x47f505569a08a180, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x47f505569a08a180, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x47f505569a08a180, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x47f505569a08a180, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x47f505569a08a180, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x47f505569a08a180, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x47f505569a08a180, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x47f505569a08a180, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x47f505569a08a180, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x47f505569a08a180, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x47f505569a08a180, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x47f505569a08a180, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x47f505569a08a180, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x47f505569a08a180, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x94ff52fc81afa797, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x94ff52fc81afa797, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x94ff52fc81afa797, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x94ff52fc81afa797, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x94ff52fc81afa797, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x94ff52fc81afa797, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x94ff52fc81afa797, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x94ff52fc81afa797, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x94ff52fc81afa797, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x94ff52fc81afa797, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x94ff52fc81afa797, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x94ff52fc81afa797, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x94ff52fc81afa797, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x94ff52fc81afa797, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x94ff52fc81afa797, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x94ff52fc81afa797, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x94ff52fc81afa797, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x94ff52fc81afa797, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x94ff52fc81afa797, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x94ff52fc81afa797, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x94ff52fc81afa797, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x94ff52fc81afa797, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x94ff52fc81afa797, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x94ff52fc81afa797, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x94ff52fc81afa797, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x94ff52fc81afa797, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x94ff52fc81afa797, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x94ff52fc81afa797, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x94ff52fc81afa797, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x94ff52fc81afa797, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x94ff52fc81afa797, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x94ff52fc81afa797, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x94ff52fc81afa797, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x94ff52fc81afa797, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x94ff52fc81afa797, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x94ff52fc81afa797, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x94ff52fc81afa797, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x94ff52fc81afa797, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x94ff52fc81afa797, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x94ff52fc81afa797, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x94ff52fc81afa797, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x94ff52fc81afa797, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x94ff52fc81afa797, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x94ff52fc81afa797, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x94ff52fc81afa797, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x94ff52fc81afa797, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x94ff52fc81afa797, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x94ff52fc81afa797, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x94ff52fc81afa797, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x94ff52fc81afa797, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x94ff52fc81afa797, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x94ff52fc81afa797, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x94ff52fc81afa797, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x94ff52fc81afa797, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x94ff52fc81afa797, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x94ff52fc81afa797, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x94ff52fc81afa797, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x94ff52fc81afa797, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xe9, rs 0x94ff52fc81afa797, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x94ff52fc81afa797, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x556b3ecaccf17ac5, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x556b3ecaccf17ac5, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x556b3ecaccf17ac5, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x556b3ecaccf17ac5, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x556b3ecaccf17ac5, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x556b3ecaccf17ac5, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x556b3ecaccf17ac5, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x556b3ecaccf17ac5, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x556b3ecaccf17ac5, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x556b3ecaccf17ac5, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x556b3ecaccf17ac5, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x556b3ecaccf17ac5, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x556b3ecaccf17ac5, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x556b3ecaccf17ac5, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x556b3ecaccf17ac5, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x556b3ecaccf17ac5, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x556b3ecaccf17ac5, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x556b3ecaccf17ac5, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x556b3ecaccf17ac5, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x556b3ecaccf17ac5, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x556b3ecaccf17ac5, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x556b3ecaccf17ac5, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x556b3ecaccf17ac5, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x556b3ecaccf17ac5, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x556b3ecaccf17ac5, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x556b3ecaccf17ac5, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x556b3ecaccf17ac5, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x556b3ecaccf17ac5, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x556b3ecaccf17ac5, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x556b3ecaccf17ac5, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x556b3ecaccf17ac5, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x556b3ecaccf17ac5, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x556b3ecaccf17ac5, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x556b3ecaccf17ac5, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x556b3ecaccf17ac5, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x556b3ecaccf17ac5, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0x556b3ecaccf17ac5, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x556b3ecaccf17ac5, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x556b3ecaccf17ac5, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x556b3ecaccf17ac5, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x556b3ecaccf17ac5, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x556b3ecaccf17ac5, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x556b3ecaccf17ac5, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x556b3ecaccf17ac5, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x556b3ecaccf17ac5, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x556b3ecaccf17ac5, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0x556b3ecaccf17ac5, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x556b3ecaccf17ac5, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x556b3ecaccf17ac5, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x556b3ecaccf17ac5, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x556b3ecaccf17ac5, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x556b3ecaccf17ac5, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x556b3ecaccf17ac5, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x556b3ecaccf17ac5, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x556b3ecaccf17ac5, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x556b3ecaccf17ac5, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x556b3ecaccf17ac5, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x556b3ecaccf17ac5, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x556b3ecaccf17ac5, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x556b3ecaccf17ac5, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x3c2cd9a9cda20766, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x3c2cd9a9cda20766, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x3c2cd9a9cda20766, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x3c2cd9a9cda20766, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x3c2cd9a9cda20766, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3c2cd9a9cda20766, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3c2cd9a9cda20766, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x3c2cd9a9cda20766, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x3c2cd9a9cda20766, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x3c2cd9a9cda20766, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x3c2cd9a9cda20766, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x3c2cd9a9cda20766, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x3c2cd9a9cda20766, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c2cd9a9cda20766, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x3c2cd9a9cda20766, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x3c2cd9a9cda20766, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x3c2cd9a9cda20766, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x3c2cd9a9cda20766, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x3c2cd9a9cda20766, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x3c2cd9a9cda20766, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x3c2cd9a9cda20766, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x3c2cd9a9cda20766, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3c2cd9a9cda20766, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x3c2cd9a9cda20766, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x3c2cd9a9cda20766, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x3c2cd9a9cda20766, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x3c2cd9a9cda20766, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x3c2cd9a9cda20766, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x3c2cd9a9cda20766, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x3c2cd9a9cda20766, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x3c2cd9a9cda20766, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x3c2cd9a9cda20766, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x3c2cd9a9cda20766, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x3c2cd9a9cda20766, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3c2cd9a9cda20766, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x3c2cd9a9cda20766, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x3c2cd9a9cda20766, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x3c2cd9a9cda20766, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x3c2cd9a9cda20766, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x3c2cd9a9cda20766, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x3c2cd9a9cda20766, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x3c2cd9a9cda20766, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x3c2cd9a9cda20766, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x3c2cd9a9cda20766, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x3c2cd9a9cda20766, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c2cd9a9cda20766, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x3c2cd9a9cda20766, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x3c2cd9a9cda20766, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x3c2cd9a9cda20766, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x3c2cd9a9cda20766, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x3c2cd9a9cda20766, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x3c2cd9a9cda20766, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x3c2cd9a9cda20766, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x3c2cd9a9cda20766, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x3c2cd9a9cda20766, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x3c2cd9a9cda20766, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x3c2cd9a9cda20766, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x3c2cd9a9cda20766, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x3c2cd9a9cda20766, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3c2cd9a9cda20766, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0xd0d070db710cd036, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xd0d070db710cd036, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xd0d070db710cd036, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xd0d070db710cd036, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0xd0d070db710cd036, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xd0d070db710cd036, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xd0d070db710cd036, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xd0d070db710cd036, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xd0d070db710cd036, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xd0d070db710cd036, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xd0d070db710cd036, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xd0d070db710cd036, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xd0d070db710cd036, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd0d070db710cd036, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xd0d070db710cd036, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xd0d070db710cd036, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xd0d070db710cd036, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0xd0d070db710cd036, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xd0d070db710cd036, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xd0d070db710cd036, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xd0d070db710cd036, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xd0d070db710cd036, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xd0d070db710cd036, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xd0d070db710cd036, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xd0d070db710cd036, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xd0d070db710cd036, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xd0d070db710cd036, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xd0d070db710cd036, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0xd0d070db710cd036, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xd0d070db710cd036, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xd0d070db710cd036, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xd0d070db710cd036, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xd0d070db710cd036, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xd0d070db710cd036, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xd0d070db710cd036, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0xd0d070db710cd036, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xd0d070db710cd036, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd0d070db710cd036, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xd0d070db710cd036, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0xd0d070db710cd036, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xd0d070db710cd036, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd0d070db710cd036, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xd0d070db710cd036, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xd0d070db710cd036, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xd0d070db710cd036, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd0d070db710cd036, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xd0d070db710cd036, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xd0d070db710cd036, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xd0d070db710cd036, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xd0d070db710cd036, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xd0d070db710cd036, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xd0d070db710cd036, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xd0d070db710cd036, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd0d070db710cd036, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xd0d070db710cd036, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xd0d070db710cd036, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xd0d070db710cd036, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0xd0d070db710cd036, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xd0d070db710cd036, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xd0d070db710cd036, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x2f39454412d6e4a7, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x2f39454412d6e4a7, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x2f39454412d6e4a7, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x2f39454412d6e4a7, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x2f39454412d6e4a7, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x2f39454412d6e4a7, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x2f39454412d6e4a7, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x2f39454412d6e4a7, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x2f39454412d6e4a7, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x2f39454412d6e4a7, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x2f39454412d6e4a7, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x2f39454412d6e4a7, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x2f39454412d6e4a7, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2f39454412d6e4a7, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x2f39454412d6e4a7, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x2f39454412d6e4a7, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x2f39454412d6e4a7, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x2f39454412d6e4a7, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x2f39454412d6e4a7, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x2f39454412d6e4a7, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x2f39454412d6e4a7, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x2f39454412d6e4a7, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x2f39454412d6e4a7, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x2f39454412d6e4a7, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x2f39454412d6e4a7, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x2f39454412d6e4a7, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x2f39454412d6e4a7, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x2f39454412d6e4a7, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x2f39454412d6e4a7, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x2f39454412d6e4a7, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x2f39454412d6e4a7, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x2f39454412d6e4a7, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x2f39454412d6e4a7, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x2f39454412d6e4a7, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x2f39454412d6e4a7, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x2f39454412d6e4a7, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x2f39454412d6e4a7, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x2f39454412d6e4a7, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x2f39454412d6e4a7, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x2f39454412d6e4a7, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x2f39454412d6e4a7, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x2f39454412d6e4a7, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x2f39454412d6e4a7, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x2f39454412d6e4a7, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x2f39454412d6e4a7, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2f39454412d6e4a7, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x2f39454412d6e4a7, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x2f39454412d6e4a7, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x2f39454412d6e4a7, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x2f39454412d6e4a7, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x2f39454412d6e4a7, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x2f39454412d6e4a7, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x2f39454412d6e4a7, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x2f39454412d6e4a7, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x2f39454412d6e4a7, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x2f39454412d6e4a7, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x2f39454412d6e4a7, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x2f39454412d6e4a7, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x2f39454412d6e4a7, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x2f39454412d6e4a7, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0xed5005cbc8b0a214, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xed5005cbc8b0a214, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xed5005cbc8b0a214, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xed5005cbc8b0a214, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xed5005cbc8b0a214, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xed5005cbc8b0a214, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xed5005cbc8b0a214, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0xed5005cbc8b0a214, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xed5005cbc8b0a214, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xed5005cbc8b0a214, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0xed5005cbc8b0a214, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xed5005cbc8b0a214, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0xed5005cbc8b0a214, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xed5005cbc8b0a214, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0xed5005cbc8b0a214, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xed5005cbc8b0a214, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xed5005cbc8b0a214, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xed5005cbc8b0a214, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xed5005cbc8b0a214, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xed5005cbc8b0a214, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xed5005cbc8b0a214, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0xed5005cbc8b0a214, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xed5005cbc8b0a214, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xed5005cbc8b0a214, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xed5005cbc8b0a214, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xed5005cbc8b0a214, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xed5005cbc8b0a214, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xed5005cbc8b0a214, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xed5005cbc8b0a214, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xed5005cbc8b0a214, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xed5005cbc8b0a214, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xed5005cbc8b0a214, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xed5005cbc8b0a214, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xed5005cbc8b0a214, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xed5005cbc8b0a214, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xed5005cbc8b0a214, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xed5005cbc8b0a214, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0xed5005cbc8b0a214, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xed5005cbc8b0a214, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xed5005cbc8b0a214, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xed5005cbc8b0a214, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0xed5005cbc8b0a214, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xed5005cbc8b0a214, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xed5005cbc8b0a214, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0xed5005cbc8b0a214, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xed5005cbc8b0a214, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xed5005cbc8b0a214, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xed5005cbc8b0a214, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xed5005cbc8b0a214, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xed5005cbc8b0a214, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0xed5005cbc8b0a214, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xed5005cbc8b0a214, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xed5005cbc8b0a214, rt 0xf2e7a490978058f3
+bad...
[truncated message content] |
|
From: <sv...@va...> - 2014-06-04 11:28:26
|
Author: dejanj
Date: Wed Jun 4 11:28:07 2014
New Revision: 2865
Log:
mips64: Support for Cavium MIPS Octeon Atomic and Count Instructions.
Implement Cavium MIPS specific instructions:
baddu, pop, dpop, saa, saad, laa, laad, lai, laid, lad, ladd, law, lawd,
las, lasd, lac, lacd
Fixes BZ #327223.
Modified:
trunk/priv/guest_mips_toIR.c
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_defs.h
trunk/priv/host_mips_isel.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Wed Jun 4 11:28:07 2014
@@ -2170,6 +2170,62 @@
/*********************************************************/
/*--- Cavium Specific Instructions ---*/
/*********************************************************/
+
+/* Convenience function to yield to thread scheduler */
+static void jump_back(IRExpr *condition)
+{
+ stmt( IRStmt_Exit(condition,
+ Ijk_Yield,
+ IRConst_U64( guest_PC_curr_instr ),
+ OFFB_PC) );
+}
+
+/* Based on s390_irgen_load_and_add32. */
+static void mips_irgen_load_and_add32(IRTemp op1addr, IRTemp new_val,
+ UChar rd, Bool putIntoRd)
+{
+ IRCAS *cas;
+ IRTemp old_mem = newTemp(Ity_I32);
+ IRTemp expd = newTemp(Ity_I32);
+
+ assign(expd, load(Ity_I32, mkexpr(op1addr)));
+
+ cas = mkIRCAS(IRTemp_INVALID, old_mem,
+ Iend_LE, mkexpr(op1addr),
+ NULL, mkexpr(expd), /* expected value */
+ NULL, mkexpr(new_val) /* new value */);
+ stmt(IRStmt_CAS(cas));
+
+ /* If old_mem contains the expected value, then the CAS succeeded.
+ Otherwise, it did not */
+ jump_back(binop(Iop_CmpNE32, mkexpr(old_mem), mkexpr(expd)));
+ if (putIntoRd)
+ putIReg(rd, mkWidenFrom32(Ity_I64, mkexpr(old_mem), True));
+}
+
+/* Based on s390_irgen_load_and_add64. */
+static void mips_irgen_load_and_add64(IRTemp op1addr, IRTemp new_val,
+ UChar rd, Bool putIntoRd)
+{
+ IRCAS *cas;
+ IRTemp old_mem = newTemp(Ity_I64);
+ IRTemp expd = newTemp(Ity_I64);
+
+ assign(expd, load(Ity_I64, mkexpr(op1addr)));
+
+ cas = mkIRCAS(IRTemp_INVALID, old_mem,
+ Iend_LE, mkexpr(op1addr),
+ NULL, mkexpr(expd), /* expected value */
+ NULL, mkexpr(new_val) /* new value */);
+ stmt(IRStmt_CAS(cas));
+
+ /* If old_mem contains the expected value, then the CAS succeeded.
+ Otherwise, it did not */
+ jump_back(binop(Iop_CmpNE64, mkexpr(old_mem), mkexpr(expd)));
+ if (putIntoRd)
+ putIReg(rd, mkexpr(old_mem));
+}
+
static Bool dis_instr_CVM ( UInt theInstr )
{
UChar opc2 = get_function(theInstr);
@@ -2177,7 +2233,7 @@
UChar regRs = get_rs(theInstr);
UChar regRt = get_rt(theInstr);
UChar regRd = get_rd(theInstr);
- UInt imm = get_imm(theInstr);
+ UInt imm = get_imm(theInstr);
UChar lenM1 = get_msb(theInstr);
UChar p = get_lsb(theInstr);
IRType ty = mode64? Ity_I64 : Ity_I32;
@@ -2188,8 +2244,8 @@
UInt size;
assign(tmpRs, getIReg(regRs));
- switch(opc1){
- case 0x1C: {
+ switch(opc1) {
+ case 0x1C: {
switch(opc2) {
case 0x03: { /* DMUL rd, rs, rt */
DIP("dmul r%d, r%d, r%d", regRd, regRs, regRt);
@@ -2199,6 +2255,277 @@
break;
}
+ case 0x18: { /* Store Atomic Add Word - SAA; Cavium OCTEON */
+ DIP("saa r%u, (r%u)", regRt, regRs);
+ IRTemp addr = newTemp(Ity_I64);
+ IRTemp new = newTemp(Ity_I32);
+ assign (addr, getIReg(regRs));
+ assign(new, binop(Iop_Add32,
+ load(Ity_I32, mkexpr(addr)),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_irgen_load_and_add32(addr, new, 0, False);
+ break;
+ }
+
+ /* Store Atomic Add Doubleword - SAAD; Cavium OCTEON */
+ case 0x19: {
+ DIP( "saad r%u, (r%u)", regRt, regRs);
+ IRTemp addr = newTemp(Ity_I64);
+ IRTemp new = newTemp(Ity_I64);
+ assign (addr, getIReg(regRs));
+ assign(new, binop(Iop_Add64,
+ load(Ity_I64, mkexpr(addr)),
+ getIReg(regRt)));
+ mips_irgen_load_and_add64(addr, new, 0, False);
+ break;
+ }
+
+ /* LAI, LAID, LAD, LADD, LAS, LASD,
+ LAC, LACD, LAA, LAAD, LAW, LAWD */
+ case 0x1f: {
+ UInt opc3 = get_sa(theInstr);
+ IRTemp addr = newTemp(Ity_I64);
+ switch (opc3) {
+ /* Load Atomic Increment Word - LAI; Cavium OCTEON2 */
+ case 0x02: {
+ DIP("lai r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new, binop(Iop_Add32,
+ load(Ity_I32, mkexpr(addr)),
+ mkU32(1)));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Increment Doubleword - LAID; Cavium OCTEON2 */
+ case 0x03: {
+ DIP("laid r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(new, binop(Iop_Add64,
+ load(Ity_I64, mkexpr(addr)),
+ mkU64(1)));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Decrement Word - LAD; Cavium OCTEON2 */
+ case 0x06: {
+ DIP("lad r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new, binop(Iop_Sub32,
+ load(Ity_I32, mkexpr(addr)),
+ mkU32(1)));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Decrement Doubleword - LADD; Cavium OCTEON2 */
+ case 0x07: {
+ DIP("ladd r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I64);
+ assign (addr, getIReg(regRs));
+ assign(new, binop(Iop_Sub64,
+ load(Ity_I64, mkexpr(addr)),
+ mkU64(1)));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Set Word - LAS; Cavium OCTEON2 */
+ case 0x0a: {
+ DIP("las r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new, mkU32(0xffffffff));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Set Doubleword - LASD; Cavium OCTEON2 */
+ case 0x0b: {
+ DIP("lasd r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I64);
+ assign (addr, getIReg(regRs));
+ assign(new, mkU64(0xffffffffffffffff));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Clear Word - LAC; Cavium OCTEON2 */
+ case 0x0e: {
+ DIP("lac r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I32);
+ assign (addr, getIReg(regRs));
+ assign(new, mkU32(0));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Clear Doubleword - LACD; Cavium OCTEON2 */
+ case 0x0f: {
+ DIP("lacd r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(new, mkU64(0));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Add Word - LAA; Cavium OCTEON2 */
+ case 0x12: {
+ DIP("laa r%u,(r%u),r%u\n", regRd, regRs, regRt);
+ IRTemp new = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new, binop(Iop_Add32,
+ load(Ity_I32, mkexpr(addr)),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Add Doubleword - LAAD; Cavium OCTEON2 */
+ case 0x13: {
+ DIP("laad r%u,(r%u),r%u\n", regRd, regRs, regRt);
+ IRTemp new = newTemp(Ity_I64);
+ assign (addr, getIReg(regRs));
+ assign(new, binop(Iop_Add64,
+ load(Ity_I64, mkexpr(addr)),
+ getIReg(regRt)));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Swap Word - LAW; Cavium OCTEON2 */
+ case 0x16: {
+ DIP("law r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new, mkNarrowTo32(ty, getIReg(regRt)));
+ mips_irgen_load_and_add32(addr, new, regRd, True);
+ break;
+ }
+ /* Load Atomic Swap Doubleword - LAWD; Cavium OCTEON2 */
+ case 0x17: {
+ DIP("lawd r%u,(r%u)\n", regRd, regRs);
+ IRTemp new = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(new, getIReg(regRt));
+ mips_irgen_load_and_add64(addr, new, regRd, True);
+ break;
+ }
+ default:
+ vex_printf("Unknown laxx instruction, opc3=0x%x\n", opc3);
+ vex_printf("Instruction=0x%08x\n", theInstr);
+ return False;
+ }
+ break;
+ }
+
+ /* Unsigned Byte Add - BADDU rd, rs, rt; Cavium OCTEON */
+ case 0x28: {
+ DIP("BADDU r%d, r%d, r%d", regRs, regRt, regRd);
+ IRTemp t0 = newTemp(Ity_I8);
+
+ assign(t0, binop(Iop_Add8,
+ mkNarrowTo8(ty, getIReg(regRs)),
+ mkNarrowTo8(ty, getIReg(regRt))));
+
+ if (mode64)
+ putIReg(regRd, binop(mkSzOp(ty, Iop_And8),
+ unop(Iop_8Uto64, mkexpr(t0)),
+ mkSzImm(ty, 0xFF)));
+ else
+ putIReg(regRd, binop(mkSzOp(ty, Iop_And8),
+ unop(Iop_8Uto32, mkexpr(t0)),
+ mkSzImm(ty, 0xFF)));
+ break;
+ }
+
+ case 0x2c: { /* Count Ones in a Word - POP; Cavium OCTEON */
+ int i, shift[5];
+ IRTemp mask[5];
+ IRTemp old = newTemp(ty);
+ IRTemp nyu = IRTemp_INVALID;
+ assign(old, getIReg(regRs));
+ DIP("pop r%d, r%d", regRd, regRs);
+
+ for (i = 0; i < 5; i++) {
+ mask[i] = newTemp(ty);
+ shift[i] = 1 << i;
+ }
+ if(mode64) {
+ assign(mask[0], mkU64(0x0000000055555555));
+ assign(mask[1], mkU64(0x0000000033333333));
+ assign(mask[2], mkU64(0x000000000F0F0F0F));
+ assign(mask[3], mkU64(0x0000000000FF00FF));
+ assign(mask[4], mkU64(0x000000000000FFFF));
+
+ for (i = 0; i < 5; i++) {
+ nyu = newTemp(ty);
+ assign(nyu,
+ binop(Iop_Add64,
+ binop(Iop_And64,
+ mkexpr(old), mkexpr(mask[i])),
+ binop(Iop_And64,
+ binop(Iop_Shr64,
+ mkexpr(old), mkU8(shift[i])),
+ mkexpr(mask[i]))));
+ old = nyu;
+ }
+ } else {
+ assign(mask[0], mkU32(0x55555555));
+ assign(mask[1], mkU32(0x33333333));
+ assign(mask[2], mkU32(0x0F0F0F0F));
+ assign(mask[3], mkU32(0x00FF00FF));
+ assign(mask[4], mkU32(0x0000FFFF));
+ assign(old, getIReg(regRs));
+
+ for (i = 0; i < 5; i++) {
+ nyu = newTemp(ty);
+ assign(nyu,
+ binop(Iop_Add32,
+ binop(Iop_And32,
+ mkexpr(old), mkexpr(mask[i])),
+ binop(Iop_And32,
+ binop(Iop_Shr32,
+ mkexpr(old), mkU8(shift[i])),
+ mkexpr(mask[i]))));
+ old = nyu;
+ }
+ }
+ putIReg(regRd, mkexpr(nyu));
+ break;
+ }
+
+ /* Count Ones in a Doubleword - DPOP; Cavium OCTEON */
+ case 0x2d: {
+ int i, shift[6];
+ IRTemp mask[6];
+ IRTemp old = newTemp(ty);
+ IRTemp nyu = IRTemp_INVALID;
+ DIP("dpop r%d, r%d", regRd, regRs);
+
+ for (i = 0; i < 6; i++) {
+ mask[i] = newTemp(ty);
+ shift[i] = 1 << i;
+ }
+ vassert(mode64); /*Caution! Only for Mode 64*/
+ assign(mask[0], mkU64(0x5555555555555555ULL));
+ assign(mask[1], mkU64(0x3333333333333333ULL));
+ assign(mask[2], mkU64(0x0F0F0F0F0F0F0F0FULL));
+ assign(mask[3], mkU64(0x00FF00FF00FF00FFULL));
+ assign(mask[4], mkU64(0x0000FFFF0000FFFFULL));
+ assign(mask[5], mkU64(0x00000000FFFFFFFFULL));
+ assign(old, getIReg(regRs));
+ for (i = 0; i < 6; i++) {
+ nyu = newTemp(Ity_I64);
+ assign(nyu,
+ binop(Iop_Add64,
+ binop(Iop_And64,
+ mkexpr(old), mkexpr(mask[i])),
+ binop(Iop_And64,
+ binop(Iop_Shr64,
+ mkexpr(old), mkU8(shift[i])),
+ mkexpr(mask[i]))));
+ old = nyu;
+ }
+ putIReg(regRd, mkexpr(nyu));
+ break;
+ }
+
case 0x32: /* 5. CINS rd, rs, p, lenm1 */
DIP("cins r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1);
assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs),
@@ -2291,7 +2618,7 @@
}
break;
} /* opc1 0x1C ends here*/
- case 0x1F:{
+ case 0x1F: {
switch(opc2) {
case 0x0A: { // lx - Load indexed instructions
switch (get_sa(theInstr)) {
@@ -14120,34 +14447,40 @@
case 0x1C: /* Special2 */
switch (function) {
- /* Cavium Specific instructions */
- case 0x03: case 0x32: case 0x33: /* DMUL, CINS , CINS32 */
- case 0x3A: case 0x3B: case 0x2B: /* EXT, EXT32, SNE */
- /* CVM Compare Instructions */
- case 0x2A: case 0x2E: case 0x2F: /* SEQ, SEQI, SNEI */
- if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) {
- if (dis_instr_CVM(cins))
- break;
- goto decode_failure;
- } else {
- goto decode_failure;
- }
+ /* Cavium Specific instructions */
+ case 0x03: case 0x32: case 0x33: /* DMUL, CINS , CINS32 */
+ case 0x3A: case 0x3B: case 0x2B: /* EXT, EXT32, SNE */
+ /* CVM Compare Instructions */
+ case 0x2A: case 0x2E: case 0x2F: /* SEQ, SEQI, SNEI */
+ /* CPU Load, Store, Memory, and Control Instructions */
+ case 0x18: case 0x19: /* SAA, SAAD */
+ case 0x1F: /* LAA, LAAD, LAI, LAID */
+ case 0x28: case 0x2C: case 0x2D: /* BADDU, POP, DPOP */
+ if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) {
+ if (dis_instr_CVM(cins))
+ break;
+ goto decode_failure;
+ } else {
+ goto decode_failure;
+ }
break;
- case 0x02: { /* MUL */
- DIP("mul r%d, r%d, r%d", rd, rs, rt);
- if (mode64) {
- IRTemp tmpRs32 = newTemp(Ity_I32);
- IRTemp tmpRt32 = newTemp(Ity_I32);
- IRTemp tmpRes = newTemp(Ity_I32);
- assign(tmpRs32, mkNarrowTo32(ty, getIReg(rs)));
- assign(tmpRt32, mkNarrowTo32(ty, getIReg(rt)));
- assign(tmpRes, binop(Iop_Mul32, mkexpr(tmpRs32), mkexpr(tmpRt32)));
- putIReg(rd, mkWidenFrom32(ty, mkexpr(tmpRes), True));
- } else
- putIReg(rd, binop(Iop_Mul32, getIReg(rs), getIReg(rt)));
- break;
- }
+ case 0x02: { /* MUL */
+ DIP("mul r%d, r%d, r%d", rd, rs, rt);
+ if (mode64) {
+ IRTemp tmpRs32 = newTemp(Ity_I32);
+ IRTemp tmpRt32 = newTemp(Ity_I32);
+ IRTemp tmpRes = newTemp(Ity_I32);
+
+ assign(tmpRs32, mkNarrowTo32(ty, getIReg(rs)));
+ assign(tmpRt32, mkNarrowTo32(ty, getIReg(rt)));
+ assign(tmpRes, binop(Iop_Mul32,
+ mkexpr(tmpRs32), mkexpr(tmpRt32)));
+ putIReg(rd, mkWidenFrom32(ty, mkexpr(tmpRes), True));
+ } else
+ putIReg(rd, binop(Iop_Mul32, getIReg(rs), getIReg(rt)));
+ break;
+ }
case 0x00: { /* MADD */
if (mode64) {
Modified: trunk/priv/host_mips_defs.c
==============================================================================
--- trunk/priv/host_mips_defs.c (original)
+++ trunk/priv/host_mips_defs.c Wed Jun 4 11:28:07 2014
@@ -1399,6 +1399,23 @@
return i;
}
+MIPSInstr *MIPSInstr_Cas(UChar sz, HReg old, HReg addr,
+ HReg expd, HReg data, Bool mode64)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Cas;
+ i->Min.Cas.sz = sz;
+ i->Min.Cas.old = old;
+ i->Min.Cas.addr = addr;
+ i->Min.Cas.expd = expd;
+ i->Min.Cas.data = data;
+ vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
+
+ if (sz == 8)
+ vassert(mode64);
+ return i;
+}
+
MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
{
MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
@@ -1777,6 +1794,55 @@
ppMIPSAMode(i->Min.LoadL.src, mode64);
return;
}
+ case Min_Cas: {
+ Bool sz8 = toBool(i->Min.Cas.sz == 8);
+ /*
+ * ll(d) old, 0(addr)
+ * bne old, expd, end
+ * nop
+ * (d)addiu old, old, 1
+ * sc(d) data, 0(addr)
+ * movn old, expd, data
+ * end:
+ */
+ // ll(d) old, 0(addr)
+ vex_printf("cas: ");
+
+ vex_printf("%s ", sz8 ? "lld" : "ll");
+ ppHRegMIPS(i->Min.Cas.old , mode64);
+ vex_printf(", 0(");
+ ppHRegMIPS(i->Min.Cas.addr , mode64);
+ vex_printf(")\n");
+
+ vex_printf("bne ");
+ ppHRegMIPS(i->Min.Cas.old , mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Cas.expd , mode64);
+ vex_printf(", end\n");
+
+ vex_printf("nop\n");
+
+ vex_printf("%s ", sz8 ? "daddiu" : "addiu");
+ ppHRegMIPS(i->Min.Cas.old , mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Cas.old , mode64);
+ vex_printf(", 1\n");
+
+ vex_printf("%s ", sz8 ? "scd" : "sc");
+ ppHRegMIPS(i->Min.Cas.data , mode64);
+ vex_printf(", 0(");
+ ppHRegMIPS(i->Min.Cas.addr , mode64);
+ vex_printf(")\n");
+
+ vex_printf("movn ");
+ ppHRegMIPS(i->Min.Cas.old , mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Cas.expd , mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Cas.data , mode64);
+ vex_printf("\nend:");
+ return;
+ }
case Min_StoreC: {
vex_printf("sc ");
ppHRegMIPS(i->Min.StoreC.src, mode64);
@@ -2062,6 +2128,12 @@
addRegUsage_MIPSAMode(u, i->Min.LoadL.src);
addHRegUse(u, HRmWrite, i->Min.LoadL.dst);
return;
+ case Min_Cas:
+ addHRegUse(u, HRmWrite, i->Min.Cas.old);
+ addHRegUse(u, HRmRead, i->Min.Cas.addr);
+ addHRegUse(u, HRmRead, i->Min.Cas.expd);
+ addHRegUse(u, HRmModify, i->Min.Cas.data);
+ return;
case Min_StoreC:
addHRegUse(u, HRmWrite, i->Min.StoreC.src);
addHRegUse(u, HRmRead, i->Min.StoreC.src);
@@ -2214,6 +2286,12 @@
mapRegs_MIPSAMode(m, i->Min.LoadL.src);
mapReg(m, &i->Min.LoadL.dst);
return;
+ case Min_Cas:
+ mapReg(m, &i->Min.Cas.old);
+ mapReg(m, &i->Min.Cas.addr);
+ mapReg(m, &i->Min.Cas.expd);
+ mapReg(m, &i->Min.Cas.data);
+ return;
case Min_StoreC:
mapReg(m, &i->Min.StoreC.src);
mapRegs_MIPSAMode(m, i->Min.StoreC.dst);
@@ -3459,8 +3537,8 @@
switch (i->Min.XAssisted.jk) {
case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
- /* case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break;
- case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; */
+ /* case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; */
+ case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
/* case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; */
@@ -3646,6 +3724,39 @@
p = mkFormI(p, 0x3C, r_dst, r_src, idx);
goto done;
}
+ case Min_Cas: {
+ if (i->Min.Cas.sz != 8 && i->Min.Cas.sz != 4)
+ goto bad;
+ UInt old = iregNo(i->Min.Cas.old, mode64);
+ UInt addr = iregNo(i->Min.Cas.addr, mode64);
+ UInt expd = iregNo(i->Min.Cas.expd, mode64);
+ UInt data = iregNo(i->Min.Cas.data, mode64);
+ Bool sz8 = toBool(i->Min.Cas.sz == 8);
+
+ /*
+ * ll(d) old, 0(addr)
+ * bne old, expd, end
+ * nop
+ * (d)addiu old, old, 1
+ * sc(d) data, 0(addr)
+ * movn old, expd, data
+ * end:
+ */
+ // ll(d) old, 0(addr)
+ p = mkFormI(p, sz8 ? 0x34 : 0x30, addr, old, 0);
+ // bne old, expd, end
+ p = mkFormI(p, 5, old, expd, 4);
+ // nop
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ // (d)addiu old, old, 1
+ p = mkFormI(p, sz8 ? 25 : 9, old, old, 1);
+ // sc(d) data, 0(addr)
+ p = mkFormI(p, sz8 ? 0x3C : 0x38, addr, data, 0);
+ // movn old, expd, data
+ p = mkFormR(p, 0, expd, data, old, 0, 0xb);
+
+ goto done;
+ }
case Min_RdWrLR: {
UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
Bool wrLR = i->Min.RdWrLR.wrLR;
Modified: trunk/priv/host_mips_defs.h
==============================================================================
--- trunk/priv/host_mips_defs.h (original)
+++ trunk/priv/host_mips_defs.h Wed Jun 4 11:28:07 2014
@@ -325,6 +325,7 @@
Min_Load, /* zero-extending load a 8|16|32 bit value from mem */
Min_Store, /* store a 8|16|32 bit value to mem */
+ Min_Cas, /* compare and swap */
Min_LoadL, /* mips Load Linked Word - LL */
Min_StoreC, /* mips Store Conditional Word - SC */
@@ -521,6 +522,13 @@
} LoadL;
struct {
UChar sz; /* 4|8 */
+ HReg old;
+ HReg addr;
+ HReg expd;
+ HReg data;
+ } Cas;
+ struct {
+ UChar sz; /* 4|8 */
MIPSAMode *dst;
HReg src;
} StoreC;
@@ -649,6 +657,8 @@
Bool mode64);
extern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src,
Bool mode64);
+extern MIPSInstr *MIPSInstr_Cas(UChar sz, HReg old, HReg addr,
+ HReg expd, HReg data, Bool mode64);
extern MIPSInstr *MIPSInstr_Call ( MIPSCondCode, Addr64, UInt, HReg, RetLoc );
extern MIPSInstr *MIPSInstr_CallAlways ( MIPSCondCode, Addr64, UInt, RetLoc );
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Wed Jun 4 11:28:07 2014
@@ -971,7 +971,9 @@
|| e->Iex.Binop.op == Iop_CmpLE32S
|| e->Iex.Binop.op == Iop_CmpLE64S
|| e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpEQ64) {
+ || e->Iex.Binop.op == Iop_CmpEQ64
+ || e->Iex.Binop.op == Iop_CasCmpEQ32
+ || e->Iex.Binop.op == Iop_CasCmpEQ64) {
Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
|| e->Iex.Binop.op == Iop_CmpLE32S
@@ -986,6 +988,7 @@
switch (e->Iex.Binop.op) {
case Iop_CmpEQ32:
+ case Iop_CasCmpEQ32:
cc = MIPScc_EQ;
size32 = True;
break;
@@ -1030,6 +1033,7 @@
size32 = False;
break;
case Iop_CmpEQ64:
+ case Iop_CasCmpEQ64:
cc = MIPScc_EQ;
size32 = False;
break;
@@ -2051,7 +2055,9 @@
|| e->Iex.Binop.op == Iop_CmpLE32S
|| e->Iex.Binop.op == Iop_CmpLE64S
|| e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpEQ64) {
+ || e->Iex.Binop.op == Iop_CmpEQ64
+ || e->Iex.Binop.op == Iop_CasCmpEQ32
+ || e->Iex.Binop.op == Iop_CasCmpEQ64) {
Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
|| e->Iex.Binop.op == Iop_CmpLE32S
@@ -2066,6 +2072,7 @@
switch (e->Iex.Binop.op) {
case Iop_CmpEQ32:
+ case Iop_CasCmpEQ32:
cc = MIPScc_EQ;
size32 = True;
break;
@@ -2102,6 +2109,7 @@
size32 = False;
break;
case Iop_CmpEQ64:
+ case Iop_CasCmpEQ64:
cc = MIPScc_EQ;
size32 = False;
break;
@@ -3933,6 +3941,20 @@
goto stmt_fail;
/* NOTREACHED */}
+ case Ist_CAS:
+ if (stmt->Ist.CAS.details->oldHi == IRTemp_INVALID) {
+ IRCAS *cas = stmt->Ist.CAS.details;
+ HReg old = lookupIRTemp(env, cas->oldLo);
+ HReg addr = iselWordExpr_R(env, cas->addr);
+ HReg expd = iselWordExpr_R(env, cas->expdLo);
+ HReg data = iselWordExpr_R(env, cas->dataLo);
+ if (typeOfIRTemp(env->type_env, cas->oldLo) == Ity_I64) {
+ addInstr(env, MIPSInstr_Cas(8, old, addr, expd, data, mode64));
+ } else if (typeOfIRTemp(env->type_env, cas->oldLo) == Ity_I32) {
+ addInstr(env, MIPSInstr_Cas(4, old, addr, expd, data, mode64));
+ }
+ }
+
/* --------- INSTR MARK --------- */
/* Doesn't generate any executable code ... */
case Ist_IMark:
@@ -3997,6 +4019,7 @@
case Ijk_NoDecode:
case Ijk_NoRedir:
case Ijk_SigBUS:
+ case Ijk_Yield:
case Ijk_SigTRAP:
case Ijk_SigFPE_IntDiv:
case Ijk_SigFPE_IntOvf:
|
|
From: <sv...@va...> - 2014-06-04 11:20:42
|
Author: sewardj
Date: Wed Jun 4 11:20:18 2014
New Revision: 13993
Log:
Make each test disable-able, and enable tests of instructions that are
currently supported.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Wed Jun 4 11:20:18 2014
@@ -2926,48 +2926,48 @@
// fabs d,s
// fabs 2d,4s,2s
- test_fabs_d_d(TyDF);
- test_fabs_s_s(TySF);
- test_fabs_2d_2d(TyDF);
- test_fabs_4s_4s(TySF);
- test_fabs_2s_2s(TyDF);
- test_fneg_2d_2d(TySF);
- test_fneg_4s_4s(TyDF);
- test_fneg_2s_2s(TySF);
+ if (1) test_fabs_d_d(TyDF);
+ if (1) test_fabs_s_s(TySF);
+ if (1) test_fabs_2d_2d(TyDF);
+ if (1) test_fabs_4s_4s(TySF);
+ if (1) test_fabs_2s_2s(TyDF);
+ if (1) test_fneg_2d_2d(TySF);
+ if (1) test_fneg_4s_4s(TyDF);
+ if (1) test_fneg_2s_2s(TySF);
// fneg d,s
// fneg 2d,4s,2s
- test_fneg_d_d(TyDF);
- test_fneg_s_s(TySF);
+ if (1) test_fneg_d_d(TyDF);
+ if (1) test_fneg_s_s(TySF);
// fsqrt d,s
// fsqrt 2d,4s,2s
- test_fsqrt_d_d(TyDF);
- test_fsqrt_s_s(TySF);
+ if (1) test_fsqrt_d_d(TyDF);
+ if (1) test_fsqrt_s_s(TySF);
// fadd d,s
// fsub d,s
- test_fadd_d_d_d(TyDF);
- test_fadd_s_s_s(TySF);
- test_fsub_d_d_d(TyDF);
- test_fsub_s_s_s(TySF);
+ if (1) test_fadd_d_d_d(TyDF);
+ if (1) test_fadd_s_s_s(TySF);
+ if (1) test_fsub_d_d_d(TyDF);
+ if (1) test_fsub_s_s_s(TySF);
// fadd 2d,4s,2s
// fsub 2d,4s,2s
- test_fadd_2d_2d_2d(TyDF);
- test_fadd_4s_4s_4s(TySF);
- test_fadd_2s_2s_2s(TySF);
- test_fsub_2d_2d_2d(TyDF);
- test_fsub_4s_4s_4s(TySF);
- test_fsub_2s_2s_2s(TySF);
+ if (1) test_fadd_2d_2d_2d(TyDF);
+ if (1) test_fadd_4s_4s_4s(TySF);
+ if (1) test_fadd_2s_2s_2s(TySF);
+ if (1) test_fsub_2d_2d_2d(TyDF);
+ if (1) test_fsub_4s_4s_4s(TySF);
+ if (1) test_fsub_2s_2s_2s(TySF);
// fabd d,s
// fabd 2d,4s,2s
- test_fabd_d_d_d(TyDF);
- test_fabd_s_s_s(TySF);
- test_fabd_2d_2d_2d(TyDF);
- test_fabd_4s_4s_4s(TySF);
- test_fabd_2s_2s_2s(TySF);
+ if (1) test_fabd_d_d_d(TyDF);
+ if (1) test_fabd_s_s_s(TySF);
+ if (1) test_fabd_2d_2d_2d(TyDF);
+ if (1) test_fabd_4s_4s_4s(TySF);
+ if (1) test_fabd_2s_2s_2s(TySF);
// faddp d,s (floating add pair)
// faddp 2d,4s,2s
@@ -2986,21 +2986,21 @@
// fcmgt 2d,4s,2s
// facge 2d,4s,2s
// facgt 2d,4s,2s
- test_fcmeq_2d_2d_2d(TyDF);
- test_fcmeq_4s_4s_4s(TySF);
- test_fcmeq_2s_2s_2s(TySF);
- test_fcmge_2d_2d_2d(TyDF);
- test_fcmge_4s_4s_4s(TySF);
- test_fcmge_2s_2s_2s(TySF);
- test_fcmgt_2d_2d_2d(TyDF);
- test_fcmgt_4s_4s_4s(TySF);
- test_fcmgt_2s_2s_2s(TySF);
- test_facge_2d_2d_2d(TyDF);
- test_facge_4s_4s_4s(TySF);
- test_facge_2s_2s_2s(TySF);
- test_facgt_2d_2d_2d(TyDF);
- test_facgt_4s_4s_4s(TySF);
- test_facgt_2s_2s_2s(TySF);
+ if (1) test_fcmeq_2d_2d_2d(TyDF);
+ if (1) test_fcmeq_4s_4s_4s(TySF);
+ if (1) test_fcmeq_2s_2s_2s(TySF);
+ if (1) test_fcmge_2d_2d_2d(TyDF);
+ if (1) test_fcmge_4s_4s_4s(TySF);
+ if (1) test_fcmge_2s_2s_2s(TySF);
+ if (1) test_fcmgt_2d_2d_2d(TyDF);
+ if (1) test_fcmgt_4s_4s_4s(TySF);
+ if (1) test_fcmgt_2s_2s_2s(TySF);
+ if (1) test_facge_2d_2d_2d(TyDF);
+ if (1) test_facge_4s_4s_4s(TySF);
+ if (1) test_facge_2s_2s_2s(TySF);
+ if (1) test_facgt_2d_2d_2d(TyDF);
+ if (1) test_facgt_4s_4s_4s(TySF);
+ if (1) test_facgt_2s_2s_2s(TySF);
// fcmeq_z d,s
// fcmge_z d,s
@@ -3023,11 +3023,11 @@
// fdiv d,s
// fdiv 2d,4s,2s
- test_fdiv_d_d_d(TyDF);
- test_fdiv_s_s_s(TySF);
- test_fdiv_2d_2d_2d(TyDF);
- test_fdiv_4s_4s_4s(TySF);
- test_fdiv_2s_2s_2s(TySF);
+ if (1) test_fdiv_d_d_d(TyDF);
+ if (1) test_fdiv_s_s_s(TySF);
+ if (1) test_fdiv_2d_2d_2d(TyDF);
+ if (1) test_fdiv_4s_4s_4s(TySF);
+ if (1) test_fdiv_2s_2s_2s(TySF);
// fmadd d,s
// fnmadd d,s
@@ -3035,8 +3035,8 @@
// fnmsub d,s
// fnmul d,s
- test_fnmul_d_d_d(TyDF);
- test_fnmul_s_s_s(TySF);
+ if (1) test_fnmul_d_d_d(TyDF);
+ if (1) test_fnmul_s_s_s(TySF);
// fmax d,s
// fmin d,s
@@ -3068,12 +3068,12 @@
// fmla 2d,4s,2s
// fmls 2d,4s,2s
- test_fmla_2d_2d_2d(TyDF);
- test_fmla_4s_4s_4s(TySF);
- test_fmla_2s_2s_2s(TySF);
- test_fmls_2d_2d_2d(TyDF);
- test_fmls_4s_4s_4s(TySF);
- test_fmls_2s_2s_2s(TySF);
+ if (1) test_fmla_2d_2d_2d(TyDF);
+ if (1) test_fmla_4s_4s_4s(TySF);
+ if (1) test_fmla_2s_2s_2s(TySF);
+ if (1) test_fmls_2d_2d_2d(TyDF);
+ if (1) test_fmls_4s_4s_4s(TySF);
+ if (1) test_fmls_2s_2s_2s(TySF);
// fmla d_d_d[],s_s_s[] (by element)
// fmls d_d_d[],s_s_s[] (by element)
@@ -3083,9 +3083,9 @@
// fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
// INCOMPLETE
- test_fmov_2d_imm_01(TyD);
- test_fmov_2d_imm_02(TyD);
- test_fmov_2d_imm_03(TyD);
+ if (1) test_fmov_2d_imm_01(TyD);
+ if (1) test_fmov_2d_imm_02(TyD);
+ if (1) test_fmov_2d_imm_03(TyD);
if (0) test_fmov_4s_imm_01(TyS);
if (0) test_fmov_4s_imm_02(TyS);
if (0) test_fmov_4s_imm_03(TyS);
@@ -3094,35 +3094,35 @@
if (0) test_fmov_2s_imm_03(TyS);
// fmov d_d,s_s
- test_fmov_d_d(TyDF);
- test_fmov_s_s(TySF);
+ if (1) test_fmov_d_d(TyDF);
+ if (1) test_fmov_s_s(TySF);
// fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1]
- test_fmov_s_w(TyS);
- test_fmov_d_x(TyD);
- test_fmov_d1_x(TyD);
- test_fmov_w_s(TyS);
- test_fmov_x_d(TyD);
- test_fmov_x_d1(TyD);
+ if (1) test_fmov_s_w(TyS);
+ if (1) test_fmov_d_x(TyD);
+ if (1) test_fmov_d1_x(TyD);
+ if (1) test_fmov_w_s(TyS);
+ if (1) test_fmov_x_d(TyD);
+ if (1) test_fmov_x_d1(TyD);
// fmov d,s #imm
- test_fmov_d_imm_01(TyNONE);
- test_fmov_d_imm_02(TyNONE);
- test_fmov_d_imm_03(TyNONE);
- test_fmov_s_imm_01(TyNONE);
- test_fmov_s_imm_02(TyNONE);
- test_fmov_s_imm_03(TyNONE);
+ if (1) test_fmov_d_imm_01(TyNONE);
+ if (1) test_fmov_d_imm_02(TyNONE);
+ if (1) test_fmov_d_imm_03(TyNONE);
+ if (1) test_fmov_s_imm_01(TyNONE);
+ if (1) test_fmov_s_imm_02(TyNONE);
+ if (1) test_fmov_s_imm_03(TyNONE);
// fmul d_d_d[],s_s_s[]
// fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
// fmul 2d,4s,2s
// fmul d,s
- test_fmul_d_d_d(TyDF);
- test_fmul_s_s_s(TySF);
- test_fmul_2d_2d_2d(TyDF);
- test_fmul_4s_4s_4s(TySF);
- test_fmul_2s_2s_2s(TySF);
+ if (1) test_fmul_d_d_d(TyDF);
+ if (1) test_fmul_s_s_s(TySF);
+ if (1) test_fmul_2d_2d_2d(TyDF);
+ if (1) test_fmul_4s_4s_4s(TySF);
+ if (1) test_fmul_2s_2s_2s(TySF);
// fmulx d_d_d[],s_s_s[]
// fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
@@ -3168,8 +3168,8 @@
// fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
// INCOMPLETE
- test_fcvtn_2s_2d(TyDF);
- test_fcvtn_4s_2d(TyDF);
+ if (1) test_fcvtn_2s_2d(TyDF);
+ if (1) test_fcvtn_4s_2d(TyDF);
// fcvtas d,s (fcvt to signed int, nearest, ties away)
// fcvtau d,s (fcvt to unsigned int, nearest, ties away)
@@ -3233,121 +3233,121 @@
// scvtf s_w, d_w, s_x, d_x
// ucvtf s_w, d_w, s_x, d_x
- test_scvtf_s_w(TyS);
- test_scvtf_d_w(TyS);
- test_scvtf_s_x(TyD);
- test_scvtf_d_x(TyD);
- test_ucvtf_s_w(TyS);
- test_ucvtf_d_w(TyS);
- test_ucvtf_s_x(TyD);
- test_ucvtf_d_x(TyD);
+ if (1) test_scvtf_s_w(TyS);
+ if (1) test_scvtf_d_w(TyS);
+ if (1) test_scvtf_s_x(TyD);
+ if (1) test_scvtf_d_x(TyD);
+ if (1) test_ucvtf_s_w(TyS);
+ if (1) test_ucvtf_d_w(TyS);
+ if (1) test_ucvtf_s_x(TyD);
+ if (1) test_ucvtf_d_x(TyD);
// ======================== INT ========================
// abs d
// neg d
- test_abs_d_d(TyD);
- test_neg_d_d(TyD);
+ if (0) test_abs_d_d(TyD);
+ if (0) test_neg_d_d(TyD);
// abs 2d,4s,2s,8h,4h,16b,8b
// neg 2d,4s,2s,8h,4h,16b,8b
- test_abs_2d_2d(TyD);
- test_abs_4s_4s(TyS);
- test_abs_2s_2s(TyS);
- test_abs_8h_8h(TyH);
- test_abs_4h_4h(TyH);
- test_abs_16b_16b(TyB);
- test_abs_8b_8b(TyB);
- test_neg_2d_2d(TyD);
- test_neg_4s_4s(TyS);
- test_neg_2s_2s(TyS);
- test_neg_8h_8h(TyH);
- test_neg_4h_4h(TyH);
- test_neg_16b_16b(TyB);
- test_neg_8b_8b(TyB);
+ if (0) test_abs_2d_2d(TyD);
+ if (0) test_abs_4s_4s(TyS);
+ if (0) test_abs_2s_2s(TyS);
+ if (0) test_abs_8h_8h(TyH);
+ if (0) test_abs_4h_4h(TyH);
+ if (0) test_abs_16b_16b(TyB);
+ if (0) test_abs_8b_8b(TyB);
+ if (1) test_neg_2d_2d(TyD);
+ if (1) test_neg_4s_4s(TyS);
+ if (1) test_neg_2s_2s(TyS);
+ if (1) test_neg_8h_8h(TyH);
+ if (1) test_neg_4h_4h(TyH);
+ if (1) test_neg_16b_16b(TyB);
+ if (1) test_neg_8b_8b(TyB);
// add d
// sub d
- test_add_d_d_d(TyD);
- test_sub_d_d_d(TyD);
+ if (1) test_add_d_d_d(TyD);
+ if (1) test_sub_d_d_d(TyD);
// add 2d,4s,2s,8h,4h,16b,8b
// sub 2d,4s,2s,8h,4h,16b,8b
- test_add_2d_2d_2d(TyD);
- test_add_4s_4s_4s(TyS);
- test_add_2s_2s_2s(TyS);
- test_add_8h_8h_8h(TyH);
- test_add_4h_4h_4h(TyH);
- test_add_16b_16b_16b(TyB);
- test_add_8b_8b_8b(TyB);
- test_sub_2d_2d_2d(TyD);
- test_sub_4s_4s_4s(TyS);
- test_sub_2s_2s_2s(TyS);
- test_sub_8h_8h_8h(TyH);
- test_sub_4h_4h_4h(TyH);
- test_sub_16b_16b_16b(TyB);
- test_sub_8b_8b_8b(TyB);
+ if (1) test_add_2d_2d_2d(TyD);
+ if (1) test_add_4s_4s_4s(TyS);
+ if (1) test_add_2s_2s_2s(TyS);
+ if (1) test_add_8h_8h_8h(TyH);
+ if (1) test_add_4h_4h_4h(TyH);
+ if (1) test_add_16b_16b_16b(TyB);
+ if (1) test_add_8b_8b_8b(TyB);
+ if (1) test_sub_2d_2d_2d(TyD);
+ if (1) test_sub_4s_4s_4s(TyS);
+ if (1) test_sub_2s_2s_2s(TyS);
+ if (1) test_sub_8h_8h_8h(TyH);
+ if (1) test_sub_4h_4h_4h(TyH);
+ if (1) test_sub_16b_16b_16b(TyB);
+ if (1) test_sub_8b_8b_8b(TyB);
// addhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
// subhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
// raddhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
// rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
- test_addhn_2s_2d_2d(TyD);
- test_addhn2_4s_2d_2d(TyD);
- test_addhn_4h_4s_4s(TyS);
- test_addhn2_8h_4s_4s(TyS);
- test_addhn_8b_8h_8h(TyH);
- test_addhn2_16b_8h_8h(TyH);
- test_subhn_2s_2d_2d(TyD);
- test_subhn2_4s_2d_2d(TyD);
- test_subhn_4h_4s_4s(TyS);
- test_subhn2_8h_4s_4s(TyS);
- test_subhn_8b_8h_8h(TyH);
- test_subhn2_16b_8h_8h(TyH);
- test_raddhn_2s_2d_2d(TyD);
- test_raddhn2_4s_2d_2d(TyD);
- test_raddhn_4h_4s_4s(TyS);
- test_raddhn2_8h_4s_4s(TyS);
- test_raddhn_8b_8h_8h(TyH);
- test_raddhn2_16b_8h_8h(TyH);
- test_rsubhn_2s_2d_2d(TyD);
- test_rsubhn2_4s_2d_2d(TyD);
- test_rsubhn_4h_4s_4s(TyS);
- test_rsubhn2_8h_4s_4s(TyS);
- test_rsubhn_8b_8h_8h(TyH);
- test_rsubhn2_16b_8h_8h(TyH);
+ if (0) test_addhn_2s_2d_2d(TyD);
+ if (0) test_addhn2_4s_2d_2d(TyD);
+ if (0) test_addhn_4h_4s_4s(TyS);
+ if (0) test_addhn2_8h_4s_4s(TyS);
+ if (0) test_addhn_8b_8h_8h(TyH);
+ if (0) test_addhn2_16b_8h_8h(TyH);
+ if (0) test_subhn_2s_2d_2d(TyD);
+ if (0) test_subhn2_4s_2d_2d(TyD);
+ if (0) test_subhn_4h_4s_4s(TyS);
+ if (0) test_subhn2_8h_4s_4s(TyS);
+ if (0) test_subhn_8b_8h_8h(TyH);
+ if (0) test_subhn2_16b_8h_8h(TyH);
+ if (0) test_raddhn_2s_2d_2d(TyD);
+ if (0) test_raddhn2_4s_2d_2d(TyD);
+ if (0) test_raddhn_4h_4s_4s(TyS);
+ if (0) test_raddhn2_8h_4s_4s(TyS);
+ if (0) test_raddhn_8b_8h_8h(TyH);
+ if (0) test_raddhn2_16b_8h_8h(TyH);
+ if (0) test_rsubhn_2s_2d_2d(TyD);
+ if (0) test_rsubhn2_4s_2d_2d(TyD);
+ if (0) test_rsubhn_4h_4s_4s(TyS);
+ if (0) test_rsubhn2_8h_4s_4s(TyS);
+ if (0) test_rsubhn_8b_8h_8h(TyH);
+ if (0) test_rsubhn2_16b_8h_8h(TyH);
// addp d (add pairs, across)
- test_addp_d_2d(TyD);
+ if (0) test_addp_d_2d(TyD);
// addp 2d,4s,2s,8h,4h,16b,8b
- test_addp_2d_2d_2d(TyD);
- test_addp_4s_4s_4s(TyS);
- test_addp_2s_2s_2s(TyS);
- test_addp_8h_8h_8h(TyH);
- test_addp_4h_4h_4h(TyH);
- test_addp_16b_16b_16b(TyB);
- test_addp_8b_8b_8b(TyB);
+ if (0) test_addp_2d_2d_2d(TyD);
+ if (0) test_addp_4s_4s_4s(TyS);
+ if (0) test_addp_2s_2s_2s(TyS);
+ if (0) test_addp_8h_8h_8h(TyH);
+ if (0) test_addp_4h_4h_4h(TyH);
+ if (0) test_addp_16b_16b_16b(TyB);
+ if (0) test_addp_8b_8b_8b(TyB);
// addv 4s,8h,4h,16b,18b (reduce across vector)
- test_addv_s_4s(TyS);
- test_addv_h_8h(TyH);
- test_addv_h_4h(TyH);
- test_addv_b_16b(TyB);
- test_addv_b_8b(TyB);
+ if (0) test_addv_s_4s(TyS);
+ if (0) test_addv_h_8h(TyH);
+ if (0) test_addv_h_4h(TyH);
+ if (0) test_addv_b_16b(TyB);
+ if (0) test_addv_b_8b(TyB);
// and 16b,8b
// bic 16b,8b
// orn 16b,8b
// orr 16b,8b
- test_and_16b_16b_16b(TyB);
- test_and_8b_8b_8b(TyB);
- test_bic_16b_16b_16b(TyB);
- test_bic_8b_8b_8b(TyB);
- test_orr_16b_16b_16b(TyB);
- test_orr_8b_8b_8b(TyB);
- test_orn_16b_16b_16b(TyB);
- test_orn_8b_8b_8b(TyB);
+ if (1) test_and_16b_16b_16b(TyB);
+ if (1) test_and_8b_8b_8b(TyB);
+ if (1) test_bic_16b_16b_16b(TyB);
+ if (1) test_bic_8b_8b_8b(TyB);
+ if (1) test_orr_16b_16b_16b(TyB);
+ if (1) test_orr_8b_8b_8b(TyB);
+ if (1) test_orn_16b_16b_16b(TyB);
+ if (1) test_orn_8b_8b_8b(TyB);
// orr 8h,4h #imm8, LSL #0 or 8
// orr 4s,2s #imm8, LSL #0, 8, 16 or 24
@@ -3355,58 +3355,58 @@
// bic 4s,2s #imm8, LSL #0, 8, 16 or 24
// movi and mvni are very similar, a superset of these.
// Cases are below.
- test_orr_8h_0x5A_lsl0(TyH);
- test_orr_8h_0xA5_lsl8(TyH);
- test_orr_4h_0x5A_lsl0(TyH);
- test_orr_4h_0xA5_lsl8(TyH);
- test_orr_4s_0x5A_lsl0(TyS);
- test_orr_4s_0x6B_lsl8(TyS);
- test_orr_4s_0x49_lsl16(TyS);
- test_orr_4s_0x3D_lsl24(TyS);
- test_orr_2s_0x5A_lsl0(TyS);
- test_orr_2s_0x6B_lsl8(TyS);
- test_orr_2s_0x49_lsl16(TyS);
- test_orr_2s_0x3D_lsl24(TyS);
- test_bic_8h_0x5A_lsl0(TyH);
- test_bic_8h_0xA5_lsl8(TyH);
- test_bic_4h_0x5A_lsl0(TyH);
- test_bic_4h_0xA5_lsl8(TyH);
- test_bic_4s_0x5A_lsl0(TyS);
- test_bic_4s_0x6B_lsl8(TyS);
- test_bic_4s_0x49_lsl16(TyS);
- test_bic_4s_0x3D_lsl24(TyS);
- test_bic_2s_0x5A_lsl0(TyS);
- test_bic_2s_0x6B_lsl8(TyS);
- test_bic_2s_0x49_lsl16(TyS);
- test_bic_2s_0x3D_lsl24(TyS);
+ if (0) test_orr_8h_0x5A_lsl0(TyH);
+ if (0) test_orr_8h_0xA5_lsl8(TyH);
+ if (0) test_orr_4h_0x5A_lsl0(TyH);
+ if (0) test_orr_4h_0xA5_lsl8(TyH);
+ if (0) test_orr_4s_0x5A_lsl0(TyS);
+ if (0) test_orr_4s_0x6B_lsl8(TyS);
+ if (0) test_orr_4s_0x49_lsl16(TyS);
+ if (0) test_orr_4s_0x3D_lsl24(TyS);
+ if (0) test_orr_2s_0x5A_lsl0(TyS);
+ if (0) test_orr_2s_0x6B_lsl8(TyS);
+ if (0) test_orr_2s_0x49_lsl16(TyS);
+ if (0) test_orr_2s_0x3D_lsl24(TyS);
+ if (0) test_bic_8h_0x5A_lsl0(TyH);
+ if (0) test_bic_8h_0xA5_lsl8(TyH);
+ if (0) test_bic_4h_0x5A_lsl0(TyH);
+ if (0) test_bic_4h_0xA5_lsl8(TyH);
+ if (0) test_bic_4s_0x5A_lsl0(TyS);
+ if (0) test_bic_4s_0x6B_lsl8(TyS);
+ if (0) test_bic_4s_0x49_lsl16(TyS);
+ if (0) test_bic_4s_0x3D_lsl24(TyS);
+ if (0) test_bic_2s_0x5A_lsl0(TyS);
+ if (0) test_bic_2s_0x6B_lsl8(TyS);
+ if (0) test_bic_2s_0x49_lsl16(TyS);
+ if (0) test_bic_2s_0x3D_lsl24(TyS);
// bif 16b,8b (vector) (bit insert if false)
// bit 16b,8b (vector) (bit insert if true)
// bsl 16b,8b (vector) (bit select)
// eor 16b,8b (vector)
- test_bif_16b_16b_16b(TyB);
- test_bif_8b_8b_8b(TyB);
- test_bit_16b_16b_16b(TyB);
- test_bit_8b_8b_8b(TyB);
- test_bsl_16b_16b_16b(TyB);
- test_bsl_8b_8b_8b(TyB);
- test_eor_16b_16b_16b(TyB);
- test_eor_8b_8b_8b(TyB);
+ if (1) test_bif_16b_16b_16b(TyB);
+ if (1) test_bif_8b_8b_8b(TyB);
+ if (1) test_bit_16b_16b_16b(TyB);
+ if (1) test_bit_8b_8b_8b(TyB);
+ if (1) test_bsl_16b_16b_16b(TyB);
+ if (1) test_bsl_8b_8b_8b(TyB);
+ if (1) test_eor_16b_16b_16b(TyB);
+ if (1) test_eor_8b_8b_8b(TyB);
// cls 4s,2s,8h,4h,16b,8b (count leading sign bits)
// clz 4s,2s,8h,4h,16b,8b (count leading zero bits)
- test_cls_4s_4s(TyS);
- test_cls_2s_2s(TyS);
- test_cls_8h_8h(TyH);
- test_cls_4h_4h(TyH);
- test_cls_16b_16b(TyB);
- test_cls_8b_8b(TyB);
- test_clz_4s_4s(TyS);
- test_clz_2s_2s(TyS);
- test_clz_8h_8h(TyH);
- test_clz_4h_4h(TyH);
- test_clz_16b_16b(TyB);
- test_clz_8b_8b(TyB);
+ if (0) test_cls_4s_4s(TyS);
+ if (0) test_cls_2s_2s(TyS);
+ if (0) test_cls_8h_8h(TyH);
+ if (0) test_cls_4h_4h(TyH);
+ if (0) test_cls_16b_16b(TyB);
+ if (0) test_cls_8b_8b(TyB);
+ if (0) test_clz_4s_4s(TyS);
+ if (0) test_clz_2s_2s(TyS);
+ if (0) test_clz_8h_8h(TyH);
+ if (0) test_clz_4h_4h(TyH);
+ if (0) test_clz_16b_16b(TyB);
+ if (0) test_clz_8b_8b(TyB);
// cmeq d
// cmge d
@@ -3414,12 +3414,12 @@
// cmhi d
// cmhs d
// cmtst d
- test_cmeq_d_d_d(TyD);
- test_cmge_d_d_d(TyD);
- test_cmgt_d_d_d(TyD);
- test_cmhi_d_d_d(TyD);
- test_cmhs_d_d_d(TyD);
- test_cmtst_d_d_d(TyD);
+ if (0) test_cmeq_d_d_d(TyD);
+ if (0) test_cmge_d_d_d(TyD);
+ if (0) test_cmgt_d_d_d(TyD);
+ if (0) test_cmhi_d_d_d(TyD);
+ if (0) test_cmhs_d_d_d(TyD);
+ if (0) test_cmtst_d_d_d(TyD);
// cmeq 2d,4s,2s,8h,4h,16b,8b
// cmge 2d,4s,2s,8h,4h,16b,8b
@@ -3427,652 +3427,652 @@
// cmhi 2d,4s,2s,8h,4h,16b,8b
// cmhs 2d,4s,2s,8h,4h,16b,8b
// cmtst 2d,4s,2s,8h,4h,16b,8b
- test_cmeq_2d_2d_2d(TyD);
- test_cmeq_4s_4s_4s(TyS);
- test_cmeq_2s_2s_2s(TyS);
- test_cmeq_8h_8h_8h(TyH);
- test_cmeq_4h_4h_4h(TyH);
- test_cmeq_16b_16b_16b(TyB);
- test_cmeq_8b_8b_8b(TyB);
- test_cmge_2d_2d_2d(TyD);
- test_cmge_4s_4s_4s(TyS);
- test_cmge_2s_2s_2s(TyS);
- test_cmge_8h_8h_8h(TyH);
- test_cmge_4h_4h_4h(TyH);
- test_cmge_16b_16b_16b(TyB);
- test_cmge_8b_8b_8b(TyB);
- test_cmgt_2d_2d_2d(TyD);
- test_cmgt_4s_4s_4s(TyS);
- test_cmgt_2s_2s_2s(TyS);
- test_cmgt_8h_8h_8h(TyH);
- test_cmgt_4h_4h_4h(TyH);
- test_cmgt_16b_16b_16b(TyB);
- test_cmgt_8b_8b_8b(TyB);
- test_cmhi_2d_2d_2d(TyD);
- test_cmhi_4s_4s_4s(TyS);
- test_cmhi_2s_2s_2s(TyS);
- test_cmhi_8h_8h_8h(TyH);
- test_cmhi_4h_4h_4h(TyH);
- test_cmhi_16b_16b_16b(TyB);
- test_cmhi_8b_8b_8b(TyB);
- test_cmhs_2d_2d_2d(TyD);
- test_cmhs_4s_4s_4s(TyS);
- test_cmhs_2s_2s_2s(TyS);
- test_cmhs_8h_8h_8h(TyH);
- test_cmhs_4h_4h_4h(TyH);
- test_cmhs_16b_16b_16b(TyB);
- test_cmhs_8b_8b_8b(TyB);
- test_cmtst_2d_2d_2d(TyD);
- test_cmtst_4s_4s_4s(TyS);
- test_cmtst_2s_2s_2s(TyS);
- test_cmtst_8h_8h_8h(TyH);
- test_cmtst_4h_4h_4h(TyH);
- test_cmtst_16b_16b_16b(TyB);
- test_cmtst_8b_8b_8b(TyB);
+ if (1) test_cmeq_2d_2d_2d(TyD);
+ if (1) test_cmeq_4s_4s_4s(TyS);
+ if (1) test_cmeq_2s_2s_2s(TyS);
+ if (1) test_cmeq_8h_8h_8h(TyH);
+ if (1) test_cmeq_4h_4h_4h(TyH);
+ if (1) test_cmeq_16b_16b_16b(TyB);
+ if (1) test_cmeq_8b_8b_8b(TyB);
+ if (1) test_cmge_2d_2d_2d(TyD);
+ if (1) test_cmge_4s_4s_4s(TyS);
+ if (1) test_cmge_2s_2s_2s(TyS);
+ if (1) test_cmge_8h_8h_8h(TyH);
+ if (1) test_cmge_4h_4h_4h(TyH);
+ if (1) test_cmge_16b_16b_16b(TyB);
+ if (1) test_cmge_8b_8b_8b(TyB);
+ if (1) test_cmgt_2d_2d_2d(TyD);
+ if (1) test_cmgt_4s_4s_4s(TyS);
+ if (1) test_cmgt_2s_2s_2s(TyS);
+ if (1) test_cmgt_8h_8h_8h(TyH);
+ if (1) test_cmgt_4h_4h_4h(TyH);
+ if (1) test_cmgt_16b_16b_16b(TyB);
+ if (1) test_cmgt_8b_8b_8b(TyB);
+ if (1) test_cmhi_2d_2d_2d(TyD);
+ if (1) test_cmhi_4s_4s_4s(TyS);
+ if (1) test_cmhi_2s_2s_2s(TyS);
+ if (1) test_cmhi_8h_8h_8h(TyH);
+ if (1) test_cmhi_4h_4h_4h(TyH);
+ if (1) test_cmhi_16b_16b_16b(TyB);
+ if (1) test_cmhi_8b_8b_8b(TyB);
+ if (1) test_cmhs_2d_2d_2d(TyD);
+ if (1) test_cmhs_4s_4s_4s(TyS);
+ if (1) test_cmhs_2s_2s_2s(TyS);
+ if (1) test_cmhs_8h_8h_8h(TyH);
+ if (1) test_cmhs_4h_4h_4h(TyH);
+ if (1) test_cmhs_16b_16b_16b(TyB);
+ if (1) test_cmhs_8b_8b_8b(TyB);
+ if (1) test_cmtst_2d_2d_2d(TyD);
+ if (1) test_cmtst_4s_4s_4s(TyS);
+ if (1) test_cmtst_2s_2s_2s(TyS);
+ if (1) test_cmtst_8h_8h_8h(TyH);
+ if (1) test_cmtst_4h_4h_4h(TyH);
+ if (1) test_cmtst_16b_16b_16b(TyB);
+ if (1) test_cmtst_8b_8b_8b(TyB);
// cmeq_z d
// cmge_z d
// cmgt_z d
// cmle_z d
// cmlt_z d
- test_cmeq_zero_d_d(TyD);
- test_cmge_zero_d_d(TyD);
- test_cmgt_zero_d_d(TyD);
- test_cmle_zero_d_d(TyD);
- test_cmlt_zero_d_d(TyD);
+ if (1) test_cmeq_zero_d_d(TyD);
+ if (0) test_cmge_zero_d_d(TyD);
+ if (0) test_cmgt_zero_d_d(TyD);
+ if (0) test_cmle_zero_d_d(TyD);
+ if (0) test_cmlt_zero_d_d(TyD);
// cmeq_z 2d,4s,2s,8h,4h,16b,8b
// cmge_z 2d,4s,2s,8h,4h,16b,8b
// cmgt_z 2d,4s,2s,8h,4h,16b,8b
// cmle_z 2d,4s,2s,8h,4h,16b,8b
// cmlt_z 2d,4s,2s,8h,4h,16b,8b
- test_cmeq_zero_2d_2d(TyD);
- test_cmeq_zero_4s_4s(TyS);
- test_cmeq_zero_2s_2s(TyS);
- test_cmeq_zero_8h_8h(TyH);
- test_cmeq_zero_4h_4h(TyH);
- test_cmeq_zero_16b_16b(TyB);
- test_cmeq_zero_8b_8b(TyB);
- test_cmge_zero_2d_2d(TyD);
- test_cmge_zero_4s_4s(TyS);
- test_cmge_zero_2s_2s(TyS);
- test_cmge_zero_8h_8h(TyH);
- test_cmge_zero_4h_4h(TyH);
- test_cmge_zero_16b_16b(TyB);
- test_cmge_zero_8b_8b(TyB);
- test_cmgt_zero_2d_2d(TyD);
- test_cmgt_zero_4s_4s(TyS);
- test_cmgt_zero_2s_2s(TyS);
- test_cmgt_zero_8h_8h(TyH);
- test_cmgt_zero_4h_4h(TyH);
- test_cmgt_zero_16b_16b(TyB);
- test_cmgt_zero_8b_8b(TyB);
- test_cmle_zero_2d_2d(TyD);
- test_cmle_zero_4s_4s(TyS);
- test_cmle_zero_2s_2s(TyS);
- test_cmle_zero_8h_8h(TyH);
- test_cmle_zero_4h_4h(TyH);
- test_cmle_zero_16b_16b(TyB);
- test_cmle_zero_8b_8b(TyB);
- test_cmlt_zero_2d_2d(TyD);
- test_cmlt_zero_4s_4s(TyS);
- test_cmlt_zero_2s_2s(TyS);
- test_cmlt_zero_8h_8h(TyH);
- test_cmlt_zero_4h_4h(TyH);
- test_cmlt_zero_16b_16b(TyB);
- test_cmlt_zero_8b_8b(TyB);
+ if (1) test_cmeq_zero_2d_2d(TyD);
+ if (1) test_cmeq_zero_4s_4s(TyS);
+ if (1) test_cmeq_zero_2s_2s(TyS);
+ if (1) test_cmeq_zero_8h_8h(TyH);
+ if (1) test_cmeq_zero_4h_4h(TyH);
+ if (1) test_cmeq_zero_16b_16b(TyB);
+ if (1) test_cmeq_zero_8b_8b(TyB);
+ if (1) test_cmge_zero_2d_2d(TyD);
+ if (1) test_cmge_zero_4s_4s(TyS);
+ if (1) test_cmge_zero_2s_2s(TyS);
+ if (1) test_cmge_zero_8h_8h(TyH);
+ if (1) test_cmge_zero_4h_4h(TyH);
+ if (1) test_cmge_zero_16b_16b(TyB);
+ if (1) test_cmge_zero_8b_8b(TyB);
+ if (1) test_cmgt_zero_2d_2d(TyD);
+ if (1) test_cmgt_zero_4s_4s(TyS);
+ if (1) test_cmgt_zero_2s_2s(TyS);
+ if (1) test_cmgt_zero_8h_8h(TyH);
+ if (1) test_cmgt_zero_4h_4h(TyH);
+ if (1) test_cmgt_zero_16b_16b(TyB);
+ if (1) test_cmgt_zero_8b_8b(TyB);
+ if (1) test_cmle_zero_2d_2d(TyD);
+ if (1) test_cmle_zero_4s_4s(TyS);
+ if (1) test_cmle_zero_2s_2s(TyS);
+ if (1) test_cmle_zero_8h_8h(TyH);
+ if (1) test_cmle_zero_4h_4h(TyH);
+ if (1) test_cmle_zero_16b_16b(TyB);
+ if (1) test_cmle_zero_8b_8b(TyB);
+ if (1) test_cmlt_zero_2d_2d(TyD);
+ if (1) test_cmlt_zero_4s_4s(TyS);
+ if (1) test_cmlt_zero_2s_2s(TyS);
+ if (1) test_cmlt_zero_8h_8h(TyH);
+ if (1) test_cmlt_zero_4h_4h(TyH);
+ if (1) test_cmlt_zero_16b_16b(TyB);
+ if (1) test_cmlt_zero_8b_8b(TyB);
// cnt 16b,8b (population count per byte)
- test_cnt_16b_16b(TyB);
- test_cnt_8b_8b(TyB);
+ if (0) test_cnt_16b_16b(TyB);
+ if (0) test_cnt_8b_8b(TyB);
// dup d,s,h,b (vec elem to scalar)
- test_dup_d_d0(TyD);
- test_dup_d_d1(TyD);
- test_dup_s_s0(TyS);
- test_dup_s_s3(TyS);
- test_dup_h_h0(TyH);
- test_dup_h_h6(TyH);
- test_dup_b_b0(TyB);
- test_dup_b_b13(TyB);
+ if (0) test_dup_d_d0(TyD);
+ if (0) test_dup_d_d1(TyD);
+ if (0) test_dup_s_s0(TyS);
+ if (0) test_dup_s_s3(TyS);
+ if (0) test_dup_h_h0(TyH);
+ if (0) test_dup_h_h6(TyH);
+ if (0) test_dup_b_b0(TyB);
+ if (0) test_dup_b_b13(TyB);
// dup 2d,4s,2s,8h,4h,16b,8b (vec elem to vector)
- test_dup_2d_d0(TyD);
- test_dup_2d_d1(TyD);
- test_dup_4s_s0(TyS);
- test_dup_4s_s3(TyS);
- test_dup_2s_s0(TyS);
- test_dup_2s_s2(TyS);
- test_dup_8h_h0(TyH);
- test_dup_8h_h6(TyH);
- test_dup_4h_h1(TyH);
- test_dup_4h_h5(TyH);
- test_dup_16b_b2(TyB);
- test_dup_16b_b12(TyB);
- test_dup_8b_b3(TyB);
- test_dup_8b_b13(TyB);
+ if (1) test_dup_2d_d0(TyD);
+ if (1) test_dup_2d_d1(TyD);
+ if (1) test_dup_4s_s0(TyS);
+ if (1) test_dup_4s_s3(TyS);
+ if (1) test_dup_2s_s0(TyS);
+ if (1) test_dup_2s_s2(TyS);
+ if (1) test_dup_8h_h0(TyH);
+ if (1) test_dup_8h_h6(TyH);
+ if (1) test_dup_4h_h1(TyH);
+ if (1) test_dup_4h_h5(TyH);
+ if (1) test_dup_16b_b2(TyB);
+ if (1) test_dup_16b_b12(TyB);
+ if (1) test_dup_8b_b3(TyB);
+ if (1) test_dup_8b_b13(TyB);
// dup 2d,4s,2s,8h,4h,16b,8b (general reg to vector)
- test_dup_2d_x(TyD);
- test_dup_4s_w(TyS);
- test_dup_2s_w(TyS);
- test_dup_8h_w(TyH);
- test_dup_4h_w(TyH);
- test_dup_16b_w(TyB);
- test_dup_8b_w(TyB);
+ if (1) test_dup_2d_x(TyD);
+ if (1) test_dup_4s_w(TyS);
+ if (1) test_dup_2s_w(TyS);
+ if (1) test_dup_8h_w(TyH);
+ if (1) test_dup_4h_w(TyH);
+ if (1) test_dup_16b_w(TyB);
+ if (1) test_dup_8b_w(TyB);
// ext 16b,8b,#imm4 (concat 2 vectors, then slice)
- test_ext_16b_16b_16b_0x0(TyB);
- test_ext_16b_16b_16b_0x7(TyB);
- test_ext_16b_16b_16b_0x8(TyB);
- test_ext_16b_16b_16b_0x9(TyB);
- test_ext_16b_16b_16b_0xF(TyB);
- test_ext_8b_8b_8b_0x0(TyB);
- test_ext_8b_8b_8b_0x1(TyB);
- test_ext_8b_8b_8b_0x6(TyB);
- test_ext_8b_8b_8b_0x7(TyB);
+ if (0) test_ext_16b_16b_16b_0x0(TyB);
+ if (0) test_ext_16b_16b_16b_0x7(TyB);
+ if (0) test_ext_16b_16b_16b_0x8(TyB);
+ if (0) test_ext_16b_16b_16b_0x9(TyB);
+ if (0) test_ext_16b_16b_16b_0xF(TyB);
+ if (0) test_ext_8b_8b_8b_0x0(TyB);
+ if (0) test_ext_8b_8b_8b_0x1(TyB);
+ if (0) test_ext_8b_8b_8b_0x6(TyB);
+ if (0) test_ext_8b_8b_8b_0x7(TyB);
// ins d[]_d[],s[]_s[],h[]_h[],b[]_b[]
- test_ins_d0_d0(TyD);
- test_ins_d0_d1(TyD);
- test_ins_d1_d0(TyD);
- test_ins_d1_d1(TyD);
- test_ins_s0_s2(TyS);
- test_ins_s3_s0(TyS);
- test_ins_s2_s1(TyS);
- test_ins_s1_s3(TyS);
- test_ins_h0_h6(TyH);
- test_ins_h7_h0(TyH);
- test_ins_h6_h1(TyH);
- test_ins_h1_h7(TyH);
- test_ins_b0_b14(TyB);
- test_ins_b15_b8(TyB);
- test_ins_b13_b9(TyB);
- test_ins_b5_b12(TyB);
+ if (0) test_ins_d0_d0(TyD);
+ if (0) test_ins_d0_d1(TyD);
+ if (0) test_ins_d1_d0(TyD);
+ if (0) test_ins_d1_d1(TyD);
+ if (0) test_ins_s0_s2(TyS);
+ if (0) test_ins_s3_s0(TyS);
+ if (0) test_ins_s2_s1(TyS);
+ if (0) test_ins_s1_s3(TyS);
+ if (0) test_ins_h0_h6(TyH);
+ if (0) test_ins_h7_h0(TyH);
+ if (0) test_ins_h6_h1(TyH);
+ if (0) test_ins_h1_h7(TyH);
+ if (0) test_ins_b0_b14(TyB);
+ if (0) test_ins_b15_b8(TyB);
+ if (0) test_ins_b13_b9(TyB);
+ if (0) test_ins_b5_b12(TyB);
// ins d[]_x, s[]_w, h[]_w, b[]_w
- test_INS_general();
+ if (1) test_INS_general();
// mla 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
// mls 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
// mul 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
- test_mla_4s_4s_s0(TyS);
- test_mla_4s_4s_s3(TyS);
- test_mla_2s_2s_s0(TyS);
- test_mla_2s_2s_s3(TyS);
- test_mla_8h_8h_h1(TyH);
- test_mla_8h_8h_h5(TyH);
- test_mla_4h_4h_h2(TyH);
- test_mla_4h_4h_h7(TyH);
- test_mls_4s_4s_s0(TyS);
- test_mls_4s_4s_s3(TyS);
- test_mls_2s_2s_s0(TyS);
- test_mls_2s_2s_s3(TyS);
- test_mls_8h_8h_h1(TyH);
- test_mls_8h_8h_h5(TyH);
- test_mls_4h_4h_h2(TyH);
- test_mls_4h_4h_h7(TyH);
- test_mul_4s_4s_s0(TyS);
- test_mul_4s_4s_s3(TyS);
- test_mul_2s_2s_s0(TyS);
- test_mul_2s_2s_s3(TyS);
- test_mul_8h_8h_h1(TyH);
- test_mul_8h_8h_h5(TyH);
- test_mul_4h_4h_h2(TyH);
- test_mul_4h_4h_h7(TyH);
+ if (0) test_mla_4s_4s_s0(TyS);
+ if (0) test_mla_4s_4s_s3(TyS);
+ if (0) test_mla_2s_2s_s0(TyS);
+ if (0) test_mla_2s_2s_s3(TyS);
+ if (0) test_mla_8h_8h_h1(TyH);
+ if (0) test_mla_8h_8h_h5(TyH);
+ if (0) test_mla_4h_4h_h2(TyH);
+ if (0) test_mla_4h_4h_h7(TyH);
+ if (0) test_mls_4s_4s_s0(TyS);
+ if (0) test_mls_4s_4s_s3(TyS);
+ if (0) test_mls_2s_2s_s0(TyS);
+ if (0) test_mls_2s_2s_s3(TyS);
+ if (0) test_mls_8h_8h_h1(TyH);
+ if (0) test_mls_8h_8h_h5(TyH);
+ if (0) test_mls_4h_4h_h2(TyH);
+ if (0) test_mls_4h_4h_h7(TyH);
+ if (0) test_mul_4s_4s_s0(TyS);
+ if (0) test_mul_4s_4s_s3(TyS);
+ if (0) test_mul_2s_2s_s0(TyS);
+ if (0) test_mul_2s_2s_s3(TyS);
+ if (0) test_mul_8h_8h_h1(TyH);
+ if (0) test_mul_8h_8h_h5(TyH);
+ if (0) test_mul_4h_4h_h2(TyH);
+ if (0) test_mul_4h_4h_h7(TyH);
// mla 4s,2s,8h,4h,16b,8b
// mls 4s,2s,8h,4h,16b,8b
// mul 4s,2s,8h,4h,16b,8b
- test_mla_4s_4s_4s(TyS);
- test_mla_2s_2s_2s(TyS);
- test_mla_8h_8h_8h(TyH);
- test_mla_4h_4h_4h(TyH);
- test_mla_16b_16b_16b(TyB);
- test_mla_8b_8b_8b(TyB);
- test_mls_4s_4s_4s(TyS);
- test_mls_2s_2s_2s(TyS);
- test_mls_8h_8h_8h(TyH);
- test_mls_4h_4h_4h(TyH);
- test_mls_16b_16b_16b(TyB);
- test_mls_8b_8b_8b(TyB);
- test_mul_4s_4s_4s(TyS);
- test_mul_2s_2s_2s(TyS);
- test_mul_8h_8h_8h(TyH);
- test_mul_4h_4h_4h(TyH);
- test_mul_16b_16b_16b(TyB);
- test_mul_8b_8b_8b(TyB);
+ if (1) test_mla_4s_4s_4s(TyS);
+ if (1) test_mla_2s_2s_2s(TyS);
+ if (1) test_mla_8h_8h_8h(TyH);
+ if (1) test_mla_4h_4h_4h(TyH);
+ if (1) test_mla_16b_16b_16b(TyB);
+ if (1) test_mla_8b_8b_8b(TyB);
+ if (1) test_mls_4s_4s_4s(TyS);
+ if (1) test_mls_2s_2s_2s(TyS);
+ if (1) test_mls_8h_8h_8h(TyH);
+ if (1) test_mls_4h_4h_4h(TyH);
+ if (1) test_mls_16b_16b_16b(TyB);
+ if (1) test_mls_8b_8b_8b(TyB);
+ if (1) test_mul_4s_4s_4s(TyS);
+ if (1) test_mul_2s_2s_2s(TyS);
+ if (1) test_mul_8h_8h_8h(TyH);
+ if (1) test_mul_4h_4h_4h(TyH);
+ if (1) test_mul_16b_16b_16b(TyB);
+ if (1) test_mul_8b_8b_8b(TyB);
// Some of these movi and mvni cases are similar to orr and bic
// cases with immediates. Maybe they should be moved together.
// movi 16b,8b #imm8, LSL #0
- test_movi_16b_0x9C_lsl0(TyB);
- test_movi_8b_0x8B_lsl0(TyB);
+ if (0) test_movi_16b_0x9C_lsl0(TyB);
+ if (0) test_movi_8b_0x8B_lsl0(TyB);
// movi 8h,4h #imm8, LSL #0 or 8
// mvni 8h,4h #imm8, LSL #0 or 8
- test_movi_8h_0x5A_lsl0(TyH);
- test_movi_8h_0xA5_lsl8(TyH);
- test_movi_4h_0x5A_lsl0(TyH);
- test_movi_4h_0xA5_lsl8(TyH);
- test_mvni_8h_0x5A_lsl0(TyH);
- test_mvni_8h_0xA5_lsl8(TyH);
- test_mvni_4h_0x5A_lsl0(TyH);
- test_mvni_4h_0xA5_lsl8(TyH);
+ if (0) test_movi_8h_0x5A_lsl0(TyH);
+ if (0) test_movi_8h_0xA5_lsl8(TyH);
+ if (0) test_movi_4h_0x5A_lsl0(TyH);
+ if (0) test_movi_4h_0xA5_lsl8(TyH);
+ if (0) test_mvni_8h_0x5A_lsl0(TyH);
+ if (0) test_mvni_8h_0xA5_lsl8(TyH);
+ if (0) test_mvni_4h_0x5A_lsl0(TyH);
+ if (0) test_mvni_4h_0xA5_lsl8(TyH);
// movi 4s,2s #imm8, LSL #0, 8, 16, 24
// mvni 4s,2s #imm8, LSL #0, 8, 16, 24
- test_movi_4s_0x5A_lsl0(TyS);
- test_movi_4s_0x6B_lsl8(TyS);
- test_movi_4s_0x49_lsl16(TyS);
- test_movi_4s_0x3D_lsl24(TyS);
- test_movi_2s_0x5A_lsl0(TyS);
- test_movi_2s_0x6B_lsl8(TyS);
- test_movi_2s_0x49_lsl16(TyS);
- test_movi_2s_0x3D_lsl24(TyS);
- test_mvni_4s_0x5A_lsl0(TyS);
- test_mvni_4s_0x6B_lsl8(TyS);
- test_mvni_4s_0x49_lsl16(TyS);
- test_mvni_4s_0x3D_lsl24(TyS);
- test_mvni_2s_0x5A_lsl0(TyS);
- test_mvni_2s_0x6B_lsl8(TyS);
- test_mvni_2s_0x49_lsl16(TyS);
- test_mvni_2s_0x3D_lsl24(TyS);
+ if (1) test_movi_4s_0x5A_lsl0(TyS);
+ if (0) test_movi_4s_0x6B_lsl8(TyS);
+ if (0) test_movi_4s_0x49_lsl16(TyS);
+ if (0) test_movi_4s_0x3D_lsl24(TyS);
+ if (0) test_movi_2s_0x5A_lsl0(TyS);
+ if (0) test_movi_2s_0x6B_lsl8(TyS);
+ if (0) test_movi_2s_0x49_lsl16(TyS);
+ if (0) test_movi_2s_0x3D_lsl24(TyS);
+ if (0) test_mvni_4s_0x5A_lsl0(TyS);
+ if (0) test_mvni_4s_0x6B_lsl8(TyS);
+ if (0) test_mvni_4s_0x49_lsl16(TyS);
+ if (0) test_mvni_4s_0x3D_lsl24(TyS);
+ if (0) test_mvni_2s_0x5A_lsl0(TyS);
+ if (0) test_mvni_2s_0x6B_lsl8(TyS);
+ if (0) test_mvni_2s_0x49_lsl16(TyS);
+ if (0) test_mvni_2s_0x3D_lsl24(TyS);
// movi 4s,2s #imm8, MSL #8 or 16
// mvni 4s,2s #imm8, MSL #8 or 16
- test_movi_4s_0x6B_msl8(TyS);
- test_movi_4s_0x94_msl16(TyS);
- test_movi_2s_0x7A_msl8(TyS);
- test_movi_2s_0xA5_msl16(TyS);
- test_mvni_4s_0x6B_msl8(TyS);
- test_mvni_4s_0x94_msl16(TyS);
- test_mvni_2s_0x7A_msl8(TyS);
- test_mvni_2s_0xA5_msl16(TyS);
+ if (0) test_movi_4s_0x6B_msl8(TyS);
+ if (0) test_movi_4s_0x94_msl16(TyS);
+ if (0) test_movi_2s_0x7A_msl8(TyS);
+ if (0) test_movi_2s_0xA5_msl16(TyS);
+ if (0) test_mvni_4s_0x6B_msl8(TyS);
+ if (0) test_mvni_4s_0x94_msl16(TyS);
+ if (0) test_mvni_2s_0x7A_msl8(TyS);
+ if (0) test_mvni_2s_0xA5_msl16(TyS);
// movi d, #imm64
// movi 2d, #imm64
- test_movi_d_0xA5(TyD);
- test_movi_2d_0xB4(TyD);
+ if (0) test_movi_d_0xA5(TyD);
+ if (0) test_movi_2d_0xB4(TyD);
// not 16b,8b
- test_not_16b_16b(TyB);
- test_not_8b_8b(TyB);
+ if (0) test_not_16b_16b(TyB);
+ if (0) test_not_8b_8b(TyB);
// pmul 16b,8b
- test_pmul_16b_16b_16b(TyB);
- test_pmul_8b_8b_8b(TyB);
+ if (0) test_pmul_16b_16b_16b(TyB);
+ if (0) test_pmul_8b_8b_8b(TyB);
// pmull{2} 8h_8b_8b,8h_16b_16b,1q_1d_1d,1q_2d_2d
- test_pmull_8h_8b_8b(TyB);
- test_pmull2_8h_16b_16b(TyB);
- //test_pmull_1q_1d_1d(TyD);
- //test_pmull_1q_2d_2d(TyD);
+ if (0) test_pmull_8h_8b_8b(TyB);
+ if (0) test_pmull2_8h_16b_16b(TyB);
+ //if (0) test_pmull_1q_1d_1d(TyD);
+ //if (0) test_pmull_1q_2d_2d(TyD);
// rbit 16b,8b
// rev16 16b,8b
// rev32 16b,8b,8h,4h
// rev64 16b,8b,8h,4h,4s,2s
- test_rbit_16b_16b(TyB);
- test_rbit_8b_8b(TyB);
- test_rev16_16b_16b(TyB);
- test_rev16_8b_8b(TyB);
- test_rev32_16b_16b(TyB);
- test_rev32_8b_8b(TyB);
- test_rev32_8h_8h(TyH);
- test_rev32_4h_4h(TyH);
- test_rev64_16b_16b(TyB);
- test_rev64_8b_8b(TyB);
- test_rev64_8h_8h(TyH);
- test_rev64_4h_4h(TyH);
- test_rev64_4s_4s(TyS);
- test_rev64_2s_2s(TyS);
+ if (0) test_rbit_16b_16b(TyB);
+ if (0) test_rbit_8b_8b(TyB);
+ if (0) test_rev16_16b_16b(TyB);
+ if (0) test_rev16_8b_8b(TyB);
+ if (0) test_rev32_16b_16b(TyB);
+ if (0) test_rev32_8b_8b(TyB);
+ if (0) test_rev32_8h_8h(TyH);
+ if (0) test_rev32_4h_4h(TyH);
+ if (0) test_rev64_16b_16b(TyB);
+ if (0) test_rev64_8b_8b(TyB);
+ if (0) test_rev64_8h_8h(TyH);
+ if (0) test_rev64_4h_4h(TyH);
+ if (0) test_rev64_4s_4s(TyS);
+ if (0) test_rev64_2s_2s(TyS);
// saba 16b,8b,8h,4h,4s,2s
// uaba 16b,8b,8h,4h,4s,2s
- test_saba_4s_4s_4s(TyS);
- test_saba_2s_2s_2s(TyS);
- test_saba_8h_8h_8h(TyH);
- test_saba_4h_4h_4h(TyH);
- test_saba_16b_16b_16b(TyB);
- test_saba_8b_8b_8b(TyB);
- test_uaba_4s_4s_4s(TyS);
- test_uaba_2s_2s_2s(TyS);
- test_uaba_8h_8h_8h(TyH);
- test_uaba_4h_4h_4h(TyH);
- test_uaba_16b_16b_16b(TyB);
- test_uaba_8b_8b_8b(TyB);
+ if (0) test_saba_4s_4s_4s(TyS);
+ if (0) test_saba_2s_2s_2s(TyS);
+ if (0) test_saba_8h_8h_8h(TyH);
+ if (0) test_saba_4h_4h_4h(TyH);
+ if (0) test_saba_16b_16b_16b(TyB);
+ if (0) test_saba_8b_8b_8b(TyB);
+ if (0) test_uaba_4s_4s_4s(TyS);
+ if (0) test_uaba_2s_2s_2s(TyS);
+ if (0) test_uaba_8h_8h_8h(TyH);
+ if (0) test_uaba_4h_4h_4h(TyH);
+ if (0) test_uaba_16b_16b_16b(TyB);
+ if (0) test_uaba_8b_8b_8b(TyB);
// sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- test_sabal_2d_2s_2s(TyS);
- test_sabal2_2d_4s_4s(TyS);
- test_sabal_4s_4h_4h(TyH);
- test_sabal2_4s_8h_8h(TyH);
- test_sabal_8h_8b_8b(TyB);
- test_sabal2_8h_16b_16b(TyB);
- test_uabal_2d_2s_2s(TyS);
- test_uabal2_2d_4s_4s(TyS);
- test_uabal_4s_4h_4h(TyH);
- test_uabal2_4s_8h_8h(TyH);
- test_uabal_8h_8b_8b(TyB);
- test_uabal2_8h_16b_16b(TyB);
+ if (0) test_sabal_2d_2s_2s(TyS);
+ if (0) test_sabal2_2d_4s_4s(TyS);
+ if (0) test_sabal_4s_4h_4h(TyH);
+ if (0) test_sabal2_4s_8h_8h(TyH);
+ if (0) test_sabal_8h_8b_8b(TyB);
+ if (0) test_sabal2_8h_16b_16b(TyB);
+ if (0) test_uabal_2d_2s_2s(TyS);
+ if (0) test_uabal2_2d_4s_4s(TyS);
+ if (0) test_uabal_4s_4h_4h(TyH);
+ if (0) test_uabal2_4s_8h_8h(TyH);
+ if (0) test_uabal_8h_8b_8b(TyB);
+ if (0) test_uabal2_8h_16b_16b(TyB);
// sabd 16b,8b,8h,4h,4s,2s
// uabd 16b,8b,8h,4h,4s,2s
- test_sabd_4s_4s_4s(TyS);
- test_sabd_2s_2s_2s(TyS);
- test_sabd_8h_8h_8h(TyH);
- test_sabd_4h_4h_4h(TyH);
- test_sabd_16b_16b_16b(TyB);
- test_sabd_8b_8b_8b(TyB);
- test_uabd_4s_4s_4s(TyS);
- test_uabd_2s_2s_2s(TyS);
- test_uabd_8h_8h_8h(TyH);
- test_uabd_4h_4h_4h(TyH);
- test_uabd_16b_16b_16b(TyB);
- test_uabd_8b_8b_8b(TyB);
+ if (0) test_sabd_4s_4s_4s(TyS);
+ if (0) test_sabd_2s_2s_2s(TyS);
+ if (0) test_sabd_8h_8h_8h(TyH);
+ if (0) test_sabd_4h_4h_4h(TyH);
+ if (0) test_sabd_16b_16b_16b(TyB);
+ if (0) test_sabd_8b_8b_8b(TyB);
+ if (0) test_uabd_4s_4s_4s(TyS);
+ if (0) test_uabd_2s_2s_2s(TyS);
+ if (0) test_uabd_8h_8h_8h(TyH);
+ if (0) test_uabd_4h_4h_4h(TyH);
+ if (0) test_uabd_16b_16b_16b(TyB);
+ if (0) test_uabd_8b_8b_8b(TyB);
// sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- test_sabdl_2d_2s_2s(TyS);
- test_sabdl2_2d_4s_4s(TyS);
- test_sabdl_4s_4h_4h(TyH);
- test_sabdl2_4s_8h_8h(TyH);
- test_sabdl_8h_8b_8b(TyB);
- test_sabdl2_8h_16b_16b(TyB);
- test_uabdl_2d_2s_2s(TyS);
- test_uabdl2_2d_4s_4s(TyS);
- test_uabdl_4s_4h_4h(TyH);
- test_uabdl2_4s_8h_8h(TyH);
- test_uabdl_8h_8b_8b(TyB);
- test_uabdl2_8h_16b_16b(TyB);
+ if (0) test_sabdl_2d_2s_2s(TyS);
+ if (0) test_sabdl2_2d_4s_4s(TyS);
+ if (0) test_sabdl_4s_4h_4h(TyH);
+ if (0) test_sabdl2_4s_8h_8h(TyH);
+ if (0) test_sabdl_8h_8b_8b(TyB);
+ if (0) test_sabdl2_8h_16b_16b(TyB);
+ if (0) test_uabdl_2d_2s_2s(TyS);
+ if (0) test_uabdl2_2d_4s_4s(TyS);
+ if (0) test_uabdl_4s_4h_4h(TyH);
+ if (0) test_uabdl2_4s_8h_8h(TyH);
+ if (0) test_uabdl_8h_8b_8b(TyB);
+ if (0) test_uabdl2_8h_16b_16b(TyB);
// sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
// uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
- test_sadalp_1d_2s(TyS);
- test_sadalp_2d_4s(TyS);
- test_sadalp_2s_4h(TyH);
- test_sadalp_4s_8h(TyH);
- test_sadalp_4h_8b(TyB);
- test_sadalp_8h_16b(TyB);
- test_uadalp_1d_2s(TyS);
- test_uadalp_2d_4s(TyS);
- test_uadalp_2s_4h(TyH);
- test_uadalp_4s_8h(TyH);
- test_uadalp_4h_8b(TyB);
- test_uadalp_8h_16b(TyB);
+ if (0) test_sadalp_1d_2s(TyS);
+ if (0) test_sadalp_2d_4s(TyS);
+ if (0) test_sadalp_2s_4h(TyH);
+ if (0) test_sadalp_4s_8h(TyH);
+ if (0) test_sadalp_4h_8b(TyB);
+ if (0) test_sadalp_8h_16b(TyB);
+ if (0) test_uadalp_1d_2s(TyS);
+ if (0) test_uadalp_2d_4s(TyS);
+ if (0) test_uadalp_2s_4h(TyH);
+ if (0) test_uadalp_4s_8h(TyH);
+ if (0) test_uadalp_4h_8b(TyB);
+ if (0) test_uadalp_8h_16b(TyB);
// saddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- test_saddl_2d_2s_2s(TyS);
- test_saddl2_2d_4s_4s(TyS);
- test_saddl_4s_4h_4h(TyH);
- test_saddl2_4s_8h_8h(TyH);
- test_saddl_8h_8b_8b(TyB);
- test_saddl2_8h_16b_16b(TyB);
- test_uaddl_2d_2s_2s(TyS);
- test_uaddl2_2d_4s_4s(TyS);
- test_uaddl_4s_4h_4h(TyH);
- test_uaddl2_4s_8h_8h(TyH);
- test_uaddl_8h_8b_8b(TyB);
- test_uaddl2_8h_16b_16b(TyB);
- test_ssubl_2d_2s_2s(TyS);
- test_ssubl2_2d_4s_4s(TyS);
- test_ssubl_4s_4h_4h(TyH);
- test_ssubl2_4s_8h_8h(TyH);
- test_ssubl_8h_8b_8b(TyB);
- test_ssubl2_8h_16b_16b(TyB);
- test_usubl_2d_2s_2s(TyS);
- test_usubl2_2d_4s_4s(TyS);
- test_usubl_4s_4h_4h(TyH);
- test_usubl2_4s_8h_8h(TyH);
- test_usubl_8h_8b_8b(TyB);
- test_usubl2_8h_16b_16b(TyB);
+ if (0) test_saddl_2d_2s_2s(TyS);
+ if (0) test_saddl2_2d_4s_4s(TyS);
+ if (0) test_saddl_4s_4h_4h(TyH);
+ if (0) test_saddl2_4s_8h_8h(TyH);
+ if (0) test_saddl_8h_8b_8b(TyB);
+ if (0) test_saddl2_8h_16b_16b(TyB);
+ if (0) test_uaddl_2d_2s_2s(TyS);
+ if (0) test_uaddl2_2d_4s_4s(TyS);
+ if (0) test_uaddl_4s_4h_4h(TyH);
+ if (0) test_uaddl2_4s_8h_8h(TyH);
+ if (0) test_uaddl_8h_8b_8b(TyB);
+ if (0) test_uaddl2_8h_16b_16b(TyB);
+ if (0) test_ssubl_2d_2s_2s(TyS);
+ if (0) test_ssubl2_2d_4s_4s(TyS);
+ if (0) test_ssubl_4s_4h_4h(TyH);
+ if (0) test_ssubl2_4s_8h_8h(TyH);
+ if (0) test_ssubl_8h_8b_8b(TyB);
+ if (0) test_ssubl2_8h_16b_16b(TyB);
+ if (0) test_usubl_2d_2s_2s(TyS);
+ if (0) test_usubl2_2d_4s_4s(TyS);
+ if (0) test_usubl_4s_4h_4h(TyH);
+ if (0) test_usubl2_4s_8h_8h(TyH);
+ if (0) test_usubl_8h_8b_8b(TyB);
+ if (0) test_usubl2_8h_16b_16b(TyB);
// saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
// uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
- test_saddlp_1d_2s(TyS);
- test_saddlp_2d_4s(TyS);
- test_saddlp_2s_4h(TyH);
- test_saddlp_4s_8h(TyH);
- test_saddlp_4h_8b(TyB);
- test_saddlp_8h_16b(TyB);
- test_uaddlp_1d_2s(TyS);
- test_uaddlp_2d_4s(TyS);
- test_uaddlp_2s_4h(TyH);
- test_uaddlp_4s_8h(TyH);
- test_uaddlp_4h_8b(TyB);
- test_uaddlp_8h_16b(TyB);
+ if (0) test_saddlp_1d_2s(TyS);
+ if (0) test_saddlp_2d_4s(TyS);
+ if (0) test_saddlp_2s_4h(TyH);
+ if (0) test_saddlp_4s_8h(TyH);
+ if (0) test_saddlp_4h_8b(TyB);
+ if (0) test_saddlp_8h_16b(TyB);
+ if (0) test_uaddlp_1d_2s(TyS);
+ if (0) test_uaddlp_2d_4s(TyS);
+ if (0) test_uaddlp_2s_4h(TyH);
+ if (0) test_uaddlp_4s_8h(TyH);
+ if (0) test_uaddlp_4h_8b(TyB);
+ if (0) test_uaddlp_8h_16b(TyB);
// saddlv h_16b/8b, s_8h/4h, d_4s
// uaddlv h_16b/8b, s_8h/4h, d_4s
- test_saddlv_h_16b(TyB);
- test_saddlv_h_8b(TyB);
- test_saddlv_s_8h(TyH);
- test_saddlv_s_4h(TyH);
- test_saddlv_d_4s(TyH);
- test_uaddlv_h_16b(TyB);
- test_uaddlv_h_8b(TyB);
- test_uaddlv_s_8h(TyH);
- test_uaddlv_s_4h(TyH);
- test_uaddlv_d_4s(TyH);
+ if (0) test_saddlv_h_16b(TyB);
+ if (0) test_saddlv_h_8b(TyB);
+ if (0) test_saddlv_s_8h(TyH);
+ if (0) test_saddlv_s_4h(TyH);
+ if (0) test_saddlv_d_4s(TyH);
+ if (0) test_uaddlv_h_16b(TyB);
+ if (0) test_uaddlv_h_8b(TyB);
+ if (0) test_uaddlv_s_8h(TyH);
+ if (0) test_uaddlv_s_4h(TyH);
+ if (0) test_uaddlv_d_4s(TyH);
// saddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
// uaddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
// ssubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
// usubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
- test_saddw2_8h_8h_16b(TyB);
- test_saddw_8h_8h_8b(TyB);
- test_saddw2_4s_4s_8h(TyH);
- test_saddw_4s_4s_4h(TyH);
- test_saddw2_2d_2d_4s(TyS);
- test_saddw_2d_2d_2s(TyS);
- test_uaddw2_8h_8h_16b(TyB);
- test_uaddw_8h_8h_8b(TyB);
- test_uaddw2_4s_4s_8h(TyH);
- test_uaddw_4s_4s_4h(TyH);
- test_uaddw2_2d_2d_4s(TyS);
- test_uaddw_2d_2d_2s(TyS);
- test_ssubw2_8h_8h_16b(TyB);
- test_ssubw_8h_8h_8b(TyB);
- test_ssubw2_4s_4s_8h(TyH);
- test_ssubw_4s_4s_4h(TyH);
- test_ssubw2_2d_2d_4s(TyS);
- test_ssubw_2d_2d_2s(TyS);
- test_usubw2_8h_8h_16b(TyB);
- test_usubw_8h_8h_8b(TyB);
- test_usubw2_4s_4s_8h(TyH);
- test_usubw_4s_4s_4h(TyH);
- test_usubw2_2d_2d_4s(TyS);
- test_usubw_2d_2d_2s(TyS);
+ if (0) test_saddw2_8h_8h_16b(TyB);
+ if (0) test_saddw_8h_8h_8b(TyB);
+ if (0) test_saddw2_4s_4s_8h(TyH);
+ if (0) test_saddw_4s_4s_4h(TyH);
+ if (0) test_saddw2_2d_2d_4s(TyS);
+ if (0) test_saddw_2d_2d_2s(TyS);
+ if (0) test_uaddw2_8h_8h_16b(TyB);
+ if (0) test_uaddw_8h_8h_8b(TyB);
+ if (0) test_uaddw2_4s_4s_8h(TyH);
+ if (0) test_uaddw_4s_4s_4h(TyH);
+ if (0) test_uaddw2_2d_2d_4s(TyS);
+ if (0) test_uaddw_2d_2d_2s(TyS);
+ if (0) test_ssubw2_8h_8h_16b(TyB);
+ if (0) test_ssubw_8h_8h_8b(TyB);
+ if (0) test_ssubw2_4s_4s_8h(TyH);
+ if (0) test_ssubw_4s_4s_4h(TyH);
+ if (0) test_ssubw2_2d_2d_4s(TyS);
+ if (0) test_ssubw_2d_2d_2s(TyS);
+ if (0) test_usubw2_8h_8h_16b(TyB);
+ if (0) test_usubw_8h_8h_8b(TyB);
+ if (0) test_usubw2_4s_4s_8h(TyH);
+ if (0) test_usubw_4s_4s_4h(TyH);
+ if (0) test_usubw2_2d_2d_4s(TyS);
+ if (0) test_usubw_2d_2d_2s(TyS);
// shadd 16b,8b,8h,4h,4s,2s
// uhadd 16b,8b,8h,4h,4s,2s
// shsub 16b,8b,8h,4h,4s,2s
// uhsub 16b,8b,8h,4h,4s,2s
- test_shadd_4s_4s_4s(TyS);
- test_shadd_2s_2s_2s(TyS);
- test_shadd_8h_8h_8h(TyH);
- test_shadd_4h_4h_4h(TyH);
- test_shadd_16b_16b_16b(TyB);
- test_shadd_8b_8b_8b(TyB);
- test_uhadd_4s_4s_4s(TyS);
- test_uhadd_2s_2s_2s(TyS);
- test_uhadd_8h_8h_8h(TyH);
- test_uhadd_4h_4h_4h(TyH);
- test_uhadd_16b_16b_16b(TyB);
- test_uhadd_8b_8b_8b(TyB);
- test_shsub_4s_4s_4s(TyS);
- test_shsub_2s_2s_2s(TyS);
- test_shsub_8h_8h_8h(TyH);
- test_shsub_4h_4h_4h(TyH);
- test_shsub_16b_16b_16b(TyB);
- test_shsub_8b_8b_8b(TyB);
- test_uhsub_4s_4s_4s(TyS);
- test_uhsub_2s_2s_2s(TyS);
- test_uhsub_8h_8h_8h(TyH);
- test_uhsub_4h_4h_4h(TyH);
- test_uhsub_16b_16b_16b(TyB);
- test_uhsub_8b_8b_8b(TyB);
+ if (0) test_shadd_4s_4s_4s(TyS);
+ if (0) test_shadd_2s_2s_2s(TyS);
+ if (0) test_shadd_8h_8h_8h(TyH);
+ if (0) test_shadd_4h_4h_4h(TyH);
+ if (0) test_shadd_16b_16b_16b(TyB);
+ if (0) test_shadd_8b_8b_8b(TyB);
+ if (0) test_uhadd_4s_4s_4s(TyS);
+ if (0) test_uhadd_2s_2s_2s(TyS);
+ if (0) test_uhadd_8h_8h_8h(TyH);
+ if (0) test_uhadd_4h_4h_4h(TyH);
+ if (0) test_uhadd_16b_16b_16b(TyB);
+ if (0) test_uhadd_8b_8b_8b(TyB);
+ if (0) test_shsub_4s_4s_4s(TyS);
+ if (0) test_shsub_2s_2s_2s(TyS);
+ if (0) test_shsub_8h_8h_8h(TyH);
+ if (0) test_shsub_4h_4h_4h(TyH);
+ if (0) test_shsub_16b_16b_16b(TyB);
+ if (0) test_shsub_8b_8b_8b(TyB);
+ if (0) test_uhsub_4s_4s_4s(TyS);
+ if (0) test_uhsub_2s_2s_2s(TyS);
+ if (0) test_uhsub_8h_8h_8h(TyH);
+ if (0) test_uhsub_4h_4h_4h(TyH);
+ if (0) test_uhsub_16b_16b_16b(TyB);
+ if (0) test_uhsub_8b_8b_8b(TyB);
// shll{2} 8h_8b/16b_#8, 4s_4h/8h_#16, 2d_2s/4s_#32
- test_shll_8h_8b_8(TyB);
- test_shll2_8h_16b_8(TyB);
- test_shll_4s_4h_16(TyH);
- test_shll2_4s_8h_16(TyH);
- test_shll_2d_2s_32(TyS);
- test_shll2_2d_4s_32(TyS);
+ if (0) test_shll_8h_8b_8(TyB);
+ if (0) test_shll2_8h_16b_8(TyB);
+ if (0) test_shll_4s_4h_16(TyH);
+ if (0) test_shll2_4s_8h_16(TyH);
+ if (0) test_shll_2d_2s_32(TyS);
+ if (0) test_shll2_2d_4s_32(TyS);
// shrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits
// rshrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits
- test_shrn_2s_2d_1(TyD);
- test_shrn_2s_2d_32(TyD);
- test_shrn2_4s_2d_1(TyD);
- test_shrn2_4s_2d_32(TyD);
- test_shrn_4h_4s_1(TyS);
- test_shrn_4h_4s_16(TyS);
- test_shrn2_8h_4s_1(TyS);
- test_shrn2_8h_4s_16(TyS);
- test_shrn_8b_8h_1(TyH);
- test_shrn_8b_8h_8(TyH);
- test_shrn2_16b_8h_1(TyH);
- test_shrn2_16b_8h_8(TyH);
- test_rshrn_2s_2d_1(TyD);
- test_rshrn_2s_2d_32(TyD);
- test_rshrn2_4s_2d_1(TyD);
- test_rshrn2_4s_2d_32(TyD);
- test_rshrn_4h_4s_1(TyS);
- test_rshrn_4h_4s_16(TyS);
- test_rshrn2_8h_4s_1(TyS);
- test_rshrn2_8h_4s_16(TyS);
- test_rshrn_8b_8h_1(TyH);
- test_rshrn_8b_8h_8(TyH);
- test_rshrn2_16b_8h_1(TyH);
- test_rshrn2_16b_8h_8(TyH);
+ if (0) test_shrn_2s_2d_1(TyD);
+ if (0) test_shrn_2s_2d_32(TyD);
+ if (0) test_shrn2_4s_2d_1(TyD);
+ if (0) test_shrn2_4s_2d_32(TyD);
+ if (0) test_shrn_4h_4s_1(TyS);
+ if (0) test_shrn_4h_4s_16(TyS);
+ if (0) test_shrn2_8h_4s_1(TyS);
+ if (0) test_shrn2_8h_4s_16(TyS);
+ if (0) test_shrn_8b_8h_1(TyH);
+ if (0) test_shrn_8b_8h_8(TyH);
+ if (0) test_shrn2_16b_8h_1(TyH);
+ if (0) test_shrn2_16b_8h_8(TyH);
+ if (0) test_rshrn_2s_2d_1(TyD);
+ if (0) test_rshrn_2s_2d_32(TyD);
+ if (0) test_rshrn2_4s_2d_1(TyD);
+ if (0) test_rshrn2_4s_2d_32(TyD);
+ if (0) test_rshrn_4h_4s_1(TyS);
+ if (0) test_rshrn_4h_4s_16(TyS);
+ if (0) test_rshrn2_8h_4s_1(TyS);
+ if (0) test_rshrn2_8h_4s_16(TyS);
+ if (0) test_rshrn_8b_8h_1(TyH);
+ if (0) test_rshrn_8b_8h_8(TyH);
+ if (0) test_rshrn2_16b_8h_1(TyH);
+ if (0) test_rshrn2_16b_8h_8(TyH);
// sli d_#imm
// sri d_#imm
- test_sli_d_d_0(TyD);
- test_sli_d_d_32(TyD);
- test_sli_d_d_63(TyD);
- test_sri_d_d_1(TyD);
- test_sri_d_d_33(TyD);
- test_sri_d_d_64(TyD);
+ if (0) test_sli_d_d_0(TyD);
+ if (0) test_sli_d_d_32(TyD);
+ if (0) test_sli_d_d_63(TyD);
+ if (0) test_sri_d_d_1(TyD);
+ if (0) test_sri_d_d_33(TyD);
+ if (0) test_sri_d_d_64(TyD);
// sli 2d,4s,2s,8h,4h,16b,8b _#imm
// sri 2d,4s,2s,8h,4h,16b,8b _#imm
- test_sli_2d_2d_0(TyD);
- test_sli_2d_2d_32(TyD);
- test_sli_2d_2d_63(TyD);
- test_sli_4s_4s_0(TyS);
- test_sli_4s_4s_16(TyS);
- test_sli_4s_4s_31(TyS);
- test_sli_2s_2s_0(TyS);
- test_sli_2s_2s_16(TyS);
- test_sli_2s_2s_31(TyS);
- test_sli_8h_8h_0(TyH);
- test_sli_8h_8h_8(TyH);
- test_sli_8h_8h_15(TyH);
- test_sli_4h_4h_0(TyH);
- test_sli_4h_4h_8(TyH);
- test_sli_4h_4h_15(TyH);
- test_sli_16b_16b_0(TyB);
- test_sli_16b_16b_3(TyB);
- test_sli_16b_16b_7(TyB);
- test_sli_8b_8b_0(TyB);
- test_sli_8b_8b_3(TyB);
- test_sli_8b_8b_7(TyB);
- test_sri_2d_2d_1(TyD);
- test_sri_2d_2d_33(TyD);
- test_sri_2d_2d_64(TyD);
- test_sri_4s_4s_1(TyS);
- test_sri_4s_4s_17(TyS);
- test_sri_4s_4s_32(TyS);
- test_sri_2s_2s_1(TyS);
- test_sri_2s_2s_17(TyS);
- test_sri_2s_2s_32(TyS);
- test_sri_8h_8h_1(TyH);
- test_sri_8h_8h_8(TyH);
- test_sri_8h_8h_16(TyH);
- test_sri_4h_4h_1(TyH);
- test_sri_4h_4h_8(TyH);
- test_sri_4h_4h_16(TyH);
- test_sri_16b_16b_1(TyB);
- test_sri_16b_16b_4(TyB);
- test_sri_16b_16b_8(TyB);
- test_sri_8b_8b_1(TyB);
- test_sri_8b_8b_4(TyB);
- test_sri_8b_8b_8(TyB);
+ if (0) test_sli_2d_2d_0(TyD);
+ if (0) test_sli_2d_2d_32(TyD);
+ if (0) test_sli_2d_2d_63(TyD);
+ if (0) test_sli_4s_4s_0(TyS);
+ if (0) test_sli_4s_4s_16(TyS);
+ if (0) test_sli_4s_4s_31(TyS);
+ if (0) test_sli_2s_2s_0(TyS);
+ if (0) test_sli_2s_2s_16(TyS);
+ if (0) test_sli_2s_2s_31(TyS);
+ if (0) test_sli_8h_8h_0(TyH);
+ if (0) test_sli_8h_8h_8(TyH);
+ if (0) test_sli_8h_8h_15(TyH);
+ if (0) test_sli_4h_4h_0(TyH);
+ if (0) test_sli_4h_4h_8(TyH);
+ if (0) test_sli_4h_4h_15(TyH);
+ if (0) test_sli_16b_16b_0(TyB);
+ if (0) test_sli_16b_16b_3(TyB);
+ if (0) test_sli_16b_16b_7(TyB);
+ if (0) test_sli_8b_8b_0(TyB);
+ if (0) test_sli_8b_8b_3(TyB);
+ if (0) test_sli_8b_8b_7(TyB);
+ if (0) test_sri_2d_2d_1(TyD);
+ if (0) test_sri_2d_2d_33(TyD);
+ if (0) test_sri_2d_2d_64(TyD);
+ if (0) test_sri_4s_4s_1(TyS);
+ if (0) test_sri_4s_4s_17(TyS);
+ if (0) test_sri_4s_4s_32(TyS);
+ if (0) test_sri_2s_2s_1(TyS);
+ if (0) test_sri_2s_2s_17(TyS);
+ if (0) test_sri_2s_2s_32(TyS);
+ if (0) test_sri_8h_8h_1(TyH);
+ if (0) test_sri_8h_8h_8(TyH);
+ if (0) test_sri_8h_8h_16(TyH);
+ if (0) test_sri_4h_4h_1(TyH);
+ if (0) test_sri_4h_4h_8(TyH);
+ if (0) test_sri_4h_4h_16(TyH);
+ if (0) test_sri_16b_16b_1(TyB);
+ if (0) test_sri_16b_16b_4(TyB);
+ if (0) test_sri_16b_16b_8(TyB);
+ if (0) test_sri_8b_8b_1(TyB);
+ if (0) test_sri_8b_8b_4(TyB);
+ if (0) test_sri_8b_8b_8(TyB);
// smax 4s,2s,8h,4h,16b,8b
// umax 4s,2s,8h,4h,16b,8b
// smin 4s,2s,8h,4h,16b,8b
// umin 4s,2s,8h,4h,16b,8b
- test_smax_4s_4s_4s(TyS);
- test_smax_2s_2s_2s(TyS);
- test_smax_8h_8h_8h(TyH);
- test_smax_4h_4h_4h(TyH);
- test_smax_16b_16b_16b(TyB);
- test_smax_8b_8b_8b(TyB);
- test_umax_4s_4s_4s(TyS);
- test_umax_2s_2s_2s(TyS);
- test_umax_8h_8h_8h(TyH);
- test_umax_4h_4h_4h(TyH);
- test_umax_16b_16b_16b(TyB);
- test_umax_8b_8b_8b(TyB);
- test_smin_4s_4s_4s(TyS);
- test_smin_2s_2s_2s(TyS);
- test_smin_8h_8h_8h(TyH);
- test_smin_4h_4h_4h(TyH);
- test_smin_16b_16b_16b(TyB);
- test_smin_8b_8b_8b(TyB);
- test_umin_4s_4s_4s(TyS);
- test_umin_2s_2s_2s(TyS);
- test_umin_8h_8h_8h(TyH);
- test_umin_4h_4h_4h(TyH);
- test_umin_16b_16b_16b(TyB);
- test_umin_8b_8b_8b(TyB);
+ if (1) test_smax_4s_4s_4s(TyS);
+ if (1) test_smax_2s_2s_2s(TyS);
+ if (1) test_smax_8h_8h_8h(TyH);
+ if (1) test_smax_4h_4h_4h(TyH);
+ if (1) test_smax_16b_16b_16b(TyB);
+ if (1) test_smax_8b_8b_8b(TyB);
+ if (1) test_umax_4s_4s_4s(TyS);
+ if (1) test_umax_2s_2s_2s(TyS);
+ if (1) test_umax_8h_8h_8h(TyH);
+ if (1) test_umax_4h_4h_4h(TyH);
+ if (1) test_umax_16b_16b_16b(TyB);
+ if (1) test_umax_8b_8b_8b(TyB);
+ if (1) test_smin_4s_4s_4s(TyS);
+ if (1) test_smin_2s_2s_2s(TyS);
+ if (1) test_smin_8h_8h_8h(TyH);
+ if (1) test_smin_4h_4h_4h(TyH);
+ if (1) test_smin_16b_16b_16b(TyB);
+ if (1) test_smin_8b_8b_8b(TyB);
+ if (1) test_umin_4s_4s_4s(TyS);
+ if (1) test_umin_2s_2s_2s(TyS);
+ if (1) test_umin_8h_8h_8h(TyH);
+ if (1) test_umin_4h_4h_4h(TyH);
+ if (1) test_umin_16b_16b_16b(TyB);
+ if (1) test_umin_8b_8b_8b(TyB);
// smaxp 4s,2s,8h,4h,16b,8b
// umaxp 4s,2s,8h,4h,16b,8b
// sminp 4s,2s,8h,4h,16b,8b
// uminp 4s,2s,8h,4h,16b,8b
- test_smaxp_4s_4s_4s(TyS);
- test_smaxp_2s_2s_2s(TyS);
- test_smaxp_8h_8h_8h(TyH);
- test_smaxp_4h_4h_4h(TyH);
- test_smaxp_16b_16b_16b(TyB);
- test_smaxp_8b_8b_8b(TyB);
- test_umaxp_4s_4s_4s(TyS);
- test_umaxp_2s_2s_2s(TyS);
- test_umaxp_8h_8h_8h(TyH);
- test_umaxp_4h_4h_4h(TyH);
- test_umaxp_16b_16b_16b(TyB);
- test_umaxp_8b_8b_8b(TyB);
- test_sminp_4s_4s_4s(TyS);
- test_sminp_2s_2s_2s(TyS);
- test_sminp_8h_8h_8h(TyH);
- test_sminp_4h_4h_4h(TyH);
- test_sminp_16b_16b_16b(TyB);
- test_sminp_8b_8b_8b(TyB);
- test_uminp_4s_4s_4s(TyS);
- test_uminp_2s_2s_2s(TyS);
- test_uminp_8h_8h_8h(TyH);
- test_uminp_4h_4h_4h(TyH);
- test_uminp_16b_16b_16b(TyB);
- test_uminp_8b_8b_8b(TyB);
+ if (0) test_smaxp_4s_4s_4s(TyS);
+ if (0) test_smaxp_2s_2s_2s(TyS);
+ if (0) test_smaxp_8h_8h_8h(TyH);
+ if (0) test_smaxp_4h_4h_4h(TyH);
+ if (0) test_smaxp_16b_16b_16b(TyB);
+ if (0) test_smaxp_8b_8b_8b(TyB);
+ if (0) test_umaxp_4s_4s_4s(TyS);
+ if (0) test_umaxp_2s_2s_2s(TyS);
+ if (0) test_umaxp_8h_8h_8h(TyH);
+ if (0) test_umaxp_4h_4h_4h(TyH);
+ if (0) test_umaxp_16b_16b_16b(TyB);
+ if (0) test_umaxp_8b_8b_8b(TyB);
+ if (0) test_sminp_4s_4s_4s(TyS);
+ if (0) test_sminp_2s_2s_2s(TyS);
+ if (0) test_sminp_8h_8h_8h(TyH);
+ if (0) test_sminp_4h_4h_4h(TyH);
+ if (0) test_sminp_16b_16b_16b(TyB);
+ if (0) test_sminp_8b_8b_8b(TyB);
+ if (0) test_uminp_4s_4s_4s(TyS);
+ if (0) test_uminp_2s_2s_2s(TyS);
+ if (0) test_uminp_8h_8h_8h(TyH);
+ if (0) test_uminp_4h_4h_4h(TyH);
+ if (0) test_uminp_16b_16b_16b(TyB);
+ if (0) test_uminp_8b_8b_8b(TyB);
// smaxv s_4s,h_8h,h_4h,b_16b,b_8b
// umaxv s_4s,h_8h,h_4h,b_16b,b_8b
// sminv s_4s,h_8h,h_4h,b_16b,b_8b
// uminv s_4s,h_8h,h_4h,b_16b,b_8b
- test_SMAXV();
- test_UMAXV();
- test_SMINV();
- test_UMINV();
+ if (1) test_SMAXV();
+ if (1) test_UMAXV();
+ if (1) test_SMINV();
+ if (1) test_UMINV();
// smlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
// umlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
@@ -4080,54 +4080,54 @@
// umlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
// smull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
// umull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
- test_smlal_2d_2s_s0(TyS);
- test_smlal_2d_2s_s3(TyS);
- test_smlal2_2d_4s_s1(TyS);
- test_smlal2_2d_4s_s2(TyS);
- test_smlal_4s_4h_h0(TyH);
- test_smlal_4s_4h_h7(TyH);
- test_smlal2_4s_8h_h1(TyH);
- test_smlal2_4s_8h_h4(TyH);
- test_umlal_2d_2s_s0(TyS);
- test_umlal_2d_2s_s3(TyS);
- test_umlal2_2d_4s_s1(TyS);
- test_umlal2_2d_4s_s2(TyS);
- test_umlal_4s_4h_h0(TyH);
- test_umlal_4s_4h_h7(TyH);
- test_umlal2_4s_8h_h1(TyH);
- test_umlal2_4s_8h_h4(TyH);
- test_smlsl_2d_2s_s0(TyS);
- test_smlsl_2d_2s_s3(TyS);
- test_smlsl2_2d_4s_s1(TyS);
- test_smlsl2_2d_4s_s2(TyS);
- test_smlsl_4s_4h_h0(TyH);
- test_smlsl_4s_4h_h7(TyH);
- test_smlsl2_4s_8h_h1(TyH);
- test_smlsl2_4s_8h_h4(TyH);
- test_umlsl_2d_2s_s0(TyS);
- test_umlsl_2d_2s_s3(TyS);
- test_umlsl2_2d_4s_s1(TyS);
- test_umlsl2_2d_4s_s2(TyS);
- test_umlsl_4s_4h_h0(TyH);
- test_umlsl_4s_4h_h7(TyH);
- test_umlsl2_4s_8h_h1(TyH);
- test_umlsl2_4s_8h_h4(TyH);
- test_smull_2d_2s_s0(TyS);
- test_smull_2d_2s_s3(TyS);
- test_smull2_2d_4s_s1(TyS);
- test_smull2_2d_4s_s2(TyS);
- test_smull_4s_4h_h0(TyH);
- test_smull_4s_4h_h7(TyH);
- test_smull2_4s_8h_h1(TyH);
- test_smull2_4s_8h_h4(TyH);
- test_umull_2d_2s_s0(TyS);
- test_umull_2d_2s_s3(TyS);
- test_umull2_2d_4s_s1(TyS);
- test_umull2_2d_4s_s2(TyS);
- test_umull_4s_4h_h0(TyH);
- test_umull_4s_4h_h7(TyH);
- test_umull2_4s_8h_h1(TyH);
- test_umull2_4s_8h_h4(TyH);
+ if (0) test_smlal_2d_2s_s0(TyS);
+ if (0) test_smlal_2d_2s_s3(TyS);
+ if (0) test_smlal2_2d_4s_s1(TyS);
+ if (0) test_smlal2_2d_4s_s2(TyS);
+ if (0) test_smlal_4s_4h_h0(TyH);
+ if (0) test_smlal_4s_4h_h7(TyH);
+ if (0) test_smlal2_4s_8h_h1(TyH);
+ if (0) test_smlal2_4s_8h_h4(TyH);
+ if (0) test_umlal_2d_2s_s0(TyS);
+ if (0) test_umlal_2d_2s_s3(TyS);
+ if (0) test_umlal2_2d_4s_s1(TyS);
+ if (0) test_umlal2_2d_4s_s2(TyS);
+ if (0) test_umlal_4s_4h_h0(TyH);
+ if (0) test_umlal_4s_4h_h7(TyH);
+ if (0) test_umlal2_4s_8h_h1(TyH);
+ if (0) test_umlal2_4s_8h_h4(TyH);
+ if (0) test_smlsl_2d_2s_s0(TyS);
+ if (0) test_smlsl_2d_2s_s3(TyS);
+ if (0) test_smlsl2_2d_4s_s1(TyS);
+ if (0) test_smlsl2_2d_4s_s2(TyS);
+ if (0) test_smlsl_4s_4h_h0(TyH);
+ if (0) test_smlsl_4s_4h_h7(TyH);
+ if (0) test_smlsl2_4s_8h_h1(TyH);
+ if (0) test_smlsl2_4s_8h_h4(TyH);
+ if (0) test_umlsl_2d_2s_s0(TyS);
+ if (0) test_umlsl_2d_2s_s3(TyS);
+ if (0) test_umlsl2_2d_4s_s1(TyS);
+ if (0) test_umlsl2_2d_4s_s2(TyS);
+ if (0) test_umlsl_4s_4h_h0(TyH);
+ if (0) test_umlsl_4s_4h_h7(TyH);
+ if (0) test_umlsl2_4s_8h_h1(TyH);
+ if (0) test_umlsl2_4s_8h_h4(TyH);
+ if (0) test_smull_2d_2s_s0(TyS);
+ if (0) test_smull_2d_2s_s3(TyS);
+ if (0) test_smull2_2d_4s_s1(TyS);
+ if (0) test_smull2_2d_4s_s2(TyS);
+ if (0) test_smull_4s_4h_h0(TyH);
+ if (0) test_smull_4s_4h_h7(TyH);
+ if (0) test_smull2_4s_8h_h1(TyH);
+ if (0) test_smull2_4s_8h_h4(TyH);
+ if (0) test_umull_2d_2s_s0(TyS);
+ if (0) test_umull_2d_2s_s3(TyS);
+ if (0) test_umull2_2d_4s_s1(TyS);
+ if (0) test_umull2_2d_4s_s2(TyS);
+ if (0) test_umull_4s_4h_h0(TyH);
+ if (0) test_umull_4s_4h_h7(TyH);
+ if (0) test_umull2_4s_8h_h1(TyH);
+ if (0) test_umull2_4s_8h_h4(TyH);
// smlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// umlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
@@ -4135,317 +4135,317 @@
// umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- test_smlal_2d_2s_2s(TyS);
- test_smlal2_2d_4s_4s(TyS);
- test_smlal_4s_4h_4h(TyH);
- test_smlal2_4s_8h_8h(TyH);
- test_smlal_8h_8b_8b(TyB);
- test_smlal2_8h_16b_16b(TyB);
- test_umlal_2d_2s_2s(TyS);
- test_umlal2_2d_4s_4s(TyS);
- test_umlal_4s_4h_4h(TyH);
- test_umlal2_4s_8h_8h(TyH);
- test_umlal_8h_8b_8b(TyB);
- test_umlal2_8h_16b_16b(TyB);
- test_smlsl_2d_2s_2s(TyS);
- test_smlsl2_2d_4s_4s(TyS);
- test_smlsl_4s_4h_4h(TyH);
- test_smlsl2_4s_8h_8h(TyH);
- test_smlsl_8h_8b_8b(TyB);
- test_smlsl2_8h_16b_16b(TyB);
- test_umlsl_2d_2s_2s(TyS);
- test_umlsl2_2d_4s_4s(TyS);
- test_umlsl_4s_4h_4h(TyH);
- test_umlsl2_4s_8h_8h(TyH);
- test_umlsl_8h_8b_8b(TyB);
- test_umlsl2_8h_16b_16b(TyB);
- test_smull_2d_2...
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