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From: <sv...@va...> - 2014-06-28 22:12:44
|
Author: sewardj
Date: Sat Jun 28 22:12:34 2014
New Revision: 14120
Log:
Track vex r2894 (representation changes to arm64 FPSR)
Modified:
trunk/coregrind/m_gdbserver/valgrind-low-arm64.c
trunk/memcheck/mc_machine.c
Modified: trunk/coregrind/m_gdbserver/valgrind-low-arm64.c
==============================================================================
--- trunk/coregrind/m_gdbserver/valgrind-low-arm64.c (original)
+++ trunk/coregrind/m_gdbserver/valgrind-low-arm64.c Sat Jun 28 22:12:34 2014
@@ -217,7 +217,22 @@
case 63: VG_(transfer) (&arm->guest_Q29, buf, dir, size, mod); break;
case 64: VG_(transfer) (&arm->guest_Q30, buf, dir, size, mod); break;
case 65: VG_(transfer) (&arm->guest_Q31, buf, dir, size, mod); break;
- case 66: VG_(transfer) (&arm->guest_FPSR, buf, dir, size, mod); break;
+ case 66: {
+ /* The ARM64 FPSR representation is not the same as the
+ architecturally defined representation. Hence use conversion
+ functions to convert to/from it. */
+ if (dir == valgrind_to_gdbserver) {
+ ULong fpsr = LibVEX_GuestARM64_get_fpsr(arm);
+ // XXX FIXME what if size != 8 ? Does this still work?
+ VG_(transfer) (&fpsr, buf, dir, size, mod);
+ } else {
+ // XXX FIXME what if size != 8 ? Does this still work?
+ ULong fpsr = 0;
+ VG_(transfer) (&fpsr, buf, dir, size, mod);
+ LibVEX_GuestARM64_set_fpsr(arm, fpsr);
+ }
+ break;
+ }
case 67: VG_(transfer) (&arm->guest_FPCR, buf, dir, size, mod); break;
default: vg_assert(0);
}
Modified: trunk/memcheck/mc_machine.c
==============================================================================
--- trunk/memcheck/mc_machine.c (original)
+++ trunk/memcheck/mc_machine.c Sat Jun 28 22:12:34 2014
@@ -1053,7 +1053,7 @@
if (o >= GOF(Q31) && o+sz <= GOF(Q31)+SZB(Q31)) return GOF(Q31);
if (o == GOF(FPCR) && sz == 4) return -1; // untracked
- if (o == GOF(FPSR) && sz == 4) return -1; // untracked
+ if (o == GOF(QCFLAG) && sz == 16) return o;
if (o == GOF(CMSTART) && sz == 8) return -1; // untracked
if (o == GOF(CMLEN) && sz == 8) return -1; // untracked
|
|
From: <sv...@va...> - 2014-06-28 22:11:31
|
Author: sewardj
Date: Sat Jun 28 22:11:16 2014
New Revision: 2894
Log:
arm64: change the representation of FPSR.QC so that it can be
used efficiently to record SIMD saturation, and remove support
for all other bits of FPSR, since we don't model them anyway.
Modified:
trunk/priv/guest_arm64_helpers.c
trunk/priv/guest_arm64_toIR.c
trunk/pub/libvex_guest_arm64.h
Modified: trunk/priv/guest_arm64_helpers.c
==============================================================================
--- trunk/priv/guest_arm64_helpers.c (original)
+++ trunk/priv/guest_arm64_helpers.c Sat Jun 28 22:11:16 2014
@@ -1178,6 +1178,28 @@
}
/* VISIBLE TO LIBVEX CLIENT */
+ULong LibVEX_GuestARM64_get_fpsr ( const VexGuestARM64State* vex_state )
+{
+ UInt w32 = vex_state->guest_QCFLAG[0] | vex_state->guest_QCFLAG[1]
+ | vex_state->guest_QCFLAG[2] | vex_state->guest_QCFLAG[3];
+ ULong fpsr = 0;
+ // QC
+ if (w32 != 0)
+ fpsr |= (1 << 27);
+ return fpsr;
+}
+
+void LibVEX_GuestARM64_set_fpsr ( /*MOD*/VexGuestARM64State* vex_state,
+ ULong fpsr )
+{
+ // QC
+ vex_state->guest_QCFLAG[0] = (UInt)((fpsr >> 27) & 1);
+ vex_state->guest_QCFLAG[1] = 0;
+ vex_state->guest_QCFLAG[2] = 0;
+ vex_state->guest_QCFLAG[3] = 0;
+}
+
+/* VISIBLE TO LIBVEX CLIENT */
void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state )
{
vex_bzero(vex_state, sizeof(*vex_state));
@@ -1345,7 +1367,7 @@
/* Describe any sections to be regarded by Memcheck as
'always-defined'. */
- .n_alwaysDefd = 10,
+ .n_alwaysDefd = 9,
/* flags thunk: OP is always defd, whereas DEP1 and DEP2
have to be tracked. See detailed comment in gdefs.h on
@@ -1359,8 +1381,7 @@
/* 5 */ ALWAYSDEFD(guest_CMLEN),
/* 6 */ ALWAYSDEFD(guest_NRADDR),
/* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL),
- /* 8 */ ALWAYSDEFD(guest_FPCR),
- /* 9 */ ALWAYSDEFD(guest_FPSR)
+ /* 8 */ ALWAYSDEFD(guest_TPIDR_EL0)
}
};
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Sat Jun 28 22:11:16 2014
@@ -697,14 +697,7 @@
#define OFFB_Q31 offsetof(VexGuestARM64State,guest_Q31)
#define OFFB_FPCR offsetof(VexGuestARM64State,guest_FPCR)
-#define OFFB_FPSR offsetof(VexGuestARM64State,guest_FPSR)
-//ZZ #define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO)
-//ZZ #define OFFB_ITSTATE offsetof(VexGuestARMState,guest_ITSTATE)
-//ZZ #define OFFB_QFLAG32 offsetof(VexGuestARMState,guest_QFLAG32)
-//ZZ #define OFFB_GEFLAG0 offsetof(VexGuestARMState,guest_GEFLAG0)
-//ZZ #define OFFB_GEFLAG1 offsetof(VexGuestARMState,guest_GEFLAG1)
-//ZZ #define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2)
-//ZZ #define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3)
+#define OFFB_QCFLAG offsetof(VexGuestARM64State,guest_QCFLAG)
#define OFFB_CMSTART offsetof(VexGuestARM64State,guest_CMSTART)
#define OFFB_CMLEN offsetof(VexGuestARM64State,guest_CMLEN)
@@ -4879,16 +4872,37 @@
/* Cases for FPSR
0xD51B44 001 Rt MSR fpsr, rT
0xD53B44 001 Rt MSR rT, fpsr
+ The only part of this we model is FPSR.QC. All other bits
+ are ignored when writing to it and RAZ when reading from it.
*/
if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4420 /*MSR*/
|| (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4420 /*MRS*/) {
Bool toSys = INSN(21,21) == 0;
UInt tt = INSN(4,0);
if (toSys) {
- stmt( IRStmt_Put( OFFB_FPSR, getIReg32orZR(tt)) );
+ /* Just deal with FPSR.QC. Make up a V128 value which is
+ zero if Xt[27] is zero and any other value if Xt[27] is
+ nonzero. */
+ IRTemp qc64 = newTemp(Ity_I64);
+ assign(qc64, binop(Iop_And64,
+ binop(Iop_Shr64, getIReg64orZR(tt), mkU8(27)),
+ mkU64(1)));
+ IRExpr* qcV128 = binop(Iop_64HLtoV128, mkexpr(qc64), mkexpr(qc64));
+ stmt( IRStmt_Put( OFFB_QCFLAG, qcV128 ) );
DIP("msr fpsr, %s\n", nameIReg64orZR(tt));
} else {
- putIReg32orZR(tt, IRExpr_Get(OFFB_FPSR, Ity_I32));
+ /* Generate a value which is all zeroes except for bit 27,
+ which must be zero if QCFLAG is all zeroes and one otherwise. */
+ IRTemp qcV128 = newTemp(Ity_V128);
+ assign(qcV128, IRExpr_Get( OFFB_QCFLAG, Ity_V128 ));
+ IRTemp qc64 = newTemp(Ity_I64);
+ assign(qc64, binop(Iop_Or64, unop(Iop_V128HIto64, mkexpr(qcV128)),
+ unop(Iop_V128to64, mkexpr(qcV128))));
+ IRExpr* res = binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpNE64, mkexpr(qc64), mkU64(0))),
+ mkU8(27));
+ putIReg64orZR(tt, res);
DIP("mrs %s, fpsr\n", nameIReg64orZR(tt));
}
return True;
@@ -4896,6 +4910,9 @@
/* Cases for NZCV
D51B42 000 Rt MSR nzcv, rT
D53B42 000 Rt MRS rT, nzcv
+ The only parts of NZCV that actually exist are bits 31:28, which
+ are the N Z C and V bits themselves. Hence the flags thunk provides
+ all the state we need.
*/
if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4200 /*MSR*/
|| (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4200 /*MRS*/) {
Modified: trunk/pub/libvex_guest_arm64.h
==============================================================================
--- trunk/pub/libvex_guest_arm64.h (original)
+++ trunk/pub/libvex_guest_arm64.h Sat Jun 28 22:11:16 2014
@@ -123,6 +123,13 @@
U128 guest_Q30;
U128 guest_Q31;
+ /* A 128-bit value which is used to represent the FPSR.QC (sticky
+ saturation) flag, when necessary. If the value stored here
+ is zero, FPSR.QC is currently zero. If it is any other value,
+ FPSR.QC is currently one. We don't currently represent any
+ other bits of FPSR, so this is all that that is for FPSR. */
+ U128 guest_QCFLAG;
+
/* Various pseudo-regs mandated by Vex or Valgrind. */
/* Emulation notes */
UInt guest_EMNOTE;
@@ -152,15 +159,9 @@
note of bits 23 and 22. */
UInt guest_FPCR;
- /* The complete FPSR. As with FPCR, the guest may write and
- read any values here, and the emulation ignores it, with the
- exception of bit 27 (QC, the sticky saturation bit) which
- does get set when required. */
- UInt guest_FPSR;
-
/* Padding to make it have an 16-aligned size */
- UInt pad_end_0;
- ULong pad_end_1;
+ /* UInt pad_end_0; */
+ /* ULong pad_end_1; */
}
VexGuestARM64State;
@@ -182,6 +183,18 @@
ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/
const VexGuestARM64State* vex_state );
+/* Calculate the ARM64 FPSR state from the saved data, in the format
+ 36x0:qc:27x0 */
+extern
+ULong LibVEX_GuestARM64_get_fpsr ( /*IN*/
+ const VexGuestARM64State* vex_state );
+
+/* Set the ARM64 FPSR representation from the given FPSR value. */
+extern
+void LibVEX_GuestARM64_set_fpsr ( /*MOD*/VexGuestARM64State* vex_state,
+ ULong fpsr );
+
+
#endif /* ndef __LIBVEX_PUB_GUEST_ARM64_H */
|
|
From: <sv...@va...> - 2014-06-28 12:22:30
|
Author: sewardj
Date: Sat Jun 28 12:22:22 2014
New Revision: 14119
Log:
Enable test cases for: sabal uabal sabdl uabdl saddl uaddl ssubl usubl
smlal umlal smlsl umlsl smull umull
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Sat Jun 28 12:22:22 2014
@@ -3802,18 +3802,18 @@
// sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- if (0) test_sabal_2d_2s_2s(TyS);
- if (0) test_sabal2_2d_4s_4s(TyS);
- if (0) test_sabal_4s_4h_4h(TyH);
- if (0) test_sabal2_4s_8h_8h(TyH);
- if (0) test_sabal_8h_8b_8b(TyB);
- if (0) test_sabal2_8h_16b_16b(TyB);
- if (0) test_uabal_2d_2s_2s(TyS);
- if (0) test_uabal2_2d_4s_4s(TyS);
- if (0) test_uabal_4s_4h_4h(TyH);
- if (0) test_uabal2_4s_8h_8h(TyH);
- if (0) test_uabal_8h_8b_8b(TyB);
- if (0) test_uabal2_8h_16b_16b(TyB);
+ if (1) test_sabal_2d_2s_2s(TyS);
+ if (1) test_sabal2_2d_4s_4s(TyS);
+ if (1) test_sabal_4s_4h_4h(TyH);
+ if (1) test_sabal2_4s_8h_8h(TyH);
+ if (1) test_sabal_8h_8b_8b(TyB);
+ if (1) test_sabal2_8h_16b_16b(TyB);
+ if (1) test_uabal_2d_2s_2s(TyS);
+ if (1) test_uabal2_2d_4s_4s(TyS);
+ if (1) test_uabal_4s_4h_4h(TyH);
+ if (1) test_uabal2_4s_8h_8h(TyH);
+ if (1) test_uabal_8h_8b_8b(TyB);
+ if (1) test_uabal2_8h_16b_16b(TyB);
// sabd 16b,8b,8h,4h,4s,2s
// uabd 16b,8b,8h,4h,4s,2s
@@ -3832,18 +3832,18 @@
// sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- if (0) test_sabdl_2d_2s_2s(TyS);
- if (0) test_sabdl2_2d_4s_4s(TyS);
- if (0) test_sabdl_4s_4h_4h(TyH);
- if (0) test_sabdl2_4s_8h_8h(TyH);
- if (0) test_sabdl_8h_8b_8b(TyB);
- if (0) test_sabdl2_8h_16b_16b(TyB);
- if (0) test_uabdl_2d_2s_2s(TyS);
- if (0) test_uabdl2_2d_4s_4s(TyS);
- if (0) test_uabdl_4s_4h_4h(TyH);
- if (0) test_uabdl2_4s_8h_8h(TyH);
- if (0) test_uabdl_8h_8b_8b(TyB);
- if (0) test_uabdl2_8h_16b_16b(TyB);
+ if (1) test_sabdl_2d_2s_2s(TyS);
+ if (1) test_sabdl2_2d_4s_4s(TyS);
+ if (1) test_sabdl_4s_4h_4h(TyH);
+ if (1) test_sabdl2_4s_8h_8h(TyH);
+ if (1) test_sabdl_8h_8b_8b(TyB);
+ if (1) test_sabdl2_8h_16b_16b(TyB);
+ if (1) test_uabdl_2d_2s_2s(TyS);
+ if (1) test_uabdl2_2d_4s_4s(TyS);
+ if (1) test_uabdl_4s_4h_4h(TyH);
+ if (1) test_uabdl2_4s_8h_8h(TyH);
+ if (1) test_uabdl_8h_8b_8b(TyB);
+ if (1) test_uabdl2_8h_16b_16b(TyB);
// sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
// uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
@@ -3864,30 +3864,30 @@
// uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- if (0) test_saddl_2d_2s_2s(TyS);
- if (0) test_saddl2_2d_4s_4s(TyS);
- if (0) test_saddl_4s_4h_4h(TyH);
- if (0) test_saddl2_4s_8h_8h(TyH);
- if (0) test_saddl_8h_8b_8b(TyB);
- if (0) test_saddl2_8h_16b_16b(TyB);
- if (0) test_uaddl_2d_2s_2s(TyS);
- if (0) test_uaddl2_2d_4s_4s(TyS);
- if (0) test_uaddl_4s_4h_4h(TyH);
- if (0) test_uaddl2_4s_8h_8h(TyH);
- if (0) test_uaddl_8h_8b_8b(TyB);
- if (0) test_uaddl2_8h_16b_16b(TyB);
- if (0) test_ssubl_2d_2s_2s(TyS);
- if (0) test_ssubl2_2d_4s_4s(TyS);
- if (0) test_ssubl_4s_4h_4h(TyH);
- if (0) test_ssubl2_4s_8h_8h(TyH);
- if (0) test_ssubl_8h_8b_8b(TyB);
- if (0) test_ssubl2_8h_16b_16b(TyB);
- if (0) test_usubl_2d_2s_2s(TyS);
- if (0) test_usubl2_2d_4s_4s(TyS);
- if (0) test_usubl_4s_4h_4h(TyH);
- if (0) test_usubl2_4s_8h_8h(TyH);
- if (0) test_usubl_8h_8b_8b(TyB);
- if (0) test_usubl2_8h_16b_16b(TyB);
+ if (1) test_saddl_2d_2s_2s(TyS);
+ if (1) test_saddl2_2d_4s_4s(TyS);
+ if (1) test_saddl_4s_4h_4h(TyH);
+ if (1) test_saddl2_4s_8h_8h(TyH);
+ if (1) test_saddl_8h_8b_8b(TyB);
+ if (1) test_saddl2_8h_16b_16b(TyB);
+ if (1) test_uaddl_2d_2s_2s(TyS);
+ if (1) test_uaddl2_2d_4s_4s(TyS);
+ if (1) test_uaddl_4s_4h_4h(TyH);
+ if (1) test_uaddl2_4s_8h_8h(TyH);
+ if (1) test_uaddl_8h_8b_8b(TyB);
+ if (1) test_uaddl2_8h_16b_16b(TyB);
+ if (1) test_ssubl_2d_2s_2s(TyS);
+ if (1) test_ssubl2_2d_4s_4s(TyS);
+ if (1) test_ssubl_4s_4h_4h(TyH);
+ if (1) test_ssubl2_4s_8h_8h(TyH);
+ if (1) test_ssubl_8h_8b_8b(TyB);
+ if (1) test_ssubl2_8h_16b_16b(TyB);
+ if (1) test_usubl_2d_2s_2s(TyS);
+ if (1) test_usubl2_2d_4s_4s(TyS);
+ if (1) test_usubl_4s_4h_4h(TyH);
+ if (1) test_usubl2_4s_8h_8h(TyH);
+ if (1) test_usubl_8h_8b_8b(TyB);
+ if (1) test_usubl2_8h_16b_16b(TyB);
// saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
// uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
@@ -4192,42 +4192,42 @@
// umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
// umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
- if (0) test_smlal_2d_2s_2s(TyS);
- if (0) test_smlal2_2d_4s_4s(TyS);
- if (0) test_smlal_4s_4h_4h(TyH);
- if (0) test_smlal2_4s_8h_8h(TyH);
- if (0) test_smlal_8h_8b_8b(TyB);
- if (0) test_smlal2_8h_16b_16b(TyB);
- if (0) test_umlal_2d_2s_2s(TyS);
- if (0) test_umlal2_2d_4s_4s(TyS);
- if (0) test_umlal_4s_4h_4h(TyH);
- if (0) test_umlal2_4s_8h_8h(TyH);
- if (0) test_umlal_8h_8b_8b(TyB);
- if (0) test_umlal2_8h_16b_16b(TyB);
- if (0) test_smlsl_2d_2s_2s(TyS);
- if (0) test_smlsl2_2d_4s_4s(TyS);
- if (0) test_smlsl_4s_4h_4h(TyH);
- if (0) test_smlsl2_4s_8h_8h(TyH);
- if (0) test_smlsl_8h_8b_8b(TyB);
- if (0) test_smlsl2_8h_16b_16b(TyB);
- if (0) test_umlsl_2d_2s_2s(TyS);
- if (0) test_umlsl2_2d_4s_4s(TyS);
- if (0) test_umlsl_4s_4h_4h(TyH);
- if (0) test_umlsl2_4s_8h_8h(TyH);
- if (0) test_umlsl_8h_8b_8b(TyB);
- if (0) test_umlsl2_8h_16b_16b(TyB);
- if (0) test_smull_2d_2s_2s(TyS);
- if (0) test_smull2_2d_4s_4s(TyS);
- if (0) test_smull_4s_4h_4h(TyH);
- if (0) test_smull2_4s_8h_8h(TyH);
- if (0) test_smull_8h_8b_8b(TyB);
- if (0) test_smull2_8h_16b_16b(TyB);
- if (0) test_umull_2d_2s_2s(TyS);
- if (0) test_umull2_2d_4s_4s(TyS);
- if (0) test_umull_4s_4h_4h(TyH);
- if (0) test_umull2_4s_8h_8h(TyH);
- if (0) test_umull_8h_8b_8b(TyB);
- if (0) test_umull2_8h_16b_16b(TyB);
+ if (1) test_smlal_2d_2s_2s(TyS);
+ if (1) test_smlal2_2d_4s_4s(TyS);
+ if (1) test_smlal_4s_4h_4h(TyH);
+ if (1) test_smlal2_4s_8h_8h(TyH);
+ if (1) test_smlal_8h_8b_8b(TyB);
+ if (1) test_smlal2_8h_16b_16b(TyB);
+ if (1) test_umlal_2d_2s_2s(TyS);
+ if (1) test_umlal2_2d_4s_4s(TyS);
+ if (1) test_umlal_4s_4h_4h(TyH);
+ if (1) test_umlal2_4s_8h_8h(TyH);
+ if (1) test_umlal_8h_8b_8b(TyB);
+ if (1) test_umlal2_8h_16b_16b(TyB);
+ if (1) test_smlsl_2d_2s_2s(TyS);
+ if (1) test_smlsl2_2d_4s_4s(TyS);
+ if (1) test_smlsl_4s_4h_4h(TyH);
+ if (1) test_smlsl2_4s_8h_8h(TyH);
+ if (1) test_smlsl_8h_8b_8b(TyB);
+ if (1) test_smlsl2_8h_16b_16b(TyB);
+ if (1) test_umlsl_2d_2s_2s(TyS);
+ if (1) test_umlsl2_2d_4s_4s(TyS);
+ if (1) test_umlsl_4s_4h_4h(TyH);
+ if (1) test_umlsl2_4s_8h_8h(TyH);
+ if (1) test_umlsl_8h_8b_8b(TyB);
+ if (1) test_umlsl2_8h_16b_16b(TyB);
+ if (1) test_smull_2d_2s_2s(TyS);
+ if (1) test_smull2_2d_4s_4s(TyS);
+ if (1) test_smull_4s_4h_4h(TyH);
+ if (1) test_smull2_4s_8h_8h(TyH);
+ if (1) test_smull_8h_8b_8b(TyB);
+ if (1) test_smull2_8h_16b_16b(TyB);
+ if (1) test_umull_2d_2s_2s(TyS);
+ if (1) test_umull2_2d_4s_4s(TyS);
+ if (1) test_umull_4s_4h_4h(TyH);
+ if (1) test_umull2_4s_8h_8h(TyH);
+ if (1) test_umull_8h_8b_8b(TyB);
+ if (1) test_umull2_8h_16b_16b(TyB);
// smov w_b[], w_h[], x_b[], x_h[], x_s[]
// umov w_b[], w_h[], w_s[], x_d[]
|
|
From: <sv...@va...> - 2014-06-28 12:21:52
|
Author: sewardj
Date: Sat Jun 28 12:21:37 2014
New Revision: 2893
Log:
arm64: implement: sabal uabal sabdl uabdl saddl uaddl ssubl usubl
smlal umlal smlsl umlsl smull umull
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Sat Jun 28 12:21:37 2014
@@ -5640,10 +5640,13 @@
static
IRTemp math_ABD ( Bool isU, UInt size, IRExpr* argLE, IRExpr* argRE )
{
- const IROp opSUB[3] = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4 };
- const IROp opGTU[3] = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4 };
- const IROp opGTS[3] = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4 };
- vassert(size <= 2);
+ const IROp opSUB[4]
+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
+ const IROp opGTU[4]
+ = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, Iop_CmpGT64Ux2 };
+ const IROp opGTS[4]
+ = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 };
+ vassert(size <= 3);
IRTemp argL = newTemp(Ity_V128);
IRTemp argR = newTemp(Ity_V128);
IRTemp msk = newTemp(Ity_V128);
@@ -5664,6 +5667,51 @@
}
+/* Generate IR that takes a V128 and sign- or zero-widens
+ either the lower or upper set of lanes to twice-as-wide,
+ resulting in a new V128 value. */
+static
+IRTemp math_WIDEN_LANES ( Bool zWiden, Bool fromUpperHalf,
+ UInt sizeNarrow, IRExpr* srcE )
+{
+ IRTemp src = newTemp(Ity_V128);
+ IRTemp res = newTemp(Ity_V128);
+ assign(src, srcE);
+ switch (sizeNarrow) {
+ case X10:
+ assign(res,
+ binop(zWiden ? Iop_ShrN64x2 : Iop_SarN64x2,
+ binop(fromUpperHalf ? Iop_InterleaveHI32x4
+ : Iop_InterleaveLO32x4,
+ mkexpr(src),
+ mkexpr(src)),
+ mkU8(32)));
+ break;
+ case X01:
+ assign(res,
+ binop(zWiden ? Iop_ShrN32x4 : Iop_SarN32x4,
+ binop(fromUpperHalf ? Iop_InterleaveHI16x8
+ : Iop_InterleaveLO16x8,
+ mkexpr(src),
+ mkexpr(src)),
+ mkU8(16)));
+ break;
+ case X00:
+ assign(res,
+ binop(zWiden ? Iop_ShrN16x8 : Iop_SarN16x8,
+ binop(fromUpperHalf ? Iop_InterleaveHI8x16
+ : Iop_InterleaveLO8x16,
+ mkexpr(src),
+ mkexpr(src)),
+ mkU8(8)));
+ break;
+ default:
+ vassert(0);
+ }
+ return res;
+}
+
+
/* Let |new64| be a V128 in which only the lower 64 bits are interesting,
and the upper can contain any value -- it is ignored. If |is2| is False,
generate IR to put |new64| in the lower half of vector reg |dd| and zero
@@ -6937,6 +6985,34 @@
vassert(size < 4);
Bool is2 = bitQ == 1;
+ if (opcode == BITS4(0,0,0,0) || opcode == BITS4(0,0,1,0)) {
+ /* -------- 0,0000 SADDL{2} -------- */
+ /* -------- 1,0000 UADDL{2} -------- */
+ /* -------- 0,0010 SSUBL{2} -------- */
+ /* -------- 1,0010 USUBL{2} -------- */
+ /* Widens, and size refers to the narrowed lanes. */
+ const IROp opADD[3] = { Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 };
+ const IROp opSUB[3] = { Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
+ if (size == X11) return False;
+ vassert(size <= 2);
+ Bool isU = bitU == 1;
+ Bool isADD = opcode == BITS4(0,0,0,0);
+ IRTemp argL = math_WIDEN_LANES(isU, is2, size, getQReg128(nn));
+ IRTemp argR = math_WIDEN_LANES(isU, is2, size, getQReg128(mm));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(isADD ? opADD[size] : opSUB[size],
+ mkexpr(argL), mkexpr(argR)));
+ putQReg128(dd, mkexpr(res));
+ const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
+ const HChar* arrWide = nameArr_Q_SZ(1, size+1);
+ const HChar* nm = isADD ? (isU ? "uaddl" : "saddl")
+ : (isU ? "usubl" : "ssubl");
+ DIP("%s%s %s.%s, %s.%s, %s.%s\n", nm, is2 ? "2" : "",
+ nameQReg128(dd), arrWide,
+ nameQReg128(nn), arrNarrow, nameQReg128(mm), arrNarrow);
+ return True;
+ }
+
if (opcode == BITS4(0,1,0,0) || opcode == BITS4(0,1,1,0)) {
/* -------- 0,0100 ADDHN{2} -------- */
/* -------- 1,0100 RADDHN{2} -------- */
@@ -6990,9 +7066,79 @@
return True;
}
+ if (opcode == BITS4(0,1,0,1) || opcode == BITS4(0,1,1,1)) {
+ /* -------- 0,0101 SABAL{2} -------- */
+ /* -------- 1,0101 UABAL{2} -------- */
+ /* -------- 0,0111 SABDL{2} -------- */
+ /* -------- 1,0111 UABDL{2} -------- */
+ /* Widens, and size refers to the narrowed lanes. */
+ const IROp opADD[3] = { Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 };
+ if (size == X11) return False;
+ vassert(size <= 2);
+ Bool isU = bitU == 1;
+ Bool isACC = opcode == BITS4(0,1,0,1);
+ IRTemp argL = math_WIDEN_LANES(isU, is2, size, getQReg128(nn));
+ IRTemp argR = math_WIDEN_LANES(isU, is2, size, getQReg128(mm));
+ IRTemp abd = math_ABD(isU, size+1, mkexpr(argL), mkexpr(argR));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, isACC ? binop(opADD[size], mkexpr(abd), getQReg128(dd))
+ : mkexpr(abd));
+ putQReg128(dd, mkexpr(res));
+ const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
+ const HChar* arrWide = nameArr_Q_SZ(1, size+1);
+ const HChar* nm = isACC ? (isU ? "uabal" : "sabal")
+ : (isU ? "uabdl" : "sabdl");
+ DIP("%s%s %s.%s, %s.%s, %s.%s\n", nm, is2 ? "2" : "",
+ nameQReg128(dd), arrWide,
+ nameQReg128(nn), arrNarrow, nameQReg128(mm), arrNarrow);
+ return True;
+ }
+
+ if (opcode == BITS4(1,1,0,0)
+ || opcode == BITS4(1,0,0,0) || opcode == BITS4(1,0,1,0)) {
+ /* -------- 0,1100 SMULL{2} -------- */ // 0 (ix)
+ /* -------- 1,1100 UMULL{2} -------- */ // 0
+ /* -------- 0,1000 SMLAL{2} -------- */ // 1
+ /* -------- 1,1000 UMLAL{2} -------- */ // 1
+ /* -------- 0,1010 SMLSL{2} -------- */ // 2
+ /* -------- 1,1010 UMLSL{2} -------- */ // 2
+ /* Widens, and size refers to the narrowed lanes. */
+ UInt ix = 3;
+ switch (opcode) {
+ case BITS4(1,1,0,0): ix = 0; break;
+ case BITS4(1,0,0,0): ix = 1; break;
+ case BITS4(1,0,1,0): ix = 2; break;
+ default: vassert(0);
+ }
+ vassert(ix >= 0 && ix <= 2);
+ const IROp opMULLU[3] = { Iop_Mull8Ux8, Iop_Mull16Ux4, Iop_Mull32Ux2 };
+ const IROp opMULLS[3] = { Iop_Mull8Sx8, Iop_Mull16Sx4, Iop_Mull32Sx2 };
+ const IROp opADD[3] = { Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 };
+ const IROp opSUB[3] = { Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
+ if (size == X11) return False;
+ vassert(size <= 2);
+ Bool isU = bitU == 1;
+ IROp mulOp = isU ? opMULLU[size] : opMULLS[size];
+ IROp accOp = (ix == 1) ? opADD[size]
+ : (ix == 2 ? opSUB[size] : Iop_INVALID);
+ IRTemp mul = math_BINARY_WIDENING_V128(is2, mulOp,
+ getQReg128(nn), getQReg128(mm));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, ix == 0 ? mkexpr(mul)
+ : binop(accOp, getQReg128(dd), mkexpr(mul)));
+ putQReg128(dd, mkexpr(res));
+ const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
+ const HChar* arrWide = nameArr_Q_SZ(1, size+1);
+ const HChar* nm = ix == 0 ? "mull" : (ix == 1 ? "mlal" : "mlsl");
+ DIP("%c%s%s %s.%s, %s.%s, %s.%s\n", isU ? 'u' : 's', nm, is2 ? "2" : "",
+ nameQReg128(dd), arrWide,
+ nameQReg128(nn), arrNarrow, nameQReg128(mm), arrNarrow);
+ return True;
+ }
+
if (bitU == 0 && opcode == BITS4(1,1,1,0)) {
/* -------- 0,1110 PMULL{2} -------- */
- /* Narrows, and size refers to the narrowed lanes. */
+ /* Widens, and size refers to the narrowed lanes. */
if (size != X00) return False;
IRTemp res
= math_BINARY_WIDENING_V128(is2, Iop_PolynomialMull8x8,
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Sat Jun 28 12:21:37 2014
@@ -854,75 +854,81 @@
static void showARM64VecBinOp(/*OUT*/const HChar** nm,
/*OUT*/const HChar** ar, ARM64VecBinOp op ) {
switch (op) {
- case ARM64vecb_ADD64x2: *nm = "add "; *ar = "2d"; return;
- case ARM64vecb_ADD32x4: *nm = "add "; *ar = "4s"; return;
- case ARM64vecb_ADD16x8: *nm = "add "; *ar = "8h"; return;
- case ARM64vecb_ADD8x16: *nm = "add "; *ar = "16b"; return;
- case ARM64vecb_SUB64x2: *nm = "sub "; *ar = "2d"; return;
- case ARM64vecb_SUB32x4: *nm = "sub "; *ar = "4s"; return;
- case ARM64vecb_SUB16x8: *nm = "sub "; *ar = "8h"; return;
- case ARM64vecb_SUB8x16: *nm = "sub "; *ar = "16b"; return;
- case ARM64vecb_MUL32x4: *nm = "mul "; *ar = "4s"; return;
- case ARM64vecb_MUL16x8: *nm = "mul "; *ar = "8h"; return;
- case ARM64vecb_MUL8x16: *nm = "mul "; *ar = "16b"; return;
- case ARM64vecb_FADD64x2: *nm = "fadd"; *ar = "2d"; return;
- case ARM64vecb_FSUB64x2: *nm = "fsub"; *ar = "2d"; return;
- case ARM64vecb_FMUL64x2: *nm = "fmul"; *ar = "2d"; return;
- case ARM64vecb_FDIV64x2: *nm = "fdiv"; *ar = "2d"; return;
- case ARM64vecb_FADD32x4: *nm = "fadd"; *ar = "4s"; return;
- case ARM64vecb_FSUB32x4: *nm = "fsub"; *ar = "4s"; return;
- case ARM64vecb_FMUL32x4: *nm = "fmul"; *ar = "4s"; return;
- case ARM64vecb_FDIV32x4: *nm = "fdiv"; *ar = "4s"; return;
- case ARM64vecb_UMAX32x4: *nm = "umax"; *ar = "4s"; return;
- case ARM64vecb_UMAX16x8: *nm = "umax"; *ar = "8h"; return;
- case ARM64vecb_UMAX8x16: *nm = "umax"; *ar = "16b"; return;
- case ARM64vecb_UMIN32x4: *nm = "umin"; *ar = "4s"; return;
- case ARM64vecb_UMIN16x8: *nm = "umin"; *ar = "8h"; return;
- case ARM64vecb_UMIN8x16: *nm = "umin"; *ar = "16b"; return;
- case ARM64vecb_SMAX32x4: *nm = "smax"; *ar = "4s"; return;
- case ARM64vecb_SMAX16x8: *nm = "smax"; *ar = "8h"; return;
- case ARM64vecb_SMAX8x16: *nm = "smax"; *ar = "16b"; return;
- case ARM64vecb_SMIN32x4: *nm = "smin"; *ar = "4s"; return;
- case ARM64vecb_SMIN16x8: *nm = "smin"; *ar = "8h"; return;
- case ARM64vecb_SMIN8x16: *nm = "smin"; *ar = "16b"; return;
- case ARM64vecb_AND: *nm = "and "; *ar = "all"; return;
- case ARM64vecb_ORR: *nm = "orr "; *ar = "all"; return;
- case ARM64vecb_XOR: *nm = "eor "; *ar = "all"; return;
- case ARM64vecb_CMEQ64x2: *nm = "cmeq"; *ar = "2d"; return;
- case ARM64vecb_CMEQ32x4: *nm = "cmeq"; *ar = "4s"; return;
- case ARM64vecb_CMEQ16x8: *nm = "cmeq"; *ar = "8h"; return;
- case ARM64vecb_CMEQ8x16: *nm = "cmeq"; *ar = "16b"; return;
- case ARM64vecb_CMHI64x2: *nm = "cmhi"; *ar = "2d"; return;
- case ARM64vecb_CMHI32x4: *nm = "cmhi"; *ar = "4s"; return;
- case ARM64vecb_CMHI16x8: *nm = "cmhi"; *ar = "8h"; return;
- case ARM64vecb_CMHI8x16: *nm = "cmhi"; *ar = "16b"; return;
- case ARM64vecb_CMGT64x2: *nm = "cmgt"; *ar = "2d"; return;
- case ARM64vecb_CMGT32x4: *nm = "cmgt"; *ar = "4s"; return;
- case ARM64vecb_CMGT16x8: *nm = "cmgt"; *ar = "8h"; return;
- case ARM64vecb_CMGT8x16: *nm = "cmgt"; *ar = "16b"; return;
- case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return;
- case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return;
- case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return;
- case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return;
- case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return;
- case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return;
- case ARM64vecb_TBL1: *nm = "tbl "; *ar = "16b"; return;
- case ARM64vecb_UZP164x2: *nm = "uzp1"; *ar = "2d"; return;
- case ARM64vecb_UZP132x4: *nm = "uzp1"; *ar = "4s"; return;
- case ARM64vecb_UZP116x8: *nm = "uzp1"; *ar = "8h"; return;
- case ARM64vecb_UZP18x16: *nm = "uzp1"; *ar = "16b"; return;
- case ARM64vecb_UZP264x2: *nm = "uzp2"; *ar = "2d"; return;
- case ARM64vecb_UZP232x4: *nm = "uzp2"; *ar = "4s"; return;
- case ARM64vecb_UZP216x8: *nm = "uzp2"; *ar = "8h"; return;
- case ARM64vecb_UZP28x16: *nm = "uzp2"; *ar = "16b"; return;
- case ARM64vecb_ZIP132x4: *nm = "zip1"; *ar = "4s"; return;
- case ARM64vecb_ZIP116x8: *nm = "zip1"; *ar = "8h"; return;
- case ARM64vecb_ZIP18x16: *nm = "zip1"; *ar = "16b"; return;
- case ARM64vecb_ZIP232x4: *nm = "zip2"; *ar = "4s"; return;
- case ARM64vecb_ZIP216x8: *nm = "zip2"; *ar = "8h"; return;
- case ARM64vecb_ZIP28x16: *nm = "zip2"; *ar = "16b"; return;
- case ARM64vecb_PMUL8x16: *nm = "pmul"; *ar = "16b"; return;
- case ARM64vecb_PMULL8x8: *nm = "pmull"; *ar = "8hb"; return;
+ case ARM64vecb_ADD64x2: *nm = "add "; *ar = "2d"; return;
+ case ARM64vecb_ADD32x4: *nm = "add "; *ar = "4s"; return;
+ case ARM64vecb_ADD16x8: *nm = "add "; *ar = "8h"; return;
+ case ARM64vecb_ADD8x16: *nm = "add "; *ar = "16b"; return;
+ case ARM64vecb_SUB64x2: *nm = "sub "; *ar = "2d"; return;
+ case ARM64vecb_SUB32x4: *nm = "sub "; *ar = "4s"; return;
+ case ARM64vecb_SUB16x8: *nm = "sub "; *ar = "8h"; return;
+ case ARM64vecb_SUB8x16: *nm = "sub "; *ar = "16b"; return;
+ case ARM64vecb_MUL32x4: *nm = "mul "; *ar = "4s"; return;
+ case ARM64vecb_MUL16x8: *nm = "mul "; *ar = "8h"; return;
+ case ARM64vecb_MUL8x16: *nm = "mul "; *ar = "16b"; return;
+ case ARM64vecb_FADD64x2: *nm = "fadd "; *ar = "2d"; return;
+ case ARM64vecb_FSUB64x2: *nm = "fsub "; *ar = "2d"; return;
+ case ARM64vecb_FMUL64x2: *nm = "fmul "; *ar = "2d"; return;
+ case ARM64vecb_FDIV64x2: *nm = "fdiv "; *ar = "2d"; return;
+ case ARM64vecb_FADD32x4: *nm = "fadd "; *ar = "4s"; return;
+ case ARM64vecb_FSUB32x4: *nm = "fsub "; *ar = "4s"; return;
+ case ARM64vecb_FMUL32x4: *nm = "fmul "; *ar = "4s"; return;
+ case ARM64vecb_FDIV32x4: *nm = "fdiv "; *ar = "4s"; return;
+ case ARM64vecb_UMAX32x4: *nm = "umax "; *ar = "4s"; return;
+ case ARM64vecb_UMAX16x8: *nm = "umax "; *ar = "8h"; return;
+ case ARM64vecb_UMAX8x16: *nm = "umax "; *ar = "16b"; return;
+ case ARM64vecb_UMIN32x4: *nm = "umin "; *ar = "4s"; return;
+ case ARM64vecb_UMIN16x8: *nm = "umin "; *ar = "8h"; return;
+ case ARM64vecb_UMIN8x16: *nm = "umin "; *ar = "16b"; return;
+ case ARM64vecb_SMAX32x4: *nm = "smax "; *ar = "4s"; return;
+ case ARM64vecb_SMAX16x8: *nm = "smax "; *ar = "8h"; return;
+ case ARM64vecb_SMAX8x16: *nm = "smax "; *ar = "16b"; return;
+ case ARM64vecb_SMIN32x4: *nm = "smin "; *ar = "4s"; return;
+ case ARM64vecb_SMIN16x8: *nm = "smin "; *ar = "8h"; return;
+ case ARM64vecb_SMIN8x16: *nm = "smin "; *ar = "16b"; return;
+ case ARM64vecb_AND: *nm = "and "; *ar = "16b"; return;
+ case ARM64vecb_ORR: *nm = "orr "; *ar = "16b"; return;
+ case ARM64vecb_XOR: *nm = "eor "; *ar = "16b"; return;
+ case ARM64vecb_CMEQ64x2: *nm = "cmeq "; *ar = "2d"; return;
+ case ARM64vecb_CMEQ32x4: *nm = "cmeq "; *ar = "4s"; return;
+ case ARM64vecb_CMEQ16x8: *nm = "cmeq "; *ar = "8h"; return;
+ case ARM64vecb_CMEQ8x16: *nm = "cmeq "; *ar = "16b"; return;
+ case ARM64vecb_CMHI64x2: *nm = "cmhi "; *ar = "2d"; return;
+ case ARM64vecb_CMHI32x4: *nm = "cmhi "; *ar = "4s"; return;
+ case ARM64vecb_CMHI16x8: *nm = "cmhi "; *ar = "8h"; return;
+ case ARM64vecb_CMHI8x16: *nm = "cmhi "; *ar = "16b"; return;
+ case ARM64vecb_CMGT64x2: *nm = "cmgt "; *ar = "2d"; return;
+ case ARM64vecb_CMGT32x4: *nm = "cmgt "; *ar = "4s"; return;
+ case ARM64vecb_CMGT16x8: *nm = "cmgt "; *ar = "8h"; return;
+ case ARM64vecb_CMGT8x16: *nm = "cmgt "; *ar = "16b"; return;
+ case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return;
+ case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return;
+ case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return;
+ case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return;
+ case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return;
+ case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return;
+ case ARM64vecb_TBL1: *nm = "tbl "; *ar = "16b"; return;
+ case ARM64vecb_UZP164x2: *nm = "uzp1 "; *ar = "2d"; return;
+ case ARM64vecb_UZP132x4: *nm = "uzp1 "; *ar = "4s"; return;
+ case ARM64vecb_UZP116x8: *nm = "uzp1 "; *ar = "8h"; return;
+ case ARM64vecb_UZP18x16: *nm = "uzp1 "; *ar = "16b"; return;
+ case ARM64vecb_UZP264x2: *nm = "uzp2 "; *ar = "2d"; return;
+ case ARM64vecb_UZP232x4: *nm = "uzp2 "; *ar = "4s"; return;
+ case ARM64vecb_UZP216x8: *nm = "uzp2 "; *ar = "8h"; return;
+ case ARM64vecb_UZP28x16: *nm = "uzp2 "; *ar = "16b"; return;
+ case ARM64vecb_ZIP132x4: *nm = "zip1 "; *ar = "4s"; return;
+ case ARM64vecb_ZIP116x8: *nm = "zip1 "; *ar = "8h"; return;
+ case ARM64vecb_ZIP18x16: *nm = "zip1 "; *ar = "16b"; return;
+ case ARM64vecb_ZIP232x4: *nm = "zip2 "; *ar = "4s"; return;
+ case ARM64vecb_ZIP216x8: *nm = "zip2 "; *ar = "8h"; return;
+ case ARM64vecb_ZIP28x16: *nm = "zip2 "; *ar = "16b"; return;
+ case ARM64vecb_PMUL8x16: *nm = "pmul "; *ar = "16b"; return;
+ case ARM64vecb_PMULL8x8: *nm = "pmull"; *ar = "8hbb"; return;
+ case ARM64vecb_UMULL2DSS: *nm = "umull"; *ar = "2dss"; return;
+ case ARM64vecb_UMULL4SHH: *nm = "umull"; *ar = "4shh"; return;
+ case ARM64vecb_UMULL8HBB: *nm = "umull"; *ar = "8hbb"; return;
+ case ARM64vecb_SMULL2DSS: *nm = "smull"; *ar = "2dss"; return;
+ case ARM64vecb_SMULL4SHH: *nm = "smull"; *ar = "4shh"; return;
+ case ARM64vecb_SMULL8HBB: *nm = "smull"; *ar = "8hbb"; return;
default: vpanic("showARM64VecBinOp");
}
}
@@ -5137,6 +5143,14 @@
011 01110 00 1 m 100111 n d PMUL Vd.16b, Vn.16b, Vm.16b
000 01110 00 1 m 111000 n d PMULL Vd.8h, Vn.8b, Vm.8b
+
+ 001 01110 10 1 m 110000 n d UMULL Vd.2d, Vn.2s, Vm.2s
+ 001 01110 01 1 m 110000 n d UMULL Vd.4s, Vn.4h, Vm.4h
+ 001 01110 00 1 m 110000 n d UMULL Vd.8h, Vn.8b, Vm.8b
+
+ 000 01110 10 1 m 110000 n d SMULL Vd.2d, Vn.2s, Vm.2s
+ 000 01110 01 1 m 110000 n d SMULL Vd.4s, Vn.4h, Vm.4h
+ 000 01110 00 1 m 110000 n d SMULL Vd.8h, Vn.8b, Vm.8b
*/
UInt vD = qregNo(i->ARM64in.VBinV.dst);
UInt vN = qregNo(i->ARM64in.VBinV.argL);
@@ -5368,6 +5382,26 @@
*p++ = X_3_8_5_6_5_5(X000, X01110001, vM, X111000, vN, vD);
break;
+ case ARM64vecb_UMULL2DSS:
+ *p++ = X_3_8_5_6_5_5(X001, X01110101, vM, X110000, vN, vD);
+ break;
+ case ARM64vecb_UMULL4SHH:
+ *p++ = X_3_8_5_6_5_5(X001, X01110011, vM, X110000, vN, vD);
+ break;
+ case ARM64vecb_UMULL8HBB:
+ *p++ = X_3_8_5_6_5_5(X001, X01110001, vM, X110000, vN, vD);
+ break;
+
+ case ARM64vecb_SMULL2DSS:
+ *p++ = X_3_8_5_6_5_5(X000, X01110101, vM, X110000, vN, vD);
+ break;
+ case ARM64vecb_SMULL4SHH:
+ *p++ = X_3_8_5_6_5_5(X000, X01110011, vM, X110000, vN, vD);
+ break;
+ case ARM64vecb_SMULL8HBB:
+ *p++ = X_3_8_5_6_5_5(X000, X01110001, vM, X110000, vN, vD);
+ break;
+
default:
goto bad;
}
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Sat Jun 28 12:21:37 2014
@@ -346,6 +346,10 @@
ARM64vecb_ZIP216x8, ARM64vecb_ZIP28x16,
ARM64vecb_PMUL8x16,
ARM64vecb_PMULL8x8,
+ ARM64vecb_UMULL2DSS,
+ ARM64vecb_UMULL4SHH, ARM64vecb_UMULL8HBB,
+ ARM64vecb_SMULL2DSS,
+ ARM64vecb_SMULL4SHH, ARM64vecb_SMULL8HBB,
ARM64vecb_INVALID
}
ARM64VecBinOp;
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Sat Jun 28 12:21:37 2014
@@ -5683,16 +5683,33 @@
break;
}
- case Iop_PolynomialMull8x8: {
+ case Iop_PolynomialMull8x8:
+ case Iop_Mull32Ux2:
+ case Iop_Mull16Ux4:
+ case Iop_Mull8Ux8:
+ case Iop_Mull32Sx2:
+ case Iop_Mull16Sx4:
+ case Iop_Mull8Sx8:
+ {
HReg iSrcL = iselIntExpr_R(env, e->Iex.Binop.arg1);
HReg iSrcR = iselIntExpr_R(env, e->Iex.Binop.arg2);
HReg vSrcL = newVRegV(env);
HReg vSrcR = newVRegV(env);
HReg dst = newVRegV(env);
+ ARM64VecBinOp op = ARM64vecb_INVALID;
+ switch (e->Iex.Binop.op) {
+ case Iop_PolynomialMull8x8: op = ARM64vecb_PMULL8x8; break;
+ case Iop_Mull32Ux2: op = ARM64vecb_UMULL2DSS; break;
+ case Iop_Mull16Ux4: op = ARM64vecb_UMULL4SHH; break;
+ case Iop_Mull8Ux8: op = ARM64vecb_UMULL8HBB; break;
+ case Iop_Mull32Sx2: op = ARM64vecb_SMULL2DSS; break;
+ case Iop_Mull16Sx4: op = ARM64vecb_SMULL4SHH; break;
+ case Iop_Mull8Sx8: op = ARM64vecb_SMULL8HBB; break;
+ default: vassert(0);
+ }
addInstr(env, ARM64Instr_VQfromXX(vSrcL, iSrcL, iSrcL));
addInstr(env, ARM64Instr_VQfromXX(vSrcR, iSrcR, iSrcR));
- addInstr(env, ARM64Instr_VBinV(ARM64vecb_PMULL8x8,
- dst, vSrcL, vSrcR));
+ addInstr(env, ARM64Instr_VBinV(op, dst, vSrcL, vSrcR));
return dst;
}
|
|
From: <sv...@va...> - 2014-06-28 07:40:30
|
Author: bart
Date: Sat Jun 28 07:40:20 2014
New Revision: 14118
Log:
Update Subversion ignore lists
Modified:
trunk/memcheck/tests/vbit-test/ (props changed)
trunk/none/tests/ (props changed)
|
|
From: Philippe W. <phi...@sk...> - 2014-06-28 04:48:24
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora (7.5.1-37.fc18) Assembler: GNU assembler version 2.23.51.0.1-7.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.8.8-202.fc18.ppc64p7 ppc64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on gcc110 ( Fedora release 18 (Spherical Cow), ppc64 ) Started at 2014-06-27 20:00:13 PDT Ended at 2014-06-27 21:44:58 PDT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 588 tests, 9 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.22s no: 1.6s ( 7.0x, -----) me: 3.0s (13.8x, -----) ca:17.9s (81.5x, -----) he: 1.8s ( 8.0x, -----) ca: 5.4s (24.5x, -----) dr: 1.7s ( 7.8x, -----) ma: 2.1s ( 9.7x, -----) bigcode1 valgrind-old:0.22s no: 1.6s ( 7.1x, -0.6%) me: 2.9s (13.1x, 4.6%) ca:18.0s (81.6x, -0.1%) he: 1.8s ( 8.0x, -0.6%) ca: 5.3s (24.3x, 1.1%) dr: 1.7s ( 7.8x, 0.0%) ma: 2.1s ( 9.7x, 0.5%) -- bigcode2 -- bigcode2 valgrind-new:0.27s no: 1.6s ( 5.9x, -----) me: 3.1s (11.3x, -----) ca:18.1s (67.2x, -----) he: 2.1s ( 7.9x, -----) ca: 5.5s (20.3x, -----) dr: 1.8s ( 6.8x, -----) ma: 2.2s ( 8.0x, -----) bigcode2 valgrind-old:0.27s no: 1.5s ( 5.7x, 2.5%) me: 3.2s (11.7x, -3.6%) ca:18.2s (67.5x, -0.4%) he: 2.1s ( 8.0x, -0.5%) ca: 5.5s (20.4x, -0.7%) dr: 1.9s ( 7.0x, -2.2%) ma: 2.2s ( 8.0x, 0.0%) -- bz2 -- bz2 valgrind-new:0.72s no: 4.6s ( 6.3x, -----) me:11.3s (15.7x, -----) ca:25.8s (35.8x, -----) he:14.7s (20.5x, -----) ca:24.4s (33.9x, -----) dr:19.3s (26.8x, -----) ma: 4.9s ( 6.8x, -----) bz2 valgrind-old:0.72s no: 4.6s ( 6.4x, -1.5%) me:11.6s (16.1x, -2.7%) ca:25.8s (35.8x, -0.2%) he:15.0s (20.8x, -1.6%) ca:24.2s (33.6x, 0.9%) dr:19.2s (26.7x, 0.4%) ma: 4.7s ( 6.5x, 4.1%) -- fbench -- fbench valgrind-new:0.33s no: 2.1s ( 6.4x, -----) me: 5.3s (16.1x, -----) ca: 8.4s (25.6x, -----) he: 5.3s (16.0x, -----) ca: 7.6s (23.2x, -----) dr: 5.0s (15.1x, -----) ma: 2.2s ( 6.6x, -----) fbench valgrind-old:0.33s no: 2.2s ( 6.6x, -2.4%) me: 5.2s (15.8x, 1.7%) ca: 8.4s (25.5x, 0.2%) he: 5.3s (16.0x, 0.0%) ca: 7.4s (22.5x, 2.7%) dr: 4.8s (14.7x, 2.8%) ma: 2.3s ( 7.0x, -6.5%) -- ffbench -- ffbench valgrind-new:0.44s no: 1.4s ( 3.2x, -----) me: 2.7s ( 6.2x, -----) ca: 2.5s ( 5.8x, -----) he: 6.9s (15.7x, -----) ca: 7.0s (15.9x, -----) dr: 4.9s (11.2x, -----) ma: 1.1s ( 2.5x, -----) ffbench valgrind-old:0.44s no: 1.3s ( 3.0x, 5.7%) me: 2.4s ( 5.3x, 14.2%) ca: 2.5s ( 5.8x, 0.4%) he: 6.9s (15.8x, -0.4%) ca: 7.0s (15.9x, 0.1%) dr: 4.9s (11.2x, 0.0%) ma: 1.0s ( 2.3x, 5.5%) -- heap -- heap valgrind-new:0.41s no: 2.4s ( 5.9x, -----) me: 9.6s (23.3x, -----) ca:13.2s (32.2x, -----) he:12.0s (29.3x, -----) ca:12.2s (29.7x, -----) dr: 8.0s (19.5x, -----) ma: 8.6s (21.0x, -----) heap valgrind-old:0.41s no: 2.4s ( 5.8x, 0.8%) me: 9.6s (23.5x, -0.9%) ca:13.1s (32.0x, 0.5%) he:12.0s (29.3x, 0.1%) ca:12.1s (29.5x, 0.7%) dr: 7.9s (19.3x, 0.9%) ma: 8.6s (21.0x, 0.1%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.41s no: 2.8s ( 6.7x, -----) me:13.6s (33.1x, -----) ca:14.1s (34.4x, -----) he:13.5s (33.0x, -----) ca:13.2s (32.2x, -----) dr: 9.0s (21.9x, -----) ma: 8.6s (21.0x, -----) heap_pdb4 valgrind-old:0.41s no: 2.6s ( 6.4x, 4.7%) me:13.6s (33.3x, -0.4%) ca:14.0s (34.2x, 0.8%) he:13.5s (33.0x, 0.0%) ca:13.1s (32.0x, 0.6%) dr: 8.9s (21.7x, 0.8%) ma: 8.8s (21.4x, -2.0%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.5s (17.7x, -----) me: 2.1s (71.3x, -----) ca: 1.9s (65.0x, -----) he: 1.9s (62.7x, -----) ca: 1.9s (64.7x, -----) dr: 1.6s (51.7x, -----) ma: 1.6s (52.0x, -----) many-loss-records valgrind-old:0.03s no: 0.6s (18.3x, -3.8%) me: 2.2s (73.0x, -2.3%) ca: 2.0s (65.3x, -0.5%) he: 1.9s (62.7x, 0.0%) ca: 1.9s (63.0x, 2.6%) dr: 1.6s (51.7x, 0.0%) ma: 1.6s (51.7x, 0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.7s (10.6x, -----) me: 3.4s (48.1x, -----) ca: 4.7s (66.7x, -----) he: 5.0s (70.7x, -----) ca: 2.9s (41.4x, -----) dr: 2.3s (32.9x, -----) ma: 2.3s (32.3x, -----) many-xpts valgrind-old:0.07s no: 0.7s (10.6x, 0.0%) me: 3.4s (48.0x, 0.3%) ca: 4.7s (66.9x, -0.2%) he: 4.9s (70.1x, 0.8%) ca: 2.9s (41.6x, -0.3%) dr: 2.3s (32.7x, 0.4%) ma: 2.2s (32.0x, 0.9%) -- sarp -- sarp valgrind-new:0.02s no: 0.4s (20.0x, -----) me: 3.0s (152.5x, -----) ca: 2.9s (146.0x, -----) he:11.4s (569.0x, -----) ca: 1.7s (86.0x, -----) dr: 1.1s (53.0x, -----) ma: 0.4s (21.5x, -----) sarp valgrind-old:0.02s no: 0.4s (20.5x, -2.5%) me: 3.0s (152.5x, 0.0%) ca: 2.9s (146.5x, -0.3%) he:11.3s (565.0x, 0.7%) ca: 1.8s (89.0x, -3.5%) dr: 1.1s (54.5x, -2.8%) ma: 0.4s (21.0x, 2.3%) -- tinycc -- tinycc valgrind-new:0.27s no: 3.0s (11.0x, -----) me:13.8s (51.1x, -----) ca:17.3s (64.0x, -----) he:19.1s (70.6x, -----) ca:15.7s (58.2x, -----) dr:12.1s (44.8x, -----) ma: 3.8s (14.1x, -----) tinycc valgrind-old:0.27s no: 3.0s (11.1x, -0.3%) me:13.8s (51.1x, -0.1%) ca:17.4s (64.6x, -0.9%) he:19.1s (70.6x, 0.1%) ca:15.7s (58.1x, 0.1%) dr:12.1s (45.0x, -0.4%) ma: 3.9s (14.5x, -2.9%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 53m3.161s user 52m12.120s sys 0m18.640s |
|
From: Christian B. <bor...@de...> - 2014-06-28 04:08:51
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.21-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-06-28 03:45:01 CEST Ended at 2014-06-28 06:08:38 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 653 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/vbit-test/vbit-test (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 4.3s (18.8x, -----) me: 6.9s (30.0x, -----) ca:26.4s (114.7x, -----) he: 5.1s (22.0x, -----) ca: 9.2s (39.8x, -----) dr: 5.4s (23.3x, -----) ma: 5.0s (21.5x, -----) bigcode1 valgrind-old:0.23s no: 4.3s (18.7x, 0.5%) me: 6.9s (30.0x, -0.1%) ca:26.4s (114.8x, -0.1%) he: 5.0s (21.9x, 0.6%) ca: 9.1s (39.7x, 0.2%) dr: 5.4s (23.4x, -0.4%) ma: 5.0s (21.5x, 0.0%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.3s (30.2x, -----) me:13.8s (57.5x, -----) ca:39.5s (164.8x, -----) he:10.1s (41.9x, -----) ca:14.3s (59.6x, -----) dr: 9.5s (39.5x, -----) ma: 8.3s (34.7x, -----) bigcode2 valgrind-old:0.24s no: 7.2s (30.0x, 0.8%) me:13.9s (57.8x, -0.5%) ca:39.7s (165.4x, -0.4%) he:10.1s (41.9x, 0.0%) ca:14.2s (59.3x, 0.6%) dr: 9.6s (39.8x, -0.8%) ma: 8.3s (34.8x, -0.4%) -- bz2 -- bz2 valgrind-new:0.70s no: 5.0s ( 7.1x, -----) me:12.7s (18.1x, -----) ca:30.7s (43.9x, -----) he:19.5s (27.9x, -----) ca:34.3s (49.0x, -----) dr:29.1s (41.5x, -----) ma: 4.8s ( 6.8x, -----) bz2 valgrind-old:0.70s no: 5.0s ( 7.2x, -0.2%) me:12.7s (18.2x, -0.2%) ca:30.7s (43.9x, -0.0%) he:19.5s (27.9x, -0.1%) ca:34.3s (49.0x, 0.0%) dr:28.9s (41.3x, 0.4%) ma: 4.7s ( 6.7x, 1.9%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 3.9x, -----) me: 4.2s (10.2x, -----) ca: 9.3s (22.6x, -----) he: 6.2s (15.2x, -----) ca: 7.2s (17.6x, -----) dr: 5.5s (13.5x, -----) ma: 1.7s ( 4.1x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, -0.0%) me: 4.2s (10.3x, -0.5%) ca: 9.4s (22.9x, -1.0%) he: 6.2s (15.2x, 0.5%) ca: 7.2s (17.6x, -0.1%) dr: 5.5s (13.5x, -0.0%) ma: 1.7s ( 4.1x, 0.6%) -- ffbench -- ffbench valgrind-new:0.20s no: 1.1s ( 5.4x, -----) me: 3.0s (14.8x, -----) ca: 3.0s (15.1x, -----) he:43.3s (216.6x, -----) ca: 9.6s (48.1x, -----) dr: 6.9s (34.5x, -----) ma: 1.0s ( 4.8x, -----) ffbench valgrind-old:0.20s no: 1.1s ( 5.3x, 1.9%) me: 3.0s (14.8x, 0.0%) ca: 3.0s (15.1x, 0.0%) he:43.3s (216.6x, -0.0%) ca: 9.6s (48.0x, 0.1%) dr: 6.9s (34.5x, -0.1%) ma: 1.0s ( 4.8x, 0.0%) -- heap -- heap valgrind-new:0.23s no: 1.9s ( 8.3x, -----) me: 8.9s (38.8x, -----) ca:13.2s (57.3x, -----) he:12.6s (54.7x, -----) ca:11.3s (49.1x, -----) dr: 7.8s (33.7x, -----) ma: 7.8s (34.1x, -----) heap valgrind-old:0.23s no: 1.9s ( 8.3x, 0.0%) me: 8.8s (38.4x, 1.0%) ca:13.2s (57.4x, -0.2%) he:12.6s (54.7x, 0.0%) ca:11.3s (49.1x, 0.1%) dr: 7.7s (33.6x, 0.3%) ma: 7.8s (34.0x, 0.5%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.1s ( 9.6x, -----) me:13.0s (59.2x, -----) ca:14.3s (64.8x, -----) he:14.1s (63.9x, -----) ca:12.4s (56.3x, -----) dr: 8.6s (39.0x, -----) ma: 8.1s (36.6x, -----) heap_pdb4 valgrind-old:0.22s no: 2.1s ( 9.5x, 0.9%) me:13.0s (59.2x, 0.0%) ca:14.3s (65.0x, -0.2%) he:14.1s (64.1x, -0.4%) ca:12.3s (56.1x, 0.2%) dr: 8.6s (39.2x, -0.5%) ma: 8.0s (36.3x, 0.7%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (24.5x, -----) me: 2.1s (106.0x, -----) ca: 1.9s (97.0x, -----) he: 2.2s (108.0x, -----) ca: 1.9s (96.0x, -----) dr: 1.7s (86.5x, -----) ma: 1.7s (84.0x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (24.0x, 2.0%) me: 2.1s (106.5x, -0.5%) ca: 1.9s (97.5x, -0.5%) he: 2.2s (108.0x, 0.0%) ca: 1.9s (96.5x, -0.5%) dr: 1.7s (86.5x, 0.0%) ma: 1.7s (83.5x, 0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.7s ( 9.3x, -----) me: 3.2s (45.4x, -----) ca:369.3s (5276.3x, -----) he: 6.6s (93.7x, -----) ca: 2.8s (40.0x, -----) dr: 2.5s (35.9x, -----) ma: 2.7s (38.3x, -----) many-xpts valgrind-old:0.07s no: 0.6s ( 9.1x, 1.5%) me: 3.2s (45.4x, 0.0%) ca:362.6s (5179.3x, 1.8%) he: 6.6s (93.7x, 0.0%) ca: 2.8s (40.0x, 0.0%) dr: 2.5s (35.7x, 0.4%) ma: 2.7s (38.1x, 0.4%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (19.0x, -----) me: 3.4s (114.3x, -----) ca: 3.2s (106.0x, -----) he:17.1s (570.3x, -----) ca: 2.1s (68.7x, -----) dr: 1.3s (44.7x, -----) ma: 0.5s (17.0x, -----) sarp valgrind-old:0.03s no: 0.6s (19.0x, 0.0%) me: 3.4s (114.3x, 0.0%) ca: 3.2s (107.3x, -1.3%) he:17.1s (570.3x, 0.0%) ca: 2.1s (68.7x, 0.0%) dr: 1.4s (45.0x, -0.7%) ma: 0.5s (17.3x, -2.0%) -- tinycc -- tinycc valgrind-new:0.22s no: 2.8s (12.7x, -----) me:14.5s (65.9x, -----) ca:29.9s (136.0x, -----) he:28.0s (127.3x, -----) ca:21.4s (97.1x, -----) dr:20.6s (93.9x, -----) ma: 4.1s (18.6x, -----) tinycc valgrind-old:0.22s no: 2.8s (12.7x, 0.0%) me:14.5s (65.7x, 0.3%) ca:30.0s (136.3x, -0.2%) he:28.1s (128.0x, -0.5%) ca:21.4s (97.2x, -0.0%) dr:20.4s (92.6x, 1.3%) ma: 4.1s (18.5x, 0.2%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 110m39.394s user 109m47.982s sys 0m44.703s |
|
From: Tom H. <to...@co...> - 2014-06-28 03:24:27
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-06-28 03:51:22 BST Ended at 2014-06-28 04:24:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 656 tests, 3 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-06-28 03:02:04
|
valgrind revision: 14115
VEX revision: 2892
C compiler: gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012]
GDB: GNU gdb (GDB) SUSE (7.5.1-2.1.1)
Assembler: GNU assembler (GNU Binutils; openSUSE 12.3) 2.23.1
C library: GNU C Library (GNU libc) stable release version 2.17 (git c758a6861537)
uname -mrs: Linux 3.7.9-1.1-desktop x86_64
Vendor version: Welcome to openSUSE 12.3 "Dartmouth" Beta 1 - Kernel %r (%t).
Nightly build on ultra ( gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] Linux 3.7.9-1.1-desktop x86_64 )
Started at 2014-06-27 21:30:01 CDT
Ended at 2014-06-27 22:01:52 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 681 tests, 1 stderr failure, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
memcheck/tests/vbit-test/vbit-test (stderr)
=================================================
./valgrind-new/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-27 21:46:42.428176523 -0500
+++ hginfo.stderrB.out 2014-06-27 21:50:28.560881764 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-27 21:46:42.412176968 -0500
+++ mssnapshot.stderrB.out 2014-06-27 21:51:00.493993303 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-new/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-06-27 21:47:09.082434266 -0500
+++ vbit-test.stderr.out 2014-06-27 21:54:01.135978419 -0500
@@ -0,0 +1 @@
+unknown opcode 5981
=================================================
./valgrind-old/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-27 21:31:19.355821511 -0500
+++ hginfo.stderrB.out 2014-06-27 21:35:16.943282667 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-27 21:31:19.357821454 -0500
+++ mssnapshot.stderrB.out 2014-06-27 21:35:48.588410812 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-old/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-06-27 21:31:26.220632548 -0500
+++ vbit-test.stderr.out 2014-06-27 21:38:47.842406512 -0500
@@ -0,0 +1 @@
+unknown opcode 5981
|
|
From: Tom H. <to...@co...> - 2014-06-28 02:50:21
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-06-28 03:12:55 BST Ended at 2014-06-28 03:50:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 688 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-28 02:49:26
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-06-28 03:02:37 BST Ended at 2014-06-28 03:49:14 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 688 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) |
|
From: Rich C. <rc...@wi...> - 2014-06-28 02:32:47
|
valgrind revision: 14115
VEX revision: 2892
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-06-27 19:22:01 CDT
Ended at 2014-06-27 21:32:37 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 603 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
memcheck/tests/vbit-test/vbit-test (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-27 20:26:35.479149037 -0500
+++ hackedbz2.stderr.out 2014-06-27 21:31:26.102282028 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-27 20:25:25.685339398 -0500
+++ err_disable3.stderr.out 2014-06-27 20:52:22.243092200 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-27 20:23:56.600305971 -0500
+++ err_disable4.stderr.out 2014-06-27 20:52:26.629143080 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-27 20:25:25.630338760 -0500
+++ threadname.stderr.out 2014-06-27 20:58:41.097487082 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-27 20:24:34.265742907 -0500
+++ threadname_xml.stderr.out 2014-06-27 20:58:43.193511397 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-new/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-06-27 20:24:34.313743464 -0500
+++ vbit-test.stderr.out 2014-06-27 21:00:37.843841393 -0500
@@ -0,0 +1 @@
+unknown opcode 5981
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-27 19:23:24.677174018 -0500
+++ hackedbz2.stderr.out 2014-06-27 20:21:50.171839343 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-27 19:23:35.342297738 -0500
+++ err_disable3.stderr.out 2014-06-27 19:42:53.679734977 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-27 19:23:42.729383432 -0500
+++ err_disable4.stderr.out 2014-06-27 19:42:58.086786101 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-27 19:23:32.760267786 -0500
+++ threadname.stderr.out 2014-06-27 19:49:08.696085337 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-27 19:23:35.340297715 -0500
+++ threadname_xml.stderr.out 2014-06-27 19:49:10.758109257 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-06-27 19:23:38.651336125 -0500
+++ vbit-test.stderr.out 2014-06-27 19:51:05.188436701 -0500
@@ -0,0 +1 @@
+unknown opcode 5981
|
|
From: Tom H. <to...@co...> - 2014-06-28 02:32:27
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-06-28 02:51:08 BST Ended at 2014-06-28 03:32:14 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 688 tests, 6 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-28 02:19:08
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-06-28 02:41:16 BST Ended at 2014-06-28 03:18:53 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 688 tests, 3 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-28 02:12:57
|
valgrind revision: 14115 VEX revision: 2892 C compiler: gcc (GCC) 4.8.2 20131212 (Red Hat 4.8.2-7) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.14.7-200.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-06-28 02:31:42 BST Ended at 2014-06-28 03:12:42 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 688 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/hackedbz2 (stderr) |