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From: <sv...@va...> - 2014-06-12 15:37:24
|
Author: florian
Date: Thu Jun 12 15:37:15 2014
New Revision: 14027
Log:
Fix the cleanup: line to avoid an error message in case the
file does not exist.
Modified:
trunk/none/tests/require-text-symbol-2.vgtest
Modified: trunk/none/tests/require-text-symbol-2.vgtest
==============================================================================
--- trunk/none/tests/require-text-symbol-2.vgtest (original)
+++ trunk/none/tests/require-text-symbol-2.vgtest Thu Jun 12 15:37:15 2014
@@ -1,3 +1,3 @@
prog: require-text-symbol
vgopts: -q "--require-text-symbol=:*libc.so*:doesntexist" --vgdb-prefix=./vgdb-prefix-require-text-symbol-2
-cleanup: rm ./vgdb-prefix-require-text-symbol-2*
+cleanup: rm -f ./vgdb-prefix-require-text-symbol-2*
|
|
From: <sv...@va...> - 2014-06-12 13:16:50
|
Author: sewardj
Date: Thu Jun 12 13:16:43 2014
New Revision: 14026
Log:
Add test cases for FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[].
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Thu Jun 12 13:16:43 2014
@@ -1205,6 +1205,13 @@
GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x, "ucvtf s7, x15", 15, 7)
GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x, "ucvtf d7, x15", 15, 7)
+GEN_THREEVEC_TEST(fmul_2d_2d_d0, "fmul v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2d_2d_d1, "fmul v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_4s_4s_s0, "fmul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_4s_4s_s3, "fmul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2s_2s_s0, "fmul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2s_2s_s3, "fmul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+
GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29)
GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29)
GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29)
@@ -3115,6 +3122,12 @@
// fmul d_d_d[],s_s_s[]
// fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+ if (1) test_fmul_2d_2d_d0(TyDF);
+ if (1) test_fmul_2d_2d_d1(TyDF);
+ if (1) test_fmul_4s_4s_s0(TySF);
+ if (1) test_fmul_4s_4s_s3(TySF);
+ if (1) test_fmul_2s_2s_s0(TySF);
+ if (1) test_fmul_2s_2s_s3(TySF);
// fmul 2d,4s,2s
// fmul d,s
|
|
From: <sv...@va...> - 2014-06-12 13:16:13
|
Author: sewardj
Date: Thu Jun 12 13:16:01 2014
New Revision: 2874
Log:
Implement FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[].
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Thu Jun 12 13:16:01 2014
@@ -1112,7 +1112,7 @@
Int off = offsetQRegLane(qregNo, laneTy, laneNo);
switch (laneTy) {
case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8:
- case Ity_F64:
+ case Ity_F64: case Ity_F32:
break;
default:
vassert(0); // Other cases are ATC
@@ -1688,6 +1688,30 @@
}
+/* Duplicates the src element exactly so as to fill a V128 value. Only
+ handles src types of F64 and F32. */
+static IRTemp math_DUP_TO_V128 ( IRTemp src, IRType srcTy )
+{
+ IRTemp res = newTemp(Ity_V128);
+ if (srcTy == Ity_F64) {
+ IRTemp i64 = newTemp(Ity_I64);
+ assign(i64, unop(Iop_ReinterpF64asI64, mkexpr(src)));
+ assign(res, binop(Iop_64HLtoV128, mkexpr(i64), mkexpr(i64)));
+ return res;
+ }
+ if (srcTy == Ity_F32) {
+ IRTemp i64a = newTemp(Ity_I64);
+ assign(i64a, unop(Iop_32Uto64, unop(Iop_ReinterpF32asI32, mkexpr(src))));
+ IRTemp i64b = newTemp(Ity_I64);
+ assign(i64b, binop(Iop_Or64, binop(Iop_Shl64, mkexpr(i64a), mkU8(32)),
+ mkexpr(i64a)));
+ assign(res, binop(Iop_64HLtoV128, mkexpr(i64b), mkexpr(i64b)));
+ return res;
+ }
+ vassert(0);
+}
+
+
/*------------------------------------------------------------*/
/*--- FP comparison helpers ---*/
/*------------------------------------------------------------*/
@@ -6842,7 +6866,53 @@
static
Bool dis_AdvSIMD_vector_x_indexed_elem(/*MB_OUT*/DisResult* dres, UInt insn)
{
+ /* 31 28 23 21 20 19 15 11 9 4
+ 0 Q U 01111 size L M m opcode H 0 n d
+ Decode fields are: u,size,opcode
+ */
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ && INSN(28,24) != BITS5(0,1,1,1,1) && INSN(10,10) !=0) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt bitL = INSN(21,21);
+ UInt bitM = INSN(20,20);
+ UInt mmLO4 = INSN(19,16);
+ UInt opcode = INSN(15,12);
+ UInt bitH = INSN(11,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ UInt mm = (bitM << 4) | mmLO4;
+ vassert(size < 4);
+
+ if (bitU == 0 && size >= X10 && opcode == BITS4(1,0,0,1)) {
+ /* -------- 0,1x,1001 FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[] -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isD = (size & 1) == 1;
+ UInt index;
+ if (!isD) index = (bitH << 1) | bitL;
+ else if (isD && bitL == 0) index = bitH;
+ else return False; // sz:L == x11 => unallocated encoding
+ vassert(index < (isD ? 2 : 4));
+ IRType ity = isD ? Ity_F64 : Ity_F32;
+ IRTemp elem = newTemp(ity);
+ assign(elem, getQRegLane(mm, index, ity));
+ IRTemp dupd = math_DUP_TO_V128(elem, ity);
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, triop(isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4,
+ mkexpr(mk_get_IR_rounding_mode()),
+ getQReg128(nn), mkexpr(dupd)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("fmul %s.%s, %s.%s, %s.%c[%u]\n", nameQReg128(dd), arr,
+ nameQReg128(nn), arr, nameQReg128(mm), isD ? 'd' : 's', index);
+ return True;
+ }
+
return False;
# undef INSN
}
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Thu Jun 12 13:16:01 2014
@@ -1809,6 +1809,14 @@
vassert(laneNo <= 1);
return i;
}
+ARM64Instr* ARM64Instr_VXfromDorS ( HReg rX, HReg rDorS, Bool fromD ) {
+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
+ i->tag = ARM64in_VXfromDorS;
+ i->ARM64in.VXfromDorS.rX = rX;
+ i->ARM64in.VXfromDorS.rDorS = rDorS;
+ i->ARM64in.VXfromDorS.fromD = fromD;
+ return i;
+}
ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ) {
ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
i->tag = ARM64in_VMov;
@@ -2472,12 +2480,19 @@
ppHRegARM64(i->ARM64in.VQfromXX.rXlo);
return;
case ARM64in_VXfromQ:
- vex_printf("mov ");
+ vex_printf("fmov ");
ppHRegARM64(i->ARM64in.VXfromQ.rX);
vex_printf(", ");
ppHRegARM64(i->ARM64in.VXfromQ.rQ);
vex_printf(".d[%u]", i->ARM64in.VXfromQ.laneNo);
return;
+ case ARM64in_VXfromDorS:
+ vex_printf("fmov ");
+ ppHRegARM64(i->ARM64in.VXfromDorS.rX);
+ vex_printf("(%c-reg), ", i->ARM64in.VXfromDorS.fromD ? 'X':'W');
+ ppHRegARM64(i->ARM64in.VXfromDorS.rDorS);
+ vex_printf("(%c-reg)", i->ARM64in.VXfromDorS.fromD ? 'D' : 'S');
+ return;
case ARM64in_VMov: {
UChar aux = '?';
switch (i->ARM64in.VMov.szB) {
@@ -2865,6 +2880,10 @@
addHRegUse(u, HRmWrite, i->ARM64in.VXfromQ.rX);
addHRegUse(u, HRmRead, i->ARM64in.VXfromQ.rQ);
return;
+ case ARM64in_VXfromDorS:
+ addHRegUse(u, HRmWrite, i->ARM64in.VXfromDorS.rX);
+ addHRegUse(u, HRmRead, i->ARM64in.VXfromDorS.rDorS);
+ return;
case ARM64in_VMov:
addHRegUse(u, HRmWrite, i->ARM64in.VMov.dst);
addHRegUse(u, HRmRead, i->ARM64in.VMov.src);
@@ -3144,6 +3163,12 @@
i->ARM64in.VXfromQ.rQ
= lookupHRegRemap(m, i->ARM64in.VXfromQ.rQ);
return;
+ case ARM64in_VXfromDorS:
+ i->ARM64in.VXfromDorS.rX
+ = lookupHRegRemap(m, i->ARM64in.VXfromDorS.rX);
+ i->ARM64in.VXfromDorS.rDorS
+ = lookupHRegRemap(m, i->ARM64in.VXfromDorS.rDorS);
+ return;
case ARM64in_VMov:
i->ARM64in.VMov.dst = lookupHRegRemap(m, i->ARM64in.VMov.dst);
i->ARM64in.VMov.src = lookupHRegRemap(m, i->ARM64in.VMov.src);
@@ -3349,6 +3374,7 @@
#define X00000 BITS8(0,0,0, 0,0,0,0,0)
#define X00001 BITS8(0,0,0, 0,0,0,0,1)
+#define X00110 BITS8(0,0,0, 0,0,1,1,0)
#define X00111 BITS8(0,0,0, 0,0,1,1,1)
#define X01000 BITS8(0,0,0, 0,1,0,0,0)
#define X10000 BITS8(0,0,0, 1,0,0,0,0)
@@ -6294,6 +6320,20 @@
goto done;
}
+ case ARM64in_VXfromDorS: {
+ /* 000 11110001 00110 000000 n d FMOV Wd, Sn
+ 100 11110011 00110 000000 n d FMOV Xd, Dn
+ */
+ UInt dd = iregNo(i->ARM64in.VXfromDorS.rX);
+ UInt nn = dregNo(i->ARM64in.VXfromDorS.rDorS);
+ Bool fromD = i->ARM64in.VXfromDorS.fromD;
+ vassert(dd < 31);
+ *p++ = X_3_8_5_6_5_5(fromD ? X100 : X000,
+ fromD ? X11110011 : X11110001,
+ X00110, X000000, nn, dd);
+ goto done;
+ }
+
case ARM64in_VMov: {
/* 000 11110 00 10000 00 10000 n d FMOV Sd, Sn
000 11110 01 10000 00 10000 n d FMOV Dd, Dn
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Thu Jun 12 13:16:01 2014
@@ -598,6 +598,7 @@
ARM64in_VDfromX, /* Move an Xreg to a Dreg */
ARM64in_VQfromXX, /* Move 2 Xregs to a Qreg */
ARM64in_VXfromQ, /* Move half a Qreg to an Xreg */
+ ARM64in_VXfromDorS, /* Move Dreg or Sreg(ZX) to an Xreg */
ARM64in_VMov, /* vector reg-reg move, 16, 8 or 4 bytes */
/* infrastructure */
ARM64in_EvCheck, /* Event check */
@@ -990,6 +991,11 @@
HReg rQ;
UInt laneNo; /* either 0 or 1 */
} VXfromQ;
+ struct {
+ HReg rX;
+ HReg rDorS;
+ Bool fromD;
+ } VXfromDorS;
/* MOV dst, src -- reg-reg move for vector registers */
struct {
UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS
@@ -1084,6 +1090,7 @@
extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX );
extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo );
extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo );
+extern ARM64Instr* ARM64Instr_VXfromDorS ( HReg rX, HReg rDorS, Bool fromD );
extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src );
extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter,
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Thu Jun 12 13:16:01 2014
@@ -2109,6 +2109,18 @@
addInstr(env, ARM64Instr_VXfromQ(dst, src, laneNo));
return dst;
}
+ case Iop_ReinterpF64asI64: {
+ HReg dst = newVRegI(env);
+ HReg src = iselDblExpr(env, e->Iex.Unop.arg);
+ addInstr(env, ARM64Instr_VXfromDorS(dst, src, True/*fromD*/));
+ return dst;
+ }
+ case Iop_ReinterpF32asI32: {
+ HReg dst = newVRegI(env);
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ addInstr(env, ARM64Instr_VXfromDorS(dst, src, False/*!fromD*/));
+ return dst;
+ }
case Iop_1Sto32:
case Iop_1Sto64: {
/* As with the iselStmt case for 'tmp:I1 = expr', we could
|
|
From: <sv...@va...> - 2014-06-12 10:15:59
|
Author: sewardj
Date: Thu Jun 12 10:15:46 2014
New Revision: 2873
Log:
Remove the old SIMD decoder entirely.
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Thu Jun 12 10:15:46 2014
@@ -5011,7 +5011,6 @@
return True;
}
-
/* Help a bit for decoding laneage for vector operations that can be
of the form 4x32, 2x64 or 2x32-and-zero-upper-half, as encoded by Q
and SZ bits, typically for vector floating point. */
@@ -5050,34 +5049,6 @@
return False;
}
-/* Helper for decoding laneage for simple vector operations,
- eg integer add. */
-static Bool getLaneInfo_SIMPLE ( /*OUT*/Bool* zeroUpper,
- /*OUT*/const HChar** arrSpec,
- Bool bitQ, UInt szBlg2 )
-{
- vassert(bitQ == True || bitQ == False);
- vassert(szBlg2 < 4);
- Bool zu = False;
- const HChar* as = NULL;
- switch ((szBlg2 << 1) | (bitQ ? 1 : 0)) {
- case 0: zu = True; as = "8b"; break;
- case 1: zu = False; as = "16b"; break;
- case 2: zu = True; as = "4h"; break;
- case 3: zu = False; as = "8h"; break;
- case 4: zu = True; as = "2s"; break;
- case 5: zu = False; as = "4s"; break;
- case 6: return False; // impliedly 1x64
- case 7: zu = False; as = "2d"; break;
- default: vassert(0);
- }
- vassert(as);
- if (arrSpec) *arrSpec = as;
- if (zeroUpper) *zeroUpper = zu;
- return True;
-}
-
-
/* Helper for decoding laneage for shift-style vector operations
that involve an immediate shift amount. */
static Bool getLaneInfo_IMMH_IMMB ( /*OUT*/UInt* shift, /*OUT*/UInt* szBlg2,
@@ -5109,7 +5080,6 @@
return False;
}
-
/* Generate IR to fold all lanes of the V128 value in 'src' as
characterised by the operator 'op', and return the result in the
bottom bits of a V128, with all other bits set to zero. */
@@ -5845,14 +5815,15 @@
/* -------- {FMOV,MOVI} (vector, immediate) -------- */
/* Allowable op:cmode
FMOV = 1:1111
- MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110
+ MOVI = 0:xx00, 0:0010, 1:0x00, 1:10x0, 1:110x, x:1110,
*/
ULong imm64lo = 0;
UInt op_cmode = (bitOP << 4) | cmode;
Bool ok = False;
switch (op_cmode) {
case BITS5(1,1,1,1,1): // 1:1111
- case BITS5(0,0,0,0,0): case BITS5(0,0,1,0,0):
+ case BITS5(0,0,0,0,0): case BITS5(0,0,1,0,0): // 0:0x00
+ case BITS5(0,0,0,1,0): // 1:0010
case BITS5(0,1,0,0,0): case BITS5(0,1,1,0,0): // 0:xx00
case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00
case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0
@@ -5886,6 +5857,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_scalar_pairwise(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -5894,6 +5866,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_scalar_shift_by_imm(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -5914,6 +5887,19 @@
UInt dd = INSN(4,0);
UInt immhb = (immh << 3) | immb;
+ if (bitU == 1 && (immh & 8) == 8 && opcode == BITS5(0,0,0,0,0)) {
+ /* -------- 1,1xxx,00000 SHR d_d_#imm -------- */
+ UInt sh = 128 - immhb;
+ vassert(sh >= 1 && sh <= 64);
+ /* Don't generate an out of range IR shift */
+ putQReg128(dd, sh == 64
+ ? mkV128(0x0000)
+ : unop(Iop_ZeroHI64ofV128,
+ binop(Iop_ShrN64x2, getQReg128(nn), mkU8(sh))));
+ DIP("shr d%u, d%u, #%u\n", dd, nn, sh);
+ return True;
+ }
+
if (bitU == 0 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) {
/* -------- 0,1xxx,01010 SHL d_d_#imm -------- */
UInt sh = immhb - 64;
@@ -5929,6 +5915,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_scalar_three_different(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6031,6 +6018,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_scalar_x_indexed_element(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6039,6 +6027,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_shift_by_immediate(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6205,6 +6194,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_three_different(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6848,6 +6838,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_vector_x_indexed_elem(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6856,6 +6847,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_crypto_aes(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6864,6 +6856,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_crypto_three_reg_sha(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6872,6 +6865,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_crypto_two_reg_sha(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -6964,6 +6958,7 @@
# undef INSN
}
+
static
Bool dis_AdvSIMD_fp_conditional_select(/*MB_OUT*/DisResult* dres, UInt insn)
{
@@ -7602,1681 +7597,6 @@
return False;
}
-static
-Bool dis_ARM64_simd_and_fp_OLD(/*MB_OUT*/DisResult* dres, UInt insn)
-{
-# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
-
- /* -------------- FMOV (scalar, immediate) -------------- */
- /* 31 28 23 20 12 9 4
- 000 11110 00 1 imm8 100 00000 d FMOV Sd, #imm
- 000 11110 01 1 imm8 100 00000 d FMOV Dd, #imm
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,21) == 1 && INSN(12,5) == BITS8(1,0,0,0,0,0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt imm8 = INSN(20,13);
- UInt dd = INSN(4,0);
- ULong imm = VFPExpandImm(imm8, isD ? 64 : 32);
- if (!isD) {
- vassert(0 == (imm & 0xFFFFFFFF00000000ULL));
- }
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, isD ? mkU64(imm) : mkU32(imm & 0xFFFFFFFFULL));
- DIP("fmov %s, #0x%llx\n",
- nameQRegLO(dd, isD ? Ity_F64 : Ity_F32), imm);
- return True;
- }
-
- /* -------------- {S,U}CVTF (scalar, integer) -------------- */
- /* 31 28 23 21 20 18 15 9 4 ix
- 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn 0
- 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn 1
- 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn 2
- 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn 3
-
- 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn 4
- 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn 5
- 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn 6
- 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn 7
-
- These are signed/unsigned conversion from integer registers to
- FP registers, all 4 32/64-bit combinations, rounded per FPCR.
- */
- if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,17) == BITS5(1,0,0,0,1)
- && INSN(15,10) == BITS6(0,0,0,0,0,0)) {
- Bool isI64 = INSN(31,31) == 1;
- Bool isF64 = INSN(22,22) == 1;
- Bool isU = INSN(16,16) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
- const IROp ops[8]
- = { Iop_I32StoF32, Iop_I32StoF64, Iop_I64StoF32, Iop_I64StoF64,
- Iop_I32UtoF32, Iop_I32UtoF64, Iop_I64UtoF32, Iop_I64UtoF64 };
- IRExpr* src = getIRegOrZR(isI64, nn);
- IRExpr* res = (isF64 && !isI64)
- ? unop(ops[ix], src)
- : binop(ops[ix], mkexpr(mk_get_IR_rounding_mode()), src);
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, res);
- DIP("%ccvtf %s, %s\n",
- isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32),
- nameIRegOrZR(isI64, nn));
- return True;
- }
-
- /* ------------ F{ADD,SUB,MUL,DIV,NMUL} (scalar) ------------ */
- /* 31 23 20 15 11 9 4
- ---------------- 0000 ------ FMUL --------
- 000 11110 001 m 0001 10 n d FDIV Sd,Sn,Sm
- 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm
- ---------------- 0010 ------ FADD --------
- ---------------- 0011 ------ FSUB --------
- ---------------- 1000 ------ FNMUL --------
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt op = INSN(15,12);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IROp iop = Iop_INVALID;
- IRType ty = isD ? Ity_F64 : Ity_F32;
- Bool neg = False;
- const HChar* nm = "???";
- switch (op) {
- case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ty); break;
- case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ty); break;
- case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ty); break;
- case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ty); break;
- case BITS4(1,0,0,0): nm = "fnmul"; iop = mkMULF(ty);
- neg = True; break;
- default: return False;
- }
- vassert(iop != Iop_INVALID);
- IRExpr* resE = triop(iop, mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn, ty), getQRegLO(mm, ty));
- IRTemp res = newTemp(ty);
- assign(res, neg ? unop(mkNEGF(ty),resE) : resE);
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, mkexpr(res));
- DIP("%s %s, %s, %s\n",
- nm, nameQRegLO(dd, ty), nameQRegLO(nn, ty), nameQRegLO(mm, ty));
- return True;
- }
-
- /* ------------ F{MOV,ABS,NEG,SQRT} D/D or S/S ------------ */
- /* 31 23 21 16 14 9 4
- 000 11110 00 10000 00 10000 n d FMOV Sd, Sn
- 000 11110 01 10000 00 10000 n d FMOV Dd, Dn
- ------------------ 01 --------- FABS ------
- ------------------ 10 --------- FNEG ------
- ------------------ 11 --------- FSQRT -----
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,17) == BITS5(1,0,0,0,0)
- && INSN(14,10) == BITS5(1,0,0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt opc = INSN(16,15);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRType ty = isD ? Ity_F64 : Ity_F32;
- IRTemp res = newTemp(ty);
- if (opc == BITS2(0,0)) {
- assign(res, getQRegLO(nn, ty));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fmov %s, %s\n",
- nameQRegLO(dd, ty), nameQRegLO(nn, ty));
- return True;
- }
- if (opc == BITS2(1,0) || opc == BITS2(0,1)) {
- Bool isAbs = opc == BITS2(0,1);
- IROp op = isAbs ? mkABSF(ty) : mkNEGF(ty);
- assign(res, unop(op, getQRegLO(nn, ty)));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("%s %s, %s\n", isAbs ? "fabs" : "fneg",
- nameQRegLO(dd, ty), nameQRegLO(nn, ty));
- return True;
- }
- if (opc == BITS2(1,1)) {
- assign(res,
- binop(mkSQRTF(ty),
- mkexpr(mk_get_IR_rounding_mode()), getQRegLO(nn, ty)));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fsqrt %s, %s\n", nameQRegLO(dd, ty), nameQRegLO(nn, ty));
- return True;
- }
- /* else fall through; other cases are ATC */
- }
-
- /* ---------------- F{ABS,NEG} (vector) ---------------- */
- /* 31 28 22 21 16 9 4
- 0q0 01110 1 sz 10000 01111 10 n d FABS Vd.T, Vn.T
- 0q1 01110 1 sz 10000 01111 10 n d FNEG Vd.T, Vn.T
- */
- if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,0,1)
- && INSN(21,17) == BITS5(1,0,0,0,0)
- && INSN(16,10) == BITS7(0,1,1,1,1,1,0)) {
- UInt bitQ = INSN(30,30);
- UInt bitSZ = INSN(22,22);
- Bool isFNEG = INSN(29,29) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- const HChar* ar = "??";
- IRType tyF = Ity_INVALID;
- Bool zeroHI = False;
- Bool ok = getLaneInfo_Q_SZ(NULL, &tyF, NULL, &zeroHI, &ar,
- (Bool)bitQ, (Bool)bitSZ);
- if (ok) {
- vassert(tyF == Ity_F64 || tyF == Ity_F32);
- IROp op = (tyF == Ity_F64) ? (isFNEG ? Iop_Neg64Fx2 : Iop_Abs64Fx2)
- : (isFNEG ? Iop_Neg32Fx4 : Iop_Abs32Fx4);
- IRTemp res = newTemp(Ity_V128);
- assign(res, unop(op, getQReg128(nn)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
- : mkexpr(res));
- DIP("%s %s.%s, %s.%s\n", isFNEG ? "fneg" : "fabs",
- nameQReg128(dd), ar, nameQReg128(nn), ar);
- return True;
- }
- /* else fall through */
- }
-
- /* -------------------- FCMP,FCMPE -------------------- */
- /* 31 23 20 15 9 4
- 000 11110 01 1 m 00 1000 n 10 000 FCMPE Dn, Dm
- 000 11110 01 1 00000 00 1000 n 11 000 FCMPE Dn, #0.0
- 000 11110 01 1 m 00 1000 n 00 000 FCMP Dn, Dm
- 000 11110 01 1 00000 00 1000 n 01 000 FCMP Dn, #0.0
-
- 000 11110 00 1 m 00 1000 n 10 000 FCMPE Sn, Sm
- 000 11110 00 1 00000 00 1000 n 11 000 FCMPE Sn, #0.0
- 000 11110 00 1 m 00 1000 n 00 000 FCMP Sn, Sm
- 000 11110 00 1 00000 00 1000 n 01 000 FCMP Sn, #0.0
-
- FCMPE generates Invalid Operation exn if either arg is any kind
- of NaN. FCMP generates Invalid Operation exn if either arg is a
- signalling NaN. We ignore this detail here and produce the same
- IR for both.
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) && INSN(21,21) == 1
- && INSN(15,10) == BITS6(0,0,1,0,0,0) && INSN(2,0) == BITS3(0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- Bool isCMPE = INSN(4,4) == 1;
- Bool cmpZero = INSN(3,3) == 1;
- IRType ty = isD ? Ity_F64 : Ity_F32;
- Bool valid = True;
- if (cmpZero && mm != 0) valid = False;
- if (valid) {
- IRTemp argL = newTemp(ty);
- IRTemp argR = newTemp(ty);
- IRTemp irRes = newTemp(Ity_I32);
- assign(argL, getQRegLO(nn, ty));
- assign(argR,
- cmpZero
- ? (IRExpr_Const(isD ? IRConst_F64i(0) : IRConst_F32i(0)))
- : getQRegLO(mm, ty));
- assign(irRes, binop(isD ? Iop_CmpF64 : Iop_CmpF32,
- mkexpr(argL), mkexpr(argR)));
- IRTemp nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes);
- IRTemp nzcv_28x0 = newTemp(Ity_I64);
- assign(nzcv_28x0, binop(Iop_Shl64, mkexpr(nzcv), mkU8(28)));
- setFlags_COPY(nzcv_28x0);
- DIP("fcmp%s %s, %s\n", isCMPE ? "e" : "", nameQRegLO(nn, ty),
- cmpZero ? "#0.0" : nameQRegLO(mm, ty));
- return True;
- }
- }
-
- /* -------------------- F{N}M{ADD,SUB} -------------------- */
- /* 31 22 20 15 14 9 4 ix
- 000 11111 0 sz 0 m 0 a n d 0 FMADD Fd,Fn,Fm,Fa
- 000 11111 0 sz 0 m 1 a n d 1 FMSUB Fd,Fn,Fm,Fa
- 000 11111 0 sz 1 m 0 a n d 2 FNMADD Fd,Fn,Fm,Fa
- 000 11111 0 sz 1 m 1 a n d 3 FNMSUB Fd,Fn,Fm,Fa
- where Fx=Dx when sz=1, Fx=Sx when sz=0
-
- -----SPEC------ ----IMPL----
- fmadd a + n * m a + n * m
- fmsub a + (-n) * m a - n * m
- fnmadd (-a) + (-n) * m -(a + n * m)
- fnmsub (-a) + n * m -(a - n * m)
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,1,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt aa = INSN(14,10);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt ix = (INSN(21,21) << 1) | INSN(15,15);
- IRType ty = isD ? Ity_F64 : Ity_F32;
- IROp opADD = mkADDF(ty);
- IROp opSUB = mkSUBF(ty);
- IROp opMUL = mkMULF(ty);
- IROp opNEG = mkNEGF(ty);
- IRTemp res = newTemp(ty);
- IRExpr* eA = getQRegLO(aa, ty);
- IRExpr* eN = getQRegLO(nn, ty);
- IRExpr* eM = getQRegLO(mm, ty);
- IRExpr* rm = mkexpr(mk_get_IR_rounding_mode());
- IRExpr* eNxM = triop(opMUL, rm, eN, eM);
- switch (ix) {
- case 0: assign(res, triop(opADD, rm, eA, eNxM)); break;
- case 1: assign(res, triop(opSUB, rm, eA, eNxM)); break;
- case 2: assign(res, unop(opNEG, triop(opADD, rm, eA, eNxM))); break;
- case 3: assign(res, unop(opNEG, triop(opSUB, rm, eA, eNxM))); break;
- default: vassert(0);
- }
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- const HChar* names[4] = { "fmadd", "fmsub", "fnmadd", "fnmsub" };
- DIP("%s %s, %s, %s, %s\n",
- names[ix], nameQRegLO(dd, ty), nameQRegLO(nn, ty),
- nameQRegLO(mm, ty), nameQRegLO(aa, ty));
- return True;
- }
-
- /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */
- /* 30 23 20 18 15 9 4
- sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to
- sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest)
- ---------------- 01 -------------- FCVTP-------- (round to +inf)
- ---------------- 10 -------------- FCVTM-------- (round to -inf)
- ---------------- 11 -------------- FCVTZ-------- (round to zero)
-
- Rd is Xd when sf==1, Wd when sf==0
- Fn is Dn when x==1, Sn when x==0
- 20:19 carry the rounding mode, using the same encoding as FPCR
- */
- if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,21) == 1
- && INSN(18,17) == BITS2(0,0) && INSN(15,10) == BITS6(0,0,0,0,0,0)) {
- Bool isI64 = INSN(31,31) == 1;
- Bool isF64 = INSN(22,22) == 1;
- UInt rm = INSN(20,19);
- Bool isU = INSN(16,16) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- /* Decide on the IR rounding mode to use. */
- IRRoundingMode irrm = 8; /*impossible*/
- HChar ch = '?';
- switch (rm) {
- case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break;
- case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break;
- case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break;
- case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break;
- default: vassert(0);
- }
- vassert(irrm != 8);
- /* Decide on the conversion primop, based on the source size,
- dest size and signedness (8 possibilities). Case coding:
- F32 ->s I32 0
- F32 ->u I32 1
- F32 ->s I64 2
- F32 ->u I64 3
- F64 ->s I32 4
- F64 ->u I32 5
- F64 ->s I64 6
- F64 ->u I64 7
- */
- UInt ix = (isF64 ? 4 : 0) | (isI64 ? 2 : 0) | (isU ? 1 : 0);
- vassert(ix < 8);
- const IROp ops[8]
- = { Iop_F32toI32S, Iop_F32toI32U, Iop_F32toI64S, Iop_F32toI64U,
- Iop_F64toI32S, Iop_F64toI32U, Iop_F64toI64S, Iop_F64toI64U };
- IROp op = ops[ix];
- // A bit of ATCery: bounce all cases we haven't seen an example of.
- if (/* F32toI32S */
- (op == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */
- || (op == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */
- || (op == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */
- /* F32toI32U */
- || (op == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */
- || (op == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */
- /* F32toI64S */
- || (op == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */
- /* F32toI64U */
- || (op == Iop_F32toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Sn */
- /* F64toI32S */
- || (op == Iop_F64toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Dn */
- || (op == Iop_F64toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Dn */
- || (op == Iop_F64toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Dn */
- /* F64toI32U */
- || (op == Iop_F64toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Dn */
- || (op == Iop_F64toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Dn */
- || (op == Iop_F64toI32U && irrm == Irrm_PosINF) /* FCVTPU Wd,Dn */
- /* F64toI64S */
- || (op == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */
- || (op == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */
- || (op == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
- /* F64toI64U */
- || (op == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */
- || (op == Iop_F64toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Dn */
- ) {
- /* validated */
- } else {
- return False;
- }
- IRType srcTy = isF64 ? Ity_F64 : Ity_F32;
- IRType dstTy = isI64 ? Ity_I64 : Ity_I32;
- IRTemp src = newTemp(srcTy);
- IRTemp dst = newTemp(dstTy);
- assign(src, getQRegLO(nn, srcTy));
- assign(dst, binop(op, mkU32(irrm), mkexpr(src)));
- putIRegOrZR(isI64, dd, mkexpr(dst));
- DIP("fcvt%c%c %s, %s\n", ch, isU ? 'u' : 's',
- nameIRegOrZR(isI64, dd), nameQRegLO(nn, srcTy));
- return True;
- }
-
- /* -------- FCVTAS (KLUDGED) (scalar, integer) -------- */
- /* 30 23 20 18 15 9 4
- 1 00 11110 0x 1 00 100 000000 n d FCVTAS Xd, Fn
- 0 00 11110 0x 1 00 100 000000 n d FCVTAS Wd, Fn
- Fn is Dn when x==1, Sn when x==0
- */
- if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0)
- && INSN(21,16) == BITS6(1,0,0,1,0,0)
- && INSN(15,10) == BITS6(0,0,0,0,0,0)) {
- Bool isI64 = INSN(31,31) == 1;
- Bool isF64 = INSN(22,22) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- /* Decide on the IR rounding mode to use. */
- /* KLUDGE: should be Irrm_NEAREST_TIE_AWAY_0 */
- IRRoundingMode irrm = Irrm_NEAREST;
- /* Decide on the conversion primop. */
- IROp op = isI64 ? (isF64 ? Iop_F64toI64S : Iop_F32toI64S)
- : (isF64 ? Iop_F64toI32S : Iop_F32toI32S);
- IRType srcTy = isF64 ? Ity_F64 : Ity_F32;
- IRType dstTy = isI64 ? Ity_I64 : Ity_I32;
- IRTemp src = newTemp(srcTy);
- IRTemp dst = newTemp(dstTy);
- assign(src, getQRegLO(nn, srcTy));
- assign(dst, binop(op, mkU32(irrm), mkexpr(src)));
- putIRegOrZR(isI64, dd, mkexpr(dst));
- DIP("fcvtas %s, %s (KLUDGED)\n",
- nameIRegOrZR(isI64, dd), nameQRegLO(nn, srcTy));
- return True;
- }
-
- /* ---------------- FRINT{I,M,P,Z} (scalar) ---------------- */
- /* 31 23 21 17 14 9 4
- 000 11110 0x 1001 111 10000 n d FRINTI Fd, Fm (round per FPCR)
- rm
- x==0 => S-registers, x==1 => D-registers
- rm (17:15) encodings:
- 111 per FPCR (FRINTI)
- 001 +inf (FRINTP)
- 010 -inf (FRINTM)
- 011 zero (FRINTZ)
- 000 tieeven
- 100 tieaway (FRINTA) -- !! FIXME KLUDGED !!
- 110 per FPCR + "exact = TRUE"
- 101 unallocated
- */
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,18) == BITS4(1,0,0,1) && INSN(14,10) == BITS5(1,0,0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt rm = INSN(17,15);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRType ty = isD ? Ity_F64 : Ity_F32;
- IRExpr* irrmE = NULL;
- UChar ch = '?';
- switch (rm) {
- case BITS3(0,1,1): ch = 'z'; irrmE = mkU32(Irrm_ZERO); break;
- case BITS3(0,1,0): ch = 'm'; irrmE = mkU32(Irrm_NegINF); break;
- case BITS3(0,0,1): ch = 'p'; irrmE = mkU32(Irrm_PosINF); break;
- // The following is a kludge. Should be: Irrm_NEAREST_TIE_AWAY_0
- case BITS3(1,0,0): ch = 'a'; irrmE = mkU32(Irrm_NEAREST); break;
- default: break;
- }
- if (irrmE) {
- IRTemp src = newTemp(ty);
- IRTemp dst = newTemp(ty);
- assign(src, getQRegLO(nn, ty));
- assign(dst, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
- irrmE, mkexpr(src)));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(dst));
- DIP("frint%c %s, %s\n",
- ch, nameQRegLO(dd, ty), nameQRegLO(nn, ty));
- return True;
- }
- /* else unhandled rounding mode case -- fall through */
- }
-
- /* ------------------ FCVT (scalar) ------------------ */
- /* 31 23 21 16 14 9 4
- 000 11110 11 10001 00 10000 n d FCVT Sd, Hn (unimp)
- --------- 11 ----- 01 --------- FCVT Dd, Hn (unimp)
- --------- 00 ----- 11 --------- FCVT Hd, Sn (unimp)
- --------- 00 ----- 01 --------- FCVT Dd, Sn
- --------- 01 ----- 11 --------- FCVT Hd, Dn (unimp)
- --------- 01 ----- 00 --------- FCVT Sd, Dn
- Rounding, when dst is smaller than src, is per the FPCR.
- */
- if (INSN(31,24) == BITS8(0,0,0,1,1,1,1,0)
- && INSN(21,17) == BITS5(1,0,0,0,1)
- && INSN(14,10) == BITS5(1,0,0,0,0)) {
- UInt b2322 = INSN(23,22);
- UInt b1615 = INSN(16,15);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- if (b2322 == BITS2(0,0) && b1615 == BITS2(0,1)) {
- /* Convert S to D */
- IRTemp res = newTemp(Ity_F64);
- assign(res, unop(Iop_F32toF64, getQRegLO(nn, Ity_F32)));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fcvt %s, %s\n",
- nameQRegLO(dd, Ity_F64), nameQRegLO(nn, Ity_F32));
- return True;
- }
- if (b2322 == BITS2(0,1) && b1615 == BITS2(0,0)) {
- /* Convert D to S */
- IRTemp res = newTemp(Ity_F32);
- assign(res, binop(Iop_F64toF32, mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn, Ity_F64)));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fcvt %s, %s\n",
- nameQRegLO(dd, Ity_F32), nameQRegLO(nn, Ity_F64));
- return True;
- }
- /* else unhandled */
- }
-
- /* ------------------ FABD (scalar) ------------------ */
- /* 31 23 20 15 9 4
- 011 11110 111 m 110101 n d FABD Dd, Dn, Dm
- 011 11110 101 m 110101 n d FABD Sd, Sn, Sm
- */
- if (INSN(31,23) == BITS9(0,1,1,1,1,1,1,0,1) && INSN(21,21) == 1
- && INSN(15,10) == BITS6(1,1,0,1,0,1)) {
- Bool isD = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRType ty = isD ? Ity_F64 : Ity_F32;
- IRTemp res = newTemp(ty);
- assign(res, unop(mkABSF(ty),
- triop(mkSUBF(ty),
- mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn,ty), getQRegLO(mm,ty))));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fabd %s, %s, %s\n",
- nameQRegLO(dd, ty), nameQRegLO(nn, ty), nameQRegLO(mm, ty));
- return True;
- }
-
- /* -------------- {S,U}CVTF (vector, integer) -------------- */
- /* 31 28 22 21 15 9 4
- 0q0 01110 0 sz 1 00001 110110 n d SCVTF Vd, Vn
- 0q1 01110 0 sz 1 00001 110110 n d UCVTF Vd, Vn
- with laneage:
- case sz:Q of 00 -> 2S, zero upper, 01 -> 4S, 10 -> illegal, 11 -> 2D
- */
- if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,0,0)
- && INSN(21,16) == BITS6(1,0,0,0,0,1)
- && INSN(15,10) == BITS6(1,1,0,1,1,0)) {
- Bool isQ = INSN(30,30) == 1;
- Bool isU = INSN(29,29) == 1;
- Bool isF64 = INSN(22,22) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- if (isQ || !isF64) {
- IRType tyF = Ity_INVALID, tyI = Ity_INVALID;
- UInt nLanes = 0;
- Bool zeroHI = False;
- const HChar* arrSpec = NULL;
- Bool ok = getLaneInfo_Q_SZ(&tyI, &tyF, &nLanes, &zeroHI, &arrSpec,
- isQ, isF64 );
- IROp op = isU ? (isF64 ? Iop_I64UtoF64 : Iop_I32UtoF32)
- : (isF64 ? Iop_I64StoF64 : Iop_I32StoF32);
- IRTemp rm = mk_get_IR_rounding_mode();
- UInt i;
- vassert(ok); /* the 'if' above should ensure this */
- for (i = 0; i < nLanes; i++) {
- putQRegLane(dd, i,
- binop(op, mkexpr(rm), getQRegLane(nn, i, tyI)));
- }
- if (zeroHI) {
- putQRegLane(dd, 1, mkU64(0));
- }
- DIP("%ccvtf %s.%s, %s.%s\n", isU ? 'u' : 's',
- nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec);
- return True; }
- /* else fall through */
- }
-
- /* ---------- F{ADD,SUB,MUL,DIV,MLA,MLS} (vector) ---------- */
- /* 31 28 22 21 20 15 9 4 case
- 0q0 01110 0 sz 1 m 110101 n d FADD Vd,Vn,Vm 1
- 0q0 01110 1 sz 1 m 110101 n d FSUB Vd,Vn,Vm 2
- 0q1 01110 0 sz 1 m 110111 n d FMUL Vd,Vn,Vm 3
- 0q1 01110 0 sz 1 m 111111 n d FDIV Vd,Vn,Vm 4
- 0q0 01110 0 sz 1 m 110011 n d FMLA Vd,Vn,Vm 5
- 0q0 01110 1 sz 1 m 110011 n d FMLS Vd,Vn,Vm 6
- 0q1 01110 1 sz 1 m 110101 n d FABD Vd,Vn,Vm 7
- */
- if (INSN(31,31) == 0
- && INSN(28,24) == BITS5(0,1,1,1,0) && INSN(21,21) == 1) {
- Bool isQ = INSN(30,30) == 1;
- UInt b29 = INSN(29,29);
- UInt b23 = INSN(23,23);
- Bool isF64 = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt b1510 = INSN(15,10);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt ix = 0;
- /**/ if (b29 == 0 && b23 == 0 && b1510 == BITS6(1,1,0,1,0,1)) ix = 1;
- else if (b29 == 0 && b23 == 1 && b1510 == BITS6(1,1,0,1,0,1)) ix = 2;
- else if (b29 == 1 && b23 == 0 && b1510 == BITS6(1,1,0,1,1,1)) ix = 3;
- else if (b29 == 1 && b23 == 0 && b1510 == BITS6(1,1,1,1,1,1)) ix = 4;
- else if (b29 == 0 && b23 == 0 && b1510 == BITS6(1,1,0,0,1,1)) ix = 5;
- else if (b29 == 0 && b23 == 1 && b1510 == BITS6(1,1,0,0,1,1)) ix = 6;
- else if (b29 == 1 && b23 == 1 && b1510 == BITS6(1,1,0,1,0,1)) ix = 7;
- IRType laneTy = Ity_INVALID;
- Bool zeroHI = False;
- const HChar* arr = "??";
- Bool ok
- = getLaneInfo_Q_SZ(NULL, &laneTy, NULL, &zeroHI, &arr, isQ, isF64);
- /* Skip MLA/MLS for the time being */
- if (ok && ix >= 1 && ix <= 4) {
- const IROp ops64[4]
- = { Iop_Add64Fx2, Iop_Sub64Fx2, Iop_Mul64Fx2, Iop_Div64Fx2 };
- const IROp ops32[4]
- = { Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4 };
- const HChar* names[4]
- = { "fadd", "fsub", "fmul", "fdiv" };
- IROp op = laneTy==Ity_F64 ? ops64[ix-1] : ops32[ix-1];
- IRTemp rm = mk_get_IR_rounding_mode();
- IRTemp t1 = newTemp(Ity_V128);
- IRTemp t2 = newTemp(Ity_V128);
- assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
- assign(t2, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
- : mkexpr(t1));
- putQReg128(dd, mkexpr(t2));
- DIP("%s %s.%s, %s.%s, %s.%s\n", names[ix-1],
- nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
- return True;
- }
- if (ok && ix >= 5 && ix <= 6) {
- IROp opADD = laneTy==Ity_F64 ? Iop_Add64Fx2 : Iop_Add32Fx4;
- IROp opSUB = laneTy==Ity_F64 ? Iop_Sub64Fx2 : Iop_Sub32Fx4;
- IROp opMUL = laneTy==Ity_F64 ? Iop_Mul64Fx2 : Iop_Mul32Fx4;
- IRTemp rm = mk_get_IR_rounding_mode();
- IRTemp t1 = newTemp(Ity_V128);
- IRTemp t2 = newTemp(Ity_V128);
- // FIXME: double rounding; use FMA primops instead
- assign(t1, triop(opMUL,
- mkexpr(rm), getQReg128(nn), getQReg128(mm)));
- assign(t2, triop(ix == 5 ? opADD : opSUB,
- mkexpr(rm), getQReg128(dd), mkexpr(t1)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2))
- : mkexpr(t2));
- DIP("%s %s.%s, %s.%s, %s.%s\n", ix == 5 ? "fmla" : "fmls",
- nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
- return True;
- }
- if (ok && ix == 7) {
- IROp opSUB = laneTy==Ity_F64 ? Iop_Sub64Fx2 : Iop_Sub32Fx4;
- IROp opABS = laneTy==Ity_F64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4;
- IRTemp rm = mk_get_IR_rounding_mode();
- IRTemp t1 = newTemp(Ity_V128);
- IRTemp t2 = newTemp(Ity_V128);
- // FIXME: use Abd primop instead?
- assign(t1, triop(opSUB,
- mkexpr(rm), getQReg128(nn), getQReg128(mm)));
- assign(t2, unop(opABS, mkexpr(t1)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2))
- : mkexpr(t2));
- DIP("fabd %s.%s, %s.%s, %s.%s\n",
- nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
- return True;
- }
- }
-
- /* ------------ FCM{EQ,GE,GT}, FAC{GE,GT} (vector) ------------ */
- /* 31 28 22 20 15 9 4 case
- 0q1 01110 0 sz 1 m 111011 n d FACGE Vd, Vn, Vm
- 0q1 01110 1 sz 1 m 111011 n d FACGT Vd, Vn, Vm
- 0q0 01110 0 sz 1 m 111001 n d FCMEQ Vd, Vn, Vm
- 0q1 01110 0 sz 1 m 111001 n d FCMGE Vd, Vn, Vm
- 0q1 01110 1 sz 1 m 111001 n d FCMGT Vd, Vn, Vm
- */
- if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) && INSN(21,21) == 1
- && INSN(15,12) == BITS4(1,1,1,0) && INSN(10,10) == 1) {
- Bool isQ = INSN(30,30) == 1;
- UInt U = INSN(29,29);
- UInt E = INSN(23,23);
- Bool isF64 = INSN(22,22) == 1;
- UInt ac = INSN(11,11);
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- /* */
- UInt EUac = (E << 2) | (U << 1) | ac;
- IROp opABS = Iop_INVALID;
- IROp opCMP = Iop_INVALID;
- IRType laneTy = Ity_INVALID;
- Bool zeroHI = False;
- Bool swap = True;
- const HChar* arr = "??";
- const HChar* nm = "??";
- Bool ok
- = getLaneInfo_Q_SZ(NULL, &laneTy, NULL, &zeroHI, &arr, isQ, isF64);
- if (ok) {
- vassert((isF64 && laneTy == Ity_F64) || (!isF64 && laneTy == Ity_F32));
- switch (EUac) {
- case BITS3(0,0,0):
- nm = "fcmeq";
- opCMP = isF64 ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4;
- swap = False;
- break;
- case BITS3(0,1,0):
- nm = "fcmge";
- opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4;
- break;
- case BITS3(0,1,1):
- nm = "facge";
- opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4;
- opABS = isF64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4;
- break;
- case BITS3(1,1,0):
- nm = "fcmgt";
- opCMP = isF64 ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4;
- break;
- case BITS3(1,1,1):
- nm = "facgt";
- opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; // wrong?
- opABS = isF64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4;
- break;
- default:
- break;
- }
- }
- if (opCMP != Iop_INVALID) {
- IRExpr* argN = getQReg128(nn);
- IRExpr* argM = getQReg128(mm);
- if (opABS != Iop_INVALID) {
- argN = unop(opABS, argN);
- argM = unop(opABS, argM);
- }
- IRExpr* res = swap ? binop(opCMP, argM, argN)
- : binop(opCMP, argN, argM);
- if (zeroHI) {
- res = unop(Iop_ZeroHI64ofV128, res);
- }
- putQReg128(dd, res);
- DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
- nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
- return True;
- }
- /* else fall through */
- }
-
- /* -------------------- FCVTN -------------------- */
- /* 31 28 23 20 15 9 4
- 0q0 01110 0s1 00001 011010 n d FCVTN Vd, Vn
- where case q:s of 00: 16Fx4(lo) <- 32Fx4
- 01: 32Fx2(lo) <- 64Fx2
- 10: 16Fx4(hi) <- 32Fx4
- 11: 32Fx2(hi) <- 64Fx2
- Only deals with the 32Fx2 <- 64Fx2 version (s==1)
- */
- if (INSN(31,31) == 0 && INSN(29,23) == BITS7(0,0,1,1,1,0,0)
- && INSN(21,10) == BITS12(1,0,0,0,0,1,0,1,1,0,1,0)) {
- UInt bQ = INSN(30,30);
- UInt bS = INSN(22,22);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- if (bS == 1) {
- IRTemp rm = mk_get_IR_rounding_mode();
- IRExpr* srcLo = getQRegLane(nn, 0, Ity_F64);
- IRExpr* srcHi = getQRegLane(nn, 1, Ity_F64);
- putQRegLane(dd, 2 * bQ + 0, binop(Iop_F64toF32, mkexpr(rm), srcLo));
- putQRegLane(dd, 2 * bQ + 1, binop(Iop_F64toF32, mkexpr(rm), srcHi));
- if (bQ == 0) {
- putQRegLane(dd, 1, mkU64(0));
- }
- DIP("fcvtn%s %s.%s, %s.2d\n", bQ ? "2" : "",
- nameQReg128(dd), bQ ? "4s" : "2s", nameQReg128(nn));
- return True;
- }
- /* else fall through */
- }
-
- /* ---------------- ADD/SUB (vector) ---------------- */
- /* 31 28 23 21 20 15 9 4
- 0q0 01110 size 1 m 100001 n d ADD Vd.T, Vn.T, Vm.T
- 0q1 01110 size 1 m 100001 n d SUB Vd.T, Vn.T, Vm.T
- */
- if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0)
- && INSN(21,21) == 1 && INSN(15,10) == BITS6(1,0,0,0,0,1)) {
- Bool isQ = INSN(30,30) == 1;
- UInt szBlg2 = INSN(23,22);
- Bool isSUB = INSN(29,29) == 1;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- Bool zeroHI = False;
- const HChar* arrSpec = "";
- Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
- if (ok) {
- const IROp opsADD[4]
- = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 };
- const IROp opsSUB[4]
- = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
- vassert(szBlg2 < 4);
- IROp op = isSUB ? opsSUB[szBlg2] : opsADD[szBlg2];
- IRTemp t = newTemp(Ity_V128);
- assign(t, binop(op, getQReg128(nn), getQReg128(mm)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t))
- : mkexpr(t));
- const HChar* nm = isSUB ? "sub" : "add";
- DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
- nameQReg128(dd), arrSpec,
- nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec);
- return True;
- }
- /* else fall through */
- }
-
- /* ---------------- ADD/SUB (scalar) ---------------- */
- /* 31 28 23 21 20 15 9 4
- 010 11110 11 1 m 100001 n d ADD Dd, Dn, Dm
- 011 11110 11 1 m 100001 n d SUB Dd, Dn, Dm
- */
- if (INSN(31,30) == BITS2(0,1) && INSN(28,21) == BITS8(1,1,1,1,0,1,1,1)
- && INSN(15,10) == BITS6(1,0,0,0,0,1)) {
- Bool isSUB = INSN(29,29) == 1;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRTemp res = newTemp(Ity_I64);
- assign(res, binop(isSUB ? Iop_Sub64 : Iop_Add64,
- getQRegLane(nn, 0, Ity_I64),
- getQRegLane(mm, 0, Ity_I64)));
- putQRegLane(dd, 0, mkexpr(res));
- putQRegLane(dd, 1, mkU64(0));
- DIP("%s %s, %s, %s\n", isSUB ? "sub" : "add",
- nameQRegLO(dd, Ity_I64),
- nameQRegLO(nn, Ity_I64), nameQRegLO(mm, Ity_I64));
- return True;
- }
-
- /* ------------ MUL/PMUL/MLA/MLS (vector) ------------ */
- /* 31 28 23 21 20 15 9 4
- 0q0 01110 size 1 m 100111 n d MUL Vd.T, Vn.T, Vm.T B/H/S only
- 0q1 01110 size 1 m 100111 n d PMUL Vd.T, Vn.T, Vm.T B only
- 0q0 01110 size 1 m 100101 n d MLA Vd.T, Vn.T, Vm.T B/H/S only
- 0q1 01110 size 1 m 100101 n d MLS Vd.T, Vn.T, Vm.T B/H/S only
- */
- if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0)
- && INSN(21,21) == 1
- && (INSN(15,10) & BITS6(1,1,1,1,0,1)) == BITS6(1,0,0,1,0,1)) {
- Bool isQ = INSN(30,30) == 1;
- UInt szBlg2 = INSN(23,22);
- UInt bit29 = INSN(29,29);
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- Bool isMLAS = INSN(11,11) == 0;
- const IROp opsADD[4]
- = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_INVALID };
- const IROp opsSUB[4]
- = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_INVALID };
- const IROp opsMUL[4]
- = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, Iop_INVALID };
- const IROp opsPMUL[4]
- = { Iop_PolynomialMul8x16, Iop_INVALID, Iop_INVALID, Iop_INVALID };
- /* Set opMUL and, if necessary, opACC. A result value of
- Iop_INVALID for opMUL indicates that the instruction is
- invalid. */
- Bool zeroHI = False;
- const HChar* arrSpec = "";
- Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
- vassert(szBlg2 < 4);
- IROp opACC = Iop_INVALID;
- IROp opMUL = Iop_INVALID;
- if (ok) {
- opMUL = (bit29 == 1 && !isMLAS) ? opsPMUL[szBlg2]
- : opsMUL[szBlg2];
- opACC = isMLAS ? (bit29 == 1 ? opsSUB[szBlg2] : opsADD[szBlg2])
- : Iop_INVALID;
- }
- if (ok && opMUL != Iop_INVALID) {
- IRTemp t1 = newTemp(Ity_V128);
- assign(t1, binop(opMUL, getQReg128(nn), getQReg128(mm)));
- IRTemp t2 = newTemp(Ity_V128);
- assign(t2, opACC == Iop_INVALID
- ? mkexpr(t1)
- : binop(opACC, getQReg128(dd), mkexpr(t1)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2))
- : mkexpr(t2));
- const HChar* nm = isMLAS ? (bit29 == 1 ? "mls" : "mla")
- : (bit29 == 1 ? "pmul" : "mul");
- DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
- nameQReg128(dd), arrSpec,
- nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec);
- return True;
- }
- /* else fall through */
- }
-
- /* ---------------- {S,U}{MIN,MAX} (vector) ---------------- */
- /* 31 28 23 21 20 15 9 4
- 0q0 01110 size 1 m 011011 n d SMIN Vd.T, Vn.T, Vm.T
- 0q1 01110 size 1 m 011011 n d UMIN Vd.T, Vn.T, Vm.T
- 0q0 01110 size 1 m 011001 n d SMAX Vd.T, Vn.T, Vm.T
- 0q1 01110 size 1 m 011001 n d UMAX Vd.T, Vn.T, Vm.T
- */
- if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0)
- && INSN(21,21) == 1
- && ((INSN(15,10) & BITS6(1,1,1,1,0,1)) == BITS6(0,1,1,0,0,1))) {
- Bool isQ = INSN(30,30) == 1;
- Bool isU = INSN(29,29) == 1;
- UInt szBlg2 = INSN(23,22);
- Bool isMAX = INSN(11,11) == 0;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- Bool zeroHI = False;
- const HChar* arrSpec = "";
- Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
- if (ok) {
- const IROp opMINS[4]
- = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2 };
- const IROp opMINU[4]
- = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, Iop_Min64Ux2 };
- const IROp opMAXS[4]
- = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2 };
- const IROp opMAXU[4]
- = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2 };
- vassert(szBlg2 < 4);
- IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2])
- : (isU ? opMINU[szBlg2] : opMINS[szBlg2]);
- IRTemp t = newTemp(Ity_V128);
- assign(t, binop(op, getQReg128(nn), getQReg128(mm)));
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t))
- : mkexpr(t));
- const HChar* nm = isMAX ? (isU ? "umax" : "smax")
- : (isU ? "umin" : "smin");
- DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
- nameQReg128(dd), arrSpec,
- nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec);
- return True;
- }
- /* else fall through */
- }
-
- /* -------------------- {S,U}{MIN,MAX}V -------------------- */
- /* 31 28 23 21 16 15 9 4
- 0q0 01110 size 11000 1 101010 n d SMINV Vd, Vn.T
- 0q1 01110 size 11000 1 101010 n d UMINV Vd, Vn.T
- 0q0 01110 size 11000 0 101010 n d SMAXV Vd, Vn.T
- 0q1 01110 size 11000 0 101010 n d UMAXV Vd, Vn.T
- */
- if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0)
- && INSN(21,17) == BITS5(1,1,0,0,0)
- && INSN(15,10) == BITS6(1,0,1,0,1,0)) {
- Bool isQ = INSN(30,30) == 1;
- Bool isU = INSN(29,29) == 1;
- UInt szBlg2 = INSN(23,22);
- Bool isMAX = INSN(16,16) == 0;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- Bool zeroHI = False;
- const HChar* arrSpec = "";
- Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2);
- if (ok) {
- if (szBlg2 == 3) ok = False;
- if (szBlg2 == 2 && !isQ) ok = False;
- }
- if (ok) {
- const IROp opMINS[3]
- = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4 };
- const IROp opMINU[3]
- = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4 };
- const IROp opMAXS[3]
- = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4 };
- const IROp opMAXU[3]
- = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4 };
- vassert(szBlg2 < 3);
- IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2])
- : (isU ? opMINU[szBlg2] : opMINS[szBlg2]);
- IRTemp tN1 = newTemp(Ity_V128);
- assign(tN1, getQReg128(nn));
- /* If Q == 0, we're just folding lanes in the lower half of
- the value. In which case, copy the lower half of the
- source into the upper half, so we can then treat it the
- same as the full width case. */
- IRTemp tN2 = newTemp(Ity_V128);
- assign(tN2, zeroHI ? mk_CatEvenLanes64x2(tN1,tN1) : mkexpr(tN1));
- IRTemp res = math_MINMAXV(tN2, op);
- if (res == IRTemp_INVALID)
- return False; /* means math_MINMAXV
- doesn't handle this case yet */
- putQReg128(dd, mkexpr(res));
- const HChar* nm = isMAX ? (isU ? "umaxv" : "smaxv")
- : (isU ? "uminv" : "sminv");
- const IRType tys[3] = { Ity_I8, Ity_I16, Ity_I32 };
- IRType laneTy = tys[szBlg2];
- DIP("%s %s, %s.%s\n", nm,
- nameQRegLO(dd, laneTy), nameQReg128(nn), arrSpec);
- return True;
- }
- /* else fall through */
- }
-
- /* ------------ {AND,BIC,ORR,ORN} (vector) ------------ */
- /* 31 28 23 20 15 9 4
- 0q0 01110 001 m 000111 n d AND Vd.T, Vn.T, Vm.T
- 0q0 01110 011 m 000111 n d BIC Vd.T, Vn.T, Vm.T
- 0q0 01110 101 m 000111 n d ORR Vd.T, Vn.T, Vm.T
- 0q0 01110 111 m 000111 n d ORN Vd.T, Vn.T, Vm.T
- T is 16b when q==1, 8b when q==0
- */
- if (INSN(31,31) == 0 && INSN(29,24) == BITS6(0,0,1,1,1,0)
- && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,1,1,1)) {
- Bool isQ = INSN(30,30) == 1;
- Bool isORR = INSN(23,23) == 1;
- Bool invert = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRTemp res = newTemp(Ity_V128);
- assign(res, binop(isORR ? Iop_OrV128 : Iop_AndV128,
- getQReg128(nn),
- invert ? unop(Iop_NotV128, getQReg128(mm))
- : getQReg128(mm)));
- putQReg128(dd, isQ ? mkexpr(res)
- : unop(Iop_ZeroHI64ofV128, mkexpr(res)));
- const HChar* names[4] = { "and", "bic", "orr", "orn" };
- const HChar* ar = isQ ? "16b" : "8b";
- DIP("%s %s.%s, %s.%s, %s.%s\n", names[INSN(23,22)],
- nameQReg128(dd), ar, nameQReg128(nn), ar, nameQReg128(mm), ar);
- return True;
- }
-
- /* ---------- CM{EQ,HI,HS,GE,GT,TST,LE,LT} (vector) ---------- */
- /* 31 28 23 21 15 9 4 ix
- 0q1 01110 size 1 m 100011 n d CMEQ Vd.T, Vn.T, Vm.T (1) ==
- 0q0 01110 size 1 m 100011 n d CMTST Vd.T, Vn.T, Vm.T (2) &, != 0
-
- 0q1 01110 size 1 m 001101 n d CMHI Vd.T, Vn.T, Vm.T (3) >u
- 0q0 01110 size 1 m 001101 n d CMGT Vd.T, Vn.T, Vm.T (4) >s
-
- 0q1 01110 size 1 m 001111 n d CMHS Vd.T, Vn.T, Vm.T (5) >=u
- 0q0 01110 size 1 m 001111 n d CMGE Vd.T, Vn.T, Vm.T (6) >=s
-
- 0q1 01110 size 100000 100010 n d CMGE Vd.T, Vn.T, #0 (7) >=s 0
- 0q0 01110 size 100000 100010 n d CMGT Vd.T, Vn.T, #0 (8) >s 0
-
- 0q1 01110 size 100000 100110 n d CMLE Vd.T, Vn.T, #0 (9) <=s 0
- 0q0 01110 size 100000 100110 n d CMEQ Vd.T, Vn.T, #0 (10) == 0
-
- 0q0 01110 size 100000 101010 n d CMLT Vd.T, Vn.T, #0 (11) <s 0
- */
- if (INSN(31,31) == 0
- && INSN(28,24) == BITS5(0,1,1,1,0) && INSN(21,21) == 1) {
- Bool isQ = INSN(30,30) == 1;
- UInt bit29 = INSN(29,29);
- UInt szBlg2 = INSN(23,22);
- UInt mm = INSN(20,16);
- UInt b1510 = INSN(15,10);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- const IROp opsEQ[4]
- = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, Iop_CmpEQ64x2 };
- const IROp opsGTS[4]
- = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 };
- const IROp opsGTU[4]
- = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, Iop_CmpGT64Ux2 };
- Bool zeroHI = False;
- const HChar* arrSpec = "??";
- Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2);
- UInt ix = 0;
- if (ok) {
- switch (b1510) {
- case BITS6(1,0,0,0,1,1): ix = bit29 ? 1 : 2; break;
- case BITS6(0,0,1,1,0,1): ix = bit29 ? 3 : 4; break;
- case BITS6(0,0,1,1,1,1): ix = bit29 ? 5 : 6; break;
- case BITS6(1,0,0,0,1,0):
- if (mm == 0) { ix = bit29 ? 7 : 8; }; break;
- case BITS6(1,0,0,1,1,0):
- if (mm == 0) { ix = bit29 ? 9 : 10; }; break;
- case BITS6(1,0,1,0,1,0):
- if (mm == 0 && bit29 == 0) { ix = 11; }; break;
- default: break;
- }
- }
- if (ix != 0) {
- vassert(ok && szBlg2 < 4);
- IRExpr* argL = getQReg128(nn);
- IRExpr* argR = (ix <= 6) ? getQReg128(mm) : mkV128(0x0000);
- IRExpr* res = NULL;
- /* Some useful identities:
- x > y can be expressed directly
- x < y == y > x
- x <= y == not (x > y)
- x >= y == not (y > x)
- */
- switch (ix) {
- case 1: res = binop(opsEQ[szBlg2], argL, argR); break;
- case 2: res = unop(Iop_NotV128, binop(opsEQ[szBlg2],
- binop(Iop_AndV128, argL, argR),
- mkV128(0x0000)));
- break;
- case 3: res = binop(opsGTU[szBlg2], argL, argR); break;
- case 4: res = binop(opsGTS[szBlg2], argL, argR); break;
- case 5: res = unop(Iop_NotV128, binop(opsGTU[szBlg2], argR, argL));
- break;
- case 6: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL));
- break;
- case 7: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL));
- break;
- case 8: res = binop(opsGTS[szBlg2], argL, argR); break;
- case 9: res = unop(Iop_NotV128,
- binop(opsGTS[szBlg2], argL, argR));
- break;
- case 10: res = binop(opsEQ[szBlg2], argL, argR); break;
- case 11: res = binop(opsGTS[szBlg2], argR, argL); break;
- default: vassert(0);
- }
- vassert(res);
- putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, res) : res);
- const HChar* nms[11] = { "eq", "tst", "hi", "gt", "hs", "ge",
- "ge", "gt", "le", "eq", "lt" };
- if (ix <= 6) {
- DIP("cm%s %s.%s, %s.%s, %s.%s\n", nms[ix-1],
- nameQReg128(dd), arrSpec,
- nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec);
- } else {
- DIP("cm%s %s.%s, %s.%s, #0\n", nms[ix-1],
- nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec);
- }
- return True;
- }
- /* else fall through */
- }
-
- /* -------------- {EOR,BSL,BIT,BIF} (vector) -------------- */
- /* 31 28 23 20 15 9 4
- 0q1 01110 00 1 m 000111 n d EOR Vd.T, Vm.T, Vn.T
- 0q1 01110 01 1 m 000111 n d BSL Vd.T, Vm.T, Vn.T
- 0q1 01110 10 1 m 000111 n d BIT Vd.T, Vm.T, Vn.T
- 0q1 01110 11 1 m 000111 n d BIF Vd.T, Vm.T, Vn.T
- */
- if (INSN(31,31) == 0 && INSN(29,24) == BITS6(1,0,1,1,1,0)
- && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,1,1,1)) {
- Bool isQ = INSN(30,30) == 1;
- UInt op = INSN(23,22);
- UInt mm = INSN(20,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRTemp argD = newTemp(Ity_V128);
- IRTemp argN = newTemp(Ity_V128);
- IRTemp argM = newTemp(Ity_V128);
- assign(argD, getQReg128(dd));
- assign(argN, getQReg128(nn));
- assign(argM, getQReg128(mm));
- const IROp opXOR = Iop_XorV128;
- const IROp opAND = Iop_AndV128;
- const IROp opNOT = Iop_NotV128;
- IRExpr* res = NULL;
- switch (op) {
- case BITS2(0,0): /* EOR */
- res = binop(opXOR, mkexpr(argM), mkexpr(argN));
- break;
- case BITS2(0,1): /* BSL */
- res = binop(opXOR, mkexpr(argM),
- binop(opAND,
- binop(opXOR, mkexpr(argM), mkexpr(argN)),
- mkexpr(argD)));
- break;
- case BITS2(1,0): /* BIT */
- res = binop(opXOR, mkexpr(argD),
- binop(opAND,
- binop(opXOR, mkexpr(argD), mkexpr(argN)),
- mkexpr(argM)));
- break;
- case BITS2(1,1): /* BIF */
- res = binop(opXOR, mkexpr(argD),
- binop(opAND,
- binop(opXOR, mkexpr(argD), mkexpr(argN)),
- unop(opNOT, mkexpr(argM))));
- break;
- default:
- vassert(0);
- }
- vassert(res);
- putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
- const HChar* nms[4] = { "eor", "bsl", "bit", "bif" };
- const HChar* arr = isQ ? "16b" : "8b";
- vassert(op < 4);
- DIP("%s %s.%s, %s.%s, %s.%s\n", nms[op],
- nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
- return True;
- }
-
- /* ------------ {USHR,SSHR,SHL} (vector, immediate) ------------ */
- /* 31 28 22 18 15 9 4
- 0q1 011110 immh immb 000001 n d USHR Vd.T, Vn.T, #shift (1)
- 0q0 011110 immh immb 000001 n d SSHR Vd.T, Vn.T, #shift (2)
- 0q0 011110 immh immb 010101 n d SHL Vd.T, Vn.T, #shift (3)
- laneTy, shift = case immh:immb of
- 0001:xxx -> B, SHR:8-xxx, SHL:xxx
- 001x:xxx -> H, SHR:16-xxxx SHL:xxxx
- 01xx:xxx -> S, SHR:32-xxxxx SHL:xxxxx
- 1xxx:xxx -> D, SHR:64-xxxxxx SHL:xxxxxx
- other -> invalid
- As usual the case laneTy==D && q==0 is not allowed.
- */
- if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,1,0)
- && INSN(10,10) == 1) {
- UInt ix = 0;
- /**/ if (INSN(29,29) == 1 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 1;
- else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 2;
- else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,1,0,1,0)) ix = 3;
- if (ix > 0) {
- Bool isQ = INSN(30,30) == 1;
- UInt immh = INSN(22,19);
- UInt immb = INSN(18,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- const IROp opsSHRN[4]
- = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 };
- const IROp opsSARN[4]
- = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 };
- const IROp opsSHLN[4]
- = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 };
- UInt szBlg2 = 0;
- UInt shift = 0;
- Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
- if (ix == 3) {
- /* The shift encoding has opposite sign for the leftwards
- case. Adjust shift to compensate. */
- shift = (8 << szBlg2) - shift;
- }
- if (ok && szBlg2 < 4 && shift > 0 && shift < (8 << szBlg2)
- && !(szBlg2 == 3/*64bit*/ && !isQ)) {
- IROp op = Iop_INVALID;
- const HChar* nm = NULL;
- switch (ix) {
- case 1: op = opsSHRN[szBlg2]; nm = "ushr"; break;
- case 2: op = opsSARN[szBlg2]; nm = "sshr"; break;
- case 3: op = opsSHLN[szBlg2]; nm = "shl"; break;
- default: vassert(0);
- }
- IRExpr* src = getQReg128(nn);
- IRExpr* res = binop(op, src, mkU8(shift));
- putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
- HChar laneCh = "bhsd"[szBlg2];
- UInt nLanes = (isQ ? 128 : 64) / (8 << szBlg2);
- DIP("%s %s.%u%c, %s.%u%c, #%u\n", nm,
- nameQReg128(dd), nLanes, laneCh,
- nameQReg128(nn), nLanes, laneCh, shift);
- return True;
- }
- /* else fall through */
- }
- }
-
- /* -------------------- {U,S}SHLL{,2} -------------------- */
- /* 31 28 22 18 15 9 4
- 0q0 011110 immh immb 101001 n d SSHLL Vd.Ta, Vn.Tb, #sh
- 0q1 011110 immh immb 101001 n d USHLL Vd.Ta, Vn.Tb, #sh
- where Ta,Tb,sh
- = case immh of 1xxx -> invalid
- 01xx -> 2d, 2s(q0)/4s(q1), immh:immb - 32 (0..31)
- 001x -> 4s, 4h(q0)/8h(q1), immh:immb - 16 (0..15)
- 0001 -> 8h, 8b(q0)/16b(q1), immh:immb - 8 (0..7)
- 0000 -> AdvSIMD modified immediate (???)
- */
- if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,1,0)
- && INSN(15,10) == BITS6(1,0,1,0,0,1)) {
- Bool isQ = INSN(30,30) == 1;
- Bool isU = INSN(29,29) == 1;
- UInt immh = INSN(22,19);
- UInt immb = INSN(18,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt immhb = (immh << 3) | immb;
- IRTemp src = newTemp(Ity_V128);
- IRTemp zero = newTemp(Ity_V128);
- IRExpr* res = NULL;
- UInt sh = 0;
- const HChar* ta = "??";
- const HChar* tb = "??";
- assign(src, getQReg128(nn));
- assign(zero, mkV128(0x0000));
- if (immh & 8) {
- /* invalid; don't assign to res */
- }
- else if (immh & 4) {
- sh = immhb - 32;
- vassert(sh < 32); /* so 32-sh is 1..32 */
- ta = "2d";
- tb = isQ ? "4s" : "2s";
- IRExpr* tmp = isQ ? mk_InterleaveHI32x4(src, zero)
- : mk_InterleaveLO32x4(src, zero);
- res = binop(isU ? Iop_ShrN64x2 : Iop_SarN64x2, tmp, mkU8(32-sh));
- }
- else if (immh & 2) {
- sh = immhb - 16;
- vassert(sh < 16); /* so 16-sh is 1..16 */
- ta = "4s";
- tb = isQ ? "8h" : "4h";
- IRExpr* tmp = isQ ? mk_InterleaveHI16x8(src, zero)
- : mk_InterleaveLO16x8(src, zero);
- res = binop(isU...
[truncated message content] |
|
From: <sv...@va...> - 2014-06-12 10:14:15
|
Author: sewardj
Date: Thu Jun 12 10:13:44 2014
New Revision: 14025
Log:
Add tests for movi_4s_#imm8,lsl8 and ushr_d_d_#imm.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Thu Jun 12 10:13:44 2014
@@ -3663,7 +3663,7 @@
// movi 4s,2s #imm8, LSL #0, 8, 16, 24
// mvni 4s,2s #imm8, LSL #0, 8, 16, 24
if (1) test_movi_4s_0x5A_lsl0(TyS);
- if (0) test_movi_4s_0x6B_lsl8(TyS);
+ if (1) test_movi_4s_0x6B_lsl8(TyS);
if (0) test_movi_4s_0x49_lsl16(TyS);
if (0) test_movi_4s_0x3D_lsl24(TyS);
if (0) test_movi_2s_0x5A_lsl0(TyS);
@@ -4811,9 +4811,9 @@
if (0) test_sshr_d_d_1(TyD);
if (0) test_sshr_d_d_32(TyD);
if (0) test_sshr_d_d_64(TyD);
- if (0) test_ushr_d_d_1(TyD);
- if (0) test_ushr_d_d_32(TyD);
- if (0) test_ushr_d_d_64(TyD);
+ if (1) test_ushr_d_d_1(TyD);
+ if (1) test_ushr_d_d_32(TyD);
+ if (1) test_ushr_d_d_64(TyD);
// shl (imm) 16b,8b,8h,4h,4s,2s,2d
// sshr (imm) 2d,4s,2s,8h,4h,16b,8b
|
|
From: <sv...@va...> - 2014-06-12 07:45:48
|
Author: bart
Date: Thu Jun 12 07:45:23 2014
New Revision: 14024
Log:
configure.ac: Fix Boost detection test
Modified:
trunk/configure.ac
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Thu Jun 12 07:45:23 2014
@@ -2690,7 +2690,7 @@
safe_CXXFLAGS=$CXXFLAGS
CXXFLAGS="$mflag_primary"
safe_LIBS="$LIBS"
-LIBS="-lboost_thread-mt $LIBS"
+LIBS="-lboost_thread-mt -lboost_system-mt $LIBS"
AC_LINK_IFELSE([AC_LANG_SOURCE([
#include <boost/thread.hpp>
@@ -2705,7 +2705,7 @@
[
ac_have_boost_1_35=yes
AC_SUBST([BOOST_CFLAGS], [])
-AC_SUBST([BOOST_LIBS], [-lboost_thread-mt])
+AC_SUBST([BOOST_LIBS], ["-lboost_thread-mt -lboost_system-mt"])
AC_MSG_RESULT([yes])
], [
ac_have_boost_1_35=no
|
|
From: Philippe W. <phi...@sk...> - 2014-06-12 04:50:08
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora (7.5.1-37.fc18) Assembler: GNU assembler version 2.23.51.0.1-7.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.8.8-202.fc18.ppc64p7 ppc64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on gcc110 ( Fedora release 18 (Spherical Cow), ppc64 ) Started at 2014-06-11 20:00:10 PDT Ended at 2014-06-11 21:46:45 PDT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 582 tests, 9 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) drd/tests/boost_thread (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 582 tests, 8 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Jun 11 20:24:47 2014 --- new.short Wed Jun 11 20:53:24 2014 *************** *** 8,10 **** ! == 582 tests, 8 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) --- 8,10 ---- ! == 582 tests, 9 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) *************** *** 22,23 **** --- 22,24 ---- helgrind/tests/tc20_verifywrap (stderr) + drd/tests/boost_thread (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.22s no: 1.6s ( 7.3x, -----) me: 2.9s (13.3x, -----) ca:17.9s (81.5x, -----) he: 1.9s ( 8.5x, -----) ca: 5.3s (24.0x, -----) dr: 1.7s ( 7.8x, -----) ma: 2.1s ( 9.5x, -----) bigcode1 valgrind-old:0.22s no: 1.6s ( 7.2x, 1.9%) me: 2.9s (13.1x, 1.4%) ca:18.3s (83.2x, -2.1%) he: 1.7s ( 7.9x, 6.5%) ca: 5.5s (24.9x, -3.6%) dr: 1.7s ( 7.5x, 3.5%) ma: 2.1s ( 9.6x, -1.0%) -- bigcode2 -- bigcode2 valgrind-new:0.23s no: 1.6s ( 6.8x, -----) me: 3.1s (13.7x, -----) ca:18.3s (79.7x, -----) he: 2.3s (10.0x, -----) ca: 5.4s (23.5x, -----) dr: 1.8s ( 8.0x, -----) ma: 2.1s ( 9.2x, -----) bigcode2 valgrind-old:0.23s no: 1.5s ( 6.7x, 1.9%) me: 3.2s (14.0x, -2.2%) ca:18.1s (78.7x, 1.3%) he: 2.2s ( 9.8x, 2.6%) ca: 5.4s (23.6x, -0.2%) dr: 1.8s ( 8.0x, -0.5%) ma: 2.1s ( 9.2x, 0.0%) -- bz2 -- bz2 valgrind-new:0.75s no: 4.9s ( 6.6x, -----) me:11.5s (15.4x, -----) ca:25.9s (34.5x, -----) he:14.8s (19.8x, -----) ca:24.5s (32.6x, -----) dr:19.3s (25.7x, -----) ma: 4.7s ( 6.2x, -----) bz2 valgrind-old:0.75s no: 4.8s ( 6.4x, 2.6%) me:12.0s (16.0x, -4.0%) ca:25.9s (34.5x, -0.0%) he:14.9s (19.9x, -0.5%) ca:24.4s (32.6x, 0.2%) dr:19.1s (25.5x, 0.7%) ma: 4.7s ( 6.2x, -0.2%) -- fbench -- fbench valgrind-new:0.34s no: 2.2s ( 6.6x, -----) me: 5.2s (15.4x, -----) ca: 8.7s (25.4x, -----) he: 5.2s (15.1x, -----) ca: 7.5s (22.1x, -----) dr: 5.0s (14.8x, -----) ma: 2.2s ( 6.4x, -----) fbench valgrind-old:0.34s no: 2.1s ( 6.3x, 4.0%) me: 5.2s (15.3x, 1.0%) ca: 8.6s (25.1x, 1.2%) he: 5.3s (15.5x, -2.5%) ca: 7.5s (22.1x, 0.0%) dr: 4.8s (14.1x, 4.4%) ma: 2.1s ( 6.3x, 1.4%) -- ffbench -- ffbench valgrind-new:0.44s no: 1.3s ( 3.0x, -----) me: 2.5s ( 5.6x, -----) ca: 2.5s ( 5.6x, -----) he: 7.0s (15.9x, -----) ca: 7.1s (16.1x, -----) dr: 5.0s (11.3x, -----) ma: 1.1s ( 2.4x, -----) ffbench valgrind-old:0.44s no: 1.0s ( 2.3x, 22.0%) me: 2.5s ( 5.6x, 0.0%) ca: 2.5s ( 5.7x, -0.8%) he: 7.0s (16.0x, -0.1%) ca: 7.4s (16.7x, -3.8%) dr: 4.9s (11.1x, 1.2%) ma: 1.0s ( 2.3x, 3.8%) -- heap -- heap valgrind-new:0.41s no: 2.4s ( 5.9x, -----) me: 9.7s (23.7x, -----) ca:13.2s (32.2x, -----) he:11.8s (28.8x, -----) ca:12.0s (29.3x, -----) dr: 8.0s (19.5x, -----) ma: 8.6s (21.0x, -----) heap valgrind-old:0.41s no: 2.4s ( 5.8x, 0.8%) me: 9.6s (23.5x, 0.8%) ca:13.2s (32.2x, 0.2%) he:11.9s (29.0x, -0.8%) ca:12.2s (29.8x, -1.7%) dr: 8.0s (19.5x, 0.0%) ma: 8.7s (21.3x, -1.4%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.41s no: 2.8s ( 6.8x, -----) me:13.5s (32.9x, -----) ca:14.2s (34.7x, -----) he:13.1s (31.9x, -----) ca:13.1s (32.0x, -----) dr: 8.9s (21.7x, -----) ma: 8.7s (21.1x, -----) heap_pdb4 valgrind-old:0.41s no: 2.6s ( 6.2x, 7.9%) me:13.5s (33.0x, -0.4%) ca:14.2s (34.7x, 0.0%) he:13.4s (32.7x, -2.4%) ca:13.3s (32.5x, -1.5%) dr: 9.0s (21.9x, -1.1%) ma: 8.7s (21.1x, 0.0%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.5s (17.7x, -----) me: 2.1s (71.3x, -----) ca: 1.9s (63.0x, -----) he: 1.8s (60.7x, -----) ca: 1.9s (62.0x, -----) dr: 1.6s (52.7x, -----) ma: 1.6s (52.3x, -----) many-loss-records valgrind-old:0.03s no: 0.6s (18.7x, -5.7%) me: 2.1s (71.0x, 0.5%) ca: 2.0s (66.0x, -4.8%) he: 1.8s (61.0x, -0.5%) ca: 1.9s (61.7x, 0.5%) dr: 1.6s (52.7x, 0.0%) ma: 1.6s (52.7x, -0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.8s (10.7x, -----) me: 3.3s (47.4x, -----) ca: 4.7s (67.0x, -----) he: 4.9s (69.6x, -----) ca: 3.0s (42.9x, -----) dr: 2.3s (33.0x, -----) ma: 2.3s (32.4x, -----) many-xpts valgrind-old:0.07s no: 0.8s (10.7x, 0.0%) me: 3.4s (47.9x, -0.9%) ca: 4.8s (68.1x, -1.7%) he: 4.9s (69.4x, 0.2%) ca: 2.9s (41.3x, 3.7%) dr: 2.3s (32.9x, 0.4%) ma: 2.3s (33.4x, -3.1%) -- sarp -- sarp valgrind-new:0.02s no: 0.4s (20.0x, -----) me: 3.0s (152.0x, -----) ca: 3.0s (148.0x, -----) he:11.2s (559.0x, -----) ca: 1.9s (96.5x, -----) dr: 1.1s (54.5x, -----) ma: 0.4s (22.0x, -----) sarp valgrind-old:0.02s no: 0.4s (21.0x, -5.0%) me: 3.1s (153.0x, -0.7%) ca: 3.0s (152.5x, -3.0%) he:11.2s (560.0x, -0.2%) ca: 1.7s (85.0x, 11.9%) dr: 1.1s (56.0x, -2.8%) ma: 0.4s (21.0x, 4.5%) -- tinycc -- tinycc valgrind-new:0.27s no: 3.0s (11.0x, -----) me:14.0s (51.9x, -----) ca:17.4s (64.3x, -----) he:19.0s (70.2x, -----) ca:15.6s (57.9x, -----) dr:12.0s (44.5x, -----) ma: 3.8s (14.1x, -----) tinycc valgrind-old:0.27s no: 3.0s (11.1x, -0.3%) me:13.8s (51.0x, 1.6%) ca:17.5s (64.8x, -0.9%) he:18.9s (70.1x, 0.2%) ca:15.6s (57.9x, 0.1%) dr:12.0s (44.4x, 0.2%) ma: 3.8s (14.1x, -0.3%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 53m20.493s user 52m26.542s sys 0m19.610s |
|
From: Christian B. <bor...@de...> - 2014-06-12 04:13:29
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.21-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-06-12 03:45:01 CEST Ended at 2014-06-12 06:13:17 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 647 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 4.4s (19.0x, -----) me: 6.9s (30.0x, -----) ca:26.4s (114.8x, -----) he: 5.1s (22.0x, -----) ca: 9.1s (39.7x, -----) dr: 5.4s (23.5x, -----) ma: 4.6s (19.9x, -----) bigcode1 valgrind-old:0.23s no: 4.4s (19.0x, 0.0%) me: 6.9s (30.0x, -0.1%) ca:26.4s (114.7x, 0.1%) he: 5.1s (22.0x, 0.2%) ca: 9.1s (39.7x, 0.1%) dr: 5.4s (23.4x, 0.2%) ma: 4.6s (19.8x, 0.4%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.4s (30.8x, -----) me:13.8s (57.5x, -----) ca:39.5s (164.8x, -----) he:10.1s (42.0x, -----) ca:14.3s (59.4x, -----) dr: 9.6s (39.8x, -----) ma: 8.0s (33.1x, -----) bigcode2 valgrind-old:0.24s no: 7.3s (30.5x, 1.1%) me:13.8s (57.5x, 0.1%) ca:39.6s (164.9x, -0.1%) he:10.1s (42.0x, -0.1%) ca:14.2s (59.3x, 0.3%) dr: 9.5s (39.7x, 0.3%) ma: 7.9s (33.1x, 0.1%) -- bz2 -- bz2 valgrind-new:0.70s no: 5.1s ( 7.3x, -----) me:12.8s (18.3x, -----) ca:30.6s (43.7x, -----) he:19.6s (28.0x, -----) ca:34.3s (49.0x, -----) dr:29.0s (41.4x, -----) ma: 3.9s ( 5.6x, -----) bz2 valgrind-old:0.70s no: 5.1s ( 7.3x, 0.0%) me:12.7s (18.1x, 0.8%) ca:30.7s (43.8x, -0.2%) he:19.6s (28.0x, 0.0%) ca:34.3s (49.0x, 0.0%) dr:29.0s (41.4x, 0.1%) ma: 3.9s ( 5.6x, -0.8%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 3.9x, -----) me: 4.2s (10.3x, -----) ca: 9.3s (22.7x, -----) he: 6.3s (15.3x, -----) ca: 7.2s (17.6x, -----) dr: 5.5s (13.5x, -----) ma: 1.7s ( 4.1x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, -0.0%) me: 4.2s (10.2x, 0.2%) ca: 9.3s (22.7x, -0.1%) he: 6.2s (15.2x, 0.6%) ca: 7.2s (17.5x, 0.6%) dr: 5.5s (13.5x, 0.0%) ma: 1.7s ( 4.1x, 0.6%) -- ffbench -- ffbench valgrind-new:0.20s no: 1.1s ( 5.3x, -----) me: 3.0s (15.0x, -----) ca: 3.0s (15.1x, -----) he:44.2s (221.1x, -----) ca: 9.6s (48.1x, -----) dr: 7.1s (35.4x, -----) ma: 1.0s ( 4.8x, -----) ffbench valgrind-old:0.20s no: 1.1s ( 5.3x, -0.9%) me: 3.0s (14.8x, 1.0%) ca: 3.0s (15.1x, 0.0%) he:44.1s (220.3x, 0.3%) ca: 9.6s (48.0x, 0.1%) dr: 7.1s (35.4x, 0.1%) ma: 1.0s ( 4.8x, -1.0%) -- heap -- heap valgrind-new:0.23s no: 1.9s ( 8.1x, -----) me: 8.6s (37.5x, -----) ca:13.1s (56.9x, -----) he:12.7s (55.1x, -----) ca:11.3s (49.0x, -----) dr: 8.3s (36.3x, -----) ma: 7.9s (34.4x, -----) heap valgrind-old:0.23s no: 1.9s ( 8.1x, 0.5%) me: 8.6s (37.5x, 0.1%) ca:13.1s (57.0x, -0.2%) he:12.7s (55.2x, -0.2%) ca:11.2s (48.6x, 0.9%) dr: 8.2s (35.5x, 2.3%) ma: 7.9s (34.3x, 0.5%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.1s ( 9.6x, -----) me:12.7s (57.9x, -----) ca:14.2s (64.7x, -----) he:14.2s (64.4x, -----) ca:12.3s (56.1x, -----) dr: 9.2s (42.0x, -----) ma: 8.0s (36.4x, -----) heap_pdb4 valgrind-old:0.22s no: 2.0s ( 9.3x, 3.3%) me:12.7s (57.8x, 0.2%) ca:14.2s (64.5x, 0.4%) he:14.2s (64.8x, -0.6%) ca:12.3s (56.0x, 0.1%) dr: 9.3s (42.2x, -0.3%) ma: 8.0s (36.2x, 0.5%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (24.0x, -----) me: 2.1s (103.0x, -----) ca: 1.9s (96.5x, -----) he: 2.2s (108.5x, -----) ca: 1.9s (95.5x, -----) dr: 1.8s (89.5x, -----) ma: 1.7s (83.5x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (24.0x, 0.0%) me: 2.1s (103.0x, 0.0%) ca: 1.9s (97.0x, -0.5%) he: 2.2s (109.0x, -0.5%) ca: 1.9s (95.5x, 0.0%) dr: 1.8s (89.5x, 0.0%) ma: 1.7s (84.0x, -0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.6s ( 9.1x, -----) me: 3.1s (44.6x, -----) ca:372.1s (5315.7x, -----) he: 6.5s (92.7x, -----) ca: 2.8s (39.7x, -----) dr: 2.6s (37.7x, -----) ma: 2.6s (37.6x, -----) many-xpts valgrind-old:0.07s no: 0.6s ( 9.1x, 0.0%) me: 3.1s (44.4x, 0.3%) ca:375.1s (5358.0x, -0.8%) he: 6.5s (93.0x, -0.3%) ca: 2.8s (39.7x, 0.0%) dr: 2.6s (37.6x, 0.4%) ma: 2.6s (37.4x, 0.4%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (19.3x, -----) me: 3.4s (114.0x, -----) ca: 3.2s (107.0x, -----) he:16.8s (560.7x, -----) ca: 2.0s (68.3x, -----) dr: 1.7s (55.7x, -----) ma: 0.5s (16.0x, -----) sarp valgrind-old:0.03s no: 0.6s (19.0x, 1.7%) me: 3.4s (114.0x, 0.0%) ca: 3.1s (104.3x, 2.5%) he:16.2s (541.3x, 3.4%) ca: 2.1s (68.7x, -0.5%) dr: 1.6s (54.0x, 3.0%) ma: 0.5s (16.0x, 0.0%) -- tinycc -- tinycc valgrind-new:0.22s no: 2.9s (13.3x, -----) me:14.6s (66.4x, -----) ca:30.1s (136.6x, -----) he:27.7s (126.0x, -----) ca:21.3s (96.9x, -----) dr:22.2s (101.0x, -----) ma: 4.0s (18.1x, -----) tinycc valgrind-old:0.22s no: 2.8s (12.9x, 3.4%) me:14.4s (65.6x, 1.1%) ca:30.0s (136.3x, 0.2%) he:27.7s (125.8x, 0.2%) ca:21.3s (97.0x, -0.1%) dr:20.6s (93.7x, 7.3%) ma: 4.0s (18.2x, -0.5%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 111m17.958s user 110m9.230s sys 0m55.854s |
|
From: Tom H. <to...@co...> - 2014-06-12 03:22:25
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-06-12 03:51:31 BST Ended at 2014-06-12 04:22:00 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 650 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) memcheck/tests/err_disable4 (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-06-12 03:01:30
|
valgrind revision: 14023
VEX revision: 2872
C compiler: gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012]
GDB: GNU gdb (GDB) SUSE (7.5.1-2.1.1)
Assembler: GNU assembler (GNU Binutils; openSUSE 12.3) 2.23.1
C library: GNU C Library (GNU libc) stable release version 2.17 (git c758a6861537)
uname -mrs: Linux 3.7.9-1.1-desktop x86_64
Vendor version: Welcome to openSUSE 12.3 "Dartmouth" Beta 1 - Kernel %r (%t).
Nightly build on ultra ( gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] Linux 3.7.9-1.1-desktop x86_64 )
Started at 2014-06-11 21:30:01 CDT
Ended at 2014-06-11 22:01:19 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 675 tests, 0 stderr failures, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
=================================================
./valgrind-new/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-11 21:46:12.131545178 -0500
+++ hginfo.stderrB.out 2014-06-11 21:49:41.929808719 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-11 21:46:12.114545645 -0500
+++ mssnapshot.stderrB.out 2014-06-11 21:50:15.395907784 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-old/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-11 21:30:26.576474639 -0500
+++ hginfo.stderrB.out 2014-06-11 21:34:30.251793361 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-11 21:30:26.559475105 -0500
+++ mssnapshot.stderrB.out 2014-06-11 21:35:01.690931291 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
|
|
From: Tom H. <to...@co...> - 2014-06-12 02:50:43
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-06-12 03:14:00 BST Ended at 2014-06-12 03:50:29 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) drd/tests/std_thread2 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-06-12 03:33:05.793740974 +0100 --- new.short 2014-06-12 03:50:29.901312530 +0100 *************** *** 8,12 **** ! == 682 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) - drd/tests/std_thread2 (stderr) --- 8,11 ---- ! == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-12 02:41:33
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-06-12 03:01:52 BST Ended at 2014-06-12 03:41:20 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) drd/tests/std_thread2 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-06-12 03:23:01.992664396 +0100 --- new.short 2014-06-12 03:41:20.681044350 +0100 *************** *** 8,12 **** ! == 682 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) - drd/tests/std_thread2 (stderr) --- 8,11 ---- ! == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-12 02:32:13
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-06-12 02:51:12 BST Ended at 2014-06-12 03:31:50 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 5 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Rich C. <rc...@wi...> - 2014-06-12 02:28:28
|
valgrind revision: 14023
VEX revision: 2872
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-06-11 19:22:02 CDT
Ended at 2014-06-11 21:28:23 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 596 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-11 20:26:38.734720813 -0500
+++ hackedbz2.stderr.out 2014-06-11 21:27:03.918774589 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-11 20:26:41.776756102 -0500
+++ err_disable3.stderr.out 2014-06-11 20:44:59.706492584 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-11 20:26:40.167737436 -0500
+++ err_disable4.stderr.out 2014-06-11 20:45:04.044542907 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-11 20:26:41.778756125 -0500
+++ threadname.stderr.out 2014-06-11 20:50:54.242605363 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-11 20:26:40.699743608 -0500
+++ threadname_xml.stderr.out 2014-06-11 20:50:56.259628762 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-11 19:23:26.966734587 -0500
+++ hackedbz2.stderr.out 2014-06-11 20:24:34.295277259 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-11 19:23:12.295564395 -0500
+++ err_disable3.stderr.out 2014-06-11 19:42:12.071786315 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-11 19:23:14.492589881 -0500
+++ err_disable4.stderr.out 2014-06-11 19:42:16.392836441 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-11 19:23:18.125632026 -0500
+++ threadname.stderr.out 2014-06-11 19:48:09.758935648 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-11 19:23:18.119631957 -0500
+++ threadname_xml.stderr.out 2014-06-11 19:48:11.821959580 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
|
|
From: Tom H. <to...@co...> - 2014-06-12 02:26:36
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-06-12 02:41:22 BST Ended at 2014-06-12 03:26:16 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Tom H. <to...@co...> - 2014-06-12 02:11:39
|
valgrind revision: 14023 VEX revision: 2872 C compiler: gcc (GCC) 4.8.2 20131212 (Red Hat 4.8.2-7) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-06-12 02:31:35 BST Ended at 2014-06-12 03:11:08 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/hackedbz2 (stderr) |