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From: <sv...@va...> - 2014-06-10 22:53:08
|
Author: sewardj
Date: Tue Jun 10 22:53:01 2014
New Revision: 14021
Log:
Enable test for movi_{16b,8b}_#imm8.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Tue Jun 10 22:53:01 2014
@@ -3646,8 +3646,8 @@
// Some of these movi and mvni cases are similar to orr and bic
// cases with immediates. Maybe they should be moved together.
// movi 16b,8b #imm8, LSL #0
- if (0) test_movi_16b_0x9C_lsl0(TyB);
- if (0) test_movi_8b_0x8B_lsl0(TyB);
+ if (1) test_movi_16b_0x9C_lsl0(TyB);
+ if (1) test_movi_8b_0x8B_lsl0(TyB);
// movi 8h,4h #imm8, LSL #0 or 8
// mvni 8h,4h #imm8, LSL #0 or 8
|
|
From: <sv...@va...> - 2014-06-10 22:52:18
|
Author: sewardj
Date: Tue Jun 10 22:52:05 2014
New Revision: 2871
Log:
Reimplement the SIMD and FP instruction decoder, so as to avoid huge
amounts of duplicated decode, and to follow the documentation more
closely.
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Tue Jun 10 22:52:05 2014
@@ -243,6 +243,11 @@
(((_b11) << 11) \
| BITS11(_b10,_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0))
+#define X00 BITS2(0,0)
+#define X01 BITS2(0,1)
+#define X10 BITS2(1,0)
+#define X11 BITS2(1,1)
+
// produces _uint[_bMax:_bMin]
#define SLICE_UInt(_uint,_bMax,_bMin) \
(( ((UInt)(_uint)) >> (_bMin)) \
@@ -5387,258 +5392,1987 @@
}
+/* Generate a "standard 7" name, from bitQ and size. */
static
-Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn)
+const HChar* nameArr_Q_SZ ( UInt bitQ, UInt size )
+{
+ vassert(bitQ <= 1 && size <= 3);
+ vassert(!(bitQ == 0 && size == 3)); // Implied 1d case
+ const HChar* nms[8]
+ = { "2d", "4s", "8h", "16b", "1d", "2s", "4h", "8b" };
+ UInt ix = (bitQ << 2) | size;
+ vassert(ix < 8);
+ return nms[ix];
+}
+
+
+static
+Bool dis_AdvSIMD_EXT(/*MB_OUT*/DisResult* dres, UInt insn)
{
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
- /* ---------------- FMOV (general) ---------------- */
- /* case 30 23 20 18 15 9 4
- (1) 0 00 11110 00 1 00 111 000000 n d FMOV Sd, Wn
- (2) 1 00 11110 01 1 00 111 000000 n d FMOV Dd, Xn
- (3) 1 00 11110 10 1 01 111 000000 n d FMOV Vd.D[1], Xn
-
- (4) 0 00 11110 00 1 00 110 000000 n d FMOV Wd, Sn
- (5) 1 00 11110 01 1 00 110 000000 n d FMOV Xd, Dn
- (6) 1 00 11110 10 1 01 110 000000 n d FMOV Xd, Vn.D[1]
- */
- if (INSN(30,24) == BITS7(0,0,1,1,1,1,0)
- && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,0,0,0)) {
- UInt sf = INSN(31,31);
- UInt ty = INSN(23,22); // type
- UInt rm = INSN(20,19); // rmode
- UInt op = INSN(18,16); // opcode
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt ix = 0; // case
- if (sf == 0) {
- if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1))
- ix = 1;
- else
- if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0))
- ix = 4;
- } else {
- vassert(sf == 1);
- if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1))
- ix = 2;
- else
- if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0))
- ix = 5;
- else
- if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1))
- ix = 3;
- else
- if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0))
- ix = 6;
- }
- if (ix > 0) {
- switch (ix) {
- case 1:
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, getIReg32orZR(nn));
- DIP("fmov s%u, w%u\n", dd, nn);
- break;
- case 2:
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, getIReg64orZR(nn));
- DIP("fmov d%u, x%u\n", dd, nn);
- break;
- case 3:
- putQRegHI64(dd, getIReg64orZR(nn));
- DIP("fmov v%u.d[1], x%u\n", dd, nn);
- break;
- case 4:
- putIReg32orZR(dd, getQRegLO(nn, Ity_I32));
- DIP("fmov w%u, s%u\n", dd, nn);
- break;
- case 5:
- putIReg64orZR(dd, getQRegLO(nn, Ity_I64));
- DIP("fmov x%u, d%u\n", dd, nn);
- break;
- case 6:
- putIReg64orZR(dd, getQRegHI64(nn));
- DIP("fmov x%u, v%u.d[1]\n", dd, nn);
- break;
- default:
- vassert(0);
- }
- return True;
- }
- /* undecodable; fall through */
- }
- /* -------------- FMOV (scalar, immediate) -------------- */
- /* 31 28 23 20 12 9 4
- 000 11110 00 1 imm8 100 00000 d FMOV Sd, #imm
- 000 11110 01 1 imm8 100 00000 d FMOV Dd, #imm
+static
+Bool dis_AdvSIMD_TBL_TBX(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 29 23 21 20 15 14 12 11 9 4
+ 0 q 001110 op2 0 m 0 len op 00 n d
+ Decode fields: op2,len,op
*/
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,21) == 1 && INSN(12,5) == BITS8(1,0,0,0,0,0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt imm8 = INSN(20,13);
- UInt dd = INSN(4,0);
- ULong imm = VFPExpandImm(imm8, isD ? 64 : 32);
- if (!isD) {
- vassert(0 == (imm & 0xFFFFFFFF00000000ULL));
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(29,24) != BITS6(0,0,1,1,1,0)
+ || INSN(21,21) != 0
+ || INSN(15,15) != 0
+ || INSN(11,10) != BITS2(0,0)) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt op2 = INSN(23,22);
+ UInt mm = INSN(20,16);
+ UInt len = INSN(14,13);
+ UInt bitOP = INSN(12,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ if (op2 == X00) {
+ /* -------- 00,xx,0 TBL, xx register table -------- */
+ /* -------- 00,xx,1 TBX, xx register table -------- */
+ /* 31 28 20 15 14 12 9 4
+ 0q0 01110 000 m 0 len 000 n d TBL Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta
+ 0q0 01110 000 m 0 len 100 n d TBX Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta
+ where Ta = 16b(q=1) or 8b(q=0)
+ */
+ Bool isQ = bitQ == 1;
+ Bool isTBX = bitOP == 1;
+ /* The out-of-range values to use. */
+ IRTemp oor_values = newTemp(Ity_V128);
+ assign(oor_values, isTBX ? getQReg128(dd) : mkV128(0));
+ /* src value */
+ IRTemp src = newTemp(Ity_V128);
+ assign(src, getQReg128(mm));
+ /* The table values */
+ IRTemp tab[4];
+ UInt i;
+ for (i = 0; i <= len; i++) {
+ vassert(i < 4);
+ tab[i] = newTemp(Ity_V128);
+ assign(tab[i], getQReg128((nn + i) % 32));
}
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, isD ? mkU64(imm) : mkU32(imm & 0xFFFFFFFFULL));
- DIP("fmov %s, #0x%llx\n",
- nameQRegLO(dd, isD ? Ity_F64 : Ity_F32), imm);
+ IRTemp res = math_TBL_TBX(tab, len, src, oor_values);
+ putQReg128(dd, isQ ? mkexpr(res)
+ : unop(Iop_ZeroHI64ofV128, mkexpr(res)) );
+ const HChar* Ta = isQ ? "16b" : "8b";
+ const HChar* nm = isTBX ? "tbx" : "tbl";
+ DIP("%s %s.%s, {v%d.16b .. v%d.16b}, %s.%s\n",
+ nm, nameQReg128(dd), Ta, nn, (nn + len) % 32, nameQReg128(mm), Ta);
return True;
}
- /* -------------- {FMOV,MOVI} (vector, immediate) -------------- */
- /* 31 28 18 15 11 9 4
- 0q op 01111 00000 abc cmode 01 defgh d MOV Dd, #imm (q=0)
- MOV Vd.2d #imm (q=1)
- Allowable op:cmode
- FMOV = 1:1111
- MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110
- */
- if (INSN(31,31) == 0
- && INSN(28,19) == BITS10(0,1,1,1,1,0,0,0,0,0)
- && INSN(11,10) == BITS2(0,1)) {
- UInt bitQ = INSN(30,30);
- UInt bitOP = INSN(29,29);
- UInt cmode = INSN(15,12);
- UInt imm8 = (INSN(18,16) << 5) | INSN(9,5);
- UInt dd = INSN(4,0);
- ULong imm64lo = 0;
- UInt op_cmode = (bitOP << 4) | cmode;
- Bool ok = False;
- switch (op_cmode) {
- case BITS5(1,1,1,1,1): // 1:1111
- case BITS5(0,0,0,0,0): case BITS5(0,0,1,0,0):
- case BITS5(0,1,0,0,0): case BITS5(0,1,1,0,0): // 0:xx00
- case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00
- case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0
- case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x
- case BITS5(1,1,1,1,0): case BITS5(0,1,1,1,0): // x:1110
- ok = True; break;
- default:
- break;
- }
- if (ok) {
- ok = AdvSIMDExpandImm(&imm64lo, bitOP, cmode, imm8);
- }
- if (ok) {
- ULong imm64hi = (bitQ == 0 && bitOP == 0) ? 0 : imm64lo;
- putQReg128(dd, binop(Iop_64HLtoV128, mkU64(imm64hi), mkU64(imm64lo)));
- DIP("mov %s, #0x%016llx'%016llx\n", nameQReg128(dd), imm64hi, imm64lo);
- return True;
- }
- /* else fall through */
- }
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
- /* -------------- {S,U}CVTF (scalar, integer) -------------- */
- /* 31 28 23 21 20 18 15 9 4 ix
- 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn 0
- 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn 1
- 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn 2
- 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn 3
- 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn 4
- 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn 5
- 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn 6
- 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn 7
+static
+Bool dis_AdvSIMD_ZIP_UZP_TRN(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
- These are signed/unsigned conversion from integer registers to
- FP registers, all 4 32/64-bit combinations, rounded per FPCR.
+
+static
+Bool dis_AdvSIMD_across_lanes(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 28 23 21 16 11 9 4
+ 0 q u 01110 size 11000 opcode 10 n d
+ Decode fields: u,size,opcode
*/
- if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,17) == BITS5(1,0,0,0,1)
- && INSN(15,10) == BITS6(0,0,0,0,0,0)) {
- Bool isI64 = INSN(31,31) == 1;
- Bool isF64 = INSN(22,22) == 1;
- Bool isU = INSN(16,16) == 1;
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
- const IROp ops[8]
- = { Iop_I32StoF32, Iop_I32StoF64, Iop_I64StoF32, Iop_I64StoF64,
- Iop_I32UtoF32, Iop_I32UtoF64, Iop_I64UtoF32, Iop_I64UtoF64 };
- IRExpr* src = getIRegOrZR(isI64, nn);
- IRExpr* res = (isF64 && !isI64)
- ? unop(ops[ix], src)
- : binop(ops[ix], mkexpr(mk_get_IR_rounding_mode()), src);
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, res);
- DIP("%ccvtf %s, %s\n",
- isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32),
- nameIRegOrZR(isI64, nn));
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,24) != BITS5(0,1,1,1,0)
+ || INSN(21,17) != BITS5(1,1,0,0,0) || INSN(11,10) != BITS2(1,0)) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt opcode = INSN(16,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ if (opcode == BITS5(0,1,0,1,0) || opcode == BITS5(1,1,0,1,0)) {
+ /* -------- 0,xx,01010: SMAXV -------- */
+ /* -------- 1,xx,01010: UMAXV -------- */
+ /* -------- 0,xx,11010: SMINV -------- */
+ /* -------- 1,xx,11010: UMINV -------- */
+ Bool isU = bitU == 1;
+ Bool isMAX = (opcode & 16) == 0;
+ if (size == X11) return False; // 1d,2d cases not allowed
+ if (size == X10 && bitQ == 0) return False; // 2s case not allowed
+ const IROp opMINS[3]
+ = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4 };
+ const IROp opMINU[3]
+ = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4 };
+ const IROp opMAXS[3]
+ = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4 };
+ const IROp opMAXU[3]
+ = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4 };
+ vassert(size < 3);
+ IROp op = isMAX ? (isU ? opMAXU[size] : opMAXS[size])
+ : (isU ? opMINU[size] : opMINS[size]);
+ IRTemp tN1 = newTemp(Ity_V128);
+ assign(tN1, getQReg128(nn));
+ /* If Q == 0, we're just folding lanes in the lower half of
+ the value. In which case, copy the lower half of the
+ source into the upper half, so we can then treat it the
+ same as the full width case. */
+ IRTemp tN2 = newTemp(Ity_V128);
+ assign(tN2, bitQ == 0 ? mk_CatEvenLanes64x2(tN1,tN1) : mkexpr(tN1));
+ IRTemp res = math_MINMAXV(tN2, op);
+ if (res == IRTemp_INVALID)
+ return False; /* means math_MINMAXV
+ doesn't handle this case yet */
+ putQReg128(dd, mkexpr(res));
+ const HChar* nm = isMAX ? (isU ? "umaxv" : "smaxv")
+ : (isU ? "uminv" : "sminv");
+ const IRType tys[3] = { Ity_I8, Ity_I16, Ity_I32 };
+ IRType laneTy = tys[size];
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s, %s.%s\n", nm,
+ nameQRegLO(dd, laneTy), nameQReg128(nn), arr);
return True;
}
- /* ------------ F{ADD,SUB,MUL,DIV,NMUL} (scalar) ------------ */
- /* 31 23 20 15 11 9 4
- ---------------- 0000 ------ FMUL --------
- 000 11110 001 m 0001 10 n d FDIV Sd,Sn,Sm
- 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm
- ---------------- 0010 ------ FADD --------
- ---------------- 0011 ------ FSUB --------
- ---------------- 1000 ------ FNMUL --------
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_copy(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 28 20 15 14 10 9 4
+ 0 q op 01110000 imm5 0 imm4 1 n d
+ Decode fields: q,op,imm4
*/
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt mm = INSN(20,16);
- UInt op = INSN(15,12);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IROp iop = Iop_INVALID;
- IRType ty = isD ? Ity_F64 : Ity_F32;
- Bool neg = False;
- const HChar* nm = "???";
- switch (op) {
- case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ty); break;
- case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ty); break;
- case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ty); break;
- case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ty); break;
- case BITS4(1,0,0,0): nm = "fnmul"; iop = mkMULF(ty);
- neg = True; break;
- default: return False;
- }
- vassert(iop != Iop_INVALID);
- IRExpr* resE = triop(iop, mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn, ty), getQRegLO(mm, ty));
- IRTemp res = newTemp(ty);
- assign(res, neg ? unop(mkNEGF(ty),resE) : resE);
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, mkexpr(res));
- DIP("%s %s, %s, %s\n",
- nm, nameQRegLO(dd, ty), nameQRegLO(nn, ty), nameQRegLO(mm, ty));
- return True;
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,21) != BITS8(0,1,1,1,0,0,0,0)
+ || INSN(15,15) != 0 || INSN(10,10) != 1) {
+ return False;
}
+ UInt bitQ = INSN(30,30);
+ UInt bitOP = INSN(29,29);
+ UInt imm5 = INSN(20,16);
+ UInt imm4 = INSN(14,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
- /* ------------ F{MOV,ABS,NEG,SQRT} D/D or S/S ------------ */
- /* 31 23 21 16 14 9 4
- 000 11110 00 10000 00 10000 n d FMOV Sd, Sn
- 000 11110 01 10000 00 10000 n d FMOV Dd, Dn
- ------------------ 01 --------- FABS ------
- ------------------ 10 --------- FNEG ------
- ------------------ 11 --------- FSQRT -----
+ /* -------- x,0,0000: DUP (element, vector) -------- */
+ /* 31 28 20 15 9 4
+ 0q0 01110000 imm5 000001 n d DUP Vd.T, Vn.Ts[index]
*/
- if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0)
- && INSN(21,17) == BITS5(1,0,0,0,0)
- && INSN(14,10) == BITS5(1,0,0,0,0)) {
- Bool isD = INSN(22,22) == 1;
- UInt opc = INSN(16,15);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- IRType ty = isD ? Ity_F64 : Ity_F32;
- IRTemp res = newTemp(ty);
- if (opc == BITS2(0,0)) {
- assign(res, getQRegLO(nn, ty));
- putQReg128(dd, mkV128(0x0000));
- putQRegLO(dd, mkexpr(res));
- DIP("fmov %s, %s\n",
- nameQRegLO(dd, ty), nameQRegLO(nn, ty));
- return True;
+ if (bitOP == 0 && imm4 == BITS4(0,0,0,0)) {
+ Bool isQ = bitQ == 1;
+ IRTemp w0 = newTemp(Ity_I64);
+ const HChar* arT = "??";
+ const HChar* arTs = "??";
+ IRType laneTy = Ity_INVALID;
+ UInt laneNo = 16; /* invalid */
+ if (imm5 & 1) {
+ arT = isQ ? "16b" : "8b";
+ arTs = "b";
+ laneNo = (imm5 >> 1) & 15;
+ laneTy = Ity_I8;
+ assign(w0, unop(Iop_8Uto64, getQRegLane(nn, laneNo, laneTy)));
}
- if (opc == BITS2(1,0) || opc == BITS2(0,1)) {
- Bool isAbs = opc == BITS2(0,1);
- IROp op = isAbs ? mkABSF(ty) : mkNEGF(ty);
- assign(res, unop(op, getQRegLO(nn, ty)));
+ else if (imm5 & 2) {
+ arT = isQ ? "8h" : "4h";
+ arTs = "h";
+ laneNo = (imm5 >> 2) & 7;
+ laneTy = Ity_I16;
+ assign(w0, unop(Iop_16Uto64, getQRegLane(nn, laneNo, laneTy)));
+ }
+ else if (imm5 & 4) {
+ arT = isQ ? "4s" : "2s";
+ arTs = "s";
+ laneNo = (imm5 >> 3) & 3;
+ laneTy = Ity_I32;
+ assign(w0, unop(Iop_32Uto64, getQRegLane(nn, laneNo, laneTy)));
+ }
+ else if ((imm5 & 8) && isQ) {
+ arT = "2d";
+ arTs = "d";
+ laneNo = (imm5 >> 4) & 1;
+ laneTy = Ity_I64;
+ assign(w0, getQRegLane(nn, laneNo, laneTy));
+ }
+ else {
+ /* invalid; leave laneTy unchanged. */
+ }
+ /* */
+ if (laneTy != Ity_INVALID) {
+ vassert(laneNo < 16);
+ IRTemp w1 = math_DUP_TO_64(w0, laneTy);
+ putQReg128(dd, binop(Iop_64HLtoV128,
+ isQ ? mkexpr(w1) : mkU64(0), mkexpr(w1)));
+ DIP("dup %s.%s, %s.%s[%u]\n",
+ nameQReg128(dd), arT, nameQReg128(nn), arTs, laneNo);
+ return True;
+ }
+ /* else fall through */
+ }
+
+ /* -------- x,0,0001: DUP (general, vector) -------- */
+ /* 31 28 20 15 9 4
+ 0q0 01110000 imm5 0 0001 1 n d DUP Vd.T, Rn
+ Q=0 writes 64, Q=1 writes 128
+ imm5: xxxx1 8B(q=0) or 16b(q=1), R=W
+ xxx10 4H(q=0) or 8H(q=1), R=W
+ xx100 2S(q=0) or 4S(q=1), R=W
+ x1000 Invalid(q=0) or 2D(q=1), R=X
+ x0000 Invalid(q=0) or Invalid(q=1)
+ Require op=0, imm4=0001
+ */
+ if (bitOP == 0 && imm4 == BITS4(0,0,0,1)) {
+ Bool isQ = bitQ == 1;
+ IRTemp w0 = newTemp(Ity_I64);
+ const HChar* arT = "??";
+ IRType laneTy = Ity_INVALID;
+ if (imm5 & 1) {
+ arT = isQ ? "16b" : "8b";
+ laneTy = Ity_I8;
+ assign(w0, unop(Iop_8Uto64, unop(Iop_64to8, getIReg64orZR(nn))));
+ }
+ else if (imm5 & 2) {
+ arT = isQ ? "8h" : "4h";
+ laneTy = Ity_I16;
+ assign(w0, unop(Iop_16Uto64, unop(Iop_64to16, getIReg64orZR(nn))));
+ }
+ else if (imm5 & 4) {
+ arT = isQ ? "4s" : "2s";
+ laneTy = Ity_I32;
+ assign(w0, unop(Iop_32Uto64, unop(Iop_64to32, getIReg64orZR(nn))));
+ }
+ else if ((imm5 & 8) && isQ) {
+ arT = "2d";
+ laneTy = Ity_I64;
+ assign(w0, getIReg64orZR(nn));
+ }
+ else {
+ /* invalid; leave laneTy unchanged. */
+ }
+ /* */
+ if (laneTy != Ity_INVALID) {
+ IRTemp w1 = math_DUP_TO_64(w0, laneTy);
+ putQReg128(dd, binop(Iop_64HLtoV128,
+ isQ ? mkexpr(w1) : mkU64(0), mkexpr(w1)));
+ DIP("dup %s.%s, %s\n",
+ nameQReg128(dd), arT, nameIRegOrZR(laneTy == Ity_I64, nn));
+ return True;
+ }
+ /* else fall through */
+ }
+
+ /* -------- 1,0,0011: INS (general) -------- */
+ /* 31 28 20 15 9 4
+ 010 01110000 imm5 000111 n d INS Vd.Ts[ix], Rn
+ where Ts,ix = case imm5 of xxxx1 -> B, xxxx
+ xxx10 -> H, xxx
+ xx100 -> S, xx
+ x1000 -> D, x
+ */
+ if (bitQ == 1 && bitOP == 0 && imm4 == BITS4(0,0,1,1)) {
+ HChar ts = '?';
+ UInt laneNo = 16;
+ IRExpr* src = NULL;
+ if (imm5 & 1) {
+ src = unop(Iop_64to8, getIReg64orZR(nn));
+ laneNo = (imm5 >> 1) & 15;
+ ts = 'b';
+ }
+ else if (imm5 & 2) {
+ src = unop(Iop_64to16, getIReg64orZR(nn));
+ laneNo = (imm5 >> 2) & 7;
+ ts = 'h';
+ }
+ else if (imm5 & 4) {
+ src = unop(Iop_64to32, getIReg64orZR(nn));
+ laneNo = (imm5 >> 3) & 3;
+ ts = 's';
+ }
+ else if (imm5 & 8) {
+ src = getIReg64orZR(nn);
+ laneNo = (imm5 >> 4) & 1;
+ ts = 'd';
+ }
+ /* */
+ if (src) {
+ vassert(laneNo < 16);
+ putQRegLane(dd, laneNo, src);
+ DIP("ins %s.%c[%u], %s\n",
+ nameQReg128(dd), ts, laneNo, nameIReg64orZR(nn));
+ return True;
+ }
+ /* else invalid; fall through */
+ }
+
+ /* -------- x,0,0101: SMOV -------- */
+ /* -------- x,0,0111: UMOV -------- */
+ /* 31 28 20 15 9 4
+ 0q0 01110 000 imm5 001111 n d UMOV Xd/Wd, Vn.Ts[index]
+ 0q0 01110 000 imm5 001011 n d SMOV Xd/Wd, Vn.Ts[index]
+ dest is Xd when q==1, Wd when q==0
+ UMOV:
+ Ts,index,ops = case q:imm5 of
+ 0:xxxx1 -> B, xxxx, 8Uto64
+ 1:xxxx1 -> invalid
+ 0:xxx10 -> H, xxx, 16Uto64
+ 1:xxx10 -> invalid
+ 0:xx100 -> S, xx, 32Uto64
+ 1:xx100 -> invalid
+ 1:x1000 -> D, x, copy64
+ other -> invalid
+ SMOV:
+ Ts,index,ops = case q:imm5 of
+ 0:xxxx1 -> B, xxxx, (32Uto64 . 8Sto32)
+ 1:xxxx1 -> B, xxxx, 8Sto64
+ 0:xxx10 -> H, xxx, (32Uto64 . 16Sto32)
+ 1:xxx10 -> H, xxx, 16Sto64
+ 0:xx100 -> invalid
+ 1:xx100 -> S, xx, 32Sto64
+ 1:x1000 -> invalid
+ other -> invalid
+ */
+ if (bitOP == 0 && (imm4 == BITS4(0,1,0,1) || imm4 == BITS4(0,1,1,1))) {
+ Bool isU = (imm4 & 2) == 2;
+ const HChar* arTs = "??";
+ UInt laneNo = 16; /* invalid */
+ // Setting 'res' to non-NULL determines valid/invalid
+ IRExpr* res = NULL;
+ if (!bitQ && (imm5 & 1)) { // 0:xxxx1
+ laneNo = (imm5 >> 1) & 15;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8);
+ res = isU ? unop(Iop_8Uto64, lane)
+ : unop(Iop_32Uto64, unop(Iop_8Sto32, lane));
+ arTs = "b";
+ }
+ else if (bitQ && (imm5 & 1)) { // 1:xxxx1
+ laneNo = (imm5 >> 1) & 15;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8);
+ res = isU ? NULL
+ : unop(Iop_8Sto64, lane);
+ arTs = "b";
+ }
+ else if (!bitQ && (imm5 & 2)) { // 0:xxx10
+ laneNo = (imm5 >> 2) & 7;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16);
+ res = isU ? unop(Iop_16Uto64, lane)
+ : unop(Iop_32Uto64, unop(Iop_16Sto32, lane));
+ arTs = "h";
+ }
+ else if (bitQ && (imm5 & 2)) { // 1:xxx10
+ laneNo = (imm5 >> 2) & 7;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16);
+ res = isU ? NULL
+ : unop(Iop_16Sto64, lane);
+ arTs = "h";
+ }
+ else if (!bitQ && (imm5 & 4)) { // 0:xx100
+ laneNo = (imm5 >> 3) & 3;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32);
+ res = isU ? unop(Iop_32Uto64, lane)
+ : NULL;
+ arTs = "s";
+ }
+ else if (bitQ && (imm5 & 4)) { // 1:xxx10
+ laneNo = (imm5 >> 3) & 3;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32);
+ res = isU ? NULL
+ : unop(Iop_32Sto64, lane);
+ arTs = "s";
+ }
+ else if (bitQ && (imm5 & 8)) { // 1:x1000
+ laneNo = (imm5 >> 4) & 1;
+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I64);
+ res = isU ? lane
+ : NULL;
+ arTs = "d";
+ }
+ /* */
+ if (res) {
+ vassert(laneNo < 16);
+ putIReg64orZR(dd, res);
+ DIP("%cmov %s, %s.%s[%u]\n", isU ? 'u' : 's',
+ nameIRegOrZR(bitQ == 1, dd),
+ nameQReg128(nn), arTs, laneNo);
+ return True;
+ }
+ /* else fall through */
+ }
+
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_modified_immediate(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 28 18 15 11 9 4
+ 0q op 01111 00000 abc cmode 01 defgh d
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,19) != BITS10(0,1,1,1,1,0,0,0,0,0)
+ || INSN(11,10) != BITS2(0,1)) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitOP = INSN(29,29);
+ UInt cmode = INSN(15,12);
+ UInt abcdefgh = (INSN(18,16) << 5) | INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ /* -------- {FMOV,MOVI} (vector, immediate) -------- */
+ /* Allowable op:cmode
+ FMOV = 1:1111
+ MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110
+ */
+ ULong imm64lo = 0;
+ UInt op_cmode = (bitOP << 4) | cmode;
+ Bool ok = False;
+ switch (op_cmode) {
+ case BITS5(1,1,1,1,1): // 1:1111
+ case BITS5(0,0,0,0,0): case BITS5(0,0,1,0,0):
+ case BITS5(0,1,0,0,0): case BITS5(0,1,1,0,0): // 0:xx00
+ case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00
+ case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0
+ case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x
+ case BITS5(1,1,1,1,0): case BITS5(0,1,1,1,0): // x:1110
+ ok = True; break;
+ default:
+ break;
+ }
+ if (ok) {
+ ok = AdvSIMDExpandImm(&imm64lo, bitOP, cmode, abcdefgh);
+ }
+ if (ok) {
+ ULong imm64hi = (bitQ == 0 && bitOP == 0) ? 0 : imm64lo;
+ putQReg128(dd, binop(Iop_64HLtoV128, mkU64(imm64hi), mkU64(imm64lo)));
+ DIP("mov %s, #0x%016llx'%016llx\n", nameQReg128(dd), imm64hi, imm64lo);
+ return True;
+ }
+ /* else fall through */
+
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_scalar_copy(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_scalar_pairwise(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_scalar_shift_by_imm(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 28 22 18 15 10 9 4
+ 01 u 111110 immh immb opcode 1 n d
+ Decode fields: u,immh,opcode
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,30) != BITS2(0,1)
+ || INSN(28,23) != BITS6(1,1,1,1,1,0) || INSN(10,10) != 1) {
+ return False;
+ }
+ UInt bitU = INSN(29,29);
+ UInt immh = INSN(22,19);
+ UInt immb = INSN(18,16);
+ UInt opcode = INSN(15,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ UInt immhb = (immh << 3) | immb;
+
+ if (bitU == 0 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) {
+ /* -------- 0,1xxx,01010 SHL d_d_#imm -------- */
+ UInt sh = immhb - 64;
+ vassert(sh >= 0 && sh < 64);
+ putQReg128(dd, unop(Iop_ZeroHI64ofV128,
+ binop(Iop_ShlN64x2, getQReg128(nn), mkU8(sh))));
+ DIP("shl d%u, d%u, #%u\n", dd, nn, sh);
+ return True;
+ }
+
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_scalar_three_different(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_scalar_three_same(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 29 28 23 21 20 15 10 9 4
+ 01 U 11110 size 1 m opcode 1 n d
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,30) != BITS2(0,1)
+ || INSN(28,24) != BITS5(1,1,1,1,0)
+ || INSN(21,21) != 1
+ || INSN(10,10) != 1) {
+ return False;
+ }
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt mm = INSN(20,16);
+ UInt opcode = INSN(15,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ vassert(size < 4);
+
+ if (size == X11 && opcode == BITS5(1,0,0,0,0)) {
+ /* -------- 0,11,10000 ADD d_d_d -------- */
+ /* -------- 1,11,10000 SUB d_d_d -------- */
+ Bool isSUB = bitU == 1;
+ IRTemp res = newTemp(Ity_I64);
+ assign(res, binop(isSUB ? Iop_Sub64 : Iop_Add64,
+ getQRegLane(nn, 0, Ity_I64),
+ getQRegLane(mm, 0, Ity_I64)));
+ putQRegLane(dd, 0, mkexpr(res));
+ putQRegLane(dd, 1, mkU64(0));
+ DIP("%s %s, %s, %s\n", isSUB ? "sub" : "add",
+ nameQRegLO(dd, Ity_I64),
+ nameQRegLO(nn, Ity_I64), nameQRegLO(mm, Ity_I64));
+ return True;
+ }
+
+ if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
+ /* -------- 1,1x,11010 FABD d_d_d, s_s_s -------- */
+ IRType ity = size == X11 ? Ity_F64 : Ity_F32;
+ IRTemp res = newTemp(ity);
+ assign(res, unop(mkABSF(ity),
+ triop(mkSUBF(ity),
+ mkexpr(mk_get_IR_rounding_mode()),
+ getQRegLO(nn,ity), getQRegLO(mm,ity))));
+ putQReg128(dd, mkV128(0x0000));
+ putQRegLO(dd, mkexpr(res));
+ DIP("fabd %s, %s, %s\n",
+ nameQRegLO(dd, ity), nameQRegLO(nn, ity), nameQRegLO(mm, ity));
+ return True;
+ }
+
+
+
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_scalar_two_reg_misc(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 29 28 23 21 16 11 9 4
+ 01 U 11110 size 10000 opcode 10 n d
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,30) != BITS2(0,1)
+ || INSN(28,24) != BITS5(1,1,1,1,0)
+ || INSN(21,17) != BITS5(1,0,0,0,0)
+ || INSN(11,10) != BITS2(1,0)) {
+ return False;
+ }
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt opcode = INSN(16,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ vassert(size < 4);
+
+ if (bitU == 0 && size == X11 && opcode == BITS5(0,1,0,0,1)) {
+ /* -------- 0,11,01001 CMEQ d_d_#0 -------- */
+ putQReg128(dd, unop(Iop_ZeroHI64ofV128,
+ binop(Iop_CmpEQ64x2, getQReg128(nn),
+ mkV128(0x0000))));
+ DIP("cmeq d%u, d%u, #0\n", dd, nn);
+ return True;
+ }
+
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_scalar_x_indexed_element(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_shift_by_immediate(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 28 22 18 15 10 9 4
+ 0 q u 011110 immh immb opcode 1 n d
+ Decode fields: u,opcode
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,23) != BITS6(0,1,1,1,1,0) || INSN(10,10) != 1) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitU = INSN(29,29);
+ UInt immh = INSN(22,19);
+ UInt immb = INSN(18,16);
+ UInt opcode = INSN(15,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ if (opcode == BITS5(0,0,0,0,0)) {
+ /* -------- 0,00000 SSHR std7_std7_#imm -------- */
+ /* -------- 1,00000 USHR std7_std7_#imm -------- */
+ /* laneTy, shift = case immh:immb of
+ 0001:xxx -> B, SHR:8-xxx
+ 001x:xxx -> H, SHR:16-xxxx
+ 01xx:xxx -> S, SHR:32-xxxxx
+ 1xxx:xxx -> D, SHR:64-xxxxxx
+ other -> invalid
+ */
+ const IROp opsSHRN[4]
+ = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 };
+ const IROp opsSARN[4]
+ = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 };
+ UInt size = 0;
+ UInt shift = 0;
+ Bool isQ = bitQ == 1;
+ Bool isU = bitU == 1;
+ Bool ok = getLaneInfo_IMMH_IMMB(&shift, &size, immh, immb);
+ vassert(size >= 0 && size <= 3);
+ if (ok && size < 4 && shift > 0 && shift < (8 << size)
+ && !(size == 3/*64bit*/ && !isQ)) {
+ IROp op = isU ? opsSHRN[size] : opsSARN[size];
+ IRExpr* src = getQReg128(nn);
+ IRExpr* res = binop(op, src, mkU8(shift));
+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
+ HChar laneCh = "bhsd"[size];
+ UInt nLanes = (isQ ? 128 : 64) / (8 << size);
+ const HChar* nm = isU ? "ushr" : "sshr";
+ DIP("%s %s.%u%c, %s.%u%c, #%u\n", nm,
+ nameQReg128(dd), nLanes, laneCh,
+ nameQReg128(nn), nLanes, laneCh, shift);
+ return True;
+ }
+ return False;
+ }
+
+ if (bitU == 0 && opcode == BITS5(0,1,0,1,0)) {
+ /* -------- 0,01010 SHL std7_std7_#imm -------- */
+ /* laneTy, shift = case immh:immb of
+ 0001:xxx -> B, xxx
+ 001x:xxx -> H, xxxx
+ 01xx:xxx -> S, xxxxx
+ 1xxx:xxx -> D, xxxxxx
+ other -> invalid
+ */
+ const IROp opsSHLN[4]
+ = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 };
+ UInt size = 0;
+ UInt shift = 0;
+ Bool isQ = bitQ == 1;
+ Bool ok = getLaneInfo_IMMH_IMMB(&shift, &size, immh, immb);
+ vassert(size >= 0 && size <= 3);
+ /* The shift encoding has opposite sign for the leftwards case.
+ Adjust shift to compensate. */
+ shift = (8 << size) - shift;
+ if (ok && size < 4 && shift > 0 && shift < (8 << size)
+ && !(size == 3/*64bit*/ && !isQ)) {
+ IROp op = opsSHLN[size];
+ IRExpr* src = getQReg128(nn);
+ IRExpr* res = binop(op, src, mkU8(shift));
+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
+ HChar laneCh = "bhsd"[size];
+ UInt nLanes = (isQ ? 128 : 64) / (8 << size);
+ const HChar* nm = "shl";
+ DIP("%s %s.%u%c, %s.%u%c, #%u\n", nm,
+ nameQReg128(dd), nLanes, laneCh,
+ nameQReg128(nn), nLanes, laneCh, shift);
+ return True;
+ }
+ return False;
+ }
+
+ if (opcode == BITS5(1,0,1,0,0)) {
+ /* -------- 0,10100 SSHLL{,2} #imm -------- */
+ /* -------- 1,10100 USHLL{,2} #imm -------- */
+ /* 31 28 22 18 15 9 4
+ 0q0 011110 immh immb 101001 n d SSHLL Vd.Ta, Vn.Tb, #sh
+ 0q1 011110 immh immb 101001 n d USHLL Vd.Ta, Vn.Tb, #sh
+ where Ta,Tb,sh
+ = case immh of 1xxx -> invalid
+ 01xx -> 2d, 2s(q0)/4s(q1), immh:immb - 32 (0..31)
+ 001x -> 4s, 4h(q0)/8h(q1), immh:immb - 16 (0..15)
+ 0001 -> 8h, 8b(q0)/16b(q1), immh:immb - 8 (0..7)
+ 0000 -> AdvSIMD modified immediate (???)
+ */
+ Bool isQ = bitQ == 1;
+ Bool isU = bitU == 1;
+ UInt immhb = (immh << 3) | immb;
+ IRTemp src = newTemp(Ity_V128);
+ IRTemp zero = newTemp(Ity_V128);
+ IRExpr* res = NULL;
+ UInt sh = 0;
+ const HChar* ta = "??";
+ const HChar* tb = "??";
+ assign(src, getQReg128(nn));
+ assign(zero, mkV128(0x0000));
+ if (immh & 8) {
+ /* invalid; don't assign to res */
+ }
+ else if (immh & 4) {
+ sh = immhb - 32;
+ vassert(sh < 32); /* so 32-sh is 1..32 */
+ ta = "2d";
+ tb = isQ ? "4s" : "2s";
+ IRExpr* tmp = isQ ? mk_InterleaveHI32x4(src, zero)
+ : mk_InterleaveLO32x4(src, zero);
+ res = binop(isU ? Iop_ShrN64x2 : Iop_SarN64x2, tmp, mkU8(32-sh));
+ }
+ else if (immh & 2) {
+ sh = immhb - 16;
+ vassert(sh < 16); /* so 16-sh is 1..16 */
+ ta = "4s";
+ tb = isQ ? "8h" : "4h";
+ IRExpr* tmp = isQ ? mk_InterleaveHI16x8(src, zero)
+ : mk_InterleaveLO16x8(src, zero);
+ res = binop(isU ? Iop_ShrN32x4 : Iop_SarN32x4, tmp, mkU8(16-sh));
+ }
+ else if (immh & 1) {
+ sh = immhb - 8;
+ vassert(sh < 8); /* so 8-sh is 1..8 */
+ ta = "8h";
+ tb = isQ ? "16b" : "8b";
+ IRExpr* tmp = isQ ? mk_InterleaveHI8x16(src, zero)
+ : mk_InterleaveLO8x16(src, zero);
+ res = binop(isU ? Iop_ShrN16x8 : Iop_SarN16x8, tmp, mkU8(8-sh));
+ } else {
+ vassert(immh == 0);
+ /* invalid; don't assign to res */
+ }
+ /* */
+ if (res) {
+ putQReg128(dd, res);
+ DIP("%cshll%s %s.%s, %s.%s, #%d\n",
+ isU ? 'u' : 's', isQ ? "2" : "",
+ nameQReg128(dd), ta, nameQReg128(nn), tb, sh);
+ return True;
+ }
+ return False;
+ }
+
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+static
+Bool dis_AdvSIMD_three_different(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_three_same(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 30 29 28 23 21 20 15 10 9 4
+ 0 Q U 01110 size 1 m opcode 1 n d
+ Decode fields: u,size,opcode
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,24) != BITS5(0,1,1,1,0)
+ || INSN(21,21) != 1
+ || INSN(10,10) != 1) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt mm = INSN(20,16);
+ UInt opcode = INSN(15,11);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ vassert(size < 4);
+
+ if (bitU == 0 && opcode == BITS5(0,0,0,1,1)) {
+ /* -------- 0,00,00011 AND 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 0,01,00011 BIC 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 0,10,00011 ORR 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 0,10,00011 ORN 16b_16b_16b, 8b_8b_8b -------- */
+ Bool isQ = bitQ == 1;
+ Bool isORR = (size & 2) == 2;
+ Bool invert = (size & 1) == 1;
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(isORR ? Iop_OrV128 : Iop_AndV128,
+ getQReg128(nn),
+ invert ? unop(Iop_NotV128, getQReg128(mm))
+ : getQReg128(mm)));
+ putQReg128(dd, isQ ? mkexpr(res)
+ : unop(Iop_ZeroHI64ofV128, mkexpr(res)));
+ const HChar* names[4] = { "and", "bic", "orr", "orn" };
+ const HChar* ar = isQ ? "16b" : "8b";
+ DIP("%s %s.%s, %s.%s, %s.%s\n", names[INSN(23,22)],
+ nameQReg128(dd), ar, nameQReg128(nn), ar, nameQReg128(mm), ar);
+ return True;
+ }
+
+ if (bitU == 1 && opcode == BITS5(0,0,0,1,1)) {
+ /* -------- 1,00,00011 EOR 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 1,01,00011 BSL 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 1,10,00011 BIT 16b_16b_16b, 8b_8b_8b -------- */
+ /* -------- 1,10,00011 BIF 16b_16b_16b, 8b_8b_8b -------- */
+ Bool isQ = bitQ == 1;
+ IRTemp argD = newTemp(Ity_V128);
+ IRTemp argN = newTemp(Ity_V128);
+ IRTemp argM = newTemp(Ity_V128);
+ assign(argD, getQReg128(dd));
+ assign(argN, getQReg128(nn));
+ assign(argM, getQReg128(mm));
+ const IROp opXOR = Iop_XorV128;
+ const IROp opAND = Iop_AndV128;
+ const IROp opNOT = Iop_NotV128;
+ IRExpr* res = NULL;
+ switch (size) {
+ case BITS2(0,0): /* EOR */
+ res = binop(opXOR, mkexpr(argM), mkexpr(argN));
+ break;
+ case BITS2(0,1): /* BSL */
+ res = binop(opXOR, mkexpr(argM),
+ binop(opAND,
+ binop(opXOR, mkexpr(argM), mkexpr(argN)),
+ mkexpr(argD)));
+ break;
+ case BITS2(1,0): /* BIT */
+ res = binop(opXOR, mkexpr(argD),
+ binop(opAND,
+ binop(opXOR, mkexpr(argD), mkexpr(argN)),
+ mkexpr(argM)));
+ break;
+ case BITS2(1,1): /* BIF */
+ res = binop(opXOR, mkexpr(argD),
+ binop(opAND,
+ binop(opXOR, mkexpr(argD), mkexpr(argN)),
+ unop(opNOT, mkexpr(argM))));
+ break;
+ default:
+ vassert(0);
+ }
+ vassert(res);
+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
+ const HChar* nms[4] = { "eor", "bsl", "bit", "bif" };
+ const HChar* arr = isQ ? "16b" : "8b";
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nms[size],
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(0,0,1,1,0)) {
+ /* -------- 0,xx,00110 CMGT std7_std7_std7 -------- */ // >s
+ /* -------- 1,xx,00110 CMHI std7_std7_std7 -------- */ // >u
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isGT = bitU == 0;
+ const IROp opsGTS[4]
+ = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 };
+ const IROp opsGTU[4]
+ = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, Iop_CmpGT64Ux2 };
+ IRExpr* argL = getQReg128(nn);
+ IRExpr* argR = getQReg128(mm);
+ IRTemp res = newTemp(Ity_V128);
+ assign(res,
+ isGT ? binop(opsGTS[size], argL, argR)
+ : binop(opsGTU[size], argL, argR));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* nm = isGT ? "cmgt" : "cmhi";
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(0,0,1,1,1)) {
+ /* -------- 0,xx,00111 CMGE std7_std7_std7 -------- */ // >=s
+ /* -------- 1,xx,00111 CMHS std7_std7_std7 -------- */ // >=u
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isGE = bitU == 0;
+ const IROp opsGTS[4]
+ = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 };
+ const IROp opsGTU[4]
+ = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, Iop_CmpGT64Ux2 };
+ IRExpr* argL = getQReg128(nn);
+ IRExpr* argR = getQReg128(mm);
+ IRTemp res = newTemp(Ity_V128);
+ assign(res,
+ isGE ? unop(Iop_NotV128, binop(opsGTS[size], argR, argL))
+ : unop(Iop_NotV128, binop(opsGTU[size], argR, argL)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* nm = isGE ? "cmge" : "cmhs";
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(0,1,1,0,0) || opcode == BITS5(0,1,1,0,1)) {
+ /* -------- 0,xx,01100 SMAX std7_std7_std7 -------- */
+ /* -------- 1,xx,01100 UMAX std7_std7_std7 -------- */
+ /* -------- 0,xx,01101 SMIN std7_std7_std7 -------- */
+ /* -------- 1,xx,01101 UMIN std7_std7_std7 -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isU = bitU == 1;
+ Bool isMAX = (opcode & 1) == 0;
+ const IROp opMINS[4]
+ = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2 };
+ const IROp opMINU[4]
+ = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, Iop_Min64Ux2 };
+ const IROp opMAXS[4]
+ = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2 };
+ const IROp opMAXU[4]
+ = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2 };
+ IROp op = isMAX ? (isU ? opMAXU[size] : opMAXS[size])
+ : (isU ? opMINU[size] : opMINS[size]);
+ IRTemp t = newTemp(Ity_V128);
+ assign(t, binop(op, getQReg128(nn), getQReg128(mm)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t))
+ : mkexpr(t));
+ const HChar* nm = isMAX ? (isU ? "umax" : "smax")
+ : (isU ? "umin" : "smin");
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(1,0,0,0,0)) {
+ /* -------- 0,xx,10000 ADD std7_std7_std7 -------- */
+ /* -------- 1,xx,10000 SUB std7_std7_std7 -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isSUB = bitU == 1;
+ const IROp opsADD[4]
+ = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 };
+ const IROp opsSUB[4]
+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
+ IROp op = isSUB ? opsSUB[size] : opsADD[size];
+ IRTemp t = newTemp(Ity_V128);
+ assign(t, binop(op, getQReg128(nn), getQReg128(mm)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t))
+ : mkexpr(t));
+ const HChar* nm = isSUB ? "sub" : "add";
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(1,0,0,0,1)) {
+ /* -------- 0,xx,10001 CMTST std7_std7_std7 -------- */ // &, != 0
+ /* -------- 1,xx,10001 CMEQ std7_std7_std7 -------- */ // ==
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isEQ = bitU == 1;
+ const IROp opsEQ[4]
+ = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, Iop_CmpEQ64x2 };
+ IRExpr* argL = getQReg128(nn);
+ IRExpr* argR = getQReg128(mm);
+ IRTemp res = newTemp(Ity_V128);
+ assign(res,
+ isEQ ? binop(opsEQ[size], argL, argR)
+ : unop(Iop_NotV128, binop(opsEQ[size],
+ binop(Iop_AndV128, argL, argR),
+ mkV128(0x0000))));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* nm = isEQ ? "cmeq" : "cmtst";
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(1,0,0,1,0)) {
+ /* -------- 0,xx,10010 MLA std7_std7_std7 -------- */
+ /* -------- 1,xx,10010 MLS std7_std7_std7 -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isMLS = bitU == 1;
+ const IROp opsADD[4]
+ = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_INVALID };
+ const IROp opsSUB[4]
+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_INVALID };
+ const IROp opsMUL[4]
+ = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, Iop_INVALID };
+ IROp opMUL = opsMUL[size];
+ IROp opADDSUB = isMLS ? opsSUB[size] : opsADD[size];
+ IRTemp res = newTemp(Ity_V128);
+ if (opMUL != Iop_INVALID && opADDSUB != Iop_INVALID) {
+ assign(res, binop(opADDSUB,
+ getQReg128(dd),
+ binop(opMUL, getQReg128(nn), getQReg128(mm))));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isMLS ? "mls" : "mla",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+ return False;
+ }
+
+ if (opcode == BITS5(1,0,0,1,1)) {
+ /* -------- 0,xx,10011 MUL std7_std7_std7 -------- */
+ /* -------- 1,xx,10011 PMUL 16b_16b_16b, 8b_8b_8b -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isPMUL = bitU == 1;
+ const IROp opsMUL[4]
+ = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, Iop_INVALID };
+ const IROp opsPMUL[4]
+ = { Iop_PolynomialMul8x16, Iop_INVALID, Iop_INVALID, Iop_INVALID };
+ IROp opMUL = isPMUL ? opsPMUL[size] : opsMUL[size];
+ IRTemp res = newTemp(Ity_V128);
+ if (opMUL != Iop_INVALID) {
+ assign(res, binop(opMUL, getQReg128(nn), getQReg128(mm)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isPMUL ? "pmul" : "mul",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+ return False;
+ }
+
+ if (bitU == 0 && opcode == BITS5(1,1,0,0,1)) {
+ /* -------- 0,0x,11001 FMLA 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ /* -------- 0,1x,11001 FMLS 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ Bool isSUB = (size & 2) == 2;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IROp opADD = isD ? Iop_Add64Fx2 : Iop_Add32Fx4;
+ IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4;
+ IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4;
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTemp(Ity_V128);
+ IRTemp t2 = newTemp(Ity_V128);
+ // FIXME: double rounding; use FMA primops instead
+ assign(t1, triop(opMUL,
+ mkexpr(rm), getQReg128(nn), getQReg128(mm)));
+ assign(t2, triop(isSUB ? opSUB : opADD,
+ mkexpr(rm), getQReg128(dd), mkexpr(t1)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t2))
+ : mkexpr(t2));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isSUB ? "fmls" : "fmla",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 0 && opcode == BITS5(1,1,0,1,0)) {
+ /* -------- 0,0x,11010 FADD 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ /* -------- 0,1x,11010 FSUB 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ Bool isSUB = (size & 2) == 2;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ const IROp ops[4]
+ = { Iop_Add32Fx4, Iop_Add64Fx2, Iop_Sub32Fx4, Iop_Sub64Fx2 };
+ IROp op = ops[size];
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTemp(Ity_V128);
+ IRTemp t2 = newTemp(Ity_V128);
+ assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
+ assign(t2, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ putQReg128(dd, mkexpr(t2));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isSUB ? "fsub" : "fadd",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
+ /* -------- 1,1x,11010 FABD 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4;
+ IROp opABS = isD ? Iop_Abs64Fx2 : Iop_Abs32Fx4;
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTemp(Ity_V128);
+ IRTemp t2 = newTemp(Ity_V128);
+ // FIXME: use Abd primop instead?
+ assign(t1, triop(opSUB,
+ mkexpr(rm), getQReg128(nn), getQReg128(mm)));
+ assign(t2, unop(opABS, mkexpr(t1)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t2))
+ : mkexpr(t2));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("fabd %s.%s, %s.%s, %s.%s\n",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,0,1,1)) {
+ /* -------- 1,0x,11011 FMUL 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTemp(Ity_V128);
+ assign(t1, triop(isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4,
+ mkexpr(rm), getQReg128(nn), getQReg128(mm)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("fmul %s.%s, %s.%s, %s.%s\n",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (size <= X01 && opcode == BITS5(1,1,1,0,0)) {
+ /* -------- 0,0x,11100 FCMEQ 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ /* -------- 1,0x,11100 FCMGE 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ Bool isGE = bitU == 1;
+ IROp opCMP = isGE ? (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4)
+ : (isD ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4);
+ IRTemp t1 = newTemp(Ity_V128);
+ assign(t1, isGE ? binop(opCMP, getQReg128(mm), getQReg128(nn)) // swapd
+ : binop(opCMP, getQReg128(nn), getQReg128(mm)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isGE ? "fcmge" : "fcmeq",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {
+ /* -------- 1,1x,11100 FCMGT 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IROp opCMP = isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4;
+ IRTemp t1 = newTemp(Ity_V128);
+ assign(t1, binop(opCMP, getQReg128(mm), getQReg128(nn))); // swapd
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", "fcmgt",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 1 && opcode == BITS5(1,1,1,0,1)) {
+ /* -------- 1,0x,11101 FACGE 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ /* -------- 1,1x,11101 FACGT 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ Bool isGT = (size & 2) == 2;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IROp opCMP = isGT ? (isD ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4)
+ : (isD ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4);
+ IROp opABS = isD ? Iop_Abs64Fx2 : Iop_Abs32Fx4;
+ IRTemp t1 = newTemp(Ity_V128);
+ assign(t1, binop(opCMP, unop(opABS, getQReg128(mm)),
+ unop(opABS, getQReg128(nn)))); // swapd
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", isGT ? "facgt" : "facge",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,1,1,1)) {
+ /* -------- 1,0x,11111 FDIV 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = (size & 1) == 1;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ vassert(size <= 1);
+ const IROp ops[2] = { Iop_Div32Fx4, Iop_Div64Fx2 };
+ IROp op = ops[size];
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTemp(Ity_V128);
+ IRTemp t2 = newTemp(Ity_V128);
+ assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
+ assign(t2, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(t1))
+ : mkexpr(t1));
+ putQReg128(dd, mkexpr(t2));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", "fdiv",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
+ return False;
+# undef INSN
+}
+
+
+static
+Bool dis_AdvSIMD_two_reg_misc(/*MB_OUT*/DisResult* dres, UInt insn)
+{
+ /* 31 30 29 28 23 21 16 11 9 4
+ 0 Q U 01110 size 10000 opcode 10 n d
+ Decode fields: U,size,opcode
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,31) != 0
+ || INSN(28,24) != BITS5(0,1,1,1,0)
+ || INSN(21,17) != BITS5(1,0,0,0,0)
+ || INSN(11,10) != BITS2(1,0)) {
+ return False;
+ }
+ UInt bitQ = INSN(30,30);
+ UInt bitU = INSN(29,29);
+ UInt size = INSN(23,22);
+ UInt opcode = INSN(16,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ vassert(size < 4);
+
+ if (opcode == BITS5(0,1,0,0,0)) {
+ /* -------- 0,xx,01000: CMGT std7_std7_#0 -------- */ // >s 0
+ /* -------- 1,xx,01000: CMGE std7_std7_#0 -------- */ // >=s 0
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ const IROp opsGTS[4]
+ = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 };
+ Bool isGT = bitU == 0;
+ IRExpr* argL = getQReg128(nn);
+ IRExpr* argR = mkV128(0x0000);
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, isGT ? binop(opsGTS[size], argL, argR)
+ : unop(Iop_NotV128, binop(opsGTS[size], argR, argL)));
+ putQReg128(dd, bitQ == 0 ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ const HChar* arr = nameArr_Q_SZ(bitQ, size);
+ DIP("cm%s %s.%s, %s.%s, #0\n", isGT ? "gt" : "ge",
+ nameQReg128(dd), arr, nameQReg128(nn), arr);
+ return True;
+ }
+
+ if (opcode == BITS5(0,1,0,0,1)) {
+ /* -------- 0,xx,01001: CMEQ std7_std7_#0 -------- */ // == 0
+ /* -------- 1,xx,01001: CMLE std7_std7_#0 -------- */ // <=s 0
...
[truncated message content] |
|
From: <sv...@va...> - 2014-06-10 12:05:43
|
Author: sewardj
Date: Tue Jun 10 12:05:33 2014
New Revision: 14020
Log:
Update.
Modified:
trunk/NEWS
trunk/docs/internals/3_9_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Jun 10 12:05:33 2014
@@ -140,6 +140,9 @@
334727 Build fails with -Werror=format-security
334788 clarify doc about --log-file initial program directory
335155 vgdb, fix error print statement.
+335262 arm64: movi 8bit version is not supported
+335263 arm64: dmb instruction is not implemented
+335496 arm64: sbc/abc instructions are not implemented
n-i-bz Fix KVM_CREATE_IRQCHIP ioctl handling
n-i-bz s390x: Fix memory corruption for multithreaded applications
n-i-bz vex arm->IR: allow PC as basereg in some LDRD cases
Modified: trunk/docs/internals/3_9_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_9_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_9_BUGSTATUS.txt Tue Jun 10 12:05:33 2014
@@ -25,10 +25,7 @@
=== VEX/arm64 ==========================================================
-335262 arm64: movi 8bit version is not supported
-335263 arm64: dmb instruction is not implemented
335440 arm64: ld1 (single structure) is not implemented
-335496 arm64: sbc/abc instructions are not implemented
335554 arm64: unhanded instruction: abs
335564 arm64: unhandled instruction fcvtpu Xn, Sn
@@ -202,3 +199,13 @@
31 May 2014
+335713 arm64: unhanded instruction: prfm (immediate)
+335735 arm64: unhanded instruction: cnt
+335736 arm64: unhanded instruction: uaddlv
+335785 vex amd64->IR: 0xC4 0xE2 0x75 0x2F 0xAC 0x18 0x40 0x7 (vmovupd)
+335848 arm64: unhanded instruction: {s,u}cvtf
+335902 arm64: unhanded instruction: sli
+335903 arm64: unhanded instruction: umull (vector)
+335907 segfault when running wine's ddrawex/tests/surface.c under valgrind
+
+Tues 10 June
|
|
From: <sv...@va...> - 2014-06-10 07:47:08
|
Author: bart
Date: Tue Jun 10 07:46:50 2014
New Revision: 14019
Log:
drd/tests/std_thread2: Filter out libstdc++ header file line numbers
Modified:
trunk/drd/tests/filter_stderr
trunk/drd/tests/std_thread2.stderr.exp
Modified: trunk/drd/tests/filter_stderr
==============================================================================
--- trunk/drd/tests/filter_stderr (original)
+++ trunk/drd/tests/filter_stderr Tue Jun 10 07:46:50 2014
@@ -18,6 +18,7 @@
-e 's/^Allocation context: Data section of .\//Allocation context: BSS section of /' \
-e '/^run: \/usr\/bin\/dsymutil.*/d' \
-e "s/, in frame #[0-9]* of thread /, in frame #? of thread /" \
+-e "s/(\(functional\|thread\):[0-9]*)/(\1:...)/" \
-e "s/(tc20_verifywrap.c:261)/(tc20_verifywrap.c:262)/" \
-e "/^Copyright (C) 2006-201., and GNU GPL'd, by Bart Van Assche.$/d" \
-e "s/\([A-Za-z_]*\) (clone.S:[0-9]*)/\1 (in \/...libc...)/" \
Modified: trunk/drd/tests/std_thread2.stderr.exp
==============================================================================
--- trunk/drd/tests/std_thread2.stderr.exp (original)
+++ trunk/drd/tests/std_thread2.stderr.exp Tue Jun 10 07:46:50 2014
@@ -2,9 +2,9 @@
Thread 2:
Conflicting store by thread 2 at 0x........ size 4
at 0x........: main::{lambda()#1}::operator()() const (std_thread2.cpp:21)
- by 0x........: void std::_Bind_simple<main::{lambda()#1} ()>::_M_invoke<>(std::_Index_tuple<>) (functional:1732)
- by 0x........: std::_Bind_simple<main::{lambda()#1} ()>::operator()() (functional:1720)
- by 0x........: std::thread::_Impl<std::_Bind_simple<main::{lambda()#1} ()> >::_M_run() (thread:115)
+ by 0x........: void std::_Bind_simple<main::{lambda()#1} ()>::_M_invoke<>(std::_Index_tuple<>) (functional:...)
+ by 0x........: std::_Bind_simple<main::{lambda()#1} ()>::operator()() (functional:...)
+ by 0x........: std::thread::_Impl<std::_Bind_simple<main::{lambda()#1} ()> >::_M_run() (thread:...)
by 0x........: execute_native_thread_routine (std_thread2.cpp:40)
Allocation context: BSS section of std_thread2
|
|
From: Philippe W. <phi...@sk...> - 2014-06-10 04:58:20
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora (7.5.1-37.fc18) Assembler: GNU assembler version 2.23.51.0.1-7.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.8.8-202.fc18.ppc64p7 ppc64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on gcc110 ( Fedora release 18 (Spherical Cow), ppc64 ) Started at 2014-06-09 20:00:09 PDT Ended at 2014-06-09 21:54:58 PDT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 582 tests, 9 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) drd/tests/std_thread2 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 581 tests, 8 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Mon Jun 9 20:29:20 2014 --- new.short Mon Jun 9 21:01:26 2014 *************** *** 8,10 **** ! == 581 tests, 8 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) --- 8,10 ---- ! == 582 tests, 9 stderr failures, 3 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) *************** *** 22,23 **** --- 22,24 ---- helgrind/tests/tc20_verifywrap (stderr) + drd/tests/std_thread2 (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 1.6s ( 6.8x, -----) me: 3.0s (13.0x, -----) ca:17.9s (77.7x, -----) he: 1.8s ( 7.6x, -----) ca: 5.3s (23.0x, -----) dr: 1.9s ( 8.1x, -----) ma: 2.2s ( 9.8x, -----) bigcode1 valgrind-old:0.23s no: 1.5s ( 6.6x, 3.2%) me: 2.9s (12.5x, 4.0%) ca:17.9s (77.9x, -0.3%) he: 1.7s ( 7.6x, 0.6%) ca: 5.5s (23.8x, -3.6%) dr: 1.7s ( 7.4x, 8.1%) ma: 2.1s ( 9.3x, 4.9%) -- bigcode2 -- bigcode2 valgrind-new:0.23s no: 1.5s ( 6.6x, -----) me: 2.9s (12.7x, -----) ca:18.1s (78.7x, -----) he: 2.3s ( 9.9x, -----) ca: 5.4s (23.6x, -----) dr: 1.8s ( 8.0x, -----) ma: 2.1s ( 9.3x, -----) bigcode2 valgrind-old:0.23s no: 1.6s ( 6.9x, -4.6%) me: 3.3s (14.5x,-14.8%) ca:18.2s (79.3x, -0.7%) he: 2.1s ( 9.1x, 7.9%) ca: 6.0s (26.0x,-10.1%) dr: 1.9s ( 8.4x, -5.5%) ma: 2.1s ( 9.2x, 1.4%) -- bz2 -- bz2 valgrind-new:0.74s no: 4.6s ( 6.2x, -----) me:11.5s (15.6x, -----) ca:25.9s (35.0x, -----) he:14.9s (20.1x, -----) ca:24.6s (33.2x, -----) dr:19.2s (26.0x, -----) ma: 4.7s ( 6.3x, -----) bz2 valgrind-old:0.74s no: 4.5s ( 6.1x, 0.4%) me:11.7s (15.9x, -2.0%) ca:25.8s (34.9x, 0.2%) he:14.9s (20.1x, -0.1%) ca:24.5s (33.1x, 0.3%) dr:19.4s (26.2x, -0.9%) ma: 4.7s ( 6.3x, -0.6%) -- fbench -- fbench valgrind-new:0.34s no: 2.1s ( 6.2x, -----) me: 5.3s (15.5x, -----) ca: 8.6s (25.2x, -----) he: 5.2s (15.4x, -----) ca: 7.5s (22.2x, -----) dr: 4.9s (14.3x, -----) ma: 2.3s ( 6.8x, -----) fbench valgrind-old:0.34s no: 2.2s ( 6.4x, -3.3%) me: 5.2s (15.3x, 1.5%) ca: 8.5s (25.0x, 0.6%) he: 5.3s (15.6x, -1.7%) ca: 7.5s (22.0x, 0.8%) dr: 5.0s (14.7x, -2.7%) ma: 2.1s ( 6.3x, 6.5%) -- ffbench -- ffbench valgrind-new:0.44s no: 1.4s ( 3.2x, -----) me: 2.7s ( 6.1x, -----) ca: 2.5s ( 5.7x, -----) he: 6.9s (15.7x, -----) ca: 7.1s (16.2x, -----) dr: 4.9s (11.1x, -----) ma: 1.0s ( 2.3x, -----) ffbench valgrind-old:0.44s no: 1.3s ( 3.0x, 5.7%) me: 2.4s ( 5.5x, 9.4%) ca: 2.5s ( 5.7x, 1.2%) he: 7.1s (16.1x, -2.6%) ca: 7.1s (16.1x, 0.3%) dr: 5.0s (11.4x, -2.2%) ma: 1.0s ( 2.3x, -1.0%) -- heap -- heap valgrind-new:0.41s no: 2.5s ( 6.1x, -----) me: 9.6s (23.4x, -----) ca:13.3s (32.4x, -----) he:11.9s (29.0x, -----) ca:12.2s (29.7x, -----) dr: 8.0s (19.5x, -----) ma: 8.7s (21.3x, -----) heap valgrind-old:0.41s no: 2.7s ( 6.5x, -7.2%) me: 9.5s (23.2x, 0.8%) ca:13.3s (32.6x, -0.5%) he:11.9s (28.9x, 0.2%) ca:12.1s (29.5x, 0.7%) dr: 8.0s (19.6x, -0.4%) ma: 8.4s (20.5x, 3.9%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.42s no: 2.5s ( 6.1x, -----) me:13.6s (32.4x, -----) ca:14.2s (33.9x, -----) he:13.2s (31.5x, -----) ca:13.2s (31.4x, -----) dr: 8.9s (21.3x, -----) ma: 8.8s (20.9x, -----) heap_pdb4 valgrind-old:0.42s no: 2.6s ( 6.3x, -3.9%) me:13.7s (32.5x, -0.4%) ca:14.6s (34.6x, -2.2%) he:13.3s (31.8x, -1.1%) ca:13.1s (31.2x, 0.5%) dr: 9.1s (21.7x, -2.1%) ma: 8.8s (20.9x, 0.0%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.5s (17.7x, -----) me: 2.1s (71.3x, -----) ca: 2.0s (65.7x, -----) he: 1.8s (61.0x, -----) ca: 1.9s (62.0x, -----) dr: 1.6s (52.3x, -----) ma: 1.6s (53.0x, -----) many-loss-records valgrind-old:0.03s no: 0.5s (17.7x, 0.0%) me: 2.1s (71.3x, 0.0%) ca: 1.9s (63.0x, 4.1%) he: 1.9s (62.0x, -1.6%) ca: 1.9s (62.0x, 0.0%) dr: 1.6s (52.3x, 0.0%) ma: 1.6s (52.3x, 1.3%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.7s (10.6x, -----) me: 3.4s (48.0x, -----) ca: 4.8s (67.9x, -----) he: 4.9s (69.4x, -----) ca: 2.9s (41.4x, -----) dr: 2.3s (32.9x, -----) ma: 2.3s (32.4x, -----) many-xpts valgrind-old:0.07s no: 0.8s (10.7x, -1.4%) me: 3.3s (47.3x, 1.5%) ca: 4.7s (67.1x, 1.1%) he: 4.8s (69.1x, 0.4%) ca: 2.9s (41.6x, -0.3%) dr: 2.2s (32.1x, 2.2%) ma: 2.3s (32.3x, 0.4%) -- sarp -- sarp valgrind-new:0.02s no: 0.4s (20.0x, -----) me: 3.0s (151.5x, -----) ca: 3.0s (150.0x, -----) he:11.2s (559.0x, -----) ca: 1.7s (85.0x, -----) dr: 1.1s (55.5x, -----) ma: 0.4s (21.0x, -----) sarp valgrind-old:0.02s no: 0.4s (20.0x, 0.0%) me: 3.0s (151.0x, 0.3%) ca: 2.9s (147.0x, 2.0%) he:11.1s (554.5x, 0.8%) ca: 1.7s (86.5x, -1.8%) dr: 1.1s (54.0x, 2.7%) ma: 0.4s (22.0x, -4.8%) -- tinycc -- tinycc valgrind-new:0.28s no: 3.0s (10.6x, -----) me:13.7s (49.0x, -----) ca:17.4s (62.3x, -----) he:18.9s (67.5x, -----) ca:15.6s (55.7x, -----) dr:12.1s (43.1x, -----) ma: 3.8s (13.6x, -----) tinycc valgrind-old:0.28s no: 3.0s (10.7x, -0.7%) me:13.8s (49.2x, -0.4%) ca:17.3s (61.8x, 0.7%) he:19.0s (68.0x, -0.7%) ca:15.8s (56.2x, -1.0%) dr:12.0s (43.0x, 0.3%) ma: 3.8s (13.6x, 0.3%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 53m31.414s user 52m30.372s sys 0m19.645s |
|
From: Christian B. <bor...@de...> - 2014-06-10 04:13:09
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.21-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-06-10 03:45:01 CEST Ended at 2014-06-10 06:12:56 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 647 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 4.4s (19.1x, -----) me: 7.0s (30.3x, -----) ca:26.4s (114.7x, -----) he: 5.1s (22.0x, -----) ca: 9.1s (39.7x, -----) dr: 5.4s (23.4x, -----) ma: 4.5s (19.8x, -----) bigcode1 valgrind-old:0.23s no: 4.4s (19.0x, 0.5%) me: 6.9s (30.0x, 1.0%) ca:26.4s (114.7x, -0.0%) he: 5.1s (22.1x, -0.2%) ca: 9.2s (39.8x, -0.1%) dr: 5.4s (23.3x, 0.6%) ma: 4.6s (19.8x, -0.2%) -- bigcode2 -- bigcode2 valgrind-new:0.25s no: 7.3s (29.3x, -----) me:13.8s (55.0x, -----) ca:39.6s (158.3x, -----) he:10.1s (40.3x, -----) ca:14.2s (56.9x, -----) dr: 9.6s (38.2x, -----) ma: 8.0s (31.9x, -----) bigcode2 valgrind-old:0.25s no: 7.4s (29.6x, -1.0%) me:13.8s (55.3x, -0.4%) ca:39.6s (158.4x, -0.0%) he:10.1s (40.4x, -0.2%) ca:14.3s (57.1x, -0.4%) dr: 9.6s (38.2x, 0.0%) ma: 8.0s (32.2x, -0.8%) -- bz2 -- bz2 valgrind-new:0.69s no: 5.1s ( 7.4x, -----) me:12.7s (18.3x, -----) ca:30.6s (44.4x, -----) he:19.6s (28.4x, -----) ca:34.3s (49.7x, -----) dr:29.0s (42.0x, -----) ma: 3.9s ( 5.6x, -----) bz2 valgrind-old:0.69s no: 5.1s ( 7.4x, -0.2%) me:12.7s (18.4x, -0.2%) ca:30.6s (44.3x, 0.2%) he:19.6s (28.4x, 0.1%) ca:34.3s (49.7x, 0.0%) dr:29.1s (42.1x, -0.2%) ma: 3.9s ( 5.6x, 0.0%) -- fbench -- fbench valgrind-new:0.40s no: 1.6s ( 4.0x, -----) me: 4.2s (10.5x, -----) ca: 9.3s (23.2x, -----) he: 6.2s (15.6x, -----) ca: 7.2s (17.9x, -----) dr: 5.5s (13.8x, -----) ma: 1.7s ( 4.2x, -----) fbench valgrind-old:0.40s no: 1.6s ( 4.0x, 0.0%) me: 4.2s (10.5x, 0.5%) ca: 9.3s (23.2x, -0.1%) he: 6.2s (15.5x, 0.3%) ca: 7.2s (18.0x, -0.7%) dr: 5.6s (14.0x, -1.3%) ma: 1.7s ( 4.2x, -0.0%) -- ffbench -- ffbench valgrind-new:0.19s no: 1.1s ( 5.6x, -----) me: 3.0s (15.6x, -----) ca: 3.0s (15.9x, -----) he:44.2s (232.6x, -----) ca: 9.6s (50.6x, -----) dr: 7.1s (37.3x, -----) ma: 1.0s ( 5.1x, -----) ffbench valgrind-old:0.19s no: 1.1s ( 5.6x, -0.9%) me: 3.0s (15.7x, -0.3%) ca: 3.0s (15.9x, 0.0%) he:45.0s (236.6x, -1.7%) ca: 9.6s (50.6x, 0.0%) dr: 7.1s (37.5x, -0.7%) ma: 1.0s ( 5.1x, 0.0%) -- heap -- heap valgrind-new:0.24s no: 1.9s ( 7.8x, -----) me: 8.7s (36.0x, -----) ca:13.1s (54.7x, -----) he:12.8s (53.2x, -----) ca:11.2s (46.5x, -----) dr: 8.1s (33.7x, -----) ma: 7.8s (32.7x, -----) heap valgrind-old:0.24s no: 1.9s ( 7.8x, -0.5%) me: 8.7s (36.1x, -0.1%) ca:13.2s (54.9x, -0.4%) he:13.1s (54.5x, -2.3%) ca:11.3s (46.9x, -1.0%) dr: 8.2s (34.3x, -1.9%) ma: 8.0s (33.2x, -1.8%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.1s ( 9.4x, -----) me:12.9s (58.6x, -----) ca:14.2s (64.8x, -----) he:14.5s (65.8x, -----) ca:12.3s (56.0x, -----) dr: 9.4s (43.0x, -----) ma: 8.1s (36.7x, -----) heap_pdb4 valgrind-old:0.22s no: 2.0s ( 9.3x, 1.0%) me:12.8s (58.3x, 0.6%) ca:14.2s (64.5x, 0.4%) he:14.0s (63.8x, 3.0%) ca:12.3s (56.0x, 0.1%) dr: 9.4s (42.6x, 0.8%) ma: 7.9s (36.1x, 1.6%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (24.0x, -----) me: 2.1s (103.5x, -----) ca: 1.9s (96.5x, -----) he: 2.2s (109.0x, -----) ca: 1.9s (95.0x, -----) dr: 1.8s (89.5x, -----) ma: 1.7s (83.5x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (24.0x, 0.0%) me: 2.1s (104.5x, -1.0%) ca: 1.9s (97.0x, -0.5%) he: 2.2s (108.5x, 0.5%) ca: 1.9s (95.5x, -0.5%) dr: 1.8s (89.5x, 0.0%) ma: 1.7s (83.0x, 0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.6s ( 9.1x, -----) me: 3.1s (44.4x, -----) ca:368.2s (5259.6x, -----) he: 6.5s (92.9x, -----) ca: 2.8s (39.7x, -----) dr: 2.6s (37.9x, -----) ma: 2.6s (37.4x, -----) many-xpts valgrind-old:0.07s no: 0.7s ( 9.3x, -1.6%) me: 3.1s (44.7x, -0.6%) ca:367.1s (5243.6x, 0.3%) he: 6.5s (93.0x, -0.2%) ca: 2.8s (39.7x, 0.0%) dr: 2.7s (38.0x, -0.4%) ma: 2.6s (37.3x, 0.4%) -- sarp -- sarp valgrind-new:0.02s no: 0.6s (29.0x, -----) me: 3.4s (171.0x, -----) ca: 3.5s (174.5x, -----) he:16.2s (812.0x, -----) ca: 2.0s (102.5x, -----) dr: 1.6s (81.0x, -----) ma: 0.5s (23.5x, -----) sarp valgrind-old:0.02s no: 0.6s (29.0x, 0.0%) me: 3.4s (171.0x, 0.0%) ca: 3.5s (172.5x, 1.1%) he:16.6s (830.5x, -2.3%) ca: 2.0s (102.5x, 0.0%) dr: 1.6s (79.5x, 1.9%) ma: 0.5s (23.5x, 0.0%) -- tinycc -- tinycc valgrind-new:0.22s no: 2.9s (13.2x, -----) me:14.4s (65.5x, -----) ca:30.0s (136.5x, -----) he:27.7s (125.8x, -----) ca:21.4s (97.1x, -----) dr:22.5s (102.2x, -----) ma: 4.0s (18.0x, -----) tinycc valgrind-old:0.22s no: 2.8s (12.9x, 2.4%) me:14.4s (65.6x, -0.1%) ca:30.0s (136.3x, 0.1%) he:27.8s (126.4x, -0.5%) ca:21.4s (97.3x, -0.2%) dr:20.5s (93.0x, 9.0%) ma: 4.0s (18.1x, -0.3%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 110m57.996s user 109m57.772s sys 0m50.756s |
|
From: Tom H. <to...@co...> - 2014-06-10 03:23:19
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-06-10 03:51:17 BST Ended at 2014-06-10 04:23:01 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 650 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-06-10 03:06:00
|
valgrind revision: 14018
VEX revision: 2870
C compiler: gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012]
GDB: GNU gdb (GDB) SUSE (7.5.1-2.1.1)
Assembler: GNU assembler (GNU Binutils; openSUSE 12.3) 2.23.1
C library: GNU C Library (GNU libc) stable release version 2.17 (git c758a6861537)
uname -mrs: Linux 3.7.9-1.1-desktop x86_64
Vendor version: Welcome to openSUSE 12.3 "Dartmouth" Beta 1 - Kernel %r (%t).
Nightly build on ultra ( gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] Linux 3.7.9-1.1-desktop x86_64 )
Started at 2014-06-09 21:30:01 CDT
Ended at 2014-06-09 22:05:50 CDT
Results differ from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 675 tests, 1 stderr failure, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
drd/tests/std_thread2 (stderr)
=================================================
== Results from 24 hours ago ==
=================================================
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 674 tests, 0 stderr failures, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
=================================================
== Difference between 24 hours ago and now ==
=================================================
*** old.short Mon Jun 9 21:47:07 2014
--- new.short Mon Jun 9 22:05:50 2014
***************
*** 8,12 ****
! == 674 tests, 0 stderr failures, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
--- 8,13 ----
! == 675 tests, 1 stderr failure, 0 stdout failures, 2 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/hginfo (stderrB)
gdbserver_tests/mssnapshot (stderrB)
+ drd/tests/std_thread2 (stderr)
=================================================
./valgrind-new/drd/tests/std_thread2.stderr.diff
=================================================
--- std_thread2.stderr.exp 2014-06-09 21:50:22.980095100 -0500
+++ std_thread2.stderr.out 2014-06-09 22:04:53.040936979 -0500
@@ -2,8 +2,8 @@
Thread 2:
Conflicting store by thread 2 at 0x........ size 4
at 0x........: main::{lambda()#1}::operator()() const (std_thread2.cpp:21)
- by 0x........: void std::_Bind_simple<main::{lambda()#1} ()>::_M_invoke<>(std::_Index_tuple<>) (functional:1732)
- by 0x........: std::_Bind_simple<main::{lambda()#1} ()>::operator()() (functional:1720)
+ by 0x........: void std::_Bind_simple<main::{lambda()#1} ()>::_M_invoke<>(std::_Index_tuple<>) (functional:1598)
+ by 0x........: std::_Bind_simple<main::{lambda()#1} ()>::operator()() (functional:1586)
by 0x........: std::thread::_Impl<std::_Bind_simple<main::{lambda()#1} ()> >::_M_run() (thread:115)
by 0x........: execute_native_thread_routine (std_thread2.cpp:40)
Allocation context: BSS section of std_thread2
=================================================
./valgrind-new/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-09 21:47:17.501237606 -0500
+++ hginfo.stderrB.out 2014-06-09 21:54:18.618548770 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-09 21:47:17.485238049 -0500
+++ mssnapshot.stderrB.out 2014-06-09 21:54:50.512662919 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-old/gdbserver_tests/hginfo.stderrB.diff
=================================================
--- hginfo.stderrB.exp 2014-06-09 21:31:48.189997760 -0500
+++ hginfo.stderrB.out 2014-06-09 21:35:29.202869985 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
Lock ga 0x........ {
Address 0x........ is 0 bytes inside data symbol "mx"
kind mbRec
=================================================
./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2014-06-09 21:31:48.247996155 -0500
+++ mssnapshot.stderrB.out 2014-06-09 21:36:00.605999188 -0500
@@ -1,5 +1,11 @@
relaying data between gdb and process ....
+Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2
+Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158"
vgdb-error value changed from 0 to 999999
+Missing separate debuginfo for /lib64/libpthread.so.0
+Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef"
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
|
|
From: Tom H. <to...@co...> - 2014-06-10 02:49:00
|
valgrind revision: 14018
VEX revision: 2870
C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2)
GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15)
Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118
C library: GNU C Library stable release version 2.14.1
uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64
Vendor version: Fedora release 15 (Lovelock)
Nightly build on bristol ( x86_64, Fedora 15 )
Started at 2014-06-10 03:12:45 BST
Ended at 2014-06-10 03:48:47 BST
Results differ from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
drd/tests/std_thread2 (stderr)
=================================================
== Results from 24 hours ago ==
=================================================
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... done
Regression test results follow
== 681 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
=================================================
== Difference between 24 hours ago and now ==
=================================================
*** old.short 2014-06-10 03:30:46.421958320 +0100
--- new.short 2014-06-10 03:48:47.309229940 +0100
***************
*** 4,6 ****
Building valgrind ... done
! Running regression tests ... done
--- 4,6 ----
Building valgrind ... done
! Running regression tests ... failed
***************
*** 8,10 ****
! == 681 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
--- 8,11 ----
! == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
! drd/tests/std_thread2 (stderr)
|
|
From: Tom H. <to...@co...> - 2014-06-10 02:43:01
|
valgrind revision: 14018
VEX revision: 2870
C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2)
GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16)
Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716
C library: GNU C Library development release version 2.14.90
uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64
Vendor version: Fedora release 16 (Verne)
Nightly build on bristol ( x86_64, Fedora 16 )
Started at 2014-06-10 03:03:17 BST
Ended at 2014-06-10 03:42:45 BST
Results differ from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
drd/tests/std_thread2 (stderr)
=================================================
== Results from 24 hours ago ==
=================================================
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... done
Regression test results follow
== 681 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
=================================================
== Difference between 24 hours ago and now ==
=================================================
*** old.short 2014-06-10 03:24:20.629720027 +0100
--- new.short 2014-06-10 03:42:45.341485575 +0100
***************
*** 4,6 ****
Building valgrind ... done
! Running regression tests ... done
--- 4,6 ----
Building valgrind ... done
! Running regression tests ... failed
***************
*** 8,10 ****
! == 681 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
--- 8,11 ----
! == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
! drd/tests/std_thread2 (stderr)
|
|
From: Tom H. <to...@co...> - 2014-06-10 02:37:03
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-06-10 02:51:06 BST Ended at 2014-06-10 03:36:46 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 5 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) drd/tests/std_thread2 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 681 tests, 4 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-06-10 03:18:15.480028617 +0100 --- new.short 2014-06-10 03:36:46.520717754 +0100 *************** *** 8,10 **** ! == 681 tests, 4 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) --- 8,10 ---- ! == 682 tests, 5 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) *************** *** 12,13 **** --- 12,14 ---- gdbserver_tests/mcmain_pic (stderr) + drd/tests/std_thread2 (stderr) exp-sgcheck/tests/preen_invars (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-06-10 02:31:05
|
valgrind revision: 14018
VEX revision: 2870
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-06-09 19:22:01 CDT
Ended at 2014-06-09 21:31:00 CDT
Results differ from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 596 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
== Results from 24 hours ago ==
=================================================
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 595 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
== Difference between 24 hours ago and now ==
=================================================
*** old.short Mon Jun 9 20:27:02 2014
--- new.short Mon Jun 9 21:31:00 2014
***************
*** 8,10 ****
! == 595 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
--- 8,10 ----
! == 596 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-09 20:28:04.839161414 -0500
+++ hackedbz2.stderr.out 2014-06-09 21:29:41.534044749 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-09 20:28:17.816311955 -0500
+++ err_disable3.stderr.out 2014-06-09 20:47:14.257495188 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-09 20:28:23.695380155 -0500
+++ err_disable4.stderr.out 2014-06-09 20:47:18.493544328 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-09 20:28:23.329375909 -0500
+++ threadname.stderr.out 2014-06-09 20:53:14.266671457 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-09 20:28:21.664356594 -0500
+++ threadname_xml.stderr.out 2014-06-09 20:53:16.360695749 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-06-09 19:22:23.619441481 -0500
+++ hackedbz2.stderr.out 2014-06-09 20:25:42.554510848 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-06-09 19:23:33.076247211 -0500
+++ err_disable3.stderr.out 2014-06-09 19:43:03.403823541 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-06-09 19:23:25.576160207 -0500
+++ err_disable4.stderr.out 2014-06-09 19:43:07.546871602 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-06-09 19:23:25.589160358 -0500
+++ threadname.stderr.out 2014-06-09 19:49:00.553966645 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-06-09 19:23:23.273133491 -0500
+++ threadname_xml.stderr.out 2014-06-09 19:49:02.610990507 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
|
|
From: Tom H. <to...@co...> - 2014-06-10 02:22:39
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-06-10 02:41:00 BST Ended at 2014-06-10 03:22:27 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == drd/tests/std_thread2 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 681 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-06-10 03:00:43.308124020 +0100 --- new.short 2014-06-10 03:22:27.700974155 +0100 *************** *** 8,10 **** ! == 681 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/preen_invars (stdout) --- 8,11 ---- ! == 682 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == ! drd/tests/std_thread2 (stderr) exp-sgcheck/tests/preen_invars (stdout) |
|
From: Tom H. <to...@co...> - 2014-06-10 02:19:51
|
valgrind revision: 14018 VEX revision: 2870 C compiler: gcc (GCC) 4.8.2 20131212 (Red Hat 4.8.2-7) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.13.10-200.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-06-10 02:31:40 BST Ended at 2014-06-10 03:19:36 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/hackedbz2 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 681 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/hackedbz2 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-06-10 02:57:12.884228645 +0100 --- new.short 2014-06-10 03:19:36.245402630 +0100 *************** *** 8,10 **** ! == 681 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/hackedbz2 (stderr) --- 8,10 ---- ! == 682 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/hackedbz2 (stderr) |