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From: Josef W. <Jos...@gm...> - 2014-05-30 09:47:07
|
Am 28.05.2014 21:34, schrieb stavros kaparelos: > >Why does this only work for x86? > Because the aim of my dissertation was to do any extensions to be valid > for Intel x86 so other architectures haven't been considered. > ... Ok, so that's just a limitation of supported configurations. These should be simulated quite fine also with other ISAs. Of course, they may not reflect the cache configuration of these other architectures then. But this is similar to the current situation: cachegrind/callgrind is simulating LRU replacement, but ARM often does random replacement in L1. In any case, configuration parameters must be able to be specified on the command line. >>Can you give some numbers about the performance penalties of the simulator with the added features? > > L2 cache inclusion for not cache-unfriendly code according to the tests > made did not introduce a slowdown greater than 10%. Most of the programs > that took part on this test were Unix commands. Cache-unfriendly > programs introduced a slowdown of 16%. I suppose the worst case is random access on a huge array. The added cost is a failed tag search in the additional L2, and the penalty then depends on L2 associativity. The usage of cachegrind is to find bottlenecks related to the cache hierarchy. I wonder if L2 miss behavior really helps a lot in this regard. It would be different if we would be able to simulate multiple private L1/L2 of a multicore chip, to understand whether there is contention at the shared L3 level generated by all the cores. > TLB measuring on normal programs (the same used to test L2 cache > inclusion), that do not have - or they have no reason to have - an > unfriendly TLB behaviour introduced a maximum slowdown of 41% and a > minimum of 2%. So TLB simulation must be optional. Does your simulation run L2/L3 accesses then with physical addresses? If so, you must have some page allocation algorithm implemented? To understand whether good/bad TLB behavior has an impact on performance, I think one should be able to see whether page walks resulting from TLB misses themself can be served from cache or not. I suppose your simulation does not include this? Josef However, the same programs with detailed page tracking > option enabled introduced a maximum slowdown of 76% and a minimum of 6%. > Moreover, TLB measuring tests on programs that are TLB unfriendly > introduced a maximum slowdown of 440% and 1400% with the page tracking > option enabled. > > Stavros > > > ------------------------------------------------------------------------------ > Time is money. Stop wasting it! Get your web API in 5 minutes. > www.restlet.com/download > http://p.sf.net/sfu/restlet > > > > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |