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From: <sv...@va...> - 2014-03-02 12:50:00
|
Author: sewardj
Date: Sun Mar 2 12:49:52 2014
New Revision: 13849
Log:
Enable sys_epoll_create1, sys_epoll_ctl, sys_epoll_pwait, sys_prctl.
Modified:
trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-arm64-linux.c Sun Mar 2 12:49:52 2014
@@ -881,6 +881,9 @@
LINXY(__NR_getxattr, sys_getxattr), // 8
LINXY(__NR_lgetxattr, sys_lgetxattr), // 9
GENXY(__NR_getcwd, sys_getcwd), // 17
+ LINXY(__NR_epoll_create1, sys_epoll_create1), // 20
+ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 21
+ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 22
GENXY(__NR_dup, sys_dup), // 23
LINXY(__NR_dup3, sys_dup3), // 24
@@ -945,6 +948,7 @@
GENX_(__NR_setrlimit, sys_setrlimit), // 164
GENXY(__NR_getrusage, sys_getrusage), // 165
GENX_(__NR_umask, sys_umask), // 166
+ LINXY(__NR_prctl, sys_prctl), // 167
GENXY(__NR_gettimeofday, sys_gettimeofday), // 169
GENX_(__NR_getpid, sys_getpid), // 172
GENX_(__NR_getppid, sys_getppid), // 173
|
|
From: <sv...@va...> - 2014-03-02 12:48:43
|
Author: sewardj
Date: Sun Mar 2 12:48:34 2014
New Revision: 13848
Log:
Add many test cases from arm64.
Modified:
trunk/none/tests/arm64/test_arm64_fp_and_simd.c
trunk/none/tests/arm64/test_arm64_int.c
Modified: trunk/none/tests/arm64/test_arm64_fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/test_arm64_fp_and_simd.c (original)
+++ trunk/none/tests/arm64/test_arm64_fp_and_simd.c Sun Mar 2 12:48:34 2014
@@ -3,6 +3,7 @@
#include <assert.h>
#include <malloc.h> // memalign
#include <string.h> // memset
+#include <math.h> // isnormal
typedef unsigned char UChar;
typedef unsigned short int UShort;
@@ -16,15 +17,20 @@
#define True ((Bool)1)
+#define ITERS 1
+
+
union _V128 {
- UChar b[16];
- UShort h[8];
- UInt i[4];
- ULong d[2];
+ UChar u8[16];
+ UShort u16[8];
+ UInt u32[4];
+ ULong u64[2];
+ float f32[4];
+ double f64[2];
};
typedef union _V128 V128;
-static UChar randUChar ( void )
+static inline UChar randUChar ( void )
{
static UInt seed = 80021;
seed = 1103515245 * seed + 12345;
@@ -41,18 +47,32 @@
return r;
}
+/* Generates a random V128. Ensures that that it contains normalised
+ FP numbers when viewed as either F32x4 or F64x2, so that it is
+ reasonable to use in FP test cases. */
static void randV128 ( V128* v )
{
+ static UInt nCalls = 0, nIters = 0;
Int i;
- for (i = 0; i < 16; i++)
- v->b[i] = randUChar();
+ nCalls++;
+ while (1) {
+ nIters++;
+ for (i = 0; i < 16; i++) {
+ v->u8[i] = randUChar();
+ }
+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
+ break;
+ }
+ if (0 == (nCalls & 0xFF))
+ printf("randV128: %u calls, %u iters\n", nCalls, nIters);
}
static void showV128 ( V128* v )
{
Int i;
for (i = 15; i >= 0; i--)
- printf("%02x", (Int)v->b[i]);
+ printf("%02x", (Int)v->u8[i]);
}
__attribute__((unused))
@@ -76,6 +96,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv s8, v7.4s ; "
@@ -92,6 +113,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv h8, v7.8h ; "
@@ -108,6 +130,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv h8, v7.4h ; "
@@ -124,6 +147,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv b8, v7.16b ; "
@@ -140,6 +164,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"uminv b8, v7.8b ; "
@@ -164,6 +189,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv s8, v7.4s ; "
@@ -180,6 +206,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv h8, v7.8h ; "
@@ -196,6 +223,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv h8, v7.4h ; "
@@ -212,6 +240,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv b8, v7.16b ; "
@@ -228,6 +257,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"umaxv b8, v7.8b ; "
@@ -249,7 +279,7 @@
/* -- D[0..1] -- */
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -257,12 +287,12 @@
"str q7, [%0, #32] "
: : "r"(&block[0]) : "memory", "x19", "v7"
);
- printf("INS v7.d[0],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ printf("INS v7.u64[0],x19 ");
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -271,13 +301,13 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.d[1],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
/* -- S[0..3] -- */
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -286,11 +316,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.s[0],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -299,11 +329,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.s[1],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -312,11 +342,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.s[2],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -325,13 +355,13 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.s[3],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
/* -- H[0..7] -- */
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -340,11 +370,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[0],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -353,11 +383,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[1],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -366,11 +396,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[2],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -379,11 +409,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[3],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -392,11 +422,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[4],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -405,11 +435,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[5],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -418,11 +448,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[6],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -431,13 +461,13 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.h[7],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
/* -- B[0,15] -- */
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -446,11 +476,11 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.b[0],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
memset(&block, 0x55, sizeof(block));
- block[1].d[0] = randULong();
+ block[1].u64[0] = randULong();
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"ldr x19, [%0, #16] ; "
@@ -459,7 +489,7 @@
: : "r"(&block[0]) : "memory", "x19", "v7"
);
printf("INS v7.b[15],x19 ");
- showV128(&block[0]); printf(" %016llx ", block[1].d[0]);
+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
showV128(&block[2]); printf("\n");
}
@@ -475,6 +505,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv s8, v7.4s ; "
@@ -491,6 +522,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv h8, v7.8h ; "
@@ -507,6 +539,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv h8, v7.4h ; "
@@ -523,6 +556,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv b8, v7.16b ; "
@@ -539,6 +573,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"sminv b8, v7.8b ; "
@@ -563,6 +598,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv s8, v7.4s ; "
@@ -579,6 +615,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv h8, v7.8h ; "
@@ -595,6 +632,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv h8, v7.4h ; "
@@ -611,6 +649,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv b8, v7.16b ; "
@@ -627,6 +666,7 @@
for (i = 0; i < 10; i++) {
memset(&block, 0x55, sizeof(block));
randV128(&block[0]);
+ randV128(&block[1]);
__asm__ __volatile__(
"ldr q7, [%0, #0] ; "
"smaxv b8, v7.8b ; "
@@ -640,8 +680,6 @@
}
-#define ITERS 100
-
/* Note this also sets the destination register to a known value (0x55..55)
since it can sometimes be an input to the instruction too. */
#define GEN_BINARY_TEST(INSN,SUFFIX) \
@@ -653,6 +691,7 @@
memset(block, 0x55, sizeof(block)); \
randV128(&block[0]); \
randV128(&block[1]); \
+ randV128(&block[2]); \
__asm__ __volatile__( \
"ldr q7, [%0, #0] ; " \
"ldr q8, [%0, #16] ; " \
@@ -679,6 +718,7 @@
V128 block[2]; \
memset(block, 0x55, sizeof(block)); \
randV128(&block[0]); \
+ randV128(&block[1]); \
__asm__ __volatile__( \
"ldr q7, [%0, #0] ; " \
"ldr q8, [%0, #16] ; " \
@@ -702,6 +742,7 @@
V128 block[2]; \
memset(block, 0x55, sizeof(block)); \
randV128(&block[0]); \
+ randV128(&block[1]); \
__asm__ __volatile__( \
"ldr q7, [%0, #0] ; " \
"ldr q8, [%0, #16] ; " \
@@ -855,6 +896,9 @@
GEN_SHIFT_TEST(sshr, 2d, 2d, 1)
GEN_SHIFT_TEST(sshr, 2d, 2d, 13)
GEN_SHIFT_TEST(sshr, 2d, 2d, 63)
+GEN_SHIFT_TEST(shl, 2d, 2d, 1)
+GEN_SHIFT_TEST(shl, 2d, 2d, 13)
+GEN_SHIFT_TEST(shl, 2d, 2d, 63)
GEN_SHIFT_TEST(ushr, 4s, 4s, 1)
GEN_SHIFT_TEST(ushr, 4s, 4s, 13)
@@ -862,6 +906,9 @@
GEN_SHIFT_TEST(sshr, 4s, 4s, 1)
GEN_SHIFT_TEST(sshr, 4s, 4s, 13)
GEN_SHIFT_TEST(sshr, 4s, 4s, 31)
+GEN_SHIFT_TEST(shl, 4s, 4s, 1)
+GEN_SHIFT_TEST(shl, 4s, 4s, 13)
+GEN_SHIFT_TEST(shl, 4s, 4s, 31)
GEN_SHIFT_TEST(ushr, 2s, 2s, 1)
GEN_SHIFT_TEST(ushr, 2s, 2s, 13)
@@ -869,6 +916,9 @@
GEN_SHIFT_TEST(sshr, 2s, 2s, 1)
GEN_SHIFT_TEST(sshr, 2s, 2s, 13)
GEN_SHIFT_TEST(sshr, 2s, 2s, 31)
+GEN_SHIFT_TEST(shl, 2s, 2s, 1)
+GEN_SHIFT_TEST(shl, 2s, 2s, 13)
+GEN_SHIFT_TEST(shl, 2s, 2s, 31)
GEN_SHIFT_TEST(ushr, 8h, 8h, 1)
GEN_SHIFT_TEST(ushr, 8h, 8h, 13)
@@ -876,6 +926,9 @@
GEN_SHIFT_TEST(sshr, 8h, 8h, 1)
GEN_SHIFT_TEST(sshr, 8h, 8h, 13)
GEN_SHIFT_TEST(sshr, 8h, 8h, 15)
+GEN_SHIFT_TEST(shl, 8h, 8h, 1)
+GEN_SHIFT_TEST(shl, 8h, 8h, 13)
+GEN_SHIFT_TEST(shl, 8h, 8h, 15)
GEN_SHIFT_TEST(ushr, 4h, 4h, 1)
GEN_SHIFT_TEST(ushr, 4h, 4h, 13)
@@ -883,16 +936,23 @@
GEN_SHIFT_TEST(sshr, 4h, 4h, 1)
GEN_SHIFT_TEST(sshr, 4h, 4h, 13)
GEN_SHIFT_TEST(sshr, 4h, 4h, 15)
+GEN_SHIFT_TEST(shl, 4h, 4h, 1)
+GEN_SHIFT_TEST(shl, 4h, 4h, 13)
+GEN_SHIFT_TEST(shl, 4h, 4h, 15)
GEN_SHIFT_TEST(ushr, 16b, 16b, 1)
GEN_SHIFT_TEST(ushr, 16b, 16b, 7)
GEN_SHIFT_TEST(sshr, 16b, 16b, 1)
GEN_SHIFT_TEST(sshr, 16b, 16b, 7)
+GEN_SHIFT_TEST(shl, 16b, 16b, 1)
+GEN_SHIFT_TEST(shl, 16b, 16b, 7)
GEN_SHIFT_TEST(ushr, 8b, 8b, 1)
GEN_SHIFT_TEST(ushr, 8b, 8b, 7)
GEN_SHIFT_TEST(sshr, 8b, 8b, 1)
GEN_SHIFT_TEST(sshr, 8b, 8b, 7)
+GEN_SHIFT_TEST(shl, 8b, 8b, 1)
+GEN_SHIFT_TEST(shl, 8b, 8b, 7)
GEN_SHIFT_TEST(ushll, 2d, 2s, 0)
GEN_SHIFT_TEST(ushll, 2d, 2s, 15)
@@ -913,27 +973,342 @@
GEN_UNARY_TEST(xtn, 4h, 4s)
GEN_UNARY_TEST(xtn2, 8h, 4s)
+
+/* Generate a test that involves one integer reg and one vector reg,
+ with no bias as towards which is input or output. */
+#define GEN_ONEINT_ONEVEC_TEST(TESTNAME,INSN,INTREGNO,VECREGNO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( void ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0]); \
+ randV128(&block[1]); \
+ randV128(&block[2]); \
+ randV128(&block[3]); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREGNO", [%0, #0] ; " \
+ "ldr x"#INTREGNO", [%0, #16] ; " \
+ INSN " ; " \
+ "str q"#VECREGNO", [%0, #32] ; " \
+ "str x"#INTREGNO", [%0, #48] ; " \
+ : : "r"(&block[0]) : "memory", "v"#VECREGNO, "x"#INTREGNO \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf("\n"); \
+ } \
+ }
+
+GEN_ONEINT_ONEVEC_TEST(umov_01, "umov x9, v10.d[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_02, "umov x9, v10.d[1]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_03, "umov w9, v10.s[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_04, "umov w9, v10.s[3]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_05, "umov w9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_06, "umov w9, v10.h[7]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_07, "umov w9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(umov_08, "umov w9, v10.b[15]", 9, 10)
+
+GEN_ONEINT_ONEVEC_TEST(smov_01, "smov x9, v10.s[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_02, "smov x9, v10.s[3]", 9, 10)
+
+GEN_ONEINT_ONEVEC_TEST(smov_03, "smov x9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_04, "smov x9, v10.h[7]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_05, "smov w9, v10.h[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_06, "smov w9, v10.h[7]", 9, 10)
+
+GEN_ONEINT_ONEVEC_TEST(smov_07, "smov x9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_08, "smov x9, v10.b[15]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_09, "smov w9, v10.b[0]", 9, 10)
+GEN_ONEINT_ONEVEC_TEST(smov_10, "smov w9, v10.b[15]", 9, 10)
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output. */
+#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( void ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0]); \
+ randV128(&block[1]); \
+ randV128(&block[2]); \
+ randV128(&block[3]); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREG1NO", [%0, #0] ; " \
+ "ldr q"#VECREG2NO", [%0, #16] ; " \
+ INSN " ; " \
+ "str q"#VECREG1NO", [%0, #32] ; " \
+ "str q"#VECREG2NO", [%0, #48] ; " \
+ : : "r"(&block[0]) : "memory", "v"#VECREG1NO, "v"#VECREG2NO \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf("\n"); \
+ } \
+ }
+
+GEN_TWOVEC_TEST(fcvtn_01, "fcvtn v22.2s, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fcvtn_02, "fcvtn2 v22.4s, v23.2d", 22, 23)
+
+GEN_UNARY_TEST(neg, 2d, 2d)
+GEN_UNARY_TEST(neg, 4s, 4s)
+GEN_UNARY_TEST(neg, 2s, 2s)
+GEN_UNARY_TEST(neg, 8h, 8h)
+GEN_UNARY_TEST(neg, 4h, 4h)
+GEN_UNARY_TEST(neg, 16b, 16b)
+GEN_UNARY_TEST(neg, 8b, 8b)
+GEN_BINARY_TEST(fadd, 2d)
+GEN_BINARY_TEST(fadd, 4s)
+GEN_BINARY_TEST(fadd, 2s)
+GEN_BINARY_TEST(fsub, 2d)
+GEN_BINARY_TEST(fsub, 4s)
+GEN_BINARY_TEST(fsub, 2s)
+GEN_BINARY_TEST(fmul, 2d)
+GEN_BINARY_TEST(fmul, 4s)
+GEN_BINARY_TEST(fmul, 2s)
+GEN_BINARY_TEST(fdiv, 2d)
+GEN_BINARY_TEST(fdiv, 4s)
+GEN_BINARY_TEST(fdiv, 2s)
+GEN_BINARY_TEST(fmla, 2d)
+GEN_BINARY_TEST(fmla, 4s)
+GEN_BINARY_TEST(fmla, 2s)
+GEN_BINARY_TEST(fmls, 2d)
+GEN_BINARY_TEST(fmls, 4s)
+GEN_BINARY_TEST(fmls, 2s)
+GEN_BINARY_TEST(fabd, 2d)
+GEN_BINARY_TEST(fabd, 4s)
+GEN_BINARY_TEST(fabd, 2s)
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. */
+#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( void ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0]); \
+ randV128(&block[1]); \
+ randV128(&block[2]); \
+ randV128(&block[3]); \
+ randV128(&block[4]); \
+ randV128(&block[5]); \
+ __asm__ __volatile__( \
+ "ldr q"#VECREG1NO", [%0, #0] ; " \
+ "ldr q"#VECREG2NO", [%0, #16] ; " \
+ "ldr q"#VECREG3NO", [%0, #32] ; " \
+ INSN " ; " \
+ "str q"#VECREG1NO", [%0, #48] ; " \
+ "str q"#VECREG2NO", [%0, #64] ; " \
+ "str q"#VECREG3NO", [%0, #80] ; " \
+ : : "r"(&block[0]) : "memory", "v"#VECREG1NO, "v"#VECREG2NO, "v"#VECREG3NO \
+ ); \
+ printf(INSN " "); \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf("\n"); \
+ } \
+ }
+
+GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23)
+GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23)
+
+/* overkill -- don't need two vecs, only one */
+GEN_TWOVEC_TEST(fmov_scalar_imm_01, "fmov d22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_scalar_imm_02, "fmov d22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_scalar_imm_03, "fmov d22, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_scalar_imm_04, "fmov s22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_scalar_imm_05, "fmov s22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_scalar_imm_06, "fmov s22, #-1.0", 22, 23)
+
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_01, "fmov s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_02, "fmov d7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_03, "fmov v7.d[1], x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_04, "fmov w15, s7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_05, "fmov x15, d7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_gen_06, "fmov x15, v7.d[1]", 15, 7)
+
+GEN_TWOVEC_TEST(movi_vector_imm_01, "fmov d22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(movi_vector_imm_02, "fmov d22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(movi_vector_imm_03, "fmov d22, #1.0", 22, 23)
+GEN_TWOVEC_TEST(movi_vector_imm_04, "fmov v22.2d, #0.125", 22, 23)
+GEN_TWOVEC_TEST(movi_vector_imm_05, "fmov v22.2d, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(movi_vector_imm_06, "fmov v22.2d, #1.0", 22, 23)
+
+GEN_ONEINT_ONEVEC_TEST(sucvtf_01, "scvtf s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_02, "scvtf d7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_03, "scvtf s7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_04, "scvtf d7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_05, "ucvtf s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_06, "ucvtf d7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_07, "ucvtf s7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(sucvtf_08, "ucvtf d7, x15", 15, 7)
+
+GEN_THREEVEC_TEST(fadd_d, "fadd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fadd_s, "fadd s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_d, "fsub d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_s, "fsub s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_d, "fmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s, "fmul s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fdiv_d, "fdiv d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fdiv_s, "fdiv s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fnmul_d, "fnmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fnmul_s, "fnmul s2, s11, s29", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fabd_d, "fabd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fabd_s, "fabd s2, s11, s29", 2, 11, 29)
+
+GEN_TWOVEC_TEST(fmov_d, "fmov d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fmov_s, "fmov s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fabs_d, "fabs d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fabs_s, "fabs s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fneg_d, "fneg d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fneg_s, "fneg s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_d, "fsqrt d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_s, "fsqrt s22, s23", 22, 23)
+
+GEN_UNARY_TEST(fneg, 2d, 2d)
+GEN_UNARY_TEST(fneg, 4s, 4s)
+GEN_UNARY_TEST(fneg, 2s, 2s)
+GEN_UNARY_TEST(fabs, 2d, 2d)
+GEN_UNARY_TEST(fabs, 4s, 4s)
+GEN_UNARY_TEST(fabs, 2s, 2s)
+
+/* IMPORTANT: keep the tests in here in the same order as the
+ implementations are in guest_arm64_toIR.c. */
int main ( void )
{
assert(sizeof(V128) == 16);
- printf("FMOV (general) MISSING\n");
- printf("FMOV (scalar, immediate) MISSING\n");
- printf("{FMOV,MOVI} (vector, immediate) MISSING\n");
- printf("{S,U}CVTF (scalar, integer) MISSING\n");
- printf("F{ADD,SUB,MUL,DIV,NMUL} (scalar) MISSING\n");
- printf("F{MOV,ABS,NEG,SQRT} D/D or S/S MISSING\n");
- printf("F{ABS,NEG} (vector) MISSING\n");
- printf("FCMP,FCMPE MISSING\n");
- printf("F{N}M{ADD,SUB} MISSING\n");
- printf("FCVT{N,P,M,Z}{S,U} (scalar, integer) MISSING\n");
- printf("FRINT{I,M,P,Z} (scalar) MISSING\n");
- printf("FCVT (scalar) MISSING\n");
- printf("FABD (scalar) MISSING\n");
- printf("{S,U}CVTF (vector, integer) MISSING\n");
- printf("F{ADD,SUB,MUL,DIV,MLA,MLS} (vector) MISSING\n");
+ printf("BEGIN: FMOV (general)\n");
+ test_fmov_gen_01();
+ test_fmov_gen_02();
+ test_fmov_gen_03();
+ test_fmov_gen_04();
+ test_fmov_gen_05();
+ test_fmov_gen_06();
+ printf("END: FMOV (general)\n\n");
+
+ printf("BEGIN: FMOV (scalar, immediate)\n");
+ test_fmov_scalar_imm_01();
+ test_fmov_scalar_imm_02();
+ test_fmov_scalar_imm_03();
+ test_fmov_scalar_imm_04();
+ test_fmov_scalar_imm_05();
+ test_fmov_scalar_imm_06();
+ printf("END: FMOV (scalar, immediate)\n\n");
+
+ printf("BEGIN: {FMOV,MOVI} (vector, immediate)\n");
+ test_movi_vector_imm_01();
+ test_movi_vector_imm_02();
+ test_movi_vector_imm_03();
+ test_movi_vector_imm_04();
+ test_movi_vector_imm_05();
+ test_movi_vector_imm_06();
+ printf("END: {FMOV,MOVI} (vector, immediate)\n\n");
+
+ printf("BEGIN: {S,U}CVTF (scalar, integer)\n");
+ test_sucvtf_01();
+ test_sucvtf_02();
+ test_sucvtf_03();
+ test_sucvtf_04();
+ //test_sucvtf_05();
+ test_sucvtf_06();
+ test_sucvtf_07();
+ test_sucvtf_08();
+ printf("END: {S,U}CVTF (scalar, integer) (MISSING 1 case of 8)\n\n");
+
+ printf("BEGIN: F{ADD,SUB,MUL,DIV,NMUL} (scalar)\n");
+ test_fadd_d();
+ test_fadd_s();
+ test_fsub_d();
+ test_fsub_s();
+ test_fmul_d();
+ test_fmul_s();
+ test_fdiv_d();
+ test_fdiv_s();
+ test_fnmul_d();
+ test_fnmul_s();
+ printf("END: F{ADD,SUB,MUL,DIV,NMUL} (scalar)\n\n");
+
+ printf("BEGIN: F{MOV,ABS,NEG,SQRT} D/D or S/S\n");
+ test_fmov_d();
+ test_fmov_s();
+ test_fabs_d();
+ test_fabs_s();
+ test_fneg_d();
+ test_fneg_s();
+ test_fsqrt_d();
+ test_fsqrt_s();
+ printf("END: F{MOV,ABS,NEG,SQRT} D/D or S/S\n\n");
+
+ printf("BEGIN: F{ABS,NEG} (vector)\n");
+ test_fabs_2d_2d();
+ //test_fabs_4s_4s();
+ //test_fabs_2s_2s();
+ test_fneg_2d_2d();
+ //test_fneg_4s_4s();
+ //test_fneg_2s_2s();
+ printf("END: F{ABS,NEG} (vector) (MISSING 4s/2s cases)\n\n");
+
+ printf("FCMP,FCMPE MISSING\n\n");
+
+ printf("F{N}M{ADD,SUB} MISSING\n\n");
+
+ printf("FCVT{N,P,M,Z}{S,U} (scalar, integer) MISSING\n\n");
+
+ printf("FRINT{I,M,P,Z} (scalar) MISSING\n\n");
+
+ printf("FCVT (scalar) MISSING\n\n");
+
+ printf("BEGIN: FABD (scalar) MISSING\n");
+ test_fabd_d();
+ test_fabd_s();
+ printf("END: FABD (scalar) MISSING\n\n");
+
+ printf("{S,U}CVTF (vector, integer) MISSING\n\n");
+
+ printf("BEGIN: F{ADD,SUB,MUL,DIV,MLA,MLS,ABD} (vector)\n");
+ test_fadd_2d();
+ test_fadd_4s();
+ test_fadd_2s();
+ test_fsub_2d();
+ test_fsub_4s();
+ test_fsub_2s();
+ test_fmul_2d();
+ test_fmul_4s();
+ test_fmul_2s();
+ test_fdiv_2d();
+ test_fdiv_4s();
+ test_fdiv_2s();
+ test_fmla_2d();
+ test_fmla_4s();
+ test_fmla_2s();
+ test_fmls_2d();
+ test_fmls_4s();
+ test_fmls_2s();
+ test_fabd_2d();
+ //test_fabd_4s();
+ //test_fabd_2s();
+ printf("END: F{ADD,SUB,MUL,DIV,MLA,MLS,ABD} (vector) (MISSING fabd 2s/4s)\n\n");
+
+ printf("BEGIN: FCVTN (MISSING 16F <- 32F cases)\n");
+ test_fcvtn_01();
+ test_fcvtn_02();
+ printf("END: FCVTN (MISSING 16F <- 32F cases)\n\n");
- printf("ADD/SUB (vector) MISSING\n");
+ printf("BEGIN: ADD/SUB (vector)\n");
test_add_2d();
test_add_4s();
test_add_2s();
@@ -948,9 +1323,14 @@
test_sub_4h();
//test_sub_16b();
//test_sub_8b();
+ printf("END: ADD/SUB (vector) (MISSING b16/b8 cases)\n\n");
- printf("ADD/SUB (scalar) MISSING\n");
+ printf("BEGIN: ADD/SUB (scalar)\n");
+ test_add_d_d_d();
+ test_sub_d_d_d();
+ printf("END: ADD/SUB (scalar)\n\n");
+ printf("BEGIN: MUL/PMUL/MLA/MLS (vector)\n");
test_mul_4s();
test_mul_2s();
test_mul_8h();
@@ -969,8 +1349,9 @@
test_mls_4h();
//test_mls_16b();
//test_mls_8b();
- printf("MUL/PMUL/MLA/MLS (vector) (partly MISSING)\n");
+ printf("END: MUL/PMUL/MLA/MLS (vector) (partly MISSING)\n\n");
+ printf("BEGIN: {S,U}{MIN,MAX} (vector)\n");
test_umax_4s();
test_umax_8h();
test_umax_4h();
@@ -991,12 +1372,16 @@
test_smin_4h();
test_smin_16b();
test_smin_8b();
+ printf("END: {S,U}{MIN,MAX} (vector)\n\n");
+ printf("BEGIN: {S,U}{MIN,MAX}V\n");
test_UMINV();
test_UMAXV();
test_SMINV();
test_SMAXV();
+ printf("END: {S,U}{MIN,MAX}V\n\n");
+ printf("BEGIN: {AND,BIC,ORR,ORN} (vector)\n");
test_and_16b();
test_and_8b();
test_bic_16b();
@@ -1005,7 +1390,9 @@
test_orr_8b();
test_orn_16b();
test_orn_8b();
+ printf("END: {AND,BIC,ORR,ORN} (vector)\n\n");
+ printf("BEGIN: CM{EQ,HI,HS,GE,GT,TST,LE,LT} (vector)\n\n");
test_cmeq_2d();
#if 0
test_cmeq_4s();
@@ -1050,8 +1437,10 @@
test_cmge_16b();
test_cmge_8b();
#endif
- printf("CM{EQ,HI,HS,GE,GT,TST,LE,LT} (vector) (w/zero cases MISSING)\n");
+ printf("END: CM{EQ,HI,HS,GE,GT,TST,LE,LT} (vector) "
+ "(w/zero and many other cases MISSING)\n\n");
+ printf("BEGIN: {EOR,BSL,BIT,BIF} (vector)\n");
test_eor_16b();
test_eor_8b();
test_bsl_16b();
@@ -1060,7 +1449,9 @@
test_bit_8b();
test_bif_16b();
test_bif_8b();
+ printf("END: {EOR,BSL,BIT,BIF} (vector)\n\n");
+ printf("BEGIN: {USHR,SSHR,SHL} (vector, immediate)\n");
test_ushr_2d_2d_1();
test_ushr_2d_2d_13();
test_ushr_2d_2d_63();
@@ -1068,41 +1459,68 @@
test_sshr_2d_2d_13();
test_sshr_2d_2d_63();
#if 0
+ test_shl_2d_2d_1();
+ test_shl_2d_2d_13();
+ test_shl_2d_2d_63();
+
test_ushr_4s_4s_1();
test_ushr_4s_4s_13();
test_ushr_4s_4s_31();
test_sshr_4s_4s_1();
test_sshr_4s_4s_13();
test_sshr_4s_4s_31();
+#endif
+ test_shl_4s_4s_1();
+ test_shl_4s_4s_13();
+ test_shl_4s_4s_31();
+#if 0
test_ushr_2s_2s_1();
test_ushr_2s_2s_13();
test_ushr_2s_2s_31();
test_sshr_2s_2s_1();
test_sshr_2s_2s_13();
test_sshr_2s_2s_31();
+ test_shl_2s_2s_1();
+ test_shl_2s_2s_13();
+ test_shl_2s_2s_31();
+
test_ushr_8h_8h_1();
test_ushr_8h_8h_13();
test_ushr_8h_8h_15();
test_sshr_8h_8h_1();
test_sshr_8h_8h_13();
test_sshr_8h_8h_15();
+ test_shl_8h_8h_1();
+ test_shl_8h_8h_13();
+ test_shl_8h_8h_15();
+
test_ushr_4h_4h_1();
test_ushr_4h_4h_13();
test_ushr_4h_4h_15();
test_sshr_4h_4h_1();
test_sshr_4h_4h_13();
test_sshr_4h_4h_15();
+ test_shl_4h_4h_1();
+ test_shl_4h_4h_13();
+ test_shl_4h_4h_15();
+
test_ushr_16b_16b_1();
test_ushr_16b_16b_7();
test_sshr_16b_16b_1();
test_sshr_16b_16b_7();
+ test_shl_16b_16b_1();
+ test_shl_16b_16b_7();
+
test_ushr_8b_8b_1();
test_ushr_8b_8b_7();
test_sshr_8b_8b_1();
test_sshr_8b_8b_7();
+ test_shl_8b_8b_1();
+ test_shl_8b_8b_7();
#endif
+ printf("END: {USHR,SSHR,SHL} (vector, immediate) (many cases MISSING)\n\n");
- printf("{U,S}SHLL{,2} (MISSING h_b and s_h versions)\n");
+ printf("BEGIN: {U,S}SHLL{,2}\n");
test_ushll_2d_2s_0();
test_ushll_2d_2s_15();
test_ushll_2d_2s_31();
@@ -1115,19 +1533,53 @@
test_sshll2_2d_4s_0();
test_sshll2_2d_4s_15();
test_sshll2_2d_4s_31();
- printf("{U,S}SHLL{,2} (MISSING h_b and s_h versions)\n");
+ printf("END: {U,S}SHLL{,2} (MISSING h_b and s_h versions)\n\n");
+ printf("BEGIN: XTN{,2}\n");
test_xtn_2s_2d();
test_xtn2_4s_2d();
test_xtn_4h_4s();
test_xtn2_8h_4s();
- printf("XTN{,2} (MISSING b_h versions)\n");
+ printf("END: XTN{,2} (MISSING b_h versions)\n\n");
- printf("DUP (element, vector) MISSING\n");
- printf("DUP (general, vector) MISSING\n");
- printf("{S,U}MOV MISSING\n");
+ printf("DUP (element, vector) COMPLETELY MISSING\n\n");
+ printf("DUP (general, vector) COMPLETELY MISSING\n\n");
+
+ printf("BEGIN: {S,U}MOV\n");
+ test_umov_01();
+ test_umov_02();
+ test_umov_03();
+ test_umov_04();
+ test_umov_05();
+ test_umov_06();
+ test_umov_07();
+ test_umov_08();
+ test_smov_01();
+ test_smov_02();
+ test_smov_03();
+ test_smov_04();
+ test_smov_05();
+ test_smov_06();
+ test_smov_07();
+ test_smov_08();
+ test_smov_09();
+ test_smov_10();
+ printf("END: {S,U}MOV\n\n");
+
+ printf("BEGIN: INS (general)\n");
test_INS_general();
+ printf("END: INS (general)\n\n");
+
+ printf("BEGIN: NEG (vector)\n");
+ test_neg_2d_2d();
+ test_neg_4s_4s();
+ test_neg_2s_2s();
+ test_neg_8h_8h();
+ test_neg_4h_4h();
+ //test_neg_16b_16b();
+ //test_neg_8b_8b();
+ printf("END: NEG (vector) (MISSING 8b/16b)\n\n");
return 0;
}
Modified: trunk/none/tests/arm64/test_arm64_int.c
==============================================================================
--- trunk/none/tests/arm64/test_arm64_int.c (original)
+++ trunk/none/tests/arm64/test_arm64_int.c Sun Mar 2 12:48:34 2014
@@ -10289,6 +10289,26 @@
////////////////////////////////////////////////////////////////
+printf("REV16\n");
+
+TESTINST2("rev16 x11,x23", 0xfd79baaee550b488, x11,x23,0);
+TESTINST2("rev16 x11,x23", 0xe861540945421773, x11,x23,0);
+TESTINST2("rev16 x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0);
+
+TESTINST2("rev16 w11,w23", 0xfd79baaee550b488, x11,x23,0);
+TESTINST2("rev16 w11,w23", 0xe861540945421773, x11,x23,0);
+TESTINST2("rev16 w11,w23", 0x9a1140d0fd1dbf6c, x11,x23,0);
+
+
+////////////////////////////////////////////////////////////////
+printf("REV32\n");
+
+TESTINST2("rev32 x11,x23", 0xfd79baaee550b488, x11,x23,0);
+TESTINST2("rev32 x11,x23", 0xe861540945421773, x11,x23,0);
+TESTINST2("rev32 x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0);
+
+
+////////////////////////////////////////////////////////////////
printf("CLZ\n");
TESTINST2("clz x17, x22", 0xFFFFFFFFFFFFFFFFULL, x17, x22, 0);
|
|
From: <sv...@va...> - 2014-03-02 12:47:29
|
Author: sewardj
Date: Sun Mar 2 12:47:18 2014
New Revision: 2830
Log:
Implement REV16, REV32, FCVTN, SHL (vector, immediate), NEG (vector)
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Sun Mar 2 12:47:18 2014
@@ -1089,7 +1089,7 @@
Int off = offsetQRegLane(qregNo, laneTy, laneNo);
switch (laneTy) {
case Ity_F64: case Ity_I64:
- case Ity_I32:
+ case Ity_I32: case Ity_F32:
case Ity_I16:
case Ity_I8:
break;
@@ -1099,12 +1099,13 @@
stmt(IRStmt_Put(off, e));
}
-/* Get from the least significant lane of a Qreg. */
+/* Get from a specified lane of a Qreg. */
static IRExpr* getQRegLane ( UInt qregNo, UInt laneNo, IRType laneTy )
{
Int off = offsetQRegLane(qregNo, laneTy, laneNo);
switch (laneTy) {
- case Ity_I64: case Ity_I32:
+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8:
+ case Ity_F64:
break;
default:
vassert(0); // Other cases are ATC
@@ -1555,102 +1556,63 @@
/*--- Misc math helpers ---*/
/*------------------------------------------------------------*/
-/* Generates a 64-bit byte swap. */
-static IRTemp math_BYTESWAP64 ( IRTemp src )
+/* Generate IR for ((x & mask) >>u sh) | ((x << sh) & mask) */
+static IRTemp math_SWAPHELPER ( IRTemp x, ULong mask, Int sh )
{
- IRTemp m8 = newTemp(Ity_I64);
- IRTemp s8 = newTemp(Ity_I64);
- IRTemp m16 = newTemp(Ity_I64);
- IRTemp s16 = newTemp(Ity_I64);
- IRTemp m32 = newTemp(Ity_I64);
- IRTemp res = newTemp(Ity_I64);
- assign( m8, mkU64(0xFF00FF00FF00FF00ULL) );
- assign( s8,
+ IRTemp maskT = newTemp(Ity_I64);
+ IRTemp res = newTemp(Ity_I64);
+ vassert(sh >= 1 && sh <= 63);
+ assign(maskT, mkU64(mask));
+ assign( res,
binop(Iop_Or64,
binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(src),mkexpr(m8)),
- mkU8(8)),
+ binop(Iop_And64,mkexpr(x),mkexpr(maskT)),
+ mkU8(sh)),
binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(src),mkU8(8)),
- mkexpr(m8))
+ binop(Iop_Shl64,mkexpr(x),mkU8(sh)),
+ mkexpr(maskT))
)
);
+ return res;
+}
- assign( m16, mkU64(0xFFFF0000FFFF0000ULL) );
- assign( s16,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s8),mkexpr(m16)),
- mkU8(16)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s8),mkU8(16)),
- mkexpr(m16))
- )
- );
+/* Generates byte swaps within 32-bit lanes. */
+static IRTemp math_UINTSWAP64 ( IRTemp src )
+{
+ IRTemp res;
+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8);
+ res = math_SWAPHELPER(res, 0xFFFF0000FFFF0000ULL, 16);
+ return res;
+}
- assign( m32, mkU64(0xFFFFFFFF00000000ULL) );
- assign( res,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s16),mkexpr(m32)),
- mkU8(32)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s16),mkU8(32)),
- mkexpr(m32))
- )
- );
+/* Generates byte swaps within 16-bit lanes. */
+static IRTemp math_USHORTSWAP64 ( IRTemp src )
+{
+ IRTemp res;
+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8);
return res;
}
+/* Generates a 64-bit byte swap. */
+static IRTemp math_BYTESWAP64 ( IRTemp src )
+{
+ IRTemp res;
+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8);
+ res = math_SWAPHELPER(res, 0xFFFF0000FFFF0000ULL, 16);
+ res = math_SWAPHELPER(res, 0xFFFFFFFF00000000ULL, 32);
+ return res;
+}
/* Generates a 64-bit bit swap. */
static IRTemp math_BITSWAP64 ( IRTemp src )
{
- IRTemp m1 = newTemp(Ity_I64);
- IRTemp s1 = newTemp(Ity_I64);
- IRTemp m2 = newTemp(Ity_I64);
- IRTemp s2 = newTemp(Ity_I64);
- IRTemp m4 = newTemp(Ity_I64);
- IRTemp s4 = newTemp(Ity_I64);
- assign( m1, mkU64(0xAAAAAAAAAAAAAAAAULL) );
- assign( s1,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(src),mkexpr(m1)),
- mkU8(1)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(src),mkU8(1)),
- mkexpr(m1))
- )
- );
-
- assign( m2, mkU64(0xCCCCCCCCCCCCCCCCULL) );
- assign( s2,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s1),mkexpr(m2)),
- mkU8(2)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s1),mkU8(2)),
- mkexpr(m2))
- )
- );
-
- assign( m4, mkU64(0xF0F0F0F0F0F0F0F0ULL) );
- assign( s4,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s2),mkexpr(m4)),
- mkU8(4)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s2),mkU8(4)),
- mkexpr(m4))
- )
- );
- return math_BYTESWAP64(s4);
+ IRTemp res;
+ res = math_SWAPHELPER(src, 0xAAAAAAAAAAAAAAAAULL, 1);
+ res = math_SWAPHELPER(res, 0xCCCCCCCCCCCCCCCCULL, 2);
+ res = math_SWAPHELPER(res, 0xF0F0F0F0F0F0F0F0ULL, 4);
+ return math_BYTESWAP64(res);
}
-
/* Duplicates the bits at the bottom of the given word to fill the
whole word. src :: Ity_I64 is assumed to have zeroes everywhere
except for the bottom bits. */
@@ -2708,19 +2670,17 @@
/* -------------- REV/REV16/REV32/RBIT -------------- */
/* 31 30 28 20 15 11 9 4
- 1 10 11010110 00000 0000 11 n d (1) REV Xd, Xn
- 0 10 11010110 00000 0000 10 n d (2) REV Wd, Wn
+ 1 10 11010110 00000 0000 11 n d (1) REV Xd, Xn
+ 0 10 11010110 00000 0000 10 n d (2) REV Wd, Wn
- 1 10 11010110 00000 0000 00 n d (3) RBIT Xd, Xn
- 0 10 11010110 00000 0000 00 n d (4) RBIT Wd, Wn
+ 1 10 11010110 00000 0000 00 n d (3) RBIT Xd, Xn
+ 0 10 11010110 00000 0000 00 n d (4) RBIT Wd, Wn
1 10 11010110 00000 0000 01 n d (5) REV16 Xd, Xn
0 10 11010110 00000 0000 01 n d (6) REV16 Wd, Wn
1 10 11010110 00000 0000 10 n d (7) REV32 Xd, Xn
-
*/
- /* Only REV and RBIT are currently implemented. */
if (INSN(30,21) == BITS10(1,0,1,1,0,1,0,1,1,0)
&& INSN(20,12) == BITS9(0,0,0,0,0,0,0,0,0)) {
UInt b31 = INSN(31,31);
@@ -2734,23 +2694,41 @@
else if (b31 == 1 && opc == BITS2(0,1)) ix = 5;
else if (b31 == 0 && opc == BITS2(0,1)) ix = 6;
else if (b31 == 1 && opc == BITS2(1,0)) ix = 7;
- if (ix >= 1 && ix <= 4) {
- Bool is64 = ix == 1 || ix == 3;
- Bool isBIT = ix == 3 || ix == 4;
+ if (ix >= 1 && ix <= 7) {
+ Bool is64 = ix == 1 || ix == 3 || ix == 5 || ix == 7;
UInt nn = INSN(9,5);
UInt dd = INSN(4,0);
IRTemp src = newTemp(Ity_I64);
IRTemp dst = IRTemp_INVALID;
- if (is64) {
+ IRTemp (*math)(IRTemp) = NULL;
+ switch (ix) {
+ case 1: case 2: math = math_BYTESWAP64; break;
+ case 3: case 4: math = math_BITSWAP64; break;
+ case 5: case 6: math = math_USHORTSWAP64; break;
+ case 7: math = math_UINTSWAP64; break;
+ default: vassert(0);
+ }
+ const HChar* names[7]
+ = { "rev", "rev", "rbit", "rbit", "rev16", "rev16", "rev32" };
+ const HChar* nm = names[ix-1];
+ vassert(math);
+ if (ix == 6) {
+ /* This has to be special cased, since the logic below doesn't
+ handle it correctly. */
assign(src, getIReg64orZR(nn));
- dst = isBIT ? math_BITSWAP64(src) : math_BYTESWAP64(src);
+ dst = math(src);
+ putIReg64orZR(dd,
+ unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(dst))));
+ } else if (is64) {
+ assign(src, getIReg64orZR(nn));
+ dst = math(src);
putIReg64orZR(dd, mkexpr(dst));
} else {
assign(src, binop(Iop_Shl64, getIReg64orZR(nn), mkU8(32)));
- dst = isBIT ? math_BITSWAP64(src) : math_BYTESWAP64(src);
+ dst = math(src);
putIReg32orZR(dd, unop(Iop_64to32, mkexpr(dst)));
}
- DIP("%s %s, %s\n", isBIT ? "rbit" : "rev",
+ DIP("%s %s, %s\n", nm,
nameIRegOrZR(is64,dd), nameIRegOrZR(is64,nn));
return True;
}
@@ -5257,7 +5235,7 @@
Bool ok = getLaneInfo_Q_SZ(NULL, &tyF, NULL, &zeroHI, &ar,
(Bool)bitQ, (Bool)bitSZ);
if (ok) {
- vassert(tyF == Ity_F64 || tyF == Ity_I32);
+ vassert(tyF == Ity_F64 || tyF == Ity_F32);
IROp op = (tyF == Ity_F64) ? (isFNEG ? Iop_Neg64Fx2 : Iop_Abs64Fx2)
: (isFNEG ? Iop_Neg32Fx4 : Iop_Abs32Fx4);
IRTemp res = newTemp(Ity_V128);
@@ -5690,6 +5668,37 @@
}
}
+ /* -------------------- FCVTN -------------------- */
+ /* 31 28 23 20 15 9 4
+ 0q0 01110 0s1 00001 011010 n d FCVTN Vd, Vn
+ where case q:s of 00: 16Fx4(lo) <- 32Fx4
+ 01: 32Fx2(lo) <- 64Fx2
+ 10: 16Fx4(hi) <- 32Fx4
+ 11: 32Fx2(hi) <- 64Fx2
+ Only deals with the 32Fx2 <- 64Fx2 version (s==1)
+ */
+ if (INSN(31,31) == 0 && INSN(29,23) == BITS7(0,0,1,1,1,0,0)
+ && INSN(21,10) == BITS12(1,0,0,0,0,1,0,1,1,0,1,0)) {
+ UInt bQ = INSN(30,30);
+ UInt bS = INSN(22,22);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ if (bS == 1) {
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRExpr* srcLo = getQRegLane(nn, 0, Ity_F64);
+ IRExpr* srcHi = getQRegLane(nn, 1, Ity_F64);
+ putQRegLane(dd, 2 * bQ + 0, binop(Iop_F64toF32, mkexpr(rm), srcLo));
+ putQRegLane(dd, 2 * bQ + 1, binop(Iop_F64toF32, mkexpr(rm), srcHi));
+ if (bQ == 0) {
+ putQRegLane(dd, 1, mkU64(0));
+ }
+ DIP("fcvtn%s %s.%s, %s.2d\n", bQ ? "2" : "",
+ nameQReg128(dd), bQ ? "4s" : "2s", nameQReg128(nn));
+ return True;
+ }
+ /* else fall through */
+ }
+
/* ---------------- ADD/SUB (vector) ---------------- */
/* 31 28 23 21 20 15 9 4
0q0 01110 size 1 m 100001 n d ADD Vd.T, Vn.T, Vm.T
@@ -6104,47 +6113,67 @@
return True;
}
- /* ------------ {USHR,SSHR} (vector, immediate) ------------ */
+ /* ------------ {USHR,SSHR,SHL} (vector, immediate) ------------ */
/* 31 28 22 18 15 9 4
- 0q1 011110 immh immb 000001 n d USHR Vd.T, Vn.T, #shift
- 0q0 011110 immh immb 000001 n d SSHR Vd.T, Vn.T, #shift
+ 0q1 011110 immh immb 000001 n d USHR Vd.T, Vn.T, #shift (1)
+ 0q0 011110 immh immb 000001 n d SSHR Vd.T, Vn.T, #shift (2)
+ 0q0 011110 immh immb 010101 n d SHL Vd.T, Vn.T, #shift (3)
laneTy, shift = case immh:immb of
- 0001:xxx -> B, 8-xxx
- 001x:xxx -> H, 16-xxxx
- 01xx:xxx -> S, 32-xxxxx
- 1xxx:xxx -> D, 64-xxxxxx
+ 0001:xxx -> B, SHR:8-xxx, SHL:xxx
+ 001x:xxx -> H, SHR:16-xxxx SHL:xxxx
+ 01xx:xxx -> S, SHR:32-xxxxx SHL:xxxxx
+ 1xxx:xxx -> D, SHR:64-xxxxxx SHL:xxxxxx
other -> invalid
As usual the case laneTy==D && q==0 is not allowed.
*/
if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,1,0)
- && INSN(15,10) == BITS6(0,0,0,0,0,1)) {
- Bool isQ = INSN(30,30) == 1;
- Bool isU = INSN(29,29) == 1;
- UInt immh = INSN(22,19);
- UInt immb = INSN(18,16);
- UInt nn = INSN(9,5);
- UInt dd = INSN(4,0);
- const IROp opsSHRN[4]
- = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 };
- const IROp opsSARN[4]
- = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 };
- UInt szBlg2 = 0;
- UInt shift = 0;
- Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
- if (ok && szBlg2 < 4 && shift > 0 && shift < (8 << szBlg2)
- && !(szBlg2 == 3/*64bit*/ && !isQ)) {
- IROp op = isU ? opsSHRN[szBlg2] : opsSARN[szBlg2];
- IRExpr* src = getQReg128(nn);
- IRExpr* res = binop(op, src, mkU8(shift));
- putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
- HChar laneCh = "bhsd"[szBlg2];
- UInt nLanes = (isQ ? 128 : 64) / (8 << szBlg2);
- DIP("%s %s.%u%c, %s.%u%c, #%u\n", isU ? "ushr" : "sshr",
- nameQReg128(dd), nLanes, laneCh,
- nameQReg128(nn), nLanes, laneCh, shift);
- return True;
+ && INSN(10,10) == 1) {
+ UInt ix = 0;
+ /**/ if (INSN(29,29) == 1 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 1;
+ else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 2;
+ else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,1,0,1,0)) ix = 3;
+ if (ix > 0) {
+ Bool isQ = INSN(30,30) == 1;
+ UInt immh = INSN(22,19);
+ UInt immb = INSN(18,16);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ const IROp opsSHRN[4]
+ = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 };
+ const IROp opsSARN[4]
+ = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 };
+ const IROp opsSHLN[4]
+ = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 };
+ UInt szBlg2 = 0;
+ UInt shift = 0;
+ Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
+ if (ix == 3) {
+ /* The shift encoding has opposite sign for the leftwards
+ case. Adjust shift to compensate. */
+ shift = (8 << szBlg2) - shift;
+ }
+ if (ok && szBlg2 < 4 && shift > 0 && shift < (8 << szBlg2)
+ && !(szBlg2 == 3/*64bit*/ && !isQ)) {
+ IROp op = Iop_INVALID;
+ const HChar* nm = NULL;
+ switch (ix) {
+ case 1: op = opsSHRN[szBlg2]; nm = "ushr"; break;
+ case 2: op = opsSARN[szBlg2]; nm = "sshr"; break;
+ case 3: op = opsSHLN[szBlg2]; nm = "shl"; break;
+ default: vassert(0);
+ }
+ IRExpr* src = getQReg128(nn);
+ IRExpr* res = binop(op, src, mkU8(shift));
+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res));
+ HChar laneCh = "bhsd"[szBlg2];
+ UInt nLanes = (isQ ? 128 : 64) / (8 << szBlg2);
+ DIP("%s %s.%u%c, %s.%u%c, #%u\n", nm,
+ nameQReg128(dd), nLanes, laneCh,
+ nameQReg128(nn), nLanes, laneCh, shift);
+ return True;
+ }
+ /* else fall through */
}
- /* else fall through */
}
/* -------------------- {U,S}SHLL{,2} -------------------- */
@@ -6514,6 +6543,35 @@
/* else invalid; fall through */
}
+ /* -------------------- NEG (vector) -------------------- */
+ /* 31 28 23 21 16 9 4
+ 0q1 01110 sz 10000 0101110 n d NEG Vd, Vn
+ sz is laneSz, q:sz == 011 is disallowed, as usual
+ */
+ if (INSN(31,31) == 0 && INSN(29,24) == BITS6(1,0,1,1,1,0)
+ && INSN(21,10) == BITS12(1,0,0,0,0,0,1,0,1,1,1,0)) {
+ Bool isQ = INSN(30,30) == 1;
+ UInt szBlg2 = INSN(23,22);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ Bool zeroHI = False;
+ const HChar* arrSpec = "";
+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
+ if (ok) {
+ const IROp opSUB[4]
+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 };
+ IRTemp res = newTemp(Ity_V128);
+ vassert(szBlg2 < 4);
+ assign(res, binop(opSUB[szBlg2], mkV128(0x0000), getQReg128(nn)));
+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(res))
+ : mkexpr(res));
+ DIP("neg %s.%s, %s.%s\n",
+ nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec);
+ return True;
+ }
+ /* else fall through */
+ }
+
/* FIXME Temporary hacks to get through ld.so FIXME */
/* ------------------ movi vD.4s, #0x0 ------------------ */
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Sun Mar 2 12:47:18 2014
@@ -906,6 +906,7 @@
switch (op) {
case ARM64vecsh_USHR64x2: *nm = "ushr "; *ar = "2d"; return;
case ARM64vecsh_SSHR64x2: *nm = "sshr "; *ar = "2d"; return;
+ case ARM64vecsh_SHL32x4: *nm = "shl "; *ar = "4s"; return;
default: vpanic("showARM64VecShiftImmOp");
}
}
@@ -1617,6 +1618,8 @@
switch (op) {
case ARM64vecsh_USHR64x2: case ARM64vecsh_SSHR64x2:
maxSh = 63; break;
+ case ARM64vecsh_SHL32x4:
+ maxSh = 31; break;
default:
vassert(0);
}
@@ -3325,6 +3328,7 @@
#define X001111 BITS8(0,0, 0,0,1,1,1,1)
#define X010000 BITS8(0,0, 0,1,0,0,0,0)
#define X010001 BITS8(0,0, 0,1,0,0,0,1)
+#define X010101 BITS8(0,0, 0,1,0,1,0,1)
#define X010110 BITS8(0,0, 0,1,0,1,1,0)
#define X011001 BITS8(0,0, 0,1,1,0,0,1)
#define X011010 BITS8(0,0, 0,1,1,0,1,0)
@@ -3347,6 +3351,7 @@
#define X111110 BITS8(0,0, 1,1,1,1,1,0)
#define X111111 BITS8(0,0, 1,1,1,1,1,1)
+#define X0100000 BITS8(0, 0,1,0,0,0,0,0)
#define X1000000 BITS8(0, 1,0,0,0,0,0,0)
#define X00100000 BITS8(0,0,1,0,0,0,0,0)
@@ -5093,6 +5098,14 @@
4s | sh in 1..31 -> let xxxxx = 32-sh in 01xx:xxx
8h | sh in 1..15 -> let xxxx = 16-sh in 001x:xxx
16b | sh in 1..7 -> let xxx = 8-sh in 0001:xxx
+
+ 0q0 011110 immh immb 010101 n d SHL Vd.T, Vn.T, #sh
+ where immh:immb
+ = case T of
+ 2d | sh in 1..63 -> let xxxxxx = sh in 1xxx:xxx
+ 4s | sh in 1..31 -> let xxxxx = sh in 01xx:xxx
+ 8h | sh in 1..15 -> let xxxx = sh in 001x:xxx
+ 16b | sh in 1..7 -> let xxx = sh in 0001:xxx
*/
UInt vD = qregNo(i->ARM64in.VShiftImmV.dst);
UInt vN = qregNo(i->ARM64in.VShiftImmV.src);
@@ -5109,6 +5122,14 @@
goto done;
}
break;
+ case ARM64vecsh_SHL32x4:
+ if (sh >= 1 && sh <= 31) {
+ UInt xxxxx = sh;
+ *p++ = X_3_6_7_6_5_5(X010, X011110,
+ X0100000 | xxxxx, X010101, vN, vD);
+ goto done;
+ }
+ break;
default:
break;
}
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Sun Mar 2 12:47:18 2014
@@ -358,6 +358,7 @@
enum {
ARM64vecsh_USHR64x2=350,
ARM64vecsh_SSHR64x2,
+ ARM64vecsh_SHL32x4,
ARM64vecsh_INVALID
}
ARM64VecShiftOp;
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Sun Mar 2 12:47:18 2014
@@ -2253,7 +2253,7 @@
/* --------- GET --------- */
case Iex_Get: {
if (ty == Ity_I64
- && 0 == (e->Iex.Get.offset & 7) && e->Iex.Get.offset < 8192-8) {
+ && 0 == (e->Iex.Get.offset & 7) && e->Iex.Get.offset < (8<<12)-8) {
HReg dst = newVRegI(env);
ARM64AMode* am
= mk_baseblock_64bit_access_amode(e->Iex.Get.offset);
@@ -2261,13 +2261,29 @@
return dst;
}
if (ty == Ity_I32
- && 0 == (e->Iex.Get.offset & 3) && e->Iex.Get.offset < 4096-4) {
+ && 0 == (e->Iex.Get.offset & 3) && e->Iex.Get.offset < (4<<12)-4) {
HReg dst = newVRegI(env);
ARM64AMode* am
= mk_baseblock_32bit_access_amode(e->Iex.Get.offset);
addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am));
return dst;
}
+ if (ty == Ity_I16
+ && 0 == (e->Iex.Get.offset & 1) && e->Iex.Get.offset < (2<<12)-2) {
+ HReg dst = newVRegI(env);
+ ARM64AMode* am
+ = mk_baseblock_16bit_access_amode(e->Iex.Get.offset);
+ addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, am));
+ return dst;
+ }
+ if (ty == Ity_I8
+ /* && no alignment check */ && e->Iex.Get.offset < (1<<12)-1) {
+ HReg dst = newVRegI(env);
+ ARM64AMode* am
+ = mk_baseblock_8bit_access_amode(e->Iex.Get.offset);
+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am));
+ return dst;
+ }
break;
}
@@ -5409,7 +5425,8 @@
//ZZ case Iop_ShrN16x8:
//ZZ case Iop_ShrN32x4:
case Iop_ShrN64x2:
- case Iop_SarN64x2: {
+ case Iop_SarN64x2:
+ case Iop_ShlN32x4: {
IRExpr* argL = e->Iex.Binop.arg1;
IRExpr* argR = e->Iex.Binop.arg2;
if (argR->tag == Iex_Const && argR->Iex.Const.con->tag == Ico_U8) {
@@ -5421,6 +5438,8 @@
op = ARM64vecsh_USHR64x2; limit = 63; break;
case Iop_SarN64x2:
op = ARM64vecsh_SSHR64x2; limit = 63; break;
+ case Iop_ShlN32x4:
+ op = ARM64vecsh_SHL32x4; limit = 31; break;
default:
vassert(0);
}
|
|
From: Philippe W. <phi...@sk...> - 2014-03-02 05:43:54
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora (7.5.1-37.fc18) Assembler: GNU assembler version 2.23.51.0.1-7.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.8.8-202.fc18.ppc64p7 ppc64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on gcc110 ( Fedora release 18 (Spherical Cow), ppc64 ) Started at 2014-03-01 20:00:08 PST Ended at 2014-03-01 21:40:51 PST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 575 tests, 36 stderr failures, 7 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) none/tests/ppc32/jm-vmx (stdout) none/tests/ppc32/jm-vmx (stderr) none/tests/ppc32/test_isa_2_06_part2 (stdout) none/tests/ppc32/test_isa_2_06_part2 (stderr) none/tests/ppc64/jm-vmx (stdout) none/tests/ppc64/jm-vmx (stderr) none/tests/ppc64/test_isa_2_06_part2 (stdout) none/tests/ppc64/test_isa_2_06_part2 (stderr) helgrind/tests/annotate_rwlock (stderr) helgrind/tests/free_is_write (stderr) helgrind/tests/hg02_deadlock (stderr) helgrind/tests/hg03_inherit (stderr) helgrind/tests/hg04_race (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/locked_vs_unlocked1_fwd (stderr) helgrind/tests/locked_vs_unlocked1_rev (stderr) helgrind/tests/locked_vs_unlocked2 (stderr) helgrind/tests/locked_vs_unlocked3 (stderr) helgrind/tests/pth_barrier1 (stderr) helgrind/tests/pth_barrier2 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/pth_destroy_cond (stderr) helgrind/tests/rwlock_race (stderr) helgrind/tests/tc01_simple_race (stderr) helgrind/tests/tc05_simple_race (stderr) helgrind/tests/tc06_two_races (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) helgrind/tests/tc14_laog_dinphils (stderr) helgrind/tests/tc16_byterace (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc19_shadowmem (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc21_pthonce (stderr) helgrind/tests/tc22_exit_w_lock (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 1.6s ( 6.9x, -----) me: 3.0s (13.0x, -----) ca:18.1s (78.5x, -----) he: 1.7s ( 7.6x, -----) ca: 5.4s (23.7x, -----) dr: 1.7s ( 7.4x, -----) ma: 2.1s ( 9.3x, -----) bigcode1 valgrind-old:0.23s no: 1.6s ( 7.0x, -1.9%) me: 2.9s (12.4x, 4.4%) ca:17.9s (77.7x, 1.1%) he: 1.7s ( 7.6x, 0.0%) ca: 5.4s (23.7x, 0.0%) dr: 1.7s ( 7.2x, 2.4%) ma: 2.1s ( 9.3x, 0.0%) -- bigcode2 -- bigcode2 valgrind-new:0.23s no: 1.5s ( 6.7x, -----) me: 3.2s (13.8x, -----) ca:18.1s (78.8x, -----) he: 2.1s ( 9.1x, -----) ca: 5.4s (23.5x, -----) dr: 1.8s ( 8.0x, -----) ma: 2.1s ( 9.3x, -----) bigcode2 valgrind-old:0.23s no: 1.5s ( 6.7x, 0.0%) me: 3.0s (13.0x, 6.0%) ca:18.1s (78.9x, -0.1%) he: 2.1s ( 9.1x, 0.0%) ca: 5.5s (24.0x, -2.0%) dr: 1.8s ( 8.0x, 0.0%) ma: 2.1s ( 9.2x, 0.5%) -- bz2 -- bz2 valgrind-new:0.72s no: 4.6s ( 6.3x, -----) me:11.8s (16.3x, -----) ca:25.8s (35.8x, -----) he:14.7s (20.4x, -----) ca:24.3s (33.7x, -----) dr:20.2s (28.1x, -----) ma: 4.7s ( 6.5x, -----) bz2 valgrind-old:0.72s no: 4.6s ( 6.3x, 0.2%) me:11.9s (16.5x, -0.8%) ca:25.7s (35.8x, 0.1%) he:14.8s (20.5x, -0.8%) ca:24.5s (34.0x, -0.7%) dr:20.2s (28.1x, 0.0%) ma: 4.7s ( 6.5x, -0.4%) -- fbench -- fbench valgrind-new:0.34s no: 2.1s ( 6.3x, -----) me: 5.3s (15.5x, -----) ca: 8.4s (24.8x, -----) he: 5.2s (15.4x, -----) ca: 7.5s (22.1x, -----) dr: 4.9s (14.3x, -----) ma: 2.1s ( 6.3x, -----) fbench valgrind-old:0.34s no: 2.1s ( 6.2x, 0.5%) me: 5.2s (15.4x, 0.8%) ca: 8.5s (24.9x, -0.6%) he: 5.2s (15.4x, 0.4%) ca: 7.5s (22.1x, 0.0%) dr: 4.9s (14.3x, 0.0%) ma: 2.1s ( 6.3x, 0.0%) -- ffbench -- ffbench valgrind-new:0.45s no: 1.3s ( 2.9x, -----) me: 2.6s ( 5.8x, -----) ca: 2.5s ( 5.5x, -----) he: 7.1s (15.8x, -----) ca: 7.1s (15.7x, -----) dr: 4.9s (11.0x, -----) ma: 1.1s ( 2.4x, -----) ffbench valgrind-old:0.45s no: 1.3s ( 3.0x, -0.8%) me: 2.5s ( 5.6x, 3.1%) ca: 2.5s ( 5.5x, -0.4%) he: 7.1s (15.8x, -0.6%) ca: 7.3s (16.2x, -3.4%) dr: 5.0s (11.0x, -0.4%) ma: 1.1s ( 2.4x, 0.0%) -- heap -- heap valgrind-new:0.41s no: 2.4s ( 5.8x, -----) me: 9.8s (23.9x, -----) ca:13.1s (31.9x, -----) he:11.7s (28.6x, -----) ca:12.1s (29.4x, -----) dr: 8.1s (19.9x, -----) ma: 8.5s (20.8x, -----) heap valgrind-old:0.41s no: 2.4s ( 6.0x, -2.5%) me: 9.6s (23.5x, 1.8%) ca:13.1s (31.9x, 0.0%) he:11.7s (28.6x, 0.0%) ca:12.2s (29.6x, -0.7%) dr: 8.1s (19.9x, 0.0%) ma: 8.6s (20.9x, -0.6%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.42s no: 2.6s ( 6.1x, -----) me:13.7s (32.6x, -----) ca:14.0s (33.3x, -----) he:13.3s (31.6x, -----) ca:13.2s (31.3x, -----) dr: 9.2s (21.8x, -----) ma: 8.6s (20.5x, -----) heap_pdb4 valgrind-old:0.42s no: 2.6s ( 6.3x, -2.7%) me:13.8s (32.7x, -0.5%) ca:14.0s (33.4x, -0.4%) he:13.0s (31.0x, 2.0%) ca:13.1s (31.3x, 0.2%) dr: 9.3s (22.2x, -1.9%) ma: 8.7s (20.6x, -0.8%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.5s (17.3x, -----) me: 2.2s (72.3x, -----) ca: 1.9s (62.0x, -----) he: 1.8s (60.0x, -----) ca: 1.9s (62.0x, -----) dr: 1.6s (52.3x, -----) ma: 1.6s (51.7x, -----) many-loss-records valgrind-old:0.03s no: 0.5s (17.7x, -1.9%) me: 2.2s (72.3x, 0.0%) ca: 1.9s (62.3x, -0.5%) he: 1.8s (60.3x, -0.6%) ca: 1.9s (62.3x, -0.5%) dr: 1.6s (52.3x, 0.0%) ma: 1.6s (51.7x, 0.0%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.8s (10.7x, -----) me: 3.4s (49.0x, -----) ca: 4.6s (66.3x, -----) he: 4.8s (68.7x, -----) ca: 2.9s (41.4x, -----) dr: 2.3s (33.3x, -----) ma: 2.3s (32.4x, -----) many-xpts valgrind-old:0.07s no: 0.7s (10.6x, 1.3%) me: 3.4s (48.9x, 0.3%) ca: 4.7s (66.7x, -0.6%) he: 4.8s (68.9x, -0.2%) ca: 2.9s (41.3x, 0.3%) dr: 2.3s (33.4x, -0.4%) ma: 2.2s (32.1x, 0.9%) -- sarp -- sarp valgrind-new:0.02s no: 0.4s (20.0x, -----) me: 3.2s (159.0x, -----) ca: 2.9s (146.0x, -----) he:11.2s (557.5x, -----) ca: 1.7s (84.5x, -----) dr: 1.1s (54.0x, -----) ma: 0.4s (20.5x, -----) sarp valgrind-old:0.02s no: 0.4s (20.0x, 0.0%) me: 3.2s (158.0x, 0.6%) ca: 2.9s (146.5x, -0.3%) he:11.2s (558.0x, -0.1%) ca: 1.8s (91.5x, -8.3%) dr: 1.1s (54.0x, 0.0%) ma: 0.4s (21.0x, -2.4%) -- tinycc -- tinycc valgrind-new:0.27s no: 3.0s (11.0x, -----) me:14.1s (52.3x, -----) ca:17.1s (63.5x, -----) he:18.9s (70.0x, -----) ca:15.6s (57.8x, -----) dr:12.4s (45.8x, -----) ma: 3.8s (14.1x, -----) tinycc valgrind-old:0.27s no: 3.0s (11.0x, -0.0%) me:14.1s (52.3x, 0.1%) ca:17.1s (63.5x, 0.1%) he:18.9s (70.1x, -0.1%) ca:15.6s (57.7x, 0.2%) dr:12.3s (45.7x, 0.2%) ma: 3.8s (14.1x, 0.0%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 53m6.473s user 52m1.745s sys 0m18.579s |
|
From: Christian B. <bor...@de...> - 2014-03-02 05:22:15
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.8-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-03-02 03:45:01 CET Ended at 2014-03-02 06:22:04 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 642 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == helgrind/tests/pth_cond_destroy_busy (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.22s no: 4.3s (19.6x, -----) me: 7.0s (31.6x, -----) ca:26.4s (120.2x, -----) he: 5.1s (23.0x, -----) ca: 9.1s (41.5x, -----) dr: 5.5s (25.0x, -----) ma: 4.7s (21.4x, -----) bigcode1 valgrind-old:0.22s no: 4.3s (19.6x, 0.2%) me: 6.9s (31.5x, 0.3%) ca:26.4s (120.1x, 0.1%) he: 5.1s (23.0x, 0.0%) ca: 9.2s (41.6x, -0.2%) dr: 5.5s (25.0x, -0.2%) ma: 4.7s (21.4x, 0.0%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.2s (30.2x, -----) me:13.9s (57.9x, -----) ca:40.8s (169.8x, -----) he:10.1s (41.9x, -----) ca:14.2s (59.2x, -----) dr: 9.7s (40.3x, -----) ma: 8.1s (33.8x, -----) bigcode2 valgrind-old:0.24s no: 7.2s (30.2x, 0.1%) me:13.8s (57.7x, 0.3%) ca:41.0s (170.7x, -0.5%) he:10.1s (41.9x, 0.0%) ca:14.2s (59.3x, -0.2%) dr: 9.7s (40.4x, -0.2%) ma: 8.1s (33.8x, 0.0%) -- bz2 -- bz2 valgrind-new:0.70s no: 5.0s ( 7.1x, -----) me:12.9s (18.5x, -----) ca:30.7s (43.8x, -----) he:19.8s (28.2x, -----) ca:34.3s (49.1x, -----) dr:31.3s (44.7x, -----) ma: 3.6s ( 5.2x, -----) bz2 valgrind-old:0.70s no: 5.0s ( 7.1x, 0.0%) me:12.9s (18.4x, 0.3%) ca:30.6s (43.7x, 0.2%) he:19.8s (28.2x, 0.0%) ca:34.4s (49.1x, -0.1%) dr:31.3s (44.8x, -0.2%) ma: 3.6s ( 5.2x, 0.0%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 3.9x, -----) me: 4.2s (10.3x, -----) ca: 9.3s (22.7x, -----) he: 6.2s (15.1x, -----) ca: 7.2s (17.6x, -----) dr: 5.7s (14.0x, -----) ma: 1.7s ( 4.1x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, 0.6%) me: 4.2s (10.3x, 0.2%) ca: 9.3s (22.7x, 0.3%) he: 6.2s (15.1x, -0.3%) ca: 7.2s (17.6x, 0.0%) dr: 5.7s (14.0x, -0.2%) ma: 1.7s ( 4.1x, -0.6%) -- ffbench -- ffbench valgrind-new:0.20s no: 1.0s ( 5.2x, -----) me: 3.0s (15.2x, -----) ca: 3.0s (15.1x, -----) he:43.5s (217.7x, -----) ca: 9.6s (48.1x, -----) dr: 6.9s (34.4x, -----) ma: 0.9s ( 4.7x, -----) ffbench valgrind-old:0.20s no: 1.0s ( 5.2x, 0.0%) me: 3.0s (15.2x, 0.0%) ca: 3.0s (15.0x, 0.3%) he:43.5s (217.7x, 0.0%) ca: 9.6s (48.2x, -0.1%) dr: 6.9s (34.4x, 0.0%) ma: 1.0s ( 4.8x, -1.1%) -- heap -- heap valgrind-new:0.23s no: 1.8s ( 7.7x, -----) me: 8.9s (38.6x, -----) ca:13.3s (57.7x, -----) he:12.8s (55.8x, -----) ca:11.3s (49.2x, -----) dr: 7.6s (33.1x, -----) ma: 7.9s (34.3x, -----) heap valgrind-old:0.23s no: 1.8s ( 7.8x, -0.6%) me: 8.9s (38.6x, 0.0%) ca:13.3s (57.8x, -0.2%) he:12.8s (55.6x, 0.3%) ca:11.2s (48.7x, 1.0%) dr: 7.6s (33.2x, -0.4%) ma: 7.9s (34.4x, -0.1%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.0s ( 8.9x, -----) me:13.0s (59.0x, -----) ca:14.4s (65.4x, -----) he:14.3s (65.0x, -----) ca:12.4s (56.4x, -----) dr: 8.8s (39.9x, -----) ma: 8.0s (36.5x, -----) heap_pdb4 valgrind-old:0.22s no: 2.0s ( 8.9x, 0.0%) me:13.0s (59.0x, 0.2%) ca:14.4s (65.7x, -0.5%) he:14.4s (65.3x, -0.4%) ca:12.4s (56.3x, 0.2%) dr: 8.8s (40.0x, -0.2%) ma: 8.0s (36.5x, -0.2%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (23.5x, -----) me: 2.1s (104.5x, -----) ca: 1.9s (97.0x, -----) he: 2.2s (108.0x, -----) ca: 1.9s (95.5x, -----) dr: 1.7s (86.0x, -----) ma: 1.6s (82.5x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (23.5x, 0.0%) me: 2.1s (104.5x, 0.0%) ca: 1.9s (97.0x, 0.0%) he: 2.2s (108.0x, 0.0%) ca: 1.9s (95.5x, 0.0%) dr: 1.7s (86.0x, 0.0%) ma: 1.6s (82.5x, 0.0%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.6s ( 8.7x, -----) me: 3.2s (45.9x, -----) ca:372.2s (5317.4x, -----) he: 6.6s (94.6x, -----) ca: 2.8s (39.9x, -----) dr: 2.5s (35.4x, -----) ma: 2.6s (37.1x, -----) many-xpts valgrind-old:0.07s no: 0.6s ( 8.6x, 1.6%) me: 3.2s (45.9x, 0.0%) ca:378.5s (5407.7x, -1.7%) he: 6.6s (94.1x, 0.5%) ca: 2.8s (39.9x, 0.0%) dr: 2.5s (35.4x, 0.0%) ma: 2.6s (37.1x, 0.0%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (19.0x, -----) me: 3.6s (120.3x, -----) ca: 3.2s (105.7x, -----) he:17.1s (570.0x, -----) ca: 2.0s (68.3x, -----) dr: 1.3s (44.7x, -----) ma: 0.5s (16.3x, -----) sarp valgrind-old:0.03s no: 0.6s (19.0x, 0.0%) me: 3.6s (120.3x, 0.0%) ca: 3.2s (106.0x, -0.3%) he:16.8s (560.7x, 1.6%) ca: 2.0s (68.3x, 0.0%) dr: 1.4s (45.0x, -0.7%) ma: 0.5s (16.3x, 0.0%) -- tinycc -- tinycc valgrind-new:0.22s no: 2.7s (12.2x, -----) me:14.9s (67.8x, -----) ca:29.9s (136.0x, -----) he:27.7s (126.0x, -----) ca:21.3s (96.9x, -----) dr:21.8s (99.1x, -----) ma: 4.0s (18.3x, -----) tinycc valgrind-old:0.22s no: 2.7s (12.3x, -1.1%) me:15.0s (68.0x, -0.3%) ca:30.1s (136.6x, -0.4%) he:27.8s (126.4x, -0.3%) ca:21.3s (96.8x, 0.0%) dr:21.8s (99.0x, 0.2%) ma: 4.0s (18.1x, 1.0%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 111m46.554s user 110m53.651s sys 0m46.853s |
|
From: Tom H. <to...@co...> - 2014-03-02 04:28:19
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-03-02 03:51:20 GMT Ended at 2014-03-02 04:28:01 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 645 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-03-02 04:07:23
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] GDB: GNU gdb (GDB) SUSE (7.5.1-2.1.1) Assembler: GNU assembler (GNU Binutils; openSUSE 12.3) 2.23.1 C library: GNU C Library (GNU libc) stable release version 2.17 (git c758a6861537) uname -mrs: Linux 3.7.9-1.1-desktop x86_64 Vendor version: Welcome to openSUSE 12.3 "Dartmouth" Beta 1 - Kernel %r (%t). Nightly build on ultra ( gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] Linux 3.7.9-1.1-desktop x86_64 ) Started at 2014-03-01 21:30:01 CST Ended at 2014-03-01 22:07:13 CST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 666 tests, 0 stderr failures, 0 stdout failures, 1 stderrB failure, 0 stdoutB failures, 0 post failures == gdbserver_tests/mssnapshot (stderrB) ================================================= ./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff ================================================= --- mssnapshot.stderrB.exp 2014-03-01 21:52:10.089923827 -0600 +++ mssnapshot.stderrB.out 2014-03-01 21:56:21.735850382 -0600 @@ -1,5 +1,11 @@ relaying data between gdb and process .... +Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2 +Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158" vgdb-error value changed from 0 to 999999 +Missing separate debuginfo for /lib64/libpthread.so.0 +Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef" +Missing separate debuginfo for /lib64/libc.so.6 +Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7" general valgrind monitor commands: help [debug] : monitor command help. With debug: + debugging commands v.wait [<ms>] : sleep <ms> (default 0) then continue ================================================= ./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff ================================================= --- mssnapshot.stderrB.exp 2014-03-01 21:33:12.964912315 -0600 +++ mssnapshot.stderrB.out 2014-03-01 21:37:29.147702574 -0600 @@ -1,5 +1,11 @@ relaying data between gdb and process .... +Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2 +Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158" vgdb-error value changed from 0 to 999999 +Missing separate debuginfo for /lib64/libpthread.so.0 +Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef" +Missing separate debuginfo for /lib64/libc.so.6 +Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7" general valgrind monitor commands: help [debug] : monitor command help. With debug: + debugging commands v.wait [<ms>] : sleep <ms> (default 0) then continue |
|
From: Tom H. <to...@co...> - 2014-03-02 03:51:47
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-03-02 03:12:53 GMT Ended at 2014-03-02 03:51:37 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 673 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == |
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From: Tom H. <to...@co...> - 2014-03-02 03:51:21
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-03-02 03:02:11 GMT Ended at 2014-03-02 03:51:08 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 673 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == |
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From: Tom H. <to...@co...> - 2014-03-02 03:31:13
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-03-02 02:51:12 GMT Ended at 2014-03-02 03:30:57 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 673 tests, 4 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Rich C. <rc...@wi...> - 2014-03-02 03:26:39
|
valgrind revision: 13847
VEX revision: 2829
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-03-01 19:22:01 CST
Ended at 2014-03-01 21:26:26 CST
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 588 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/dw4 (stderr)
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-03-01 20:23:40.666946084 -0600
+++ hackedbz2.stderr.out 2014-03-01 21:25:09.184734561 -0600
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/dw4.stderr.diff
=================================================
--- dw4.stderr.exp 2014-03-01 20:25:05.703932552 -0600
+++ dw4.stderr.out 2014-03-01 20:43:22.265653165 -0600
@@ -1,3 +1,11 @@
+
+parse_type_DIE: confused by:
+ <1><492>: DW_TAG_structure_type
+ DW_AT_signature : 8 byte signature: 9b d0 55 13 bb 1e e9 37
+
+WARNING: Serious error when reading debug info
+When reading debug info from /usr/local/src/valgrind/nightly/valgrind-new/memcheck/tests/dw4:
+parse_type_DIE: confused by the above DIE
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:49)
@@ -8,12 +16,10 @@
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:51)
- Location 0x........ is 0 bytes inside S2[0].i,
- a global variable declared at dw4.c:42
+ Address 0x........ is 4 bytes inside data symbol "S2"
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:52)
- Location 0x........ is 0 bytes inside local.i,
- declared at dw4.c:46, in frame #1 of thread 1
+ Address 0x........ is on thread 1's stack
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-03-01 20:25:05.803933712 -0600
+++ err_disable3.stderr.out 2014-03-01 20:43:28.924730413 -0600
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-03-01 20:25:03.515907170 -0600
+++ err_disable4.stderr.out 2014-03-01 20:43:33.128779182 -0600
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-03-01 20:25:03.528907321 -0600
+++ threadname.stderr.out 2014-03-01 20:49:19.512797393 -0600
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-03-01 20:25:02.291892971 -0600
+++ threadname_xml.stderr.out 2014-03-01 20:49:21.539820908 -0600
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-03-01 19:22:25.924317406 -0600
+++ hackedbz2.stderr.out 2014-03-01 20:22:17.780984520 -0600
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/dw4.stderr.diff
=================================================
--- dw4.stderr.exp 2014-03-01 19:22:30.851374562 -0600
+++ dw4.stderr.out 2014-03-01 19:40:33.374932326 -0600
@@ -1,3 +1,11 @@
+
+parse_type_DIE: confused by:
+ <1><492>: DW_TAG_structure_type
+ DW_AT_signature : 8 byte signature: 9b d0 55 13 bb 1e e9 37
+
+WARNING: Serious error when reading debug info
+When reading debug info from /usr/local/src/valgrind/nightly/valgrind-old/memcheck/tests/dw4:
+parse_type_DIE: confused by the above DIE
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:49)
@@ -8,12 +16,10 @@
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:51)
- Location 0x........ is 0 bytes inside S2[0].i,
- a global variable declared at dw4.c:42
+ Address 0x........ is 4 bytes inside data symbol "S2"
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:52)
- Location 0x........ is 0 bytes inside local.i,
- declared at dw4.c:46, in frame #1 of thread 1
+ Address 0x........ is on thread 1's stack
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-03-01 19:22:30.392369238 -0600
+++ err_disable3.stderr.out 2014-03-01 19:40:40.053009794 -0600
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-03-01 19:22:31.246379144 -0600
+++ err_disable4.stderr.out 2014-03-01 19:40:44.190057786 -0600
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-03-01 19:22:31.279379527 -0600
+++ threadname.stderr.out 2014-03-01 19:46:30.952080383 -0600
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-03-01 19:22:30.423369597 -0600
+++ threadname_xml.stderr.out 2014-03-01 19:46:32.998104117 -0600
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
|
|
From: Tom H. <to...@co...> - 2014-03-02 03:19:15
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-03-02 02:41:30 GMT Ended at 2014-03-02 03:19:01 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 673 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Tom H. <to...@co...> - 2014-03-02 03:11:18
|
valgrind revision: 13847 VEX revision: 2829 C compiler: gcc (GCC) 4.8.2 20131212 (Red Hat 4.8.2-7) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.13.3-201.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-03-02 02:31:55 GMT Ended at 2014-03-02 03:11:05 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 673 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/dw4 (stderr) exp-sgcheck/tests/hackedbz2 (stderr) |