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From: <sv...@va...> - 2014-03-15 12:47:39
|
Author: bart
Date: Sat Mar 15 12:47:28 2014
New Revision: 13874
Log:
strmem intercepts: Add mempcpy() intercepts for ld-linux on x86
Modified:
trunk/shared/vg_replace_strmem.c
Modified: trunk/shared/vg_replace_strmem.c
==============================================================================
--- trunk/shared/vg_replace_strmem.c (original)
+++ trunk/shared/vg_replace_strmem.c Sat Mar 15 12:47:28 2014
@@ -1343,6 +1343,8 @@
#if defined(VGO_linux)
GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy)
GLIBC25_MEMPCPY(VG_Z_LD_SO_1, mempcpy) /* ld.so.1 */
+ GLIBC25_MEMPCPY(VG_Z_LD_LINUX_SO_3, mempcpy) /* ld-linux.so.3 */
+ GLIBC25_MEMPCPY(VG_Z_LD_LINUX_X86_64_SO_2, mempcpy) /* ld-linux-x86-64.so.2 */
#elif defined(VGO_darwin)
//GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy)
|
|
From: <sv...@va...> - 2014-03-15 11:41:51
|
Author: sewardj
Date: Sat Mar 15 11:41:39 2014
New Revision: 2840
Log:
Un-break the arm32 compilation pipeline following the change of
arity of Iop_Mul32Fx4, Iop_Sub32Fx4, Iop_Add32Fx4 in r2809.
Modified:
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
trunk/priv/host_arm_isel.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sat Mar 15 11:41:39 2014
@@ -2875,6 +2875,31 @@
return True;
}
+/* Generate specific vector FP binary ops, possibly with a fake
+ rounding mode as required by the primop. */
+static
+IRExpr* binop_w_fake_RM ( IROp op, IRExpr* argL, IRExpr* argR )
+{
+ switch (op) {
+ case Iop_Add32Fx4:
+ case Iop_Sub32Fx4:
+ case Iop_Mul32Fx4:
+ return triop(op, get_FAKE_roundingmode(), argL, argR );
+ case Iop_Add32x4: case Iop_Add16x8:
+ case Iop_Sub32x4: case Iop_Sub16x8:
+ case Iop_Mul32x4: case Iop_Mul16x8:
+ case Iop_Mul32x2: case Iop_Mul16x4:
+ case Iop_Add32Fx2:
+ case Iop_Sub32Fx2:
+ case Iop_Mul32Fx2:
+ case Iop_PwAdd32Fx2:
+ return binop(op, argL, argR);
+ default:
+ ppIROp(op);
+ vassert(0);
+ }
+}
+
/* VTBL, VTBX */
static
Bool dis_neon_vtb ( UInt theInstr, IRTemp condT )
@@ -4601,7 +4626,8 @@
/* VABD */
if (Q) {
assign(res, unop(Iop_Abs32Fx4,
- binop(Iop_Sub32Fx4,
+ triop(Iop_Sub32Fx4,
+ get_FAKE_roundingmode(),
mkexpr(arg_n),
mkexpr(arg_m))));
} else {
@@ -4616,7 +4642,7 @@
break;
}
}
- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m)));
} else {
if (U == 0) {
/* VMLA, VMLS */
@@ -4641,9 +4667,11 @@
default: vassert(0);
}
}
- assign(res, binop(op2,
- Q ? getQReg(dreg) : getDRegI64(dreg),
- binop(op, mkexpr(arg_n), mkexpr(arg_m))));
+ assign(res, binop_w_fake_RM(
+ op2,
+ Q ? getQReg(dreg) : getDRegI64(dreg),
+ binop_w_fake_RM(op, mkexpr(arg_n),
+ mkexpr(arg_m))));
DIP("vml%c.f32 %c%u, %c%u, %c%u\n",
P ? 's' : 'a', Q ? 'q' : 'd',
@@ -4654,7 +4682,7 @@
if ((C >> 1) != 0)
return False;
op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2 ;
- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m)));
DIP("vmul.f32 %c%u, %c%u, %c%u\n",
Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
@@ -5318,10 +5346,10 @@
}
}
op2 = INSN(10,10) ? sub : add;
- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m)));
if (Q)
- putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)),
- condT);
+ putQReg(dreg, binop_w_fake_RM(op2, getQReg(dreg), mkexpr(res)),
+ condT);
else
putDRegI64(dreg, binop(op2, getDRegI64(dreg), mkexpr(res)),
condT);
@@ -5548,7 +5576,7 @@
vassert(0);
}
}
- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m)));
if (Q)
putQReg(dreg, mkexpr(res), condT);
else
Modified: trunk/priv/host_arm_defs.c
==============================================================================
--- trunk/priv/host_arm_defs.c (original)
+++ trunk/priv/host_arm_defs.c Sat Mar 15 11:41:39 2014
@@ -790,6 +790,7 @@
case ARMneon_VTBL: return "vtbl";
case ARMneon_VRECPS: return "vrecps";
case ARMneon_VRSQRTS: return "vrecps";
+ case ARMneon_INVALID: return "??invalid??";
/* ... */
default: vpanic("showARMNeonBinOp");
}
Modified: trunk/priv/host_arm_defs.h
==============================================================================
--- trunk/priv/host_arm_defs.h (original)
+++ trunk/priv/host_arm_defs.h Sat Mar 15 11:41:39 2014
@@ -468,6 +468,7 @@
ARMneon_VQDMULL,
ARMneon_VRECPS,
ARMneon_VRSQRTS,
+ ARMneon_INVALID
/* ... */
}
ARMNeonBinOp;
Modified: trunk/priv/host_arm_isel.c
==============================================================================
--- trunk/priv/host_arm_isel.c (original)
+++ trunk/priv/host_arm_isel.c Sat Mar 15 11:41:39 2014
@@ -4254,26 +4254,11 @@
return res;
}
case Iop_Abs32Fx4: {
- DECLARE_PATTERN(p_vabd_32fx4);
- DEFINE_PATTERN(p_vabd_32fx4,
- unop(Iop_Abs32Fx4,
- binop(Iop_Sub32Fx4,
- bind(0),
- bind(1))));
- if (matchIRExpr(&mi, p_vabd_32fx4, e)) {
- HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, mi.bindee[0]);
- HReg argR = iselNeonExpr(env, mi.bindee[1]);
- addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
- res, argL, argR, 0, True));
- return res;
- } else {
- HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
- addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
- res, argL, 0, True));
- return res;
- }
+ HReg res = newVRegV(env);
+ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+ addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
+ res, argL, 0, True));
+ return res;
}
case Iop_Rsqrte32Fx4: {
HReg res = newVRegV(env);
@@ -4457,15 +4442,6 @@
res, argL, argR, size, True));
return res;
}
- case Iop_Add32Fx4: {
- HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
- UInt size = 0;
- addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
- res, argL, argR, size, True));
- return res;
- }
case Iop_Recps32Fx4: {
HReg res = newVRegV(env);
HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
@@ -4632,15 +4608,6 @@
res, argL, argR, size, True));
return res;
}
- case Iop_Sub32Fx4: {
- HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
- UInt size = 0;
- addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
- res, argL, argR, size, True));
- return res;
- }
case Iop_QSub8Ux16:
case Iop_QSub16Ux8:
case Iop_QSub32Ux4:
@@ -5083,15 +5050,6 @@
res, argL, argR, size, True));
return res;
}
- case Iop_Mul32Fx4: {
- HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
- UInt size = 0;
- addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
- res, argL, argR, size, True));
- return res;
- }
case Iop_Mull8Ux8:
case Iop_Mull16Ux4:
case Iop_Mull32Ux2: {
@@ -5352,6 +5310,23 @@
res, argL, argR, imm4, True));
return res;
}
+ case Iop_Mul32Fx4:
+ case Iop_Sub32Fx4:
+ case Iop_Add32Fx4: {
+ HReg res = newVRegV(env);
+ HReg argL = iselNeonExpr(env, triop->arg2);
+ HReg argR = iselNeonExpr(env, triop->arg3);
+ UInt size = 0;
+ ARMNeonBinOp op = ARMneon_INVALID;
+ switch (triop->op) {
+ case Iop_Mul32Fx4: op = ARMneon_VMULFP; break;
+ case Iop_Sub32Fx4: op = ARMneon_VSUBFP; break;
+ case Iop_Add32Fx4: op = ARMneon_VADDFP; break;
+ default: vassert(0);
+ }
+ addInstr(env, ARMInstr_NBinary(op, res, argL, argR, size, True));
+ return res;
+ }
default:
break;
}
|
|
From: <sv...@va...> - 2014-03-15 08:35:27
|
Author: sewardj
Date: Sat Mar 15 08:35:15 2014
New Revision: 13873
Log:
Update for ARM fe fixes for 332037 and n-i-bz LDRD .. [PC, ]
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Sat Mar 15 08:35:15 2014
@@ -66,10 +66,12 @@
331830 ppc64: WARNING: unhandled syscall: 96/97
331839 drd/tests/sem_open specifies invalid semaphore name
331847 outcome of drd/tests/thread_name is nondeterministic
+332037 Valgrind cannot handle Thumb "add pc, reg"
332055 drd asserts on platforms with VG_STACK_REDZONE_SZB == 0 and
consistency checks enabled
n-i-bz Fix KVM_CREATE_IRQCHIP ioctl handling
n-i-bz s390x: Fix memory corruption for multithreaded applications
+n-i-bz vex arm->IR: allow PC as basereg in some LDRD cases
Release 3.9.0 (31 October 2013)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
From: <sv...@va...> - 2014-03-15 08:33:24
|
Author: sewardj
Date: Sat Mar 15 08:33:06 2014
New Revision: 2839
Log:
LDRD/STRD reg+/-#imm8: allow PC as the base register in the
case "ldrd Rt, Rt2, [PC, #+/-imm8]". n-i-bz.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sat Mar 15 08:33:06 2014
@@ -20401,7 +20401,7 @@
/* -------------- LDRD/STRD reg+/-#imm8 -------------- */
/* Doubleword loads and stores of the form:
- ldrd/strd Rt, Rt2, [Rn, #-imm8] or
+ ldrd/strd Rt, Rt2, [Rn, #+/-imm8] or
ldrd/strd Rt, Rt2, [Rn], #+/-imm8 or
ldrd/strd Rt, Rt2, [Rn, #+/-imm8]!
*/
@@ -20419,8 +20419,11 @@
if (bP == 0 && bW == 0) valid = False;
if (bW == 1 && (rN == rT || rN == rT2)) valid = False;
if (isBadRegT(rT) || isBadRegT(rT2)) valid = False;
- if (rN == 15) valid = False;
if (bL == 1 && rT == rT2) valid = False;
+ /* It's OK to use PC as the base register only in the
+ following case: ldrd Rt, Rt2, [PC, #+/-imm8] */
+ if (rN == 15 && (bL == 0/*store*/
+ || bW == 1/*wb*/)) valid = False;
if (valid) {
IRTemp preAddr = newTemp(Ity_I32);
|
|
From: <sv...@va...> - 2014-03-15 08:14:19
|
Author: sewardj
Date: Sat Mar 15 08:14:06 2014
New Revision: 2838
Log:
Correctly handle add(hi) when the destination register is the PC.
Fixes #332037.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sat Mar 15 08:14:06 2014
@@ -18203,9 +18203,9 @@
condT = IRTemp_INVALID;
// now uncond
/* non-interworking branch */
- irsb->next = binop(Iop_Or32, mkexpr(res), mkU32(1));
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, binop(Iop_Or32, mkexpr(res), mkU32(1)));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
}
DIP("add(hi) r%u, r%u\n", rD, rM);
goto decode_success;
|