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From: Carl E. L. <ce...@li...> - 2014-02-19 20:34:30
|
IBM will be supporting both big endian and little endian on power. I am
working on porting Valgrind to run under little endian. I am getting a
number of errors as follows that do not occur when run on big endian
Valgrind:
Conditional jump or move depends on uninitialised value(s)
Use of uninitialised value of size 8
I suspect that there is still an issue with the setting and/or checking
of the Vbits in memcheck that determine if the values are initialized or
not.
In file memchec/mc_machine.c there is a comment before function
get_otrack_shadow_offset_wrk() about the function being endian dependent
"This function is dependent on the host's endianness, hence we
assert that the use case is supported. "
I am not seeing where the endian dependency is and specifically how I
should change the code to go from PPC64 big endian to PPC little endian.
Hope someone can help identify where the endian dependency is and how to
fix it for power. I am still trying to figure out what all this code is
trying to do. Thanks.
Carl Love
|
|
From: Lionel C. <lio...@gm...> - 2014-02-19 18:42:41
|
On 24 May 2012 04:33, Lionel Cons <lio...@go...> wrote: > On Thu, Sep 8, 2011 at 10:57 PM, Petr Pavlu <se...@da...> wrote: >> Hello, >> >> I would like to inform the list that I started working on a port >> of Valgrind to Solaris OS. The port aims at x86 architecture and >> recent Solaris versions (i.e. SunOS 5.11 kernel). Code lives >> at [1] but it currently doesn't do much. I'm sending this email >> to make sure nobody already works on it. >> >> [1] https://bitbucket.org/setupji/valgrind-solaris > > Petr, what's the current status of valgrind on solaris? Is both 32bit > and 64bit x86 supported? Are you going to support SPARC64? Are there any major updates since May 2012? Are you planning to support the (open-)solaris fork "Illumos" [http://www.illumos.org]? Lionel |
|
From: <sv...@va...> - 2014-02-19 17:43:12
|
Author: sewardj
Date: Wed Feb 19 17:42:59 2014
New Revision: 2822
Log:
Implement unchainXDirect_ARM64.
Modified:
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/main_main.c
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Wed Feb 19 17:42:59 2014
@@ -6264,6 +6264,7 @@
vassert(is_imm64_to_iregNo_EXACTLY4(
p, /*x*/9, Ptr_to_ULong(disp_cp_chain_me_EXPECTED)));
vassert(p[4] == 0xD63F0120);
+
/* And what we want to change it to is:
movw x9, place_to_jump_to[15:0]
movk x9, place_to_jump_to[31:15], lsl 16
@@ -6276,7 +6277,6 @@
The replacement has the same length as the original.
*/
-
(void)imm64_to_iregNo_EXACTLY4(
p, /*x*/9, Ptr_to_ULong(place_to_jump_to));
p[4] = 0xD61F0120;
@@ -6286,67 +6286,47 @@
}
-//ZZ /* NB: what goes on here has to be very closely coordinated with the
-//ZZ emitInstr case for XDirect, above. */
-//ZZ VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
-//ZZ void* place_to_jump_to_EXPECTED,
-//ZZ void* disp_cp_chain_me )
-//ZZ {
-//ZZ /* What we're expecting to see is:
-//ZZ (general case)
-//ZZ movw r12, lo16(place_to_jump_to_EXPECTED)
-//ZZ movt r12, lo16(place_to_jump_to_EXPECTED)
-//ZZ bx r12
-//ZZ viz
-//ZZ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
-//ZZ E1 2F FF 1C
-//ZZ ---OR---
-//ZZ in the case where the displacement falls within 26 bits
-//ZZ b disp24; undef; undef
-//ZZ viz
-//ZZ EA <3 bytes == disp24>
-//ZZ FF 00 00 00
-//ZZ FF 00 00 00
-//ZZ */
-//ZZ UInt* p = (UInt*)place_to_unchain;
-//ZZ vassert(0 == (3 & (HWord)p));
-//ZZ
-//ZZ Bool valid = False;
-//ZZ if (is_imm32_to_iregNo_EXACTLY2(
-//ZZ p, /*r*/12, (UInt)Ptr_to_ULong(place_to_jump_to_EXPECTED))
-//ZZ && p[2] == 0xE12FFF1C) {
-//ZZ valid = True; /* it's the long form */
-//ZZ if (0)
-//ZZ vex_printf("QQQ unchainXDirect_ARM: found long form\n");
-//ZZ } else
-//ZZ if ((p[0] >> 24) == 0xEA && p[1] == 0xFF000000 && p[2] == 0xFF000000) {
-//ZZ /* It's the short form. Check the displacement is right. */
-//ZZ Int simm24 = p[0] & 0x00FFFFFF;
-//ZZ simm24 <<= 8; simm24 >>= 8;
-//ZZ if ((UChar*)p + (simm24 << 2) + 8 == (UChar*)place_to_jump_to_EXPECTED) {
-//ZZ valid = True;
-//ZZ if (0)
-//ZZ vex_printf("QQQ unchainXDirect_ARM: found short form\n");
-//ZZ }
-//ZZ }
-//ZZ vassert(valid);
-//ZZ
-//ZZ /* And what we want to change it to is:
-//ZZ movw r12, lo16(disp_cp_chain_me)
-//ZZ movt r12, hi16(disp_cp_chain_me)
-//ZZ blx r12
-//ZZ viz
-//ZZ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
-//ZZ E1 2F FF 3C
-//ZZ */
-//ZZ (void)imm32_to_iregNo_EXACTLY2(
-//ZZ p, /*r*/12, (UInt)Ptr_to_ULong(disp_cp_chain_me));
-//ZZ p[2] = 0xE12FFF3C;
-//ZZ VexInvalRange vir = {(HWord)p, 12};
-//ZZ return vir;
-//ZZ }
-//ZZ
-//ZZ
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me )
+{
+ /* What we're expecting to see is:
+ movw x9, place_to_jump_to_EXPECTED[15:0]
+ movk x9, place_to_jump_to_EXPECTED[31:15], lsl 16
+ movk x9, place_to_jump_to_EXPECTED[47:32], lsl 32
+ movk x9, place_to_jump_to_EXPECTED[63:48], lsl 48
+ br x9
+ viz
+ <16 bytes generated by imm64_to_iregNo_EXACTLY4>
+ D6 1F 01 20
+ */
+ UInt* p = (UInt*)place_to_unchain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(is_imm64_to_iregNo_EXACTLY4(
+ p, /*x*/9, Ptr_to_ULong(place_to_jump_to_EXPECTED)));
+ vassert(p[4] == 0xD61F0120);
+
+ /* And what we want to change it to is:
+ movw x9, disp_cp_chain_me_to[15:0]
+ movk x9, disp_cp_chain_me_to[31:15], lsl 16
+ movk x9, disp_cp_chain_me_to[47:32], lsl 32
+ movk x9, disp_cp_chain_me_to[63:48], lsl 48
+ blr x9
+ viz
+ <16 bytes generated by imm64_to_iregNo_EXACTLY4>
+ D6 3F 01 20
+ */
+ (void)imm64_to_iregNo_EXACTLY4(
+ p, /*x*/9, Ptr_to_ULong(disp_cp_chain_me));
+ p[4] = 0xD63F0120;
+
+ VexInvalRange vir = {(HWord)p, 20};
+ return vir;
+}
+
+
//ZZ /* Patch the counter address into a profile inc point, as previously
//ZZ created by the ARMin_ProfInc case for emit_ARMInstr. */
//ZZ VexInvalRange patchProfInc_ARM ( void* place_to_patch,
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Wed Feb 19 17:42:59 2014
@@ -1116,10 +1116,10 @@
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to );
-//ZZ extern VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
-//ZZ void* place_to_jump_to_EXPECTED,
-//ZZ void* disp_cp_chain_me );
-//ZZ
+extern VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me );
+
//ZZ /* Patch the counter location into an existing ProfInc point. */
//ZZ extern VexInvalRange patchProfInc_ARM ( void* place_to_patch,
//ZZ ULong* location_of_counter );
Modified: trunk/priv/main_main.c
==============================================================================
--- trunk/priv/main_main.c (original)
+++ trunk/priv/main_main.c Wed Feb 19 17:42:59 2014
@@ -1048,6 +1048,8 @@
unchainXDirect = unchainXDirect_AMD64; break;
case VexArchARM:
unchainXDirect = unchainXDirect_ARM; break;
+ case VexArchARM64:
+ unchainXDirect = unchainXDirect_ARM64; break;
case VexArchS390X:
unchainXDirect = unchainXDirect_S390; break;
case VexArchPPC32:
|
|
From: <sv...@va...> - 2014-02-19 17:00:12
|
Author: petarj
Date: Wed Feb 19 16:59:57 2014
New Revision: 13819
Log:
Removing fixed issue #326444 from the bug list
Issue #326444 has just been marked as fixed.
Modified:
trunk/docs/internals/3_9_BUGSTATUS.txt
Modified: trunk/docs/internals/3_9_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_9_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_9_BUGSTATUS.txt Wed Feb 19 16:59:57 2014
@@ -18,7 +18,6 @@
325874 Crash KCachegrind while load big file
326026 Iop names for count leading zeros/sign bits incorrectly imply a "signedness" in incoming lanes
326436 False positive in libstdc++ std::list::push_back
-326444 Cavium MIPS Octeon Specific Load Indexed Instructions
326469 unhandled instruction bytes: 0x66 0xF 0x3A 0x63 0xC1 0xE 0x89 0xC8
326487 child of debugged process exits without becoming zombie
326623 A false positive conflict report in a field assignment in a constructor
|
|
From: Florian K. <fl...@ei...> - 2014-02-19 16:38:28
|
On 02/19/2014 12:11 PM, Maran Pakkirisamy wrote: > The test case fails from VEX r2818. Also the failure is not happening > always. Sometimes the testcase passes. > If I revert the changes in trunk/pub/libvex_guest_s390x.h, the testcase > passes all the time. Reverting r2818 is not exactly what we want as the problem is s390x specific. Can you add this assert somewhere vassert(sizeof(VexGuestS390XState) == 432); and see whether it fires? 432 is the expected size of the guest state but there is some trickery with a [0] array at the end of the guest state. This *should* work according to my reading of the docs but who knows. Florian |
|
From: Maran P. <ma...@li...> - 2014-02-19 16:25:51
|
On 02/19/2014 01:28 PM, Bart Van Assche wrote: > On 02/19/14 04:19, Maran Pakkirisamy wrote: > > > -ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) > +valgrind: m_threadstate.c:95 (vgPlain_get_ThreadState): Assertion > 'VG_(threads)[tid].tid == tid' failed. >> + at 0x........: report_and_quit (m_libcassert.c:?) >> + by 0x........: vgPlain_assert_fail (m_libcassert.c:?) >> + by 0x........: vgPlain_get_ThreadState (m_threadstate.c:?) >> + by 0x........: vgSysWrap_s390x_linux_sys_clone_before > (syswrap-s390x-linux.c:217) >> + by 0x........: vgPlain_client_syscall (syswrap-main.c:1585) >> + by 0x........: handle_syscall (scheduler.c:?) > Hello Maran, > > Can you have a closer look at this ? This failure occurs on s390 only. > There might be an issue with thread handling in the core s390 Valgrind code. > Hi Bart, The test case fails from VEX r2818. Also the failure is not happening always. Sometimes the testcase passes. If I revert the changes in trunk/pub/libvex_guest_s390x.h, the testcase passes all the time. I am not sure if the alignment of guest state is not consistent at all the places and it causes the issue. --Maran |
|
From: <sv...@va...> - 2014-02-19 13:41:26
|
Author: florian
Date: Wed Feb 19 13:41:14 2014
New Revision: 13818
Log:
Remove those bugs that are already reported in NEWS as being
fixed and have a FIXED status in Bugzilla.
Modified:
trunk/docs/internals/3_9_BUGSTATUS.txt
Modified: trunk/docs/internals/3_9_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_9_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_9_BUGSTATUS.txt Wed Feb 19 13:41:14 2014
@@ -3,7 +3,6 @@
For bugs reported before this time, see 3_8_BUGSTATUS.txt
-324894 Phase 3 support for IBM Power ISA 2.07
325110 Add test-cases for Power ISA 2.06 insns: divdo/divdo. and divduo/divduo.
325124 [MIPSEL] Compilation error
325222 eight bad if statements ?
@@ -13,17 +12,13 @@
325477 Phase 4 support for IBM Power ISA 2.07
325538 cavim octeon mips64 ï¼valgrind reported "dumping core" and "Assertion 'sizeof(*regs) == sizeof(prs->pr_reg)' failed.
325628 Phase 5 support for IBM Power ISA 2.07
-325714 Empty vgcore but RLIMIT_CORE is big enough (too big)
325751 Missing the two privileged Power PC Transactional Memory Instructions
325816 Phase 6 support for IBM Power ISA 2.07
325856 sgcheck generates internal Valgrind error on IBM Power
325874 Crash KCachegrind while load big file
326026 Iop names for count leading zeros/sign bits incorrectly imply a "signedness" in incoming lanes
-326091 False positive in libstdc++ std::string::_S_construct (gcc 4.7.2)
-326113 valgrind libvex hwcaps error on AMD64
326436 False positive in libstdc++ std::list::push_back
326444 Cavium MIPS Octeon Specific Load Indexed Instructions
-326462 Refactor vgdb module to isolate ptrace stuff into separate module
326469 unhandled instruction bytes: 0x66 0xF 0x3A 0x63 0xC1 0xE 0x89 0xC8
326487 child of debugged process exits without becoming zombie
326623 A false positive conflict report in a field assignment in a constructor
@@ -34,13 +29,10 @@
326839 Don't see a writing into a none allocated memory
326921 coregrind fails to compile m_trampoline.S with MIPS/Linux port of Valgrind
326955 64 bit false positive move depends on uninitialised value wcscpy
-326983 insn_basic test might crash because of setting and not clearing DF flag
327138 valgrind.h __VALGRIND_MINOR__ says 8, in 3.9.0 tarball
327151 valgrind appears to stop compiling when it enters the drd directory
327155 Valgrind compilation hang on MIPS
327223 Support for Cavium MIPS Octeon Atomic and Count Instructions
-327238 assertion failure in Callgrind: bbcc.c:585 (vgCallgrind_setup_bbcc): Assertion 'passed <= last_bb->cjmp_count' failed
-327284 s390x VEX miscompilation of -march=z10 binary
327285 vex amd64->IR: unhandled instruction bytes: 0x8F 0xEA 0xF8 0x10 0xCE 0x3 0x1D 0x0
327427 ifunc wrapper crashes when symbols are discarded because of false mmap overlaps
327548 false positive while destroying mutex
@@ -48,36 +40,29 @@
327639 vex amd64->IR pcmpestri SSE4.2 instruction is unsupported 0x34
327665 out of memory error
327745 valgrind 3.9.0 build fails on Mac OS X 10.6.8
-327837 dwz compressed alternate .debug_info and debug_str not read correctly.
327859 Support for android devices
327881 False Positive Warning on std::atomic_bool
-327916 DW_TAG_typedef may have no name
327943 s390x missing index/strchr suppression for ld.so (bad backtrace?)
327945 valgrind_3.9.0 failed to compile in ppc 32
328011 3.9.0 segfaults running any program, on any valgrind tool
328081 embedded gdbserver and non-stop mode
328089 unhandled instruction bytes: 0xF0 0xF 0xC0 0x10
-328100 XABORT not implemented
328147 vex mips->IR: unhandled instruction bytes: 0x0 0x0 0x0 0xE
-328205 Implement additional Xen hypercalls
328357 vex amd64->IR: unhandled instruction bytes: 0x8F 0xEA 0xF8 0x10 0xEF 0x3 0x5 0x0
328423 Unrecognised instructions: _fips_armv7_tick and _armv7_tick
328441 valgrind_3.9.0 failed to compile in mips32 âError: illegal operands `cfc1 $t0,$31'â
328454 add support Backtraces with ARM unwind tables (EXIDX)
-328455 s390x: valgrind is gettting SIGILL after emitting wrong register pair for ldxbr
328468 unwind x86/amd64 gcc <= 4.4 compiled code does not unwind properly at "ret" instruction
328490 drd reports false positive for concurrent __atomic_base access
328549 Valgrind crashes on Android 4.4 / x86 on most programs
328559 Some back trace generation (from mmap function) problem on ARM
328563 make track-fds support xml output
-328711 valgrind.1 manpage "memcheck options" section is badly generated
328721 MSVC 2008 compiler warns about while(0) in warning level 4
328730 Unimplemented system call #531 in FreeBSD: SYS_posix_fadvise
328747 Valgrind memcheck exits with SIGTRAP on PPC
328878 vex amd64->IR pcmpestri SSE4.2 instruction is unsupported 0x14
329104 kcachegrind crashs when on loading some of my cachegrind traces (SIGFPE).
329245 unhandled instruction bytes: 0x48 0xF 0x5A 0x7 0x48 0xF 0x5A 0x4F
-329612 Incorrect handling of AT_BASE for image execution
329619 leak-check gets assertion failure when nesting VALGRIND_MALLOCLIKE_BLOCK
329694 clang warns about using uninitialized variable
329726 Mozilla
@@ -94,8 +79,6 @@
330319 unhandled instruction bytes: 0xF 0x1 0xD5 0x31 0xC0 0xC3 0x48 0x8D
330321 Serious error when reading debug info - DW_AT_signature 9b d0 55 13 bb 1e e9 37
330349 Endless loop happen when using lackey with --trace-mem=yes on ARM
-330459 --track-fds=yes doesn't track eventfds
-330469 Add clock_adjtime syscall support
330590 Missing support for multiple VEX CMP instruction Opcodes (Causes SIGILL)
330594 Missing sysalls on PowerPC / uClibc
330617 ppc false positive conditional jump depends on uninitialised value
|
|
From: <sv...@va...> - 2014-02-19 11:57:34
|
Author: dejanj
Date: Wed Feb 19 11:57:22 2014
New Revision: 13817
Log:
mips32: Support for 64bit FPU on MIPS32 platforms.
Tests for 64bit FPU instructions on MIPS32 platforms.
Some mips instructions can cause SIGILL (Illegal instruction),
so we need to add SIGILL signal and a proper handler for that signal.
Added:
trunk/none/tests/mips32/round_fpu64.c
trunk/none/tests/mips32/round_fpu64.stderr.exp
trunk/none/tests/mips32/round_fpu64.stdout.exp
trunk/none/tests/mips32/round_fpu64.stdout.exp-fpu32
trunk/none/tests/mips32/round_fpu64.vgtest
Modified:
trunk/NEWS
trunk/coregrind/m_machine.c
trunk/coregrind/m_scheduler/scheduler.c
trunk/none/tests/mips32/ (props changed)
trunk/none/tests/mips32/Makefile.am
trunk/none/tests/mips32/MoveIns.c
trunk/none/tests/mips32/round.c
trunk/none/tests/mips32/round.stdout.exp
trunk/none/tests/mips32/test_fcsr.c
trunk/none/tests/mips32/vfp.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Feb 19 11:57:22 2014
@@ -5,6 +5,7 @@
* ================== PLATFORM CHANGES =================
* Support for Android on MIPS32.
+* Support for 64bit FPU on MIPS32 platforms.
* ==================== TOOL CHANGES ====================
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Wed Feb 19 11:57:22 2014
@@ -1459,6 +1459,8 @@
#elif defined(VGA_mips32)
{
+ /* Define the position of F64 bit in FIR register. */
+# define FP64 22
va = VexArchMIPS32;
UInt model = VG_(get_machine_model)();
if (model == -1)
@@ -1521,6 +1523,16 @@
}
}
+ /* Check if CPU has FPU and 32 dbl. prec. FP registers */
+ int FIR = 0;
+ __asm__ __volatile__(
+ "cfc1 %0, $0" "\n\t"
+ : "=r" (FIR)
+ );
+ if (FIR & (1 << FP64)) {
+ vai.hwcaps |= VEX_PRID_CPU_32FPR;
+ }
+
VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
Modified: trunk/coregrind/m_scheduler/scheduler.c
==============================================================================
--- trunk/coregrind/m_scheduler/scheduler.c (original)
+++ trunk/coregrind/m_scheduler/scheduler.c Wed Feb 19 11:57:22 2014
@@ -200,6 +200,7 @@
switch (event) {
case VEX_TRC_JMP_TINVAL: return "TINVAL";
case VEX_TRC_JMP_NOREDIR: return "NOREDIR";
+ case VEX_TRC_JMP_SIGILL: return "SIGILL";
case VEX_TRC_JMP_SIGTRAP: return "SIGTRAP";
case VEX_TRC_JMP_SIGSEGV: return "SIGSEGV";
case VEX_TRC_JMP_SIGBUS: return "SIGBUS";
@@ -1434,6 +1435,10 @@
break;
}
+ case VEX_TRC_JMP_SIGILL:
+ VG_(synth_sigill)(tid, VG_(get_IP)(tid));
+ break;
+
case VEX_TRC_JMP_SIGTRAP:
VG_(synth_sigtrap)(tid);
break;
Modified: trunk/none/tests/mips32/Makefile.am
==============================================================================
--- trunk/none/tests/mips32/Makefile.am (original)
+++ trunk/none/tests/mips32/Makefile.am Wed Feb 19 11:57:22 2014
@@ -31,7 +31,9 @@
unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
- test_math.stdout.exp test_math.stderr.exp test_math.vgtest
+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
+ round_fpu64.stderr.exp round_fpu64.vgtest
check_PROGRAMS = \
allexec \
@@ -51,7 +53,8 @@
mips32_dspr2 \
unaligned_load_store \
test_fcsr \
- test_math
+ test_math \
+ round_fpu64
AM_CFLAGS += @FLAG_M32@
AM_CXXFLAGS += @FLAG_M32@
Modified: trunk/none/tests/mips32/MoveIns.c
==============================================================================
--- trunk/none/tests/mips32/MoveIns.c (original)
+++ trunk/none/tests/mips32/MoveIns.c Wed Feb 19 11:57:22 2014
@@ -181,6 +181,32 @@
}
// movf.d fd, fs
+#if (__mips_fpr==64)
+#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
+{ \
+ double out; \
+ int out1; \
+ int out2; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 %3, $f2\n\t" \
+ "move $t0, %4\n\t" \
+ "ldc1 $f4, 8($t0)\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $f4\n\t" \
+ "mfhc1 %2, $f4\n\t" \
+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \
+ : "r" (cc), "r" (mem) \
+ : "t0", "t1", "cc", "memory" \
+ ); \
+ printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
+ instruction, out1, out2, cc); \
+}
+#else
#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
{ \
double out; \
@@ -206,6 +232,7 @@
printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
instruction, out1, out2, cc); \
}
+#endif
// movn.s fd, fs, rt
#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
Modified: trunk/none/tests/mips32/round.c
==============================================================================
--- trunk/none/tests/mips32/round.c (original)
+++ trunk/none/tests/mips32/round.c Wed Feb 19 11:57:22 2014
@@ -132,31 +132,19 @@
{
switch(mode) {
case TO_NEAREST:
- __asm__ volatile("cfc1 $t0, $31\n\t"
- "srl $t0, 2\n\t"
- "sll $t0, 2\n\t"
- "ctc1 $t0, $31\n\t");
+ __asm__ volatile("ctc1 $zero, $31" "\n\t");
break;
case TO_ZERO:
- __asm__ volatile("cfc1 $t0, $31\n\t"
- "srl $t0, 2\n\t"
- "sll $t0, 2\n\t"
- "addiu $t0, 1\n\t"
- "ctc1 $t0, $31\n\t");
+ __asm__ volatile("li $t0, 0x1" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
break;
case TO_PLUS_INFINITY:
- __asm__ volatile("cfc1 $t0, $31\n\t"
- "srl $t0, 2\n\t"
- "sll $t0, 2\n\t"
- "addiu $t0, 2\n\t"
- "ctc1 $t0, $31\n\t");
+ __asm__ volatile("li $t0, 0x2" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
break;
case TO_MINUS_INFINITY:
- __asm__ volatile("cfc1 $t0, $31\n\t"
- "srl $t0, 2\n\t"
- "sll $t0, 2\n\t"
- "addiu $t0, 3\n\t"
- "ctc1 $t0, $31\n\t");
+ __asm__ volatile("li $t0, 0x3" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
break;
}
}
Modified: trunk/none/tests/mips32/round.stdout.exp
==============================================================================
--- trunk/none/tests/mips32/round.stdout.exp (original)
+++ trunk/none/tests/mips32/round.stdout.exp Wed Feb 19 11:57:22 2014
@@ -4,19 +4,19 @@
ceil.w.s 457 456.250000
fcsr: 0x1004
ceil.w.s 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s 1385 1384.500000
fcsr: 0x1004
ceil.w.s -7 -7.250000
fcsr: 0x1004
ceil.w.s 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s -5786 -5786.250000
fcsr: 0x1004
ceil.w.s 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s 1 0.015625
fcsr: 0x1004
ceil.w.s 1 0.031250
@@ -26,45 +26,45 @@
ceil.w.s -45786 -45786.500000
fcsr: 0x1004
ceil.w.s 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s 35 34.031250
fcsr: 0x1004
ceil.w.s 45787 45786.750000
fcsr: 0x1004
ceil.w.s 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s -45667 -45667.250000
fcsr: 0x1004
ceil.w.s -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s -347856 -347856.500000
fcsr: 0x1004
ceil.w.s 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.s -1 -1.250000
fcsr: 0x1004
ceil.w.s 24 23.062500
fcsr: 0x1004
ceil.w.d 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d 457 456.250000
fcsr: 0x1004
ceil.w.d 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d 1385 1384.500000
fcsr: 0x1004
ceil.w.d -7 -7.250000
fcsr: 0x1004
ceil.w.d 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d -5786 -5786.250000
fcsr: 0x1004
ceil.w.d 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d 1 0.015625
fcsr: 0x1004
ceil.w.d 1 0.031250
@@ -74,45 +74,45 @@
ceil.w.d -45786 -45786.500000
fcsr: 0x1004
ceil.w.d 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d 35 34.031250
fcsr: 0x1004
ceil.w.d 45787 45786.750000
fcsr: 0x1004
ceil.w.d 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d -45667 -45667.250000
fcsr: 0x1004
ceil.w.d -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d -347856 -347856.500000
fcsr: 0x1004
ceil.w.d 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
ceil.w.d -1 -1.250000
fcsr: 0x1004
ceil.w.d 24 23.062500
fcsr: 0x1004
floor.w.s 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s 456 456.250000
fcsr: 0x1004
floor.w.s 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s 1384 1384.500000
fcsr: 0x1004
floor.w.s -8 -7.250000
fcsr: 0x1004
floor.w.s 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s -5787 -5786.250000
fcsr: 0x1004
floor.w.s 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s 0 0.015625
fcsr: 0x1004
floor.w.s 0 0.031250
@@ -122,45 +122,45 @@
floor.w.s -45787 -45786.500000
fcsr: 0x1004
floor.w.s 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s 34 34.031250
fcsr: 0x1004
floor.w.s 45786 45786.750000
fcsr: 0x1004
floor.w.s 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s -45668 -45667.250000
fcsr: 0x1004
floor.w.s -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s -347857 -347856.500000
fcsr: 0x1004
floor.w.s 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.s -2 -1.250000
fcsr: 0x1004
floor.w.s 23 23.062500
fcsr: 0x1004
floor.w.d 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d 456 456.250000
fcsr: 0x1004
floor.w.d 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d 1384 1384.500000
fcsr: 0x1004
floor.w.d -8 -7.250000
fcsr: 0x1004
floor.w.d 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d -5787 -5786.250000
fcsr: 0x1004
floor.w.d 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d 0 0.015625
fcsr: 0x1004
floor.w.d 0 0.031250
@@ -170,45 +170,45 @@
floor.w.d -45787 -45786.500000
fcsr: 0x1004
floor.w.d 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d 34 34.031250
fcsr: 0x1004
floor.w.d 45786 45786.750000
fcsr: 0x1004
floor.w.d 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d -45668 -45667.250000
fcsr: 0x1004
floor.w.d -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d -347857 -347856.500000
fcsr: 0x1004
floor.w.d 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
floor.w.d -2 -1.250000
fcsr: 0x1004
floor.w.d 23 23.062500
fcsr: 0x1004
round.w.s 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s 456 456.250000
fcsr: 0x1004
round.w.s 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s 1384 1384.500000
fcsr: 0x1004
round.w.s -7 -7.250000
fcsr: 0x1004
round.w.s 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s -5786 -5786.250000
fcsr: 0x1004
round.w.s 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s 0 0.015625
fcsr: 0x1004
round.w.s 0 0.031250
@@ -218,45 +218,45 @@
round.w.s -45786 -45786.500000
fcsr: 0x1004
round.w.s 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s 34 34.031250
fcsr: 0x1004
round.w.s 45787 45786.750000
fcsr: 0x1004
round.w.s 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s -45667 -45667.250000
fcsr: 0x1004
round.w.s -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s -347856 -347856.500000
fcsr: 0x1004
round.w.s 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.s -1 -1.250000
fcsr: 0x1004
round.w.s 23 23.062500
fcsr: 0x1004
round.w.d 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d 456 456.250000
fcsr: 0x1004
round.w.d 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d 1384 1384.500000
fcsr: 0x1004
round.w.d -7 -7.250000
fcsr: 0x1004
round.w.d 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d -5786 -5786.250000
fcsr: 0x1004
round.w.d 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d 0 0.015625
fcsr: 0x1004
round.w.d 0 0.031250
@@ -266,45 +266,45 @@
round.w.d -45786 -45786.500000
fcsr: 0x1004
round.w.d 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d 34 34.031250
fcsr: 0x1004
round.w.d 45787 45786.750000
fcsr: 0x1004
round.w.d 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d -45667 -45667.250000
fcsr: 0x1004
round.w.d -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d -347856 -347856.500000
fcsr: 0x1004
round.w.d 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
round.w.d -1 -1.250000
fcsr: 0x1004
round.w.d 23 23.062500
fcsr: 0x1004
trunc.w.s 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s 456 456.250000
fcsr: 0x1004
trunc.w.s 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s 1384 1384.500000
fcsr: 0x1004
trunc.w.s -7 -7.250000
fcsr: 0x1004
trunc.w.s 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s -5786 -5786.250000
fcsr: 0x1004
trunc.w.s 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s 0 0.015625
fcsr: 0x1004
trunc.w.s 0 0.031250
@@ -314,45 +314,45 @@
trunc.w.s -45786 -45786.500000
fcsr: 0x1004
trunc.w.s 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s 34 34.031250
fcsr: 0x1004
trunc.w.s 45786 45786.750000
fcsr: 0x1004
trunc.w.s 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s -45667 -45667.250000
fcsr: 0x1004
trunc.w.s -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s -347856 -347856.500000
fcsr: 0x1004
trunc.w.s 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.s -1 -1.250000
fcsr: 0x1004
trunc.w.s 23 23.062500
fcsr: 0x1004
trunc.w.d 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d 456 456.250000
fcsr: 0x1004
trunc.w.d 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d 1384 1384.500000
fcsr: 0x1004
trunc.w.d -7 -7.250000
fcsr: 0x1004
trunc.w.d 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d -5786 -5786.250000
fcsr: 0x1004
trunc.w.d 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d 0 0.015625
fcsr: 0x1004
trunc.w.d 0 0.031250
@@ -362,23 +362,23 @@
trunc.w.d -45786 -45786.500000
fcsr: 0x1004
trunc.w.d 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d 34 34.031250
fcsr: 0x1004
trunc.w.d 45786 45786.750000
fcsr: 0x1004
trunc.w.d 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d -45667 -45667.250000
fcsr: 0x1004
trunc.w.d -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d -347856 -347856.500000
fcsr: 0x1004
trunc.w.d 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
trunc.w.d -1 -1.250000
fcsr: 0x1004
trunc.w.d 23 23.062500
@@ -386,807 +386,807 @@
-------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode --------------------------
roundig mode: near
cvt.d.s 0.000000 0.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 456.250000 456.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 3.000000 3.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -1.000000 -1.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 1384.500000 1384.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -7.250000 -7.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 1000000000.000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -5786.250000 -5786.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 1752.000000 1752.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 0.015625 0.015625
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 0.031250 0.031250
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -248562.750000 -248562.750000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -45786.500000 -45786.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 456.000000 456.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 34.031250 34.031250
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 45786.750000 45786.750000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 1752065.000000 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 107.000000 107.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -45667.250000 -45667.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -7.000000 -7.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -347856.500000 -347856.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 356047.000000 356047.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s -1.250000 -1.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.s 23.062500 23.062500
-fcsr: 0x4
+fcsr: 0x0
roundig mode: zero
cvt.d.s 0.000000 0.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 456.250000 456.250000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 3.000000 3.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -1.000000 -1.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 1384.500000 1384.500000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -7.250000 -7.250000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 1000000000.000000 1000000000.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -5786.250000 -5786.250000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 1752.000000 1752.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 0.015625 0.015625
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 0.031250 0.031250
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -248562.750000 -248562.750000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -45786.500000 -45786.500000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 456.000000 456.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 34.031250 34.031250
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 45786.750000 45786.750000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 1752065.000000 1752065.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 107.000000 107.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -45667.250000 -45667.250000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -7.000000 -7.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -347856.500000 -347856.500000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 356047.000000 356047.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s -1.250000 -1.250000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.s 23.062500 23.062500
-fcsr: 0x5
+fcsr: 0x1
roundig mode: +inf
cvt.d.s 0.000000 0.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 456.250000 456.250000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 3.000000 3.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -1.000000 -1.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 1384.500000 1384.500000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -7.250000 -7.250000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 1000000000.000000 1000000000.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -5786.250000 -5786.250000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 1752.000000 1752.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 0.015625 0.015625
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 0.031250 0.031250
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -248562.750000 -248562.750000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -45786.500000 -45786.500000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 456.000000 456.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 34.031250 34.031250
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 45786.750000 45786.750000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 1752065.000000 1752065.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 107.000000 107.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -45667.250000 -45667.250000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -7.000000 -7.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -347856.500000 -347856.500000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 356047.000000 356047.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s -1.250000 -1.250000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.s 23.062500 23.062500
-fcsr: 0x6
+fcsr: 0x2
roundig mode: -inf
cvt.d.s 0.000000 0.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 456.250000 456.250000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 3.000000 3.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -1.000000 -1.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 1384.500000 1384.500000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -7.250000 -7.250000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 1000000000.000000 1000000000.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -5786.250000 -5786.250000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 1752.000000 1752.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 0.015625 0.015625
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 0.031250 0.031250
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -248562.750000 -248562.750000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -45786.500000 -45786.500000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 456.000000 456.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 34.031250 34.031250
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 45786.750000 45786.750000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 1752065.000000 1752065.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 107.000000 107.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -45667.250000 -45667.250000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -7.000000 -7.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -347856.500000 -347856.500000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 356047.000000 356047.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s -1.250000 -1.250000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.s 23.062500 23.062500
-fcsr: 0x7
+fcsr: 0x3
roundig mode: near
cvt.d.w 0.000000 0
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 456.000000 456
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 3.000000 3
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -1.000000 -1
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -1.000000 -1
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 356.000000 356
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 1000000000.000000 1000000000
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -5786.000000 -5786
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 1752.000000 1752
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 24575.000000 24575
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 10.000000 10
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -248562.000000 -248562
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -45786.000000 -45786
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 456.000000 456
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 34.000000 34
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 45786.000000 45786
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 1752065.000000 1752065
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 107.000000 107
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -45667.000000 -45667
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -7.000000 -7
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -347856.000000 -347856
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w -2147483648.000000 -2147483648
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 268435455.000000 268435455
-fcsr: 0x4
+fcsr: 0x0
cvt.d.w 23.000000 23
-fcsr: 0x4
+fcsr: 0x0
roundig mode: zero
cvt.d.w 0.000000 0
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 456.000000 456
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 3.000000 3
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -1.000000 -1
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -1.000000 -1
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 356.000000 356
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 1000000000.000000 1000000000
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -5786.000000 -5786
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 1752.000000 1752
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 24575.000000 24575
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 10.000000 10
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -248562.000000 -248562
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -45786.000000 -45786
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 456.000000 456
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 34.000000 34
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 45786.000000 45786
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 1752065.000000 1752065
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 107.000000 107
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -45667.000000 -45667
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -7.000000 -7
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -347856.000000 -347856
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w -2147483648.000000 -2147483648
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 268435455.000000 268435455
-fcsr: 0x5
+fcsr: 0x1
cvt.d.w 23.000000 23
-fcsr: 0x5
+fcsr: 0x1
roundig mode: +inf
cvt.d.w 0.000000 0
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 456.000000 456
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 3.000000 3
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -1.000000 -1
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -1.000000 -1
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 356.000000 356
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 1000000000.000000 1000000000
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -5786.000000 -5786
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 1752.000000 1752
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 24575.000000 24575
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 10.000000 10
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -248562.000000 -248562
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -45786.000000 -45786
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 456.000000 456
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 34.000000 34
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 45786.000000 45786
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 1752065.000000 1752065
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 107.000000 107
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -45667.000000 -45667
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -7.000000 -7
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -347856.000000 -347856
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w -2147483648.000000 -2147483648
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 268435455.000000 268435455
-fcsr: 0x6
+fcsr: 0x2
cvt.d.w 23.000000 23
-fcsr: 0x6
+fcsr: 0x2
roundig mode: -inf
cvt.d.w 0.000000 0
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 456.000000 456
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 3.000000 3
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -1.000000 -1
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -1.000000 -1
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 356.000000 356
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 1000000000.000000 1000000000
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -5786.000000 -5786
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 1752.000000 1752
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 24575.000000 24575
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 10.000000 10
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -248562.000000 -248562
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -45786.000000 -45786
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 456.000000 456
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 34.000000 34
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 45786.000000 45786
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 1752065.000000 1752065
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 107.000000 107
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -45667.000000 -45667
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -7.000000 -7
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -347856.000000 -347856
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w -2147483648.000000 -2147483648
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 268435455.000000 268435455
-fcsr: 0x7
+fcsr: 0x3
cvt.d.w 23.000000 23
-fcsr: 0x7
+fcsr: 0x3
roundig mode: near
cvt.s.d 0.000000 0.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 456.250000 456.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 3.000000 3.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -1.000000 -1.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 1384.500000 1384.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -7.250000 -7.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 1000000000.000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -5786.250000 -5786.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 1752.000000 1752.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 0.015625 0.015625
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 0.031250 0.031250
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -248562.750000 -248562.750000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -45786.500000 -45786.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 456.000000 456.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 34.031250 34.031250
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 45786.750000 45786.750000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 1752065.000000 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 107.000000 107.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -45667.250000 -45667.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -7.000000 -7.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -347856.500000 -347856.500000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 356047.000000 356047.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d -1.250000 -1.250000
-fcsr: 0x4
+fcsr: 0x0
cvt.s.d 23.062500 23.062500
-fcsr: 0x4
+fcsr: 0x0
roundig mode: zero
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cvt.w.s 1000000000 1000000000.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s -5787 -5786.250000
fcsr: 0x1007
cvt.w.s 1752 1752.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s 0 0.015625
fcsr: 0x1007
cvt.w.s 0 0.031250
@@ -1343,46 +1343,46 @@
cvt.w.s -45787 -45786.500000
fcsr: 0x1007
cvt.w.s 456 456.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s 34 34.031250
fcsr: 0x1007
cvt.w.s 45786 45786.750000
fcsr: 0x1007
cvt.w.s 1752065 1752065.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s 107 107.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s -45668 -45667.250000
fcsr: 0x1007
cvt.w.s -7 -7.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s -347857 -347856.500000
fcsr: 0x1007
cvt.w.s 356047 356047.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.s -2 -1.250000
fcsr: 0x1007
cvt.w.s 23 23.062500
fcsr: 0x1007
roundig mode: near
cvt.w.d 0 0.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d 456 456.250000
fcsr: 0x1004
cvt.w.d 3 3.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d -1 -1.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d 1384 1384.500000
fcsr: 0x1004
cvt.w.d -7 -7.250000
fcsr: 0x1004
cvt.w.d 1000000000 1000000000.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d -5786 -5786.250000
fcsr: 0x1004
cvt.w.d 1752 1752.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d 0 0.015625
fcsr: 0x1004
cvt.w.d 0 0.031250
@@ -1392,46 +1392,46 @@
cvt.w.d -45786 -45786.500000
fcsr: 0x1004
cvt.w.d 456 456.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d 34 34.031250
fcsr: 0x1004
cvt.w.d 45787 45786.750000
fcsr: 0x1004
cvt.w.d 1752065 1752065.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d 107 107.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d -45667 -45667.250000
fcsr: 0x1004
cvt.w.d -7 -7.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d -347856 -347856.500000
fcsr: 0x1004
cvt.w.d 356047 356047.000000
-fcsr: 0x4
+fcsr: 0x0
cvt.w.d -1 -1.250000
fcsr: 0x1004
cvt.w.d 23 23.062500
fcsr: 0x1004
roundig mode: zero
cvt.w.d 0 0.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d 456 456.250000
fcsr: 0x1005
cvt.w.d 3 3.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d -1 -1.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d 1384 1384.500000
fcsr: 0x1005
cvt.w.d -7 -7.250000
fcsr: 0x1005
cvt.w.d 1000000000 1000000000.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d -5786 -5786.250000
fcsr: 0x1005
cvt.w.d 1752 1752.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d 0 0.015625
fcsr: 0x1005
cvt.w.d 0 0.031250
@@ -1441,46 +1441,46 @@
cvt.w.d -45786 -45786.500000
fcsr: 0x1005
cvt.w.d 456 456.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d 34 34.031250
fcsr: 0x1005
cvt.w.d 45786 45786.750000
fcsr: 0x1005
cvt.w.d 1752065 1752065.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d 107 107.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d -45667 -45667.250000
fcsr: 0x1005
cvt.w.d -7 -7.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d -347856 -347856.500000
fcsr: 0x1005
cvt.w.d 356047 356047.000000
-fcsr: 0x5
+fcsr: 0x1
cvt.w.d -1 -1.250000
fcsr: 0x1005
cvt.w.d 23 23.062500
fcsr: 0x1005
roundig mode: +inf
cvt.w.d 0 0.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d 457 456.250000
fcsr: 0x1006
cvt.w.d 3 3.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d -1 -1.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d 1385 1384.500000
fcsr: 0x1006
cvt.w.d -7 -7.250000
fcsr: 0x1006
cvt.w.d 1000000000 1000000000.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d -5786 -5786.250000
fcsr: 0x1006
cvt.w.d 1752 1752.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d 1 0.015625
fcsr: 0x1006
cvt.w.d 1 0.031250
@@ -1490,46 +1490,46 @@
cvt.w.d -45786 -45786.500000
fcsr: 0x1006
cvt.w.d 456 456.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d 35 34.031250
fcsr: 0x1006
cvt.w.d 45787 45786.750000
fcsr: 0x1006
cvt.w.d 1752065 1752065.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d 107 107.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d -45667 -45667.250000
fcsr: 0x1006
cvt.w.d -7 -7.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d -347856 -347856.500000
fcsr: 0x1006
cvt.w.d 356047 356047.000000
-fcsr: 0x6
+fcsr: 0x2
cvt.w.d -1 -1.250000
fcsr: 0x1006
cvt.w.d 24 23.062500
fcsr: 0x1006
roundig mode: -inf
cvt.w.d 0 0.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d 456 456.250000
fcsr: 0x1007
cvt.w.d 3 3.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d -1 -1.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d 1384 1384.500000
fcsr: 0x1007
cvt.w.d -8 -7.250000
fcsr: 0x1007
cvt.w.d 1000000000 1000000000.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d -5787 -5786.250000
fcsr: 0x1007
cvt.w.d 1752 1752.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d 0 0.015625
fcsr: 0x1007
cvt.w.d 0 0.031250
@@ -1539,23 +1539,23 @@
cvt.w.d -45787 -45786.500000
fcsr: 0x1007
cvt.w.d 456 456.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d 34 34.031250
fcsr: 0x1007
cvt.w.d 45786 45786.750000
fcsr: 0x1007
cvt.w.d 1752065 1752065.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d 107 107.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d -45668 -45667.250000
fcsr: 0x1007
cvt.w.d -7 -7.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d -347857 -347856.500000
fcsr: 0x1007
cvt.w.d 356047 356047.000000
-fcsr: 0x7
+fcsr: 0x3
cvt.w.d -2 -1.250000
fcsr: 0x1007
cvt.w.d 23 23.062500
Added: trunk/none/tests/mips32/round_fpu64.c
==============================================================================
--- trunk/none/tests/mips32/round_fpu64.c (added)
+++ trunk/none/tests/mips32/round_fpu64.c Wed Feb 19 11:57:22 2014
@@ -0,0 +1,204 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <setjmp.h>
+
+#define MAX_ARR 24
+#define PERROR \
+ printf("This test is testing mips32r2 instructions in fpu64 mode.\n");
+#define FLAGS_RM_MASK 0xFFFFFFFF
+
+typedef enum {
+ CVTLS, CVTLD, ROUNDLS, ROUNDLD,
+ TRUNCLS, TRUNCLD, FLOORLS, FLOORLD,
+ CEILLS, CEILLD
+} flt_round_op_t;
+
+const char *flt_round_op_names[] = {
+ "cvt.l.s", "cvt.l.d", "round.l.s", "round.l.d",
+ "trunc.l.s", "trunc.l.d", "floor.l.s", "floor.l.d"
+ "ceil.l.s", "ceil.l.d"
+};
+
+typedef enum {
+ TO_NEAREST=0, TO_ZERO, TO_PLUS_INFINITY, TO_MINUS_INFINITY } round_mode_t;
+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" };
+
+const float fs_f[] = {
+ 0, 456.25, 3, -1,
+ 1384.5, -7.25, 1000000000, -5786.25,
+ 1752, 0.015625, 0.03125, -248562.75,
+ -45786.5, 456, 34.03125, 45786.75,
+ 1752065, 107, -45667.25, -7,
+ -347856.5, 356047, -1.25, 23.0625
+};
+
+const double fs_d[] = {
+ 0, 456.25, 3, -1,
+ 1384.5, -7.25, 1000000000, -5786.25,
+ 1752, 0.015625, 0.03125, -24856226678933.75,
+ -45786.5, 456, 34.03125, 45786.75,
+ 1752065, 107, -45667.25, -7,
+ -347856.5, 356047, -1.25, 23.0625
+};
+
+#define UNOPsl(op) \
+ __asm__ __volatile__( \
+ op" $f0, %2" "\n\t" \
+ "sdc1 $f0, 0(%1)" "\n\t" \
+ "cfc1 %0, $31" "\n\t" \
+ : "=r" (fcsr) \
+ : "r"(&fd_l), "f"(fs_f[i]) \
+ : "$f0" \
+ );
+
+#define UNOPdl(op) \
+ __asm__ __volatile__( \
+ op" $f0, %2" "\n\t" \
+ "sdc1 $f0, 0(%1)" "\n\t" \
+ "cfc1 %0, $31" "\n\t" \
+ : "=r" (fcsr) \
+ : "r"(&fd_l), "f"(fs_d[i]) \
+ : "$f0" \
+ );
+
+#define TEST_FPU64 \
+ __asm__ __volatile__( \
+ "cvt.l.s $f0, $f0" "\n\t" \
+ : \
+ : \
+ : "$f0" \
+ );
+
+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64)
+void set_rounding_mode(round_mode_t mode)
+{
+ switch(mode) {
+ case TO_NEAREST:
+ __asm__ volatile("ctc1 $zero, $31" "\n\t");
+ break;
+ case TO_ZERO:
+ __asm__ volatile("li $t0, 0x1" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
+ break;
+ case TO_PLUS_INFINITY:
+ __asm__ volatile("li $t0, 0x2" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
+ break;
+ case TO_MINUS_INFINITY:
+ __asm__ volatile("li $t0, 0x3" "\n\t"
+ "ctc1 $t0, $31" "\n\t");
+ break;
+ }
+}
+
+struct test {
+ void (*test)(void);
+ int sig;
+ int code;
+};
+
+static void handler(int sig)
+{
+ PERROR;
+ exit(0);
+}
+
+int FCSRRoundingMode(flt_round_op_t op)
+{
+ long long int fd_l;
+ int i;
+ int fcsr = 0;
+ round_mode_t rm;
+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) {
+ printf("roundig mode: %s\n", round_mode_name[rm]);
+ for (i = 0; i < MAX_ARR; i++) {
+ set_rounding_mode(rm);
+ switch(op) {
+ case CVTLS:
+ UNOPsl("cvt.l.s");
+ printf("%s %lld %f\n",
+ flt_round_op_names[op], fd_l, fs_f[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case CVTLD:
+ UNOPdl("cvt.l.d");
+ printf("%s %lld %lf\n",
+ flt_round_op_names[op], fd_l, fs_d[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case ROUNDLS:
+ UNOPsl("round.l.s");
+ printf("%s %lld %f\n",
+ flt_round_op_names[op], fd_l, fs_f[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case ROUNDLD:
+ UNOPdl("round.l.d");
+ printf("%s %lld %lf\n",
+ flt_round_op_names[op], fd_l, fs_d[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case TRUNCLS:
+ UNOPsl("trunc.l.s");
+ printf("%s %lld %f\n",
+ flt_round_op_names[op], fd_l, fs_f[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case TRUNCLD:
+ UNOPdl("trunc.l.d");
+ printf("%s %lld %lf\n",
+ flt_round_op_names[op], fd_l, fs_d[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case FLOORLS:
+ UNOPsl("floor.l.s");
+ printf("%s %lld %f\n",
+ flt_round_op_names[op], fd_l, fs_f[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case FLOORLD:
+ UNOPdl("floor.l.d");
+ printf("%s %lld %lf\n",
+ flt_round_op_names[op], fd_l, fs_d[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case CEILLS:
+ UNOPsl("ceil.l.s");
+ printf("%s %lld %f\n",
+ flt_round_op_names[op], fd_l, fs_f[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ case CEILLD:
+ UNOPdl("ceil.l.d");
+ printf("%s %lld %lf\n",
+ flt_round_op_names[op], fd_l, fs_d[i]);
+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK);
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ }
+ return 0;
+}
+#endif
+
+
+int main()
+{
+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64)
+ flt_round_op_t op;
+ signal(SIGILL, handler);
+ /* Test fpu64 mode. */
+ TEST_FPU64;
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Conversion Operations Using the FCSR Rounding Mode");
+ for (op = CVTLS; op <= CEILLD; op++)
+ FCSRRoundingMode(op);
+#else
+ PERROR;
+#endif
+ return 0;
+}
Added: trunk/none/tests/mips32/round_fpu64.stderr.exp
==============================================================================
(empty)
Added: trunk/none/tests/mips32/round_fpu64.stdout.exp
==============================================================================
--- trunk/none/tests/mips32/round_fpu64.stdout.exp (added)
+++ trunk/none/tests/mips32/round_fpu64.stdout.exp Wed Feb 19 11:57:22 2014
@@ -0,0 +1,1961 @@
+-------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode --------------------------
+roundig mode: near
+cvt.l.s 0 0.000000
+fcsr: 0x0
+cvt.l.s 456 456.250000
+fcsr: 0x1004
+cvt.l.s 3 3.000000
+fcsr: 0x0
+cvt.l.s -1 -1.000000
+fcsr: 0x0
+cvt.l.s 1384 1384.500000
+fcsr: 0x1004
+cvt.l.s -7 -7.250000
+fcsr: 0x1004
+cvt.l.s 1000000000 1000000000.000000
+fcsr: 0x0
+cvt.l.s -5786 -5786.250000
+fcsr: 0x1004
+cvt.l.s 1752 1752.000000
+fcsr: 0x0
+cvt.l.s 0 0.015625
+fcsr: 0x1004
+cvt.l.s 0 0.031250
+fcsr: 0x1004
+cvt.l.s -248563 -248562.750000
+fcsr: 0x1004
+cvt.l.s -45786 -45786.500000
+fcsr: 0x1004
+cvt.l.s 456 456.000000
+fcsr: 0x0
+cvt.l.s 34 34.031250
+fcsr: 0x1004
+cvt.l.s 45787 45786.750000
+fcsr: 0x1004
+cvt.l.s 1752065 1752065.000000
+fcsr: 0x0
+cvt.l.s 107 107.000000
+fcsr: 0x0
+cvt.l.s -45667 -45667.250000
+fcsr: 0x1004
+cvt.l.s -7 -7.000000
+fcsr: 0x0
+cvt.l.s -347856 -347856.500000
+fcsr: 0x1004
+cvt.l.s 356047 356047.000000
+fcsr: 0x0
+cvt.l.s -1 -1.250000
+fcsr: 0x1004
+cvt.l.s 23 23.062500
+fcsr: 0x1004
+roundig mode: zero
+cvt.l.s 0 0.000000
+fcsr: 0x1
+cvt.l.s 456 456.250000
+fcsr: 0x1005
+cvt.l.s 3 3.000000
+fcsr: 0x1
+cvt.l.s -1 -1.000000
+fcsr: 0x1
+cvt.l.s 1384 1384.500000
+fcsr: 0x1005
+cvt.l.s -7 -7.250000
+fcsr: 0x1005
+cvt.l.s 1000000000 1000000000.000000
+fcsr: 0x1
+cvt.l.s -5786 -5786.250000
+fcsr: 0x1005
+cvt.l.s 1752 1752.000000
+fcsr: 0x1
+cvt.l.s 0 0.015625
+fcsr: 0x1005
+cvt.l.s 0 0.031250
+fcsr: 0x1005
+cvt.l.s -248562 -248562.750000
+fcsr: 0x1005
+cvt.l.s -45786 -45786.500000
+fcsr: 0x1005
+cvt.l.s 456 456.000000
+fcsr: 0x1
+cvt.l.s 34 34.031250
+fcsr: 0x1005
+cvt.l.s 45786 45786.750000
+fcsr: 0x1005
+cvt.l.s 1752065 1752065.000000
+fcsr: 0x1
+cvt.l.s 107 107.000000
+fcsr: 0x1
+cvt.l.s -45667 -45667.250000
+fcsr: 0x1005
+cvt.l.s -7 -7.000000
+fcsr: 0x1
+cvt.l.s -347856 -347856.500000
+fcsr: 0x1005
+cvt.l.s 356047 356047.000000
+fcsr: 0x1
+cvt.l.s -1 -1.250000
+fcsr: 0x1005
+cvt.l.s 23 23.062500
+fcsr: 0x1005
+roundig mode: +inf
+cvt.l.s 0 0.000000
+fcsr: 0x2
+cvt.l.s 457 456.250000
+fcsr: 0x1006
+cvt.l.s 3 3.000000
+fcsr: 0x2
+cvt.l.s -1 -1.000000
+fcsr: 0x2
+cvt.l.s 1385 1384.500000
+fcsr: 0x1006
+cvt.l.s -7 -7.250000
+fcsr: 0x1006
+cvt.l.s 1000000000 1000000000.000000
+fcsr: 0x2
+cvt.l.s -5786 -5786.250000
+fcsr: 0x1006
+cvt.l.s 1752 1752.000000
+fcsr: 0x2
+cvt.l.s 1 0.015625
+fcsr: 0x1006
+cvt.l.s 1 0.031250
+fcsr: 0x1006
+cvt.l.s -248562 -248562.750000
+fcsr: 0x1006
+cvt.l.s -45786 -45786.500000
+fcsr: 0x1006
+cvt.l.s 456 456.000000
+fcsr: 0x2
+cvt.l.s 35 34.031250
+fcsr: 0x1006
+cvt.l.s 45787 45786.750000
+fcsr: 0x1006
+cvt.l.s 1752065 1752065.000000
+fcsr: 0x2
+cvt.l.s 107 107.000000
+fcsr: 0x2
+cvt.l.s -45667 -45667.250000
+fcsr: 0x1006
+cvt.l.s -7 -7.000000
+fcsr: 0x2
+cvt.l.s -347856 -347856.500000
+fcsr: 0x1006
+cvt.l.s 356047 356047.000000
+fcsr: 0x2
+cvt.l.s -1 -1.250000
+fcsr: 0x1006
+cvt.l.s 24 23.062500
+fcsr: 0x1006
+roundig mode: -inf
+cvt.l.s 0 0.000000
+fcsr: 0x3
+cvt.l.s 456 456.250000
+fcsr: 0x1007
+cvt.l.s 3 3.000000
+fcsr: 0x3
+cvt.l.s -1 -1.000000
+fcsr: 0x3
+cvt.l.s 1384 1384.500000
+fcsr: 0x1007
+cvt.l.s -8 -7.250000
+fcsr: 0x1007
+cvt.l.s 1000000000 1000000000.000000
+fcsr: 0x3
+cvt.l.s -5787 -5786.250000
+fcsr: 0x1007
+cvt.l.s 1752 1752.000000
+fcsr: 0x3
+cvt.l.s 0 0.015625
+fcsr: 0x1007
+cvt.l.s 0 0.031250
+fcsr: 0x1007
+cvt.l.s -248563 -248562.750000
+fcsr: 0x1007
+cvt.l.s -45787 -45786.500000
+fcsr: 0x1007
+cvt.l.s 456 456.000000
+fcsr: 0x3
+cvt.l.s 34 34.031250
+fcsr: 0x1007
+cvt.l.s 45786 45786.750000
+fcsr: 0x1007
+cvt.l.s 1752065 1752065.000000
+fcsr: 0x3
+cvt.l.s 107 107.000000
+fcsr: 0x3
+cvt.l.s -45668 -45667.250000
+fcsr: 0x1007
+cvt.l.s -7 -7.000000
+fcsr: 0x3
+cvt.l.s -347857 -347856.500000
+fcsr: 0x1007
+cvt.l.s 356047 356047.000000
+fcsr: 0x3
+cvt.l.s -2 -1.250000
+fcsr: 0x1007
+cvt.l.s 23 23.062500
+fcsr: 0x1007
+roundig mode: near
+cvt.l.d 0 0.000000
+fcsr: 0x0
+cvt.l.d 456 456.250000
+fcsr: 0x1004
+cvt.l.d 3 3.000000
+fcsr: 0x0
+cvt.l.d -1 -1.000000
+fcsr: 0x0
+cvt.l.d 1384 1384.500000
+fcsr: 0x1004
+cvt.l.d -7 -7.250000
+fcsr: 0x1004
+cvt.l.d 1000000000 1000000000.000000
+fcsr: 0x0
+cvt.l.d -5786 -5786.250000
+fcsr: 0x1004
+cvt.l.d 1752 1752.000000
+fcsr: 0x0
+cvt.l.d 0 0.015625
+fcsr: 0x1004
+cvt.l.d 0 0.031250
+fcsr: 0x1004
+cvt.l.d -24856226678934 -24856226678933.750000
+fcsr: 0x1004
+cvt.l.d -45786 -45786.500000
+fcsr: 0x1004
+cvt.l.d 456 456.000000
+fcsr: 0x0
+cvt.l.d 34 34.031250
+fcsr: 0x1004
+cvt.l.d 45787 45786.750000
+fcsr: 0x1004
+cvt.l.d 1752065 1752065.000000
+fcsr: 0x0
+cvt.l.d 107 107.000000
+fcsr: 0x0
+cvt.l.d -45667 -45667.250000
+fcsr: 0x1004
+cvt.l.d -7 -7.000000
+fcsr: 0x0
+cvt.l.d -347856 -347856.500000
+fcsr: 0x1004
+cvt.l.d 356047 356047.000000
+fcsr: 0x0
+cvt.l.d -1 -1.250000
+fcsr: 0x1004
+cvt.l.d 23 23.062500
+fcsr: 0x1004
+roundig mode: zero
+cvt.l.d 0 0.000000
+fcsr: 0x1
+cvt.l.d 456 456.250000
+fcsr: 0x1005
+cvt.l.d 3 3.000000
+fcsr: 0x1
+cvt.l.d -1 -1.000000
+fcsr: 0x1
+cvt.l.d 1384 1384.500000
+fcsr: 0x1005
+cvt.l.d -7 -7.250000
+fcsr: 0x1005
+cvt.l.d 1000000000 1000000000.000000
+fcsr: 0x1
+cvt.l.d -5786 -5786.250000
+fcsr: 0x1005
+cvt.l.d 1752 1752.000000
+fcsr: 0x1
+cvt.l.d 0 0.015625
+fcsr: 0x1005
+cvt.l.d 0 0.031250
+fcsr: 0x1005
+cvt.l.d -24856226678933 -24856226678933.750000
+fcsr: 0x1005
+cvt.l.d -45786 -45786.500000
+fcsr: 0x1005
+cvt.l.d 456 456.000000
+fcsr: 0x1
+cvt.l.d 34 34.031250
+fcsr: 0x1005
+cvt.l.d 45786 45786.750000
+fcsr: 0x1005
+cvt.l.d 1752065 1752065.000000
+fcsr: 0x1
+cvt.l.d 107 107.000000
+fcsr: 0x1
+cvt.l.d -45667 -45667.250000
+fcsr: 0x1005
+cvt.l.d -7 -7.000000
+fcsr: 0x1
+cvt.l.d -347856 -347856.500000
+fcsr: 0x1005
+cvt.l.d 356047 356047.000000
+fcsr: 0x1
+cvt.l.d -1 -1.250000
+fcsr: 0x1005
+cvt.l.d 23 23.062500
+fcsr: 0x1005
+roundig mode: +inf
+cvt.l.d 0 0.000000
+fcsr: 0x2
+cvt.l.d 457 456.250000
+fcsr: 0x1006
+cvt.l.d 3 3.000000
+fcsr: 0x2
+cvt.l.d -1 -1.000000
+fcsr: 0x2
+cvt.l.d 1385 1384.500000
+fcsr: 0x1006
+cvt.l.d -7 -7.250000
+fcsr: 0x1006
+cvt.l.d 1000000000 1000000000.000000
+fcsr: 0x2
+cvt.l.d -5786 -5786.250000
+fcsr: 0x1006
+cvt.l.d 1752 1752.000000
+fcsr: 0x2
+cvt.l.d 1 0.015625
+fcsr: 0x1006
+cvt.l.d 1 0.031250
+fcsr: 0x1006
+cvt.l.d -24856226678933 -24856226678933.750000
+fcsr: 0x1006
+cvt.l.d -45786 -45786.500000
+fcsr: 0x1006
+cvt.l.d 456 456.000000
+fcsr: 0x2
+cvt.l.d 35 34.031250
+fcsr: 0x1006
+cvt.l.d 45787 45786.750000
+fcsr: 0x1006
+cvt.l.d 1752065 1752065.000000
+fcsr: 0x2
+cvt.l.d 107 107.000000
+fcsr: 0x2
+cvt.l.d -45667 -45667.250000
+fcsr: 0x1006
+cvt.l.d -7 -7.000000
+fcsr: 0x2
+cvt.l.d -347856 -347856.500000
+fcsr: 0x1006
+cvt.l.d 356047 356047.000000
+fcsr: 0x2
+cvt.l.d -1 -1.250000
+fcsr: 0x1006
+cvt.l.d 24 23.062500
+fcsr: 0x1006
+roundig mode: -inf
+cvt.l.d 0 0.000000
+fcsr: 0x3
+cvt.l.d 456 456.250000
+fcsr: 0x1007
+cvt.l.d 3 3.000000
+fcsr: 0x3
+cvt.l.d -1 -1.000000
+fcsr: 0x3
+cvt.l.d 1384 1384.500000
+fcsr: 0x1007
+cvt.l.d -8 -7.250000
+fcsr: 0x1007
+cvt.l.d 1000000000 1000000000.000000
+fcsr: 0x3
+cvt.l.d -5787 -5786.250000
+fcsr: 0x1007
+cvt.l.d 1752 1752.000000
+fcsr: 0x3
+cvt.l.d 0 0.015625
+fcsr: 0x1007
+cvt.l.d 0 0.031250
+fcsr: 0x1007
+cvt.l.d -24856226678934 -24856226678933.750000
+fcsr: 0x1007
+cvt.l.d -45787 -45786.500000
+fcsr: 0x1007
+cvt.l.d 456 456.000000
+fcsr: 0x3
+cvt.l.d 34 34.031250
+fcsr: 0x1007
+cvt.l.d 45786 45786.750000
+fcsr: 0x1007
+cvt.l.d 1752065 1752065.000000
+fcsr: 0x3
+cvt.l.d 107 107.000000
+fcsr: 0x3
+cvt.l.d -45668 -45667.250000
+fcsr: 0x1007
+cvt.l.d -7 -7.000000
+fcsr: 0x3
+cvt.l.d -347857 -347856.500000
+fcsr: 0x1007
+cvt.l.d 356047 356047.000000
+fcsr: 0x3
+cvt.l.d -2 -1.250000
+fcsr: 0x1007
+cvt.l.d 23 23.062500
+fcsr: 0x1007
+roundig mode: near
+round.l.s 0 0.000000
+fcsr: 0x0
+round.l.s 456 456.250000
+fcsr: 0x1004
+round.l.s 3 3.000000
+fcsr: 0x0
+round.l.s -1 -1.000000
+fcsr: 0x0
+round.l.s 1384 1384.500000
+fcsr: 0x1004
+round.l.s -7 -7.250000
+fcsr: 0x1004
+round.l.s 1000000000 1000000000.000000
+fcsr: 0x0
+round.l.s -5786 -5786.250000
+fcsr: 0x1004
+round.l.s 1752 1752.000000
+fcsr: 0x0
+round.l.s 0 0.015625
+fcsr: 0x1004
+round.l.s 0 0.031250
+fcsr: 0x1004
+round.l.s -248563 -248562.750000
+fcsr: 0x1004
+round.l.s -45786 -45786.500000
+fcsr: 0x1004
+round.l.s 456 456.000000
+fcsr: 0x0
+round.l.s 34 34.031250
+fcsr: 0x1004
+round.l.s 45787 45786.750000
+fcsr: 0x1004
+round.l.s 1752065 1752065.000000
+fcsr: 0x0
+round.l.s 107 107.000000
+fcsr: 0x0
+round.l.s -45667 -45667.250000
+fcsr: 0x1004
+round.l.s -7 -7.000000
+fcsr: 0x0
+round.l.s -347856 -347856.500000
+fcsr: 0x1004
+round.l.s 356047 356047.000000
+fcsr: 0x0
+round.l.s -1 -1.250000
+fcsr: 0x1004
+round.l.s 23 23.062500
+fcsr: 0x1004
+roundig mode: zero
+round.l.s 0 0.000000
+fcsr: 0x1
+round.l.s 456 456.250000
+fcsr: 0x1005
+round.l.s 3 3.000000
+fcsr: 0x1
+round.l.s -1 -1.000000
+fcsr: 0x1
+round.l.s 1384 1384.500000
+fcsr: 0x1005
+round.l.s -7 -7.250000
+fcsr: 0x1005
+round.l.s 1000000000 1000000000.000000
+fcsr: 0x1
+round.l.s -5786 -5786.250000
+fcsr: 0x1005
+round.l.s 1752 1752.000000
+fcsr: 0x1
+round.l.s 0 0.015625
+fcsr: 0x1005
+round.l.s 0 0.031250
+fcsr: 0x1005
+round.l.s -248563 -248562.750000
+fcsr: 0x1005
+round.l.s -45786 -45786.500000
+fcsr: 0x1005
+round.l.s 456 456.000000
+fcsr: 0x1
+round.l.s 34 34.031250
+fcsr: 0x1005
+round.l.s 45787 45786.750000
+fcsr: 0x1005
+round.l.s 1752065 1752065.000000
+fcsr: 0x1
+round.l.s 107 107.000000
+fcsr: 0x1
+round.l.s -45667 -45667.250000
+fcsr: 0x1005
+round.l.s -7 -7.000000
+fcsr: 0x1
+round.l.s -347856 -347856.500000
+fcsr: 0x1005
+round.l.s 356047 356047.000000
+fcsr: 0x1
+round.l.s -1 -1.250000
+fcsr: 0x1005
+round...
[truncated message content] |
Author: dejanj
Date: Wed Feb 19 11:56:29 2014
New Revision: 2821
Log:
mips32: VEX Support for 64bit FPU on MIPS32 platforms.
This patch is adding support for mips32 with 64bit FPU.
Assume that floating-point registers are 64 bits wide.
Modified:
trunk/priv/guest_mips_defs.h
trunk/priv/guest_mips_helpers.c
trunk/priv/guest_mips_toIR.c
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_isel.c
trunk/priv/ir_defs.c
trunk/pub/libvex.h
trunk/pub/libvex_guest_mips32.h
trunk/pub/libvex_ir.h
trunk/pub/libvex_trc_values.h
Modified: trunk/priv/guest_mips_defs.h
==============================================================================
--- trunk/priv/guest_mips_defs.h (original)
+++ trunk/priv/guest_mips_defs.h Wed Feb 19 11:56:29 2014
@@ -99,8 +99,12 @@
extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
#endif
-extern UInt mips_dirtyhelper_calculate_FCSR ( void* guest_state, UInt fs,
- UInt ft, flt_op op );
+/* Calculate FCSR in fp32 mode. */
+extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs,
+ UInt ft, flt_op op );
+/* Calculate FCSR in fp64 mode. */
+extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* guest_state, UInt fs,
+ UInt ft, flt_op op );
/*---------------------------------------------------------*/
/*--- Condition code stuff ---*/
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Wed Feb 19 11:56:29 2014
@@ -44,7 +44,7 @@
these functions are generated by the back end.
*/
-#define ALWAYSDEFD32(field) \
+#define ALWAYSDEFD32(field) \
{ offsetof(VexGuestMIPS32State, field), \
(sizeof ((VexGuestMIPS32State*)0)->field) }
@@ -1133,14 +1133,14 @@
);
#define ASM_VOLATILE_UNARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
- "ctc1 %2, $31" "\n\t" \
- "dmtc1 %1, $f24" "\n\t" \
- #inst" $f24, $f24" "\n\t" \
- "cfc1 %0, $31" "\n\t" \
- "ctc1 $t0, $31" "\n\t" \
+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ "ctc1 %2, $31" "\n\t" \
+ "ldc1 $f24, 0(%1)" "\n\t" \
+ #inst" $f24, $f24" "\n\t" \
+ "cfc1 %0, $31" "\n\t" \
+ "ctc1 $t0, $31" "\n\t" \
: "=r" (ret) \
- : "r" (fsVal), "r" (fcsr) \
+ : "r" (&(addr[fs])), "r" (fcsr) \
: "t0", "$f24" \
);
@@ -1173,144 +1173,257 @@
: "t0", "$f20", "$f21", "$f22", "$f23" \
);
-#define ASM_VOLATILE_BINARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
- "ctc1 %3, $31" "\n\t" \
- "dmtc1 %1, $f24" "\n\t" \
- "dmtc1 %2, $f25" "\n\t" \
- #inst" $f24, $f24, $f25" "\n\t" \
- "cfc1 %0, $31" "\n\t" \
- "ctc1 $t0, $31" "\n\t" \
- : "=r" (ret) \
- : "r" (fsVal), "r" (ftVal), "r" (fcsr) \
- : "t0", "$f24", "$f25" \
+#define ASM_VOLATILE_BINARY64(inst) \
+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ "ctc1 %3, $31" "\n\t" \
+ "ldc1 $f24, 0(%1)" "\n\t" \
+ "ldc1 $f26, 0(%2)" "\n\t" \
+ #inst" $f24, $f24, $f26" "\n\t" \
+ "cfc1 %0, $31" "\n\t" \
+ "ctc1 $t0, $31" "\n\t" \
+ : "=r" (ret) \
+ : "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \
+ : "t0", "$f24", "$f26" \
);
/* TODO: Add cases for all fpu instructions because all fpu instructions are
change the value of FCSR register. */
-extern UInt mips_dirtyhelper_calculate_FCSR ( void* gs, UInt fs, UInt ft,
- flt_op inst )
+extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* gs, UInt fs, UInt ft,
+ flt_op inst )
+{
+ UInt ret = 0;
+#if defined(__mips__)
+ VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
+ UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
+#if defined (_MIPSEL)
+ ULong *addr = (ULong *)&guest_state->guest_f0;
+ loFsVal = (UInt)addr[fs];
+ hiFsVal = (UInt)addr[fs+1];
+ loFtVal = (UInt)addr[ft];
+ hiFtVal = (UInt)addr[ft+1];
+#elif defined (_MIPSEB)
+ UInt *addr = (UInt *)&guest_state->guest_f0;
+ loFsVal = (UInt)addr[fs*2];
+ hiFsVal = (UInt)addr[fs*2+2];
+ loFtVal = (UInt)addr[ft*2];
+ hiFtVal = (UInt)addr[ft*2+2];
+#endif
+ UInt fcsr = guest_state->guest_FCSR;
+ switch (inst) {
+ case ROUNDWD:
+ ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)
+ break;
+ case FLOORWS:
+ ASM_VOLATILE_UNARY32(floor.w.s)
+ break;
+ case FLOORWD:
+ ASM_VOLATILE_UNARY32_DOUBLE(floor.w.d)
+ break;
+ case TRUNCWS:
+ ASM_VOLATILE_UNARY32(trunc.w.s)
+ break;
+ case TRUNCWD:
+ ASM_VOLATILE_UNARY32_DOUBLE(trunc.w.d)
+ break;
+ case CEILWS:
+ ASM_VOLATILE_UNARY32(ceil.w.s)
+ break;
+ case CEILWD:
+ ASM_VOLATILE_UNARY32_DOUBLE(ceil.w.d)
+ break;
+ case CVTDS:
+ ASM_VOLATILE_UNARY32(cvt.d.s)
+ break;
+ case CVTDW:
+ ASM_VOLATILE_UNARY32(cvt.d.w)
+ break;
+ case CVTSW:
+ ASM_VOLATILE_UNARY32(cvt.s.w)
+ break;
+ case CVTSD:
+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.d)
+ break;
+ case CVTWS:
+ ASM_VOLATILE_UNARY32(cvt.w.s)
+ break;
+ case CVTWD:
+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.w.d)
+ break;
+ case ROUNDWS:
+ ASM_VOLATILE_UNARY32(round.w.s)
+ break;
+#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \
+ || (__mips == 64)
+ case CEILLS:
+ ASM_VOLATILE_UNARY32(ceil.l.s)
+ break;
+ case CEILLD:
+ ASM_VOLATILE_UNARY32_DOUBLE(ceil.l.d)
+ break;
+ case CVTDL:
+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.d.l)
+ break;
+ case CVTLS:
+ ASM_VOLATILE_UNARY32(cvt.l.s)
+ break;
+ case CVTLD:
+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.l.d)
+ break;
+ case CVTSL:
+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.l)
+ break;
+ case FLOORLS:
+ ASM_VOLATILE_UNARY32(floor.l.s)
+ break;
+ case FLOORLD:
+ ASM_VOLATILE_UNARY32_DOUBLE(floor.l.d)
+ break;
+ case ROUNDLS:
+ ASM_VOLATILE_UNARY32(round.l.s)
+ break;
+ case ROUNDLD:
+ ASM_VOLATILE_UNARY32_DOUBLE(round.l.d)
+ break;
+ case TRUNCLS:
+ ASM_VOLATILE_UNARY32(trunc.l.s)
+ break;
+ case TRUNCLD:
+ ASM_VOLATILE_UNARY32_DOUBLE(trunc.l.d)
+ break;
+#endif
+ case ADDS:
+ ASM_VOLATILE_BINARY32(add.s)
+ break;
+ case ADDD:
+ ASM_VOLATILE_BINARY32_DOUBLE(add.d)
+ break;
+ case SUBS:
+ ASM_VOLATILE_BINARY32(sub.s)
+ break;
+ case SUBD:
+ ASM_VOLATILE_BINARY32_DOUBLE(sub.d)
+ break;
+ case DIVS:
+ ASM_VOLATILE_BINARY32(div.s)
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+#endif
+ return ret;
+}
+
+/* TODO: Add cases for all fpu instructions because all fpu instructions are
+ change the value of FCSR register. */
+extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* gs, UInt fs, UInt ft,
+ flt_op inst )
{
UInt ret = 0;
#if defined(__mips__)
#if defined(VGA_mips32)
VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
- UInt *addr = (UInt *)&guest_state->guest_f0;
- UInt loFsVal = addr[fs];
- UInt hiFsVal = addr[fs+1];
- UInt loFtVal = addr[ft];
- UInt hiFtVal = addr[ft+1];
-#define ASM_VOLATILE_UNARY(inst) ASM_VOLATILE_UNARY32(inst)
-#define ASM_VOLATILE_UNARY_DOUBLE(inst) ASM_VOLATILE_UNARY32_DOUBLE(inst)
-#define ASM_VOLATILE_BINARY(inst) ASM_VOLATILE_BINARY32(inst)
-#define ASM_VOLATILE_BINARY_DOUBLE(inst) ASM_VOLATILE_BINARY32_DOUBLE(inst)
#else
VexGuestMIPS64State* guest_state = (VexGuestMIPS64State*)gs;
- ULong *addr = (ULong *)&guest_state->guest_f0;
- ULong fsVal = addr[fs];
- ULong ftVal = addr[ft];
-#define ASM_VOLATILE_UNARY(inst) ASM_VOLATILE_UNARY64(inst)
-#define ASM_VOLATILE_UNARY_DOUBLE(inst) ASM_VOLATILE_UNARY64(inst)
-#define ASM_VOLATILE_BINARY(inst) ASM_VOLATILE_BINARY64(inst)
-#define ASM_VOLATILE_BINARY_DOUBLE(inst) ASM_VOLATILE_BINARY64(inst)
#endif
- UInt fcsr = guest_state->guest_FCSR;
+ ULong *addr = (ULong *)&guest_state->guest_f0;
+ UInt fcsr = guest_state->guest_FCSR;
switch (inst) {
case ROUNDWD:
- ASM_VOLATILE_UNARY_DOUBLE(round.w.d)
+ ASM_VOLATILE_UNARY64(round.w.d)
break;
case FLOORWS:
- ASM_VOLATILE_UNARY(floor.w.s)
+ ASM_VOLATILE_UNARY64(floor.w.s)
break;
case FLOORWD:
- ASM_VOLATILE_UNARY_DOUBLE(floor.w.d)
+ ASM_VOLATILE_UNARY64(floor.w.d)
break;
case TRUNCWS:
- ASM_VOLATILE_UNARY(trunc.w.s)
+ ASM_VOLATILE_UNARY64(trunc.w.s)
break;
case TRUNCWD:
- ASM_VOLATILE_UNARY_DOUBLE(trunc.w.d)
+ ASM_VOLATILE_UNARY64(trunc.w.d)
break;
case CEILWS:
- ASM_VOLATILE_UNARY(ceil.w.s)
+ ASM_VOLATILE_UNARY64(ceil.w.s)
break;
case CEILWD:
- ASM_VOLATILE_UNARY_DOUBLE(ceil.w.d)
+ ASM_VOLATILE_UNARY64(ceil.w.d)
break;
case CVTDS:
- ASM_VOLATILE_UNARY(cvt.d.s)
+ ASM_VOLATILE_UNARY64(cvt.d.s)
break;
case CVTDW:
- ASM_VOLATILE_UNARY(cvt.d.w)
+ ASM_VOLATILE_UNARY64(cvt.d.w)
break;
case CVTSW:
- ASM_VOLATILE_UNARY(cvt.s.w)
+ ASM_VOLATILE_UNARY64(cvt.s.w)
break;
case CVTSD:
- ASM_VOLATILE_UNARY_DOUBLE(cvt.s.d)
+ ASM_VOLATILE_UNARY64(cvt.s.d)
break;
case CVTWS:
- ASM_VOLATILE_UNARY(cvt.w.s)
+ ASM_VOLATILE_UNARY64(cvt.w.s)
break;
case CVTWD:
- ASM_VOLATILE_UNARY_DOUBLE(cvt.w.d)
+ ASM_VOLATILE_UNARY64(cvt.w.d)
break;
case ROUNDWS:
- ASM_VOLATILE_UNARY(round.w.s)
+ ASM_VOLATILE_UNARY64(round.w.s)
break;
#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \
|| (__mips == 64)
case CEILLS:
- ASM_VOLATILE_UNARY(ceil.l.s)
+ ASM_VOLATILE_UNARY64(ceil.l.s)
break;
case CEILLD:
- ASM_VOLATILE_UNARY_DOUBLE(ceil.l.d)
+ ASM_VOLATILE_UNARY64(ceil.l.d)
break;
case CVTDL:
- ASM_VOLATILE_UNARY_DOUBLE(cvt.d.l)
+ ASM_VOLATILE_UNARY64(cvt.d.l)
break;
case CVTLS:
- ASM_VOLATILE_UNARY(cvt.l.s)
+ ASM_VOLATILE_UNARY64(cvt.l.s)
break;
case CVTLD:
- ASM_VOLATILE_UNARY_DOUBLE(cvt.l.d)
+ ASM_VOLATILE_UNARY64(cvt.l.d)
break;
case CVTSL:
- ASM_VOLATILE_UNARY_DOUBLE(cvt.s.l)
+ ASM_VOLATILE_UNARY64(cvt.s.l)
break;
case FLOORLS:
- ASM_VOLATILE_UNARY(floor.l.s)
+ ASM_VOLATILE_UNARY64(floor.l.s)
break;
case FLOORLD:
- ASM_VOLATILE_UNARY_DOUBLE(floor.l.d)
+ ASM_VOLATILE_UNARY64(floor.l.d)
break;
case ROUNDLS:
- ASM_VOLATILE_UNARY(round.l.s)
+ ASM_VOLATILE_UNARY64(round.l.s)
break;
case ROUNDLD:
- ASM_VOLATILE_UNARY_DOUBLE(round.l.d)
+ ASM_VOLATILE_UNARY64(round.l.d)
break;
case TRUNCLS:
- ASM_VOLATILE_UNARY(trunc.l.s)
+ ASM_VOLATILE_UNARY64(trunc.l.s)
break;
case TRUNCLD:
- ASM_VOLATILE_UNARY_DOUBLE(trunc.l.d)
+ ASM_VOLATILE_UNARY64(trunc.l.d)
break;
#endif
case ADDS:
- ASM_VOLATILE_BINARY(add.s)
+ ASM_VOLATILE_BINARY64(add.s)
break;
case ADDD:
- ASM_VOLATILE_BINARY_DOUBLE(add.d)
+ ASM_VOLATILE_BINARY64(add.d)
break;
case SUBS:
- ASM_VOLATILE_BINARY(sub.s)
+ ASM_VOLATILE_BINARY64(sub.s)
break;
case SUBD:
- ASM_VOLATILE_BINARY_DOUBLE(sub.d)
+ ASM_VOLATILE_BINARY64(sub.d)
break;
case DIVS:
- ASM_VOLATILE_BINARY(div.s)
+ ASM_VOLATILE_BINARY64(div.s)
break;
default:
vassert(0);
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Wed Feb 19 11:56:29 2014
@@ -72,6 +72,9 @@
disInstr_MIPS below. */
static Bool mode64 = False;
+/* CPU has FPU and 32 dbl. prec. FP registers. */
+static Bool fp_mode64 = False;
+
/* Define 1.0 in single and double precision. */
#define ONE_SINGLE 0x3F800000
#define ONE_DOUBLE 0x3FF0000000000000ULL
@@ -541,6 +544,11 @@
binop(Iop_Shr32, getFCSR(), mkU8(24+cc))), \
mkU32(0x1)));
+#define ILLEGAL_INSTRUCTON \
+ putPC(mkU32(guest_PC_curr_instr + 4)); \
+ dres.jk_StopHere = Ijk_SigILL; \
+ dres.whatNext = Dis_StopHere;
+
/*------------------------------------------------------------*/
/*--- Field helpers ---*/
/*------------------------------------------------------------*/
@@ -1105,22 +1113,30 @@
{
IRDirty *d;
IRTemp fcsr = newTemp(Ity_I32);
- /* IRExpr_BBPTR() => Need to pass pointer to guest
- state to helper. */
- d = unsafeIRDirty_1_N(fcsr, 0,
- "mips_dirtyhelper_calculate_FCSR",
- &mips_dirtyhelper_calculate_FCSR,
- mkIRExprVec_4(IRExpr_BBPTR(),
- mkU32(fs),
- mkU32(ft),
- mkU32(inst)));
+ /* IRExpr_BBPTR() => Need to pass pointer to guest state to helper. */
+ if (fp_mode64)
+ d = unsafeIRDirty_1_N(fcsr, 0,
+ "mips_dirtyhelper_calculate_FCSR_fp64",
+ &mips_dirtyhelper_calculate_FCSR_fp64,
+ mkIRExprVec_4(IRExpr_BBPTR(),
+ mkU32(fs),
+ mkU32(ft),
+ mkU32(inst)));
+ else
+ d = unsafeIRDirty_1_N(fcsr, 0,
+ "mips_dirtyhelper_calculate_FCSR_fp32",
+ &mips_dirtyhelper_calculate_FCSR_fp32,
+ mkIRExprVec_4(IRExpr_BBPTR(),
+ mkU32(fs),
+ mkU32(ft),
+ mkU32(inst)));
if (opN == 1) { /* Unary operation. */
/* Declare we're reading guest state. */
- if (!mode64 && !sz32)
- d->nFxState = 3;
- else
+ if (sz32 || fp_mode64)
d->nFxState = 2;
+ else
+ d->nFxState = 3;
vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read; /* read */
@@ -1128,22 +1144,19 @@
d->fxState[0].size = sizeof(UInt);
d->fxState[1].fx = Ifx_Read; /* read */
d->fxState[1].offset = floatGuestRegOffset(fs);
- if (mode64)
- d->fxState[1].size = sizeof(ULong);
- else
- d->fxState[1].size = sizeof(UInt);
+ d->fxState[1].size = sizeof(ULong);
- if (!mode64 && !sz32) {
+ if (!(sz32 || fp_mode64)) {
d->fxState[2].fx = Ifx_Read; /* read */
d->fxState[2].offset = floatGuestRegOffset(fs+1);
- d->fxState[2].size = sizeof(UInt);
+ d->fxState[2].size = sizeof(ULong);
}
} else if (opN == 2) { /* Binary operation. */
/* Declare we're reading guest state. */
- if (!mode64 && !sz32)
- d->nFxState = 5;
- else
+ if (sz32 || fp_mode64)
d->nFxState = 3;
+ else
+ d->nFxState = 5;
vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read; /* read */
@@ -1151,22 +1164,18 @@
d->fxState[0].size = sizeof(UInt);
d->fxState[1].fx = Ifx_Read; /* read */
d->fxState[1].offset = floatGuestRegOffset(fs);
+ d->fxState[1].size = sizeof(ULong);
d->fxState[2].fx = Ifx_Read; /* read */
d->fxState[2].offset = floatGuestRegOffset(ft);
- if (mode64) {
- d->fxState[1].size = sizeof(ULong);
- d->fxState[2].size = sizeof(ULong);
- } else {
- d->fxState[1].size = sizeof(UInt);
- d->fxState[2].size = sizeof(UInt);
- }
- if (!mode64 && !sz32) {
+ d->fxState[2].size = sizeof(ULong);
+
+ if (!(sz32 || fp_mode64)) {
d->fxState[3].fx = Ifx_Read; /* read */
d->fxState[3].offset = floatGuestRegOffset(fs+1);
- d->fxState[3].size = sizeof(UInt);
+ d->fxState[3].size = sizeof(ULong);
d->fxState[4].fx = Ifx_Read; /* read */
d->fxState[4].offset = floatGuestRegOffset(ft+1);
- d->fxState[4].size = sizeof(UInt);
+ d->fxState[4].size = sizeof(ULong);
}
}
@@ -1192,6 +1201,12 @@
stmt(IRStmt_Put(integerGuestRegOffset(archreg), e));
}
+static IRExpr *mkNarrowTo32(IRType ty, IRExpr * src)
+{
+ vassert(ty == Ity_I32 || ty == Ity_I64);
+ return ty == Ity_I64 ? unop(Iop_64to32, src) : src;
+}
+
static void putLO(IRExpr * e)
{
if (mode64) {
@@ -1285,12 +1300,6 @@
return 0;
}
-static IRExpr *mkNarrowTo32(IRType ty, IRExpr * src)
-{
- vassert(ty == Ity_I32 || ty == Ity_I64);
- return ty == Ity_I64 ? unop(Iop_64to32, src) : src;
-}
-
static IRExpr *getLoFromF64(IRType ty, IRExpr * src)
{
vassert(ty == Ity_F32 || ty == Ity_F64);
@@ -1386,21 +1395,21 @@
(UInt) branch_offset), OFFB_PC);
}
-static IRExpr *getFReg(UInt dregNo)
+static IRExpr *getFReg(UInt fregNo)
{
- vassert(dregNo < 32);
- IRType ty = mode64 ? Ity_F64 : Ity_F32;
- return IRExpr_Get(floatGuestRegOffset(dregNo), ty);
+ vassert(fregNo < 32);
+ IRType ty = fp_mode64 ? Ity_F64 : Ity_F32;
+ return IRExpr_Get(floatGuestRegOffset(fregNo), ty);
}
static IRExpr *getDReg(UInt dregNo)
{
- if (mode64) {
- vassert(dregNo < 32);
- IRType ty = Ity_F64;
- return IRExpr_Get(floatGuestRegOffset(dregNo), ty);
+ vassert(dregNo < 32);
+ if (fp_mode64) {
+ return IRExpr_Get(floatGuestRegOffset(dregNo), Ity_F64);
} else {
- vassert(dregNo < 32);
+ /* Read a floating point register pair and combine their contents into a
+ 64-bit value */
IRTemp t0 = newTemp(Ity_F32);
IRTemp t1 = newTemp(Ity_F32);
IRTemp t2 = newTemp(Ity_F64);
@@ -1423,14 +1432,14 @@
static void putFReg(UInt dregNo, IRExpr * e)
{
vassert(dregNo < 32);
- IRType ty = mode64 ? Ity_F64 : Ity_F32;
+ IRType ty = fp_mode64 ? Ity_F64 : Ity_F32;
vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e));
}
static void putDReg(UInt dregNo, IRExpr * e)
{
- if (mode64) {
+ if (fp_mode64) {
vassert(dregNo < 32);
IRType ty = Ity_F64;
vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
@@ -1725,7 +1734,7 @@
switch (fmt) {
case 0x10: { /* C.cond.S */
DIP("C.%s.S %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I32);
t1 = newTemp(Ity_I32);
t2 = newTemp(Ity_I32);
@@ -1740,7 +1749,8 @@
getFReg(ft))));
assign(ccIR, binop(Iop_CmpF64, mkexpr(tmp5), mkexpr(tmp6)));
- putHI(mkWidenFrom32(Ity_I64, mkexpr(ccIR), True));
+ putHI(mkWidenFrom32(mode64 ? Ity_I64: Ity_I32,
+ mkexpr(ccIR), True));
/* Map compare result from IR to MIPS
FP cmp result | MIPS | IR
--------------------------
@@ -1757,7 +1767,8 @@
binop(Iop_And32, binop(Iop_Xor32, mkexpr(ccIR),
binop(Iop_Shr32, mkexpr(ccIR), mkU8(6))),
mkU32(1))))));
- putLO(mkWidenFrom32(Ity_I64, mkexpr(ccMIPS), True));
+ putLO(mkWidenFrom32(mode64 ? Ity_I64: Ity_I32,
+ mkexpr(ccMIPS), True));
/* UN */
assign(t0, binop(Iop_And32, mkexpr(ccMIPS), mkU32(0x1)));
@@ -11829,7 +11840,7 @@
trap_code = get_code(cins);
function = get_function(cins);
IRType ty = mode64 ? Ity_I64 : Ity_I32;
- IRType tyF = mode64 ? Ity_F64 : Ity_F32;
+ IRType tyF = fp_mode64 ? Ity_F64 : Ity_F32;
ac = get_acNo(cins);
@@ -11862,110 +11873,119 @@
lastn = mkexpr(t0);
break;
- case 0x11: /* COP1 */
- {
+ case 0x11: { /* COP1 */
+ if (fmt == 0x3 && fd == 0 && function == 0) { /* MFHC1 */
+ DIP("mfhc1 r%d, f%d", rt, fs);
+ if (fp_mode64) {
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I32);
+ assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs)));
+ assign(t1, unop(Iop_64HIto32, mkexpr(t0)));
+ putIReg(rt, mkWidenFrom32(ty, mkexpr(t1), True));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
+ break;
+ } else if (fmt == 0x7 && fd == 0 && function == 0) { /* MTHC1 */
+ DIP("mthc1 r%d, f%d", rt, fs);
+ if (fp_mode64) {
+ t0 = newTemp(Ity_I64);
+ assign(t0, binop(Iop_32HLto64, getIReg(rt),
+ unop(Iop_ReinterpF32asI32,
+ getLoFromF64(Ity_F64 /* 32FPR mode. */,
+ getDReg(fs)))));
+ putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
+ break;
+ } else if (fmt == 0x8) { /* BC */
+ /* FcConditionalCode(bc1_cc) */
UInt bc1_cc = get_bc1_cc(cins);
- if (0x08 == fmt) {
- switch (fmt) {
- case 0x08: /* BC */
- {
- DIP("tf: %d, nd: %d", tf, nd);
- /* FcConditionalCode(bc1_cc) */
- t1 = newTemp(Ity_I1);
- t2 = newTemp(Ity_I32);
- t3 = newTemp(Ity_I1);
+ t1 = newTemp(Ity_I1);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I1);
- assign(t1, binop(Iop_CmpEQ32, mkU32(0), mkU32(bc1_cc)));
- assign(t2, IRExpr_ITE(mkexpr(t1),
- binop(Iop_And32,
- binop(Iop_Shr32, getFCSR(),
- mkU8(23)),
- mkU32(0x1)),
- binop(Iop_And32,
- binop(Iop_Shr32, getFCSR(),
- mkU8(24 + bc1_cc)),
- mkU32(0x1))
- ));
-
- if (tf == 1 && nd == 0) {
- /* branch on true */
- DIP("bc1t %d, %d", bc1_cc, imm);
- assign(t3, binop(Iop_CmpEQ32, mkU32(1), mkexpr(t2)));
- dis_branch(False, mkexpr(t3), imm, &bstmt);
- break;
- } else if (tf == 0 && nd == 0) {
- /* branch on false */
- DIP("bc1f %d, %d", bc1_cc, imm);
- assign(t3, binop(Iop_CmpEQ32, mkU32(0), mkexpr(t2)));
- dis_branch(False, mkexpr(t3), imm, &bstmt);
+ assign(t1, binop(Iop_CmpEQ32, mkU32(0), mkU32(bc1_cc)));
+ assign(t2, IRExpr_ITE(mkexpr(t1),
+ binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(), mkU8(23)),
+ mkU32(0x1)),
+ binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + bc1_cc)),
+ mkU32(0x1))));
+
+ if (tf == 1 && nd == 0) {
+ /* branch on true */
+ DIP("bc1t %d, %d", bc1_cc, imm);
+ assign(t3, binop(Iop_CmpEQ32, mkU32(1), mkexpr(t2)));
+ dis_branch(False, mkexpr(t3), imm, &bstmt);
+ break;
+ } else if (tf == 0 && nd == 0) {
+ /* branch on false */
+ DIP("bc1f %d, %d", bc1_cc, imm);
+ assign(t3, binop(Iop_CmpEQ32, mkU32(0), mkexpr(t2)));
+ dis_branch(False, mkexpr(t3), imm, &bstmt);
+ break;
+ } else if (nd == 1 && tf == 0) {
+ DIP("bc1fl %d, %d", bc1_cc, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, mkexpr(t2),
+ mkU32(0x0)), imm);
+ break;
+ } else if (nd == 1 && tf == 1) {
+ DIP("bc1tl %d, %d", bc1_cc, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpEQ32, mkexpr(t2),
+ mkU32(0x0)), imm);
+ break;
+ } else
+ goto decode_failure;
+ } else {
+ switch (function) {
+ case 0x4: { /* SQRT.fmt */
+ switch (fmt) {
+ case 0x10: { /* S */
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm,
+ getLoFromF64(tyF, getFReg(fs)))));
break;
- } else if (nd == 1 && tf == 0) {
- DIP("bc1fl %d, %d", bc1_cc, imm);
- lastn = dis_branch_likely(binop(Iop_CmpNE32, mkexpr(t2),
- mkU32(0x0)), imm);
- break;
- } else if (nd == 1 && tf == 1) {
- DIP("bc1tl %d, %d", bc1_cc, imm);
- lastn = dis_branch_likely(binop(Iop_CmpEQ32, mkexpr(t2),
- mkU32(0x0)), imm);
+ }
+ case 0x11: { /* D */
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs)));
break;
- } else
+ }
+ default:
goto decode_failure;
- }
-
- default:
- goto decode_failure;
- }
- } else {
- switch (function) {
-
- case 0x4: /* SQRT.fmt */
- {
- switch (fmt) {
- case 0x10: /* S */
- {
- IRExpr *rm = get_IR_roundingmode();
- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm,
- getLoFromF64(tyF, getFReg(fs)))));
- }
- break;
- case 0x11: /* D */
- {
- IRExpr *rm = get_IR_roundingmode();
- putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs)));
- }
- break;
}
}
break;
case 0x5: /* abs.fmt */
switch (fmt) {
- case 0x10: /* S */
- DIP("abs.s f%d, f%d", fd, fs);
- putFReg(fd, mkWidenFromF32(tyF, unop(Iop_AbsF32,
- getLoFromF64(tyF, getFReg(fs)))));
- break;
- case 0x11: /* D */
- DIP("abs.d f%d, f%d", fd, fs);
- putDReg(fd, unop(Iop_AbsF64, getDReg(fs)));
- break;
- default:
- goto decode_failure;
+ case 0x10: /* S */
+ DIP("abs.s f%d, f%d", fd, fs);
+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_AbsF32,
+ getLoFromF64(tyF, getFReg(fs)))));
+ break;
+ case 0x11: /* D */
+ DIP("abs.d f%d, f%d", fd, fs);
+ putDReg(fd, unop(Iop_AbsF64, getDReg(fs)));
+ break;
+ default:
+ goto decode_failure;
}
break; /* case 0x5 */
case 0x02: /* MUL.fmt */
switch (fmt) {
- case 0x11: /* D */
- {
+ case 0x11: { /* D */
DIP("mul.d f%d, f%d, f%d", fd, fs, ft);
IRExpr *rm = get_IR_roundingmode();
putDReg(fd, triop(Iop_MulF64, rm, getDReg(fs),
getDReg(ft)));
break;
}
- case 0x10: /* S */
- {
+ case 0x10: { /* S */
DIP("mul.s f%d, f%d, f%d", fd, fs, ft);
IRExpr *rm = get_IR_roundingmode();
putFReg(fd, mkWidenFromF32(tyF, triop(Iop_MulF32, rm,
@@ -11973,23 +11993,21 @@
getLoFromF64(tyF, getFReg(ft)))));
break;
}
- default:
- goto decode_failure;
+ default:
+ goto decode_failure;
}
break; /* MUL.fmt */
case 0x03: /* DIV.fmt */
switch (fmt) {
- case 0x11: /* D */
- {
+ case 0x11: { /* D */
DIP("div.d f%d, f%d, f%d", fd, fs, ft);
IRExpr *rm = get_IR_roundingmode();
putDReg(fd, triop(Iop_DivF64, rm, getDReg(fs),
getDReg(ft)));
break;
}
- case 0x10: /* S */
- {
+ case 0x10: { /* S */
DIP("div.s f%d, f%d, f%d", fd, fs, ft);
calculateFCSR(fs, ft, DIVS, False, 2);
IRExpr *rm = get_IR_roundingmode();
@@ -11998,8 +12016,8 @@
getLoFromF64(tyF, getFReg(ft)))));
break;
}
- default:
- goto decode_failure;
+ default:
+ goto decode_failure;
}
break; /* DIV.fmt */
@@ -12031,8 +12049,8 @@
switch (fmt) {
case 0x11: /* D */
DIP("mov.d f%d, f%d", fd, fs);
- if (mode64) {
- putFReg(fd, getFReg(fs));
+ if (fp_mode64) {
+ putDReg(fd, getDReg(fs));
} else {
putFReg(fd, getFReg(fs));
putFReg(fd + 1, getFReg(fs + 1));
@@ -12067,19 +12085,27 @@
switch (fmt) {
case 0x10: /* S */
DIP("round.l.s f%d, f%d", fd, fs);
- calculateFCSR(fs, 0, ROUNDLS, True, 1);
- t0 = newTemp(Ity_I64);
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, ROUNDLS, True, 1);
+ t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_F32toI64S, mkU32(0x0),
- getLoFromF64(Ity_F64, getFReg(fs))));
+ assign(t0, binop(Iop_F32toI64S, mkU32(0x0),
+ getLoFromF64(Ity_F64, getFReg(fs))));
- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
- break;
+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
+ break;
case 0x11: /* D */
DIP("round.l.d f%d, f%d", fd, fs);
- calculateFCSR(fs, 0, ROUNDLD, False, 1);
- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x0),
- getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, ROUNDLD, False, 1);
+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x0),
+ getDReg(fs)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
goto decode_failure;
@@ -12091,18 +12117,26 @@
switch (fmt) {
case 0x10: /* S */
DIP("trunc.l.s f%d, f%d", fd, fs);
- calculateFCSR(fs, 0, TRUNCLS, True, 1);
- t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_F32toI64S, mkU32(0x3),
- getLoFromF64(Ity_F64, getFReg(fs))));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, TRUNCLS, True, 1);
+ t0 = newTemp(Ity_I64);
+ assign(t0, binop(Iop_F32toI64S, mkU32(0x3),
+ getLoFromF64(Ity_F64, getFReg(fs))));
- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x11: /* D */
DIP("trunc.l.d f%d, f%d", fd, fs);
- calculateFCSR(fs, 0, TRUNCLD, False, 1);
- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x3),
- getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, TRUNCLD, False, 1);
+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x3),
+ getDReg(fs)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
goto decode_failure;
@@ -12139,7 +12173,6 @@
switch (fmt) {
case 0x10: /* S */
DIP("movn.s f%d, f%d, r%d", fd, fs, rt);
-
t1 = newTemp(Ity_F64);
t2 = newTemp(Ity_F64);
t3 = newTemp(Ity_I1);
@@ -12149,13 +12182,19 @@
assign(t2, getFReg(fd));
assign(t3, binop(Iop_CmpNE64, mkU64(0), getIReg(rt)));
} else {
- assign(t1, unop(Iop_F32toF64, getFReg(fs)));
- assign(t2, unop(Iop_F32toF64, getFReg(fd)));
- assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt)));
+ if (fp_mode64) {
+ assign(t1, getFReg(fs));
+ assign(t2, getFReg(fd));
+ assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt)));
+ } else {
+ assign(t1, unop(Iop_F32toF64, getFReg(fs)));
+ assign(t2, unop(Iop_F32toF64, getFReg(fd)));
+ assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt)));
+ }
}
assign(t4, IRExpr_ITE(mkexpr(t3), mkexpr(t1), mkexpr(t2)));
- if (mode64) {
+ if (fp_mode64) {
IRTemp f = newTemp(Ity_F64);
IRTemp fd_hi = newTemp(Ity_I32);
t5 = newTemp(Ity_I64);
@@ -12163,7 +12202,7 @@
assign(fd_hi, unop(Iop_64HIto32, unop(Iop_ReinterpF64asI64,
mkexpr(f))));
- assign(t5, mkWidenFrom32(ty, unop(Iop_64to32,
+ assign(t5, mkWidenFrom32(Ity_I64, unop(Iop_64to32,
unop(Iop_ReinterpF64asI64, mkexpr(t4))), True));
putFReg(fd, unop (Iop_ReinterpI64asF64, mkexpr(t5)));
@@ -12198,10 +12237,13 @@
t2 = newTemp(Ity_F64);
t3 = newTemp(Ity_I1);
t4 = newTemp(Ity_F64);
- if (mode64) {
+ if (fp_mode64) {
assign(t1, getFReg(fs));
assign(t2, getFReg(fd));
- assign(t3, binop(Iop_CmpEQ64, mkU64(0), getIReg(rt)));
+ if (mode64)
+ assign(t3, binop(Iop_CmpEQ64, mkU64(0), getIReg(rt)));
+ else
+ assign(t3, binop(Iop_CmpEQ32, mkU32(0), getIReg(rt)));
} else {
assign(t1, unop(Iop_F32toF64, getFReg(fs)));
assign(t2, unop(Iop_F32toF64, getFReg(fd)));
@@ -12209,14 +12251,14 @@
}
assign(t4, IRExpr_ITE(mkexpr(t3), mkexpr(t1), mkexpr(t2)));
- if (mode64) {
+ if (fp_mode64) {
IRTemp f = newTemp(Ity_F64);
IRTemp fd_hi = newTemp(Ity_I32);
t7 = newTemp(Ity_I64);
assign(f, getFReg(fd));
assign(fd_hi, unop(Iop_64HIto32,
unop(Iop_ReinterpF64asI64, mkexpr(f))));
- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32,
+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32,
unop(Iop_ReinterpF64asI64, mkexpr(t4))), True));
putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t7)));
@@ -12279,7 +12321,7 @@
t6 = newTemp(Ity_F64);
t7 = newTemp(Ity_I64);
- if (mode64) {
+ if (fp_mode64) {
assign(t5, getFReg(fs));
assign(t6, getFReg(fd));
} else {
@@ -12303,13 +12345,13 @@
assign(t4, IRExpr_ITE(mkexpr(t3),
mkexpr(t5), mkexpr(t6)));
- if (mode64) {
+ if (fp_mode64) {
IRTemp f = newTemp(Ity_F64);
IRTemp fd_hi = newTemp(Ity_I32);
assign(f, getFReg(fd));
assign(fd_hi, unop(Iop_64HIto32,
unop(Iop_ReinterpF64asI64, mkexpr(f))));
- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32,
+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32,
unop(Iop_ReinterpF64asI64, mkexpr(t4))),
True));
@@ -12359,7 +12401,7 @@
t5 = newTemp(Ity_F64);
t6 = newTemp(Ity_F64);
- if (mode64) {
+ if (fp_mode64) {
assign(t5, getFReg(fs));
assign(t6, getFReg(fd));
} else {
@@ -12383,14 +12425,14 @@
assign(t4, IRExpr_ITE(mkexpr(t3),
mkexpr(t5), mkexpr(t6)));
- if (mode64) {
+ if (fp_mode64) {
IRTemp f = newTemp(Ity_F64);
IRTemp fd_hi = newTemp(Ity_I32);
t7 = newTemp(Ity_I64);
assign(f, getFReg(fd));
assign(fd_hi, unop(Iop_64HIto32,
unop(Iop_ReinterpF64asI64, mkexpr(f))));
- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32,
+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32,
unop(Iop_ReinterpF64asI64, mkexpr(t4))),
True));
@@ -12427,10 +12469,10 @@
case 0x4: /* MTC1 (Move Word to Floating Point) */
DIP("mtc1 r%d, f%d", rt, fs);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I32);
t1 = newTemp(Ity_F32);
- assign(t0, unop(Iop_64to32, getIReg(rt)));
+ assign(t0, mkNarrowTo32(ty, getIReg(rt)));
assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
putFReg(fs, mkWidenFromF32(tyF, mkexpr(t1)));
@@ -12446,7 +12488,7 @@
case 0x0: /* MFC1 */
DIP("mfc1 r%d, f%d", rt, fs);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
@@ -12570,7 +12612,7 @@
case 0x10: /* S */
DIP("cvt.d.s f%d, f%d", fd, fs);
calculateFCSR(fs, 0, CVTDS, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12590,7 +12632,7 @@
case 0x14:
DIP("cvt.d.w %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTDW, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12609,7 +12651,7 @@
}
case 0x15: { /* L */
- if (mode64) {
+ if (fp_mode64) {
DIP("cvt.d.l %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTDL, False, 1);
t0 = newTemp(Ity_I64);
@@ -12631,7 +12673,7 @@
case 0x14: /* W */
DIP("cvt.s.w %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTSW, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12653,14 +12695,10 @@
case 0x11: /* D */
DIP("cvt.s.d %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTSD, False, 1);
- if (mode64) {
- t0 = newTemp(Ity_F32);
- assign(t0, binop(Iop_F64toF32, get_IR_roundingmode(),
- getFReg(fs)));
- putFReg(fd, mkWidenFromF32(tyF, mkexpr(t0)));
- } else
- putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
- getDReg(fs)));
+ t0 = newTemp(Ity_F32);
+ assign(t0, binop(Iop_F64toF32, get_IR_roundingmode(),
+ getDReg(fs)));
+ putFReg(fd, mkWidenFromF32(tyF, mkexpr(t0)));
break;
case 0x15: /* L */
@@ -12683,33 +12721,23 @@
case 0x10: /* S */
DIP("cvt.w.s %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTWS, True, 1);
- if (mode64) {
- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_RoundF32toInt,
- get_IR_roundingmode(), getLoFromF64(tyF,
- getFReg(fs)))));
- } else
- putFReg(fd, binop(Iop_RoundF32toInt, get_IR_roundingmode(),
- getFReg(fs)));
+ putFReg(fd,
+ mkWidenFromF32(tyF,
+ binop(Iop_RoundF32toInt,
+ get_IR_roundingmode(),
+ getLoFromF64(tyF, getFReg(fs))))
+ );
break;
case 0x11:
DIP("cvt.w.d %d, %d", fd, fs);
calculateFCSR(fs, 0, CVTWD, False, 1);
- if (mode64) {
- t0 = newTemp(Ity_I32);
- t1 = newTemp(Ity_F32);
- assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(),
- getFReg(fs)));
- assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
- putFReg(fd, mkWidenFromF32(tyF, mkexpr(t1)));
- } else {
- t0 = newTemp(Ity_I32);
-
- assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(),
- getDReg(fs)));
-
- putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
- }
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_F32);
+ assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(),
+ getDReg(fs)));
+ assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ putFReg(fd, mkWidenFromF32(tyF, mkexpr(t1)));
break;
default:
@@ -12722,20 +12750,28 @@
switch (fmt) {
case 0x10: /* S */
DIP("cvt.l.s %d, %d", fd, fs);
- calculateFCSR(fs, 0, CVTLS, True, 1);
- t0 = newTemp(Ity_I64);
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CVTLS, True, 1);
+ t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_F32toI64S, get_IR_roundingmode(),
- getLoFromF64(Ity_F64, getFReg(fs))));
+ assign(t0, binop(Iop_F32toI64S, get_IR_roundingmode(),
+ getLoFromF64(tyF, getFReg(fs))));
- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x11: { /* D */
DIP("cvt.l.d %d, %d", fd, fs);
- calculateFCSR(fs, 0, CVTLD, False, 1);
- putFReg(fd, binop(Iop_RoundF64toInt,
- get_IR_roundingmode(), getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CVTLD, False, 1);
+ putDReg(fd, binop(Iop_RoundF64toInt,
+ get_IR_roundingmode(), getDReg(fs)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
}
@@ -12748,20 +12784,28 @@
switch (fmt) {
case 0x10: /* S */
DIP("floor.l.s %d, %d", fd, fs);
- calculateFCSR(fs, 0, FLOORLS, True, 1);
- t0 = newTemp(Ity_I64);
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, FLOORLS, True, 1);
+ t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_F32toI64S, mkU32(0x1),
- getLoFromF64(Ity_F64, getFReg(fs))));
+ assign(t0, binop(Iop_F32toI64S, mkU32(0x1),
+ getLoFromF64(tyF, getFReg(fs))));
- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x11: /* D */
DIP("floor.l.d %d, %d", fd, fs);
- calculateFCSR(fs, 0, FLOORLD, False, 1);
- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x1),
- getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, FLOORLD, False, 1);
+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x1),
+ getDReg(fs)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
goto decode_failure;
@@ -12773,7 +12817,7 @@
case 0x10: /* S */
DIP("round.w.s f%d, f%d", fd, fs);
calculateFCSR(fs, 0, ROUNDWS, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12797,7 +12841,7 @@
case 0x11: /* D */
DIP("round.w.d f%d, f%d", fd, fs);
calculateFCSR(fs, 0, ROUNDWD, False, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I32);
assign(t0, binop(Iop_F64toI32S, mkU32(0x0),
getDReg(fs)));
@@ -12823,7 +12867,7 @@
case 0x10: /* S */
DIP("floor.w.s f%d, f%d", fd, fs);
calculateFCSR(fs, 0, FLOORWS, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12847,7 +12891,7 @@
case 0x11: /* D */
DIP("floor.w.d f%d, f%d", fd, fs);
calculateFCSR(fs, 0, FLOORWD, False, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I32);
assign(t0, binop(Iop_F64toI32S, mkU32(0x1),
getDReg(fs)));
@@ -12874,7 +12918,7 @@
case 0x10: /* S */
DIP("trunc.w.s %d, %d", fd, fs);
calculateFCSR(fs, 0, TRUNCWS, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12897,7 +12941,7 @@
case 0x11: /* D */
DIP("trunc.w.d %d, %d", fd, fs);
calculateFCSR(fs, 0, TRUNCWD, False, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I32);
assign(t0, binop(Iop_F64toI32S, mkU32(0x3),
@@ -12925,7 +12969,7 @@
case 0x10: /* S */
DIP("ceil.w.s %d, %d", fd, fs);
calculateFCSR(fs, 0, CEILWS, True, 1);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
t3 = newTemp(Ity_F32);
@@ -12949,7 +12993,7 @@
case 0x11: /* D */
DIP("ceil.w.d %d, %d", fd, fs);
calculateFCSR(fs, 0, CEILWD, False, 1);
- if (!mode64) {
+ if (!fp_mode64) {
t0 = newTemp(Ity_I32);
assign(t0, binop(Iop_F64toI32S, mkU32(0x2),
getDReg(fs)));
@@ -12972,20 +13016,28 @@
switch (fmt) {
case 0x10: /* S */
DIP("ceil.l.s %d, %d", fd, fs);
- calculateFCSR(fs, 0, CEILLS, True, 1);
- t0 = newTemp(Ity_I64);
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CEILLS, True, 1);
+ t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_F32toI64S, mkU32(0x2),
- getLoFromF64(Ity_F64, getFReg(fs))));
+ assign(t0, binop(Iop_F32toI64S, mkU32(0x2),
+ getLoFromF64(tyF, getFReg(fs))));
- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x11: /* D */
DIP("ceil.l.d %d, %d", fd, fs);
- calculateFCSR(fs, 0, CEILLD, False, 1);
- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x2),
- getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CEILLD, False, 1);
+ putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x2),
+ getFReg(fs)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
@@ -13061,17 +13113,24 @@
case 0x31: /* LWC1 */
/* Load Word to Floating Point - LWC1 (MIPS32) */
DIP("lwc1 f%d, %d(r%d)", ft, imm, rs);
- if (mode64) {
- t0 = newTemp(Ity_I64);
+ if (fp_mode64) {
t1 = newTemp(Ity_F32);
t2 = newTemp(Ity_I64);
- /* new LO */
- assign(t0, binop(Iop_Add64, getIReg(rs),
- mkU64(extend_s_16to64(imm))));
+ if (mode64) {
+ t0 = newTemp(Ity_I64);
+ /* new LO */
+ assign(t0, binop(Iop_Add64, getIReg(rs),
+ mkU64(extend_s_16to64(imm))));
+ } else {
+ t0 = newTemp(Ity_I32);
+ /* new LO */
+ assign(t0, binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm))));
+ }
assign(t1, load(Ity_F32, mkexpr(t0)));
- assign(t2, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32,
- mkexpr(t1)), True));
- putFReg(ft, unop(Iop_ReinterpI64asF64, mkexpr(t2)));
+ assign(t2, mkWidenFrom32(Ity_I64, unop(Iop_ReinterpF32asI32,
+ mkexpr(t1)), True));
+ putDReg(ft, unop(Iop_ReinterpI64asF64, mkexpr(t2)));
} else {
t0 = newTemp(Ity_I32);
assign(t0, binop(Iop_Add32, getIReg(rs),
@@ -13082,7 +13141,7 @@
case 0x39: /* SWC1 */
DIP("swc1 f%d, %d(r%d)", ft, imm, rs);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t2 = newTemp(Ity_I32);
LOAD_STORE_PATTERN;
@@ -13101,22 +13160,16 @@
case 0x35:
/* Load Doubleword to Floating Point - LDC1 (MIPS32) */
- LOAD_STORE_PATTERN;
- if (mode64)
- putFReg(ft, load(Ity_F64, mkexpr(t1)));
- else
- putDReg(ft, load(Ity_F64, mkexpr(t1)));
DIP("ldc1 f%d, %d(%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putDReg(ft, load(Ity_F64, mkexpr(t1)));
break;
case 0x3D:
/* Store Doubleword from Floating Point - SDC1 */
- LOAD_STORE_PATTERN;
- if (mode64)
- store(mkexpr(t1), getFReg(ft));
- else
- store(mkexpr(t1), getDReg(ft));
DIP("sdc1 f%d, %d(%d)", ft, imm, rs);
+ LOAD_STORE_PATTERN;
+ store(mkexpr(t1), getDReg(ft));
break;
case 0x23: /* LW */
@@ -13175,19 +13228,20 @@
case 0x0: { /* LWXC1 */
/* Load Word Indexed to Floating Point - LWXC1 (MIPS32r2) */
DIP("lwxc1 f%d, r%d(r%d)", fd, rt, rs);
- if (mode64) {
+ if (fp_mode64) {
t0 = newTemp(Ity_I64);
t1 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
t3 = newTemp(Ity_F32);
t4 = newTemp(Ity_I64);
+ t2 = newTemp(ty);
/* new LO */
- assign(t2, binop(Iop_Add64, getIReg(rs), getIReg(rt)));
+ assign(t2, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs),
+ getIReg(rt)));
assign(t3, load(Ity_F32, mkexpr(t2)));
- assign(t4, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32,
- mkexpr(t3)), True));
+ assign(t4, mkWidenFrom32(Ity_I64, unop(Iop_ReinterpF32asI32,
+ mkexpr(t3)), True));
putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t4)));
} else {
@@ -13201,10 +13255,11 @@
case 0x1: { /* LDXC1 */
/* Load Doubleword Indexed to Floating Point
LDXC1 (MIPS32r2 and MIPS64) */
- if (mode64) {
+ if (fp_mode64) {
DIP("ldxc1 f%d, r%d(r%d)", fd, rt, rs);
- t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt)));
+ t0 = newTemp(ty);
+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs),
+ getIReg(rt)));
putFReg(fd, load(Ity_F64, mkexpr(t0)));
break;
} else {
@@ -13238,10 +13293,10 @@
case 0x8: { /* Store Word Indexed from Floating Point - SWXC1 */
DIP("swxc1 f%d, r...
[truncated message content] |
|
From: <sv...@va...> - 2014-02-19 11:16:18
|
Author: florian
Date: Wed Feb 19 11:16:00 2014
New Revision: 13816
Log:
Fix BZ #327212. Check for absolute path name at the end of
expand_file_name -- not at the beginning.
Modified:
trunk/NEWS
trunk/coregrind/m_options.c
trunk/docs/internals/3_9_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Feb 19 11:16:00 2014
@@ -39,6 +39,7 @@
326444 Cavium MIPS Octeon Specific Load Indexed Instructions
326462 Refactor vgdb to isolate invoker stuff into separate module
326983 Clear direction flag after tests on amd64.
+327212 Do not prepend the current directory to absolute path names.
327238 Callgrind Assertion 'passed <= last_bb->cjmp_count' failed
327284 s390x: Fix translation of the risbg instruction
327837 dwz compressed alternate .debug_info and .debug_str not read correctly
Modified: trunk/coregrind/m_options.c
==============================================================================
--- trunk/coregrind/m_options.c (original)
+++ trunk/coregrind/m_options.c Wed Feb 19 11:16:00 2014
@@ -168,18 +168,8 @@
goto bad;
}
- // If 'format' starts with a '/', do not prefix with startup dir.
- if (format[0] != '/') {
- j += VG_(strlen)(base_dir);
- }
-
- // The 10 is slop, it should be enough in most cases.
- len = j + VG_(strlen)(format) + 10;
+ len = VG_(strlen)(format) + 1;
out = VG_(malloc)( "options.efn.1", len );
- if (format[0] != '/') {
- VG_(strcpy)(out, base_dir);
- out[j++] = '/';
- }
#define ENSURE_THIS_MUCH_SPACE(x) \
if (j + x >= len) { \
@@ -261,6 +251,18 @@
ENSURE_THIS_MUCH_SPACE(1);
out[j++] = 0;
+ // If 'out' is not an absolute path name, prefix it with the startup dir.
+ if (out[0] != '/') {
+ len = VG_(strlen)(base_dir) + 1 + VG_(strlen)(out) + 1;
+
+ HChar *absout = VG_(malloc)("options.efn.4", len);
+ VG_(strcpy)(absout, base_dir);
+ VG_(strcat)(absout, "/");
+ VG_(strcat)(absout, out);
+ VG_(free)(out);
+ out = absout;
+ }
+
return out;
bad: {
Modified: trunk/docs/internals/3_9_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_9_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_9_BUGSTATUS.txt Wed Feb 19 11:16:00 2014
@@ -38,7 +38,6 @@
327138 valgrind.h __VALGRIND_MINOR__ says 8, in 3.9.0 tarball
327151 valgrind appears to stop compiling when it enters the drd directory
327155 Valgrind compilation hang on MIPS
-327212 expand_file_name prepends current directory when expansion starts with /
327223 Support for Cavium MIPS Octeon Atomic and Count Instructions
327238 assertion failure in Callgrind: bbcc.c:585 (vgCallgrind_setup_bbcc): Assertion 'passed <= last_bb->cjmp_count' failed
327284 s390x VEX miscompilation of -march=z10 binary
|
|
From: Bart V. A. <bva...@ac...> - 2014-02-19 07:58:14
|
On 02/19/14 04:19, Maran Pakkirisamy wrote: > valgrind revision: 13815 > VEX revision: 2820 > C compiler: gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-3) > GDB: GNU gdb (GDB) Red Hat Enterprise Linux (7.2-60.el6) > Assembler: GNU assembler version 2.20.51.0.2-5.36.el6 20100205 > C library: GNU C Library stable release version 2.12 > uname -mrs: Linux 2.6.32-358.el6.s390x s390x > Vendor version: Red Hat Enterprise Linux Server release 6.4 (Santiago) > > Nightly build on rhels390 ( RHEL 6.4 with gcc 4.4.7 on zEC12 (s390x) ) > Started at 2014-02-19 03:45:25 CET > Ended at 2014-02-19 04:19:47 CET > Results differ from 24 hours ago > > ================================================= > ./valgrind-new/drd/tests/pth_create_chain.stderr.diff ================================================= > --- pth_create_chain.stderr.exp 2014-02-19 03:56:26.000000000 +0100 > +++ pth_create_chain.stderr.out 2014-02-19 04:05:32.000000000 +0100 > @@ -1,3 +1,259 @@ > > > -ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) > +valgrind: m_threadstate.c:95 (vgPlain_get_ThreadState): Assertion 'VG_(threads)[tid].tid == tid' failed. > + at 0x........: report_and_quit (m_libcassert.c:?) > + by 0x........: vgPlain_assert_fail (m_libcassert.c:?) > + by 0x........: vgPlain_get_ThreadState (m_threadstate.c:?) > + by 0x........: vgSysWrap_s390x_linux_sys_clone_before (syswrap-s390x-linux.c:217) > + by 0x........: vgPlain_client_syscall (syswrap-main.c:1585) > + by 0x........: handle_syscall (scheduler.c:?) Hello Maran, Can you have a closer look at this ? This failure occurs on s390 only. There might be an issue with thread handling in the core s390 Valgrind code. Thanks, Bart. |
|
From: Philippe W. <phi...@sk...> - 2014-02-19 05:40:55
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora (7.5.1-37.fc18) Assembler: GNU assembler version 2.23.51.0.1-7.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.8.8-202.fc18.ppc64p7 ppc64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on gcc110 ( Fedora release 18 (Spherical Cow), ppc64 ) Started at 2014-02-18 20:00:14 PST Ended at 2014-02-18 21:37:54 PST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 575 tests, 36 stderr failures, 7 stdout failures, 0 stderrB failures, 0 stdoutB failures, 2 post failures == memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/ppc64/power_ISA2_05 (stdout) memcheck/tests/supp_unknown (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) none/tests/ppc32/jm-vmx (stdout) none/tests/ppc32/jm-vmx (stderr) none/tests/ppc32/test_isa_2_06_part2 (stdout) none/tests/ppc32/test_isa_2_06_part2 (stderr) none/tests/ppc64/jm-vmx (stdout) none/tests/ppc64/jm-vmx (stderr) none/tests/ppc64/test_isa_2_06_part2 (stdout) none/tests/ppc64/test_isa_2_06_part2 (stderr) helgrind/tests/annotate_rwlock (stderr) helgrind/tests/free_is_write (stderr) helgrind/tests/hg02_deadlock (stderr) helgrind/tests/hg03_inherit (stderr) helgrind/tests/hg04_race (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/locked_vs_unlocked1_fwd (stderr) helgrind/tests/locked_vs_unlocked1_rev (stderr) helgrind/tests/locked_vs_unlocked2 (stderr) helgrind/tests/locked_vs_unlocked3 (stderr) helgrind/tests/pth_barrier1 (stderr) helgrind/tests/pth_barrier2 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/pth_destroy_cond (stderr) helgrind/tests/rwlock_race (stderr) helgrind/tests/tc01_simple_race (stderr) helgrind/tests/tc05_simple_race (stderr) helgrind/tests/tc06_two_races (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) helgrind/tests/tc14_laog_dinphils (stderr) helgrind/tests/tc16_byterace (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc19_shadowmem (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc21_pthonce (stderr) helgrind/tests/tc22_exit_w_lock (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.22s no: 1.6s ( 7.0x, -----) me: 2.9s (13.2x, -----) ca:18.1s (82.1x, -----) he: 1.9s ( 8.6x, -----) ca: 5.3s (24.2x, -----) dr: 1.9s ( 8.5x, -----) ma: 2.2s (10.2x, -----) bigcode1 valgrind-old:0.22s no: 1.7s ( 7.8x,-10.3%) me: 3.1s (14.2x, -7.2%) ca:18.1s (82.0x, 0.1%) he: 1.7s ( 7.9x, 8.5%) ca: 5.3s (24.0x, 0.9%) dr: 1.7s ( 7.8x, 8.1%) ma: 2.1s ( 9.6x, 5.8%) -- bigcode2 -- bigcode2 valgrind-new:0.23s no: 1.6s ( 6.7x, -----) me: 3.5s (15.4x, -----) ca:18.1s (78.9x, -----) he: 2.1s ( 9.2x, -----) ca: 5.4s (23.6x, -----) dr: 1.8s ( 8.0x, -----) ma: 2.1s ( 9.2x, -----) bigcode2 valgrind-old:0.23s no: 1.5s ( 6.6x, 1.9%) me: 3.2s (13.8x, 10.7%) ca:18.2s (79.2x, -0.3%) he: 2.1s ( 9.2x, -0.5%) ca: 5.4s (23.5x, 0.6%) dr: 1.9s ( 8.0x, -0.5%) ma: 2.1s ( 9.3x, -0.9%) -- bz2 -- bz2 valgrind-new:0.72s no: 4.6s ( 6.3x, -----) me:11.8s (16.3x, -----) ca:26.1s (36.2x, -----) he:14.9s (20.7x, -----) ca:24.2s (33.6x, -----) dr:20.3s (28.2x, -----) ma: 4.7s ( 6.5x, -----) bz2 valgrind-old:0.72s no: 4.5s ( 6.3x, 0.4%) me:11.8s (16.4x, -0.6%) ca:26.1s (36.2x, 0.1%) he:14.7s (20.4x, 1.2%) ca:24.5s (34.1x, -1.3%) dr:20.4s (28.3x, -0.2%) ma: 4.7s ( 6.5x, -0.6%) -- fbench -- fbench valgrind-new:0.34s no: 2.1s ( 6.2x, -----) me: 5.2s (15.4x, -----) ca: 8.5s (24.9x, -----) he: 5.2s (15.4x, -----) ca: 7.5s (22.0x, -----) dr: 4.9s (14.4x, -----) ma: 2.1s ( 6.3x, -----) fbench valgrind-old:0.34s no: 2.1s ( 6.2x, -1.0%) me: 5.3s (15.6x, -1.7%) ca: 8.5s (24.9x, -0.1%) he: 5.2s (15.4x, 0.4%) ca: 7.5s (22.0x, 0.0%) dr: 4.9s (14.4x, 0.0%) ma: 2.1s ( 6.3x, 0.5%) -- ffbench -- ffbench valgrind-new:0.45s no: 1.3s ( 2.9x, -----) me: 2.5s ( 5.7x, -----) ca: 2.5s ( 5.6x, -----) he: 7.3s (16.3x, -----) ca: 7.3s (16.2x, -----) dr: 5.0s (11.1x, -----) ma: 1.1s ( 2.4x, -----) ffbench valgrind-old:0.45s no: 1.3s ( 2.9x, 0.0%) me: 2.6s ( 5.7x, -0.4%) ca: 2.5s ( 5.6x, 0.0%) he: 7.3s (16.2x, 0.4%) ca: 7.3s (16.3x, -0.4%) dr: 5.0s (11.2x, -1.0%) ma: 1.0s ( 2.2x, 8.2%) -- heap -- heap valgrind-new:0.41s no: 2.4s ( 5.9x, -----) me:10.1s (24.5x, -----) ca:13.1s (31.9x, -----) he:11.7s (28.6x, -----) ca:12.2s (29.6x, -----) dr: 8.5s (20.6x, -----) ma: 8.8s (21.4x, -----) heap valgrind-old:0.41s no: 2.4s ( 6.0x, -0.4%) me:10.1s (24.7x, -0.6%) ca:13.1s (32.0x, -0.2%) he:11.9s (29.0x, -1.2%) ca:12.1s (29.6x, 0.1%) dr: 8.5s (20.8x, -0.6%) ma: 8.7s (21.3x, 0.3%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.42s no: 2.6s ( 6.1x, -----) me:14.1s (33.7x, -----) ca:14.2s (33.7x, -----) he:13.2s (31.5x, -----) ca:13.2s (31.4x, -----) dr: 9.3s (22.1x, -----) ma: 9.0s (21.4x, -----) heap_pdb4 valgrind-old:0.42s no: 2.6s ( 6.3x, -2.7%) me:14.2s (33.8x, -0.4%) ca:14.1s (33.5x, 0.7%) he:13.0s (31.0x, 1.4%) ca:13.1s (31.3x, 0.4%) dr: 9.4s (22.3x, -0.8%) ma: 8.9s (21.2x, 1.1%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.5s (17.7x, -----) me: 2.2s (73.7x, -----) ca: 1.9s (62.0x, -----) he: 1.8s (60.3x, -----) ca: 1.9s (62.0x, -----) dr: 1.6s (52.7x, -----) ma: 1.6s (52.3x, -----) many-loss-records valgrind-old:0.03s no: 0.5s (17.7x, 0.0%) me: 2.2s (73.7x, 0.0%) ca: 1.9s (62.7x, -1.1%) he: 1.8s (60.7x, -0.6%) ca: 1.9s (62.0x, 0.0%) dr: 1.6s (52.7x, 0.0%) ma: 1.6s (52.7x, -0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.7s (10.4x, -----) me: 3.5s (49.4x, -----) ca: 4.7s (66.9x, -----) he: 4.8s (68.7x, -----) ca: 2.9s (41.4x, -----) dr: 2.3s (33.0x, -----) ma: 2.3s (32.3x, -----) many-xpts valgrind-old:0.07s no: 0.7s (10.6x, -1.4%) me: 3.5s (49.3x, 0.3%) ca: 4.7s (66.7x, 0.2%) he: 4.8s (68.6x, 0.2%) ca: 2.9s (41.3x, 0.3%) dr: 2.3s (33.1x, -0.4%) ma: 2.3s (32.4x, -0.4%) -- sarp -- sarp valgrind-new:0.02s no: 0.4s (20.0x, -----) me: 3.1s (157.5x, -----) ca: 2.9s (146.0x, -----) he:11.0s (552.0x, -----) ca: 1.7s (85.5x, -----) dr: 1.1s (53.5x, -----) ma: 0.4s (20.5x, -----) sarp valgrind-old:0.02s no: 0.4s (20.0x, 0.0%) me: 3.2s (158.0x, -0.3%) ca: 2.9s (146.0x, 0.0%) he:11.0s (552.0x, -0.0%) ca: 1.7s (84.5x, 1.2%) dr: 1.1s (53.5x, 0.0%) ma: 0.4s (20.5x, 0.0%) -- tinycc -- tinycc valgrind-new:0.27s no: 3.0s (11.1x, -----) me:14.2s (52.6x, -----) ca:17.4s (64.5x, -----) he:19.2s (71.2x, -----) ca:15.8s (58.4x, -----) dr:12.5s (46.3x, -----) ma: 3.8s (14.2x, -----) tinycc valgrind-old:0.27s no: 3.1s (11.4x, -2.7%) me:14.3s (52.9x, -0.6%) ca:17.5s (64.9x, -0.7%) he:19.0s (70.4x, 1.1%) ca:15.7s (58.1x, 0.4%) dr:12.5s (46.2x, 0.2%) ma: 3.9s (14.4x, -1.3%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 54m36.842s user 53m1.385s sys 0m20.011s |
|
From: Tom H. <to...@co...> - 2014-02-19 04:26:56
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.11.10-301.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-02-19 03:51:51 GMT Ended at 2014-02-19 04:26:32 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 645 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2014-02-19 04:05:39
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] GDB: GNU gdb (GDB) SUSE (7.5.1-2.1.1) Assembler: GNU assembler (GNU Binutils; openSUSE 12.3) 2.23.1 C library: GNU C Library (GNU libc) stable release version 2.17 (git c758a6861537) uname -mrs: Linux 3.7.9-1.1-desktop x86_64 Vendor version: Welcome to openSUSE 12.3 "Dartmouth" Beta 1 - Kernel %r (%t). Nightly build on ultra ( gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] Linux 3.7.9-1.1-desktop x86_64 ) Started at 2014-02-18 21:30:01 CST Ended at 2014-02-18 22:05:26 CST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 666 tests, 0 stderr failures, 0 stdout failures, 1 stderrB failure, 0 stdoutB failures, 0 post failures == gdbserver_tests/mssnapshot (stderrB) ================================================= ./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff ================================================= --- mssnapshot.stderrB.exp 2014-02-18 21:48:02.738272574 -0600 +++ mssnapshot.stderrB.out 2014-02-18 21:54:33.077609026 -0600 @@ -1,5 +1,11 @@ relaying data between gdb and process .... +Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2 +Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158" vgdb-error value changed from 0 to 999999 +Missing separate debuginfo for /lib64/libpthread.so.0 +Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef" +Missing separate debuginfo for /lib64/libc.so.6 +Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7" general valgrind monitor commands: help [debug] : monitor command help. With debug: + debugging commands v.wait [<ms>] : sleep <ms> (default 0) then continue ================================================= ./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff ================================================= --- mssnapshot.stderrB.exp 2014-02-18 21:32:26.364369268 -0600 +++ mssnapshot.stderrB.out 2014-02-18 21:36:54.514851894 -0600 @@ -1,5 +1,11 @@ relaying data between gdb and process .... +Missing separate debuginfo for /lib64/ld-linux-x86-64.so.2 +Try: zypper install -C "debuginfo(build-id)=ecb8ef1a6904a2a3ec60a527f415f520c8636158" vgdb-error value changed from 0 to 999999 +Missing separate debuginfo for /lib64/libpthread.so.0 +Try: zypper install -C "debuginfo(build-id)=ef5f5dbcb2398c608fef7884e1bfb65be3b5f0ef" +Missing separate debuginfo for /lib64/libc.so.6 +Try: zypper install -C "debuginfo(build-id)=bd1473e8e6a4c10a14731b5be4b35b4e87db2af7" general valgrind monitor commands: help [debug] : monitor command help. With debug: + debugging commands v.wait [<ms>] : sleep <ms> (default 0) then continue |
|
From: Tom H. <to...@co...> - 2014-02-19 03:55:09
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.11.10-301.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-02-19 03:13:34 GMT Ended at 2014-02-19 03:54:58 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 673 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == |
|
From: Maran P. <ma...@li...> - 2014-02-19 03:46:41
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.8-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP1 gcc 4.3.4 on z196 (s390x) ) Started at 2014-02-19 03:45:01 CET Ended at 2014-02-19 04:46:29 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 642 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) drd/tests/pth_barrier3 (stderr) drd/tests/pth_barrier_thr_cr (stderr) drd/tests/pth_create_chain (stderr) --tools=none,memcheck --reps=5 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 4.4s (19.0x, -----) me: 7.0s (30.3x, -----) bigcode1 valgrind-old:0.23s no: 4.3s (18.6x, 2.3%) me: 7.0s (30.3x, 0.0%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.2s (29.9x, -----) me:13.9s (57.9x, -----) bigcode2 valgrind-old:0.24s no: 7.3s (30.3x, -1.4%) me:13.9s (57.9x, 0.0%) -- bz2 -- bz2 valgrind-new:0.70s no: 4.9s ( 7.1x, -----) me:13.0s (18.6x, -----) bz2 valgrind-old:0.70s no: 4.9s ( 7.0x, 0.2%) me:13.0s (18.6x, 0.0%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 3.9x, -----) me: 4.2s (10.3x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, 0.0%) me: 4.2s (10.3x, 0.0%) -- ffbench -- ffbench valgrind-new:0.20s no: 1.0s ( 5.1x, -----) me: 3.4s (16.8x, -----) ffbench valgrind-old:0.20s no: 1.0s ( 5.1x, 0.0%) me: 3.4s (16.9x, -0.3%) -- heap -- heap valgrind-new:0.23s no: 1.8s ( 7.7x, -----) me: 8.9s (38.6x, -----) heap valgrind-old:0.23s no: 1.8s ( 7.7x, 0.6%) me: 8.9s (38.6x, -0.1%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 1.9s ( 8.8x, -----) me:13.1s (59.6x, -----) heap_pdb4 valgrind-old:0.22s no: 1.9s ( 8.8x, 0.0%) me:13.0s (59.2x, 0.7%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (23.5x, -----) me: 2.1s (104.5x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (23.0x, 2.1%) me: 2.1s (104.0x, 0.5%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.6s ( 8.6x, -----) me: 3.2s (45.7x, -----) many-xpts valgrind-old:0.07s no: 0.6s ( 8.4x, 1.7%) me: 3.2s (45.7x, 0.0%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (19.3x, -----) me: 3.6s (121.0x, -----) sarp valgrind-old:0.03s no: 0.6s (19.3x, 0.0%) me: 3.6s (121.3x, -0.3%) -- tinycc -- tinycc valgrind-new:0.22s no: 2.7s (12.1x, -----) me:15.0s (68.0x, -----) tinycc valgrind-old:0.22s no: 2.7s (12.1x, 0.0%) me:15.0s (68.1x, -0.1%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 44 timings ================= real 19m52.024s user 19m29.426s sys 0m20.244s |
|
From: Tom H. <to...@co...> - 2014-02-19 03:44:37
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.11.10-301.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-02-19 03:02:32 GMT Ended at 2014-02-19 03:44:21 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 673 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == |
|
From: Maran P. <ma...@li...> - 2014-02-19 03:33:11
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.7.0 20120604 (Red Hat 4.7.0-7) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-42.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: unknown uname -mrs: Linux 3.3.4-5.fc17.s390x s390x Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on fedoras390 ( Fedora 17 with gcc 4.7.0 on z196 (s390x) ) Started at 2014-02-19 03:45:25 CET Ended at 2014-02-19 04:33:21 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 647 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) drd/tests/pth_barrier3 (stderr) --tools=none,memcheck --reps=5 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.22s no: 2.8s (12.8x, -----) me: 6.4s (29.1x, -----) bigcode1 valgrind-old:0.22s no: 2.9s (13.1x, -2.5%) me: 6.3s (28.9x, 0.9%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 5.2s (21.5x, -----) me:11.7s (48.7x, -----) bigcode2 valgrind-old:0.24s no: 5.2s (21.8x, -1.0%) me:11.8s (49.2x, -1.2%) -- bz2 -- bz2 valgrind-new:0.68s no: 4.0s ( 5.9x, -----) me:11.6s (17.0x, -----) bz2 valgrind-old:0.68s no: 4.0s ( 5.9x, -0.2%) me:11.4s (16.8x, 0.9%) -- fbench -- fbench valgrind-new:0.36s no: 1.5s ( 4.2x, -----) me: 5.7s (15.8x, -----) fbench valgrind-old:0.36s no: 1.5s ( 4.2x, 0.0%) me: 5.7s (15.9x, -0.2%) -- ffbench -- ffbench valgrind-new:0.21s no: 1.2s ( 5.6x, -----) me: 3.4s (16.4x, -----) ffbench valgrind-old:0.21s no: 1.2s ( 5.6x, 0.0%) me: 3.4s (16.3x, 0.3%) -- heap -- heap valgrind-new:0.23s no: 1.3s ( 5.5x, -----) me: 8.1s (35.2x, -----) heap valgrind-old:0.23s no: 1.2s ( 5.3x, 3.2%) me: 8.1s (35.3x, -0.2%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 1.3s ( 6.0x, -----) me:12.4s (56.5x, -----) heap_pdb4 valgrind-old:0.22s no: 1.3s ( 6.1x, -0.8%) me:12.4s (56.3x, 0.3%) -- many-loss-records -- many-loss-records valgrind-new:0.03s no: 0.4s (13.0x, -----) me: 2.0s (67.0x, -----) many-loss-records valgrind-old:0.03s no: 0.4s (12.0x, 7.7%) me: 2.0s (66.7x, 0.5%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.5s ( 6.4x, -----) me: 3.4s (48.3x, -----) many-xpts valgrind-old:0.07s no: 0.5s ( 6.4x, 0.0%) me: 3.4s (48.6x, -0.6%) -- sarp -- sarp valgrind-new:0.03s no: 0.5s (15.0x, -----) me: 5.5s (183.3x, -----) sarp valgrind-old:0.03s no: 0.5s (15.0x, 0.0%) me: 5.5s (184.3x, -0.5%) -- tinycc -- tinycc valgrind-new:0.23s no: 2.2s ( 9.5x, -----) me:15.3s (66.6x, -----) tinycc valgrind-old:0.23s no: 2.1s ( 9.3x, 2.7%) me:15.3s (66.6x, 0.0%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 44 timings ================= real 18m31.500s user 18m9.762s sys 0m19.303s |
|
From: Rich C. <rc...@wi...> - 2014-02-19 03:25:31
|
valgrind revision: 13815
VEX revision: 2820
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-02-18 19:22:01 CST
Ended at 2014-02-18 21:25:16 CST
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 588 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/dw4 (stderr)
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-02-18 20:23:35.886820264 -0600
+++ hackedbz2.stderr.out 2014-02-18 21:23:58.019838598 -0600
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/dw4.stderr.diff
=================================================
--- dw4.stderr.exp 2014-02-18 20:23:42.639898603 -0600
+++ dw4.stderr.out 2014-02-18 20:42:03.342667254 -0600
@@ -1,3 +1,11 @@
+
+parse_type_DIE: confused by:
+ <1><492>: DW_TAG_structure_type
+ DW_AT_signature : 8 byte signature: 9b d0 55 13 bb 1e e9 37
+
+WARNING: Serious error when reading debug info
+When reading debug info from /usr/local/src/valgrind/nightly/valgrind-new/memcheck/tests/dw4:
+parse_type_DIE: confused by the above DIE
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:49)
@@ -8,12 +16,10 @@
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:51)
- Location 0x........ is 0 bytes inside S2[0].i,
- a global variable declared at dw4.c:42
+ Address 0x........ is 4 bytes inside data symbol "S2"
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:52)
- Location 0x........ is 0 bytes inside local.i,
- declared at dw4.c:46, in frame #1 of thread 1
+ Address 0x........ is on thread 1's stack
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-02-18 20:23:45.886936270 -0600
+++ err_disable3.stderr.out 2014-02-18 20:42:09.987744340 -0600
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-02-18 20:23:38.445849950 -0600
+++ err_disable4.stderr.out 2014-02-18 20:42:14.136792470 -0600
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-02-18 20:23:43.982914183 -0600
+++ threadname.stderr.out 2014-02-18 20:48:00.162806529 -0600
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-02-18 20:23:42.611898278 -0600
+++ threadname_xml.stderr.out 2014-02-18 20:48:02.204830217 -0600
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-02-18 19:22:36.528370049 -0600
+++ hackedbz2.stderr.out 2014-02-18 20:22:08.629808043 -0600
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/dw4.stderr.diff
=================================================
--- dw4.stderr.exp 2014-02-18 19:22:29.675290550 -0600
+++ dw4.stderr.out 2014-02-18 19:40:18.145685291 -0600
@@ -1,3 +1,11 @@
+
+parse_type_DIE: confused by:
+ <1><492>: DW_TAG_structure_type
+ DW_AT_signature : 8 byte signature: 9b d0 55 13 bb 1e e9 37
+
+WARNING: Serious error when reading debug info
+When reading debug info from /usr/local/src/valgrind/nightly/valgrind-old/memcheck/tests/dw4:
+parse_type_DIE: confused by the above DIE
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:49)
@@ -8,12 +16,10 @@
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:51)
- Location 0x........ is 0 bytes inside S2[0].i,
- a global variable declared at dw4.c:42
+ Address 0x........ is 4 bytes inside data symbol "S2"
Uninitialised byte(s) found during client check request
at 0x........: croak (dw4.c:27)
by 0x........: main (dw4.c:52)
- Location 0x........ is 0 bytes inside local.i,
- declared at dw4.c:46, in frame #1 of thread 1
+ Address 0x........ is on thread 1's stack
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-02-18 19:22:31.553312336 -0600
+++ err_disable3.stderr.out 2014-02-18 19:40:24.758762006 -0600
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-02-18 19:22:29.676290562 -0600
+++ err_disable4.stderr.out 2014-02-18 19:40:28.826809197 -0600
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-02-18 19:22:30.661301989 -0600
+++ threadname.stderr.out 2014-02-18 19:46:14.276816573 -0600
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-02-18 19:22:30.987305770 -0600
+++ threadname_xml.stderr.out 2014-02-18 19:46:16.292839960 -0600
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
|
|
From: Maran P. <ma...@li...> - 2014-02-19 03:19:36
|
valgrind revision: 13815 VEX revision: 2820 C compiler: gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-3) GDB: GNU gdb (GDB) Red Hat Enterprise Linux (7.2-60.el6) Assembler: GNU assembler version 2.20.51.0.2-5.36.el6 20100205 C library: GNU C Library stable release version 2.12 uname -mrs: Linux 2.6.32-358.el6.s390x s390x Vendor version: Red Hat Enterprise Linux Server release 6.4 (Santiago) Nightly build on rhels390 ( RHEL 6.4 with gcc 4.4.7 on zEC12 (s390x) ) Started at 2014-02-19 03:45:25 CET Ended at 2014-02-19 04:19:47 CET Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 641 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) drd/tests/pth_barrier3 (stderr) drd/tests/pth_create_chain (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 641 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) helgrind/tests/pth_barrier3 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) drd/tests/pth_barrier3 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short 2014-02-19 03:56:08.000000000 +0100 --- new.short 2014-02-19 04:06:54.000000000 +0100 *************** *** 8,10 **** ! == 641 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) --- 8,10 ---- ! == 641 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) *************** *** 13,14 **** --- 13,15 ---- drd/tests/pth_barrier3 (stderr) + drd/tests/pth_create_chain (stderr) --tools=none,memcheck --reps=5 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.16s no: 1.7s (10.6x, -----) me: 3.1s (19.6x, -----) bigcode1 valgrind-old:0.16s no: 1.7s (10.6x, 0.0%) me: 3.1s (19.6x, 0.0%) -- bigcode2 -- bigcode2 valgrind-new:0.17s no: 3.6s (21.4x, -----) me: 7.6s (44.5x, -----) bigcode2 valgrind-old:0.17s no: 3.6s (21.4x, 0.0%) me: 7.6s (44.5x, 0.1%) -- bz2 -- bz2 valgrind-new:0.70s no: 2.5s ( 3.6x, -----) me:10.1s (14.4x, -----) bz2 valgrind-old:0.70s no: 2.5s ( 3.6x, 0.0%) me:10.1s (14.4x, 0.0%) -- fbench -- fbench valgrind-new:0.36s no: 1.4s ( 3.8x, -----) me: 3.6s (10.0x, -----) fbench valgrind-old:0.36s no: 1.4s ( 3.8x, -0.0%) me: 3.6s ( 9.9x, 0.3%) -- ffbench -- ffbench valgrind-new:0.18s no: 0.8s ( 4.3x, -----) me: 3.0s (16.5x, -----) ffbench valgrind-old:0.18s no: 0.8s ( 4.3x, 0.0%) me: 3.0s (16.4x, 0.3%) -- heap -- heap valgrind-new:0.11s no: 0.7s ( 6.6x, -----) me: 6.0s (54.8x, -----) heap valgrind-old:0.11s no: 0.7s ( 6.6x, 0.0%) me: 6.0s (54.8x, 0.0%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.13s no: 0.8s ( 6.5x, -----) me: 9.0s (69.2x, -----) heap_pdb4 valgrind-old:0.13s no: 0.8s ( 6.5x, 0.0%) me: 9.0s (69.3x, -0.1%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.2s (24.0x, -----) me: 1.5s (149.0x, -----) many-loss-records valgrind-old:0.01s no: 0.2s (24.0x, 0.0%) me: 1.5s (149.0x, 0.0%) -- many-xpts -- many-xpts valgrind-new:0.04s no: 0.3s ( 7.5x, -----) me: 2.2s (55.2x, -----) many-xpts valgrind-old:0.04s no: 0.3s ( 7.5x, 0.0%) me: 2.2s (56.0x, -1.4%) -- sarp -- sarp valgrind-new:0.02s no: 0.2s (12.5x, -----) me: 2.5s (122.5x, -----) sarp valgrind-old:0.02s no: 0.2s (12.5x, 0.0%) me: 2.5s (124.5x, -1.6%) -- tinycc -- tinycc valgrind-new:0.17s no: 1.6s ( 9.6x, -----) me:12.1s (71.2x, -----) tinycc valgrind-old:0.17s no: 1.6s ( 9.6x, 0.0%) me:12.1s (71.1x, 0.2%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 44 timings ================= real 12m53.095s user 12m40.116s sys 0m10.983s |