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From: <sv...@va...> - 2013-10-13 18:38:40
|
Author: philippe
Date: Sun Oct 13 18:38:30 2013
New Revision: 13635
Log:
Add definedness checking when dereferencing ptr during heuristic reachedness
Patch ensures that no heuristic reachedness is obtained with undefined data.
Modified:
trunk/memcheck/mc_leakcheck.c
Modified: trunk/memcheck/mc_leakcheck.c
==============================================================================
--- trunk/memcheck/mc_leakcheck.c (original)
+++ trunk/memcheck/mc_leakcheck.c Sun Oct 13 18:38:30 2013
@@ -685,19 +685,25 @@
// Detects inner pointers to Std::String for layout being
// length capacity refcount char_array[] \0
// where ptr points to the beginning of the char_array.
- if ( ptr == ch->data + 3 * sizeof(SizeT)) {
- const SizeT length = *((SizeT*)ch->data);
- const SizeT capacity = *((SizeT*)ch->data+1);
- if (length <= capacity
- && (3 * sizeof(SizeT) + capacity + 1 == ch->szB)) {
- // ??? could check there is no null byte from ptr to ptr+length-1
- // ??? and that there is a null byte at ptr+length.
- // ???
- // ??? could check that ch->allockind is MC_AllocNew ???
- // ??? probably not a good idea, as I guess stdstring
- // ??? allocator can be done via custom allocator
- // ??? or even a call to malloc ????
- return LchStdString;
+ // Note: we check definedness for length and capacity but
+ // not for refcount, as refcount size might be smaller than
+ // a SizeT, giving a uninitialised hole in the first 3 SizeT.
+ if ( ptr == ch->data + 3 * sizeof(SizeT)
+ && MC_(is_valid_aligned_word)(ch->data + sizeof(SizeT))) {
+ const SizeT capacity = *((SizeT*)(ch->data + sizeof(SizeT)));
+ if (3 * sizeof(SizeT) + capacity + 1 == ch->szB
+ && MC_(is_valid_aligned_word)(ch->data)) {
+ const SizeT length = *((SizeT*)ch->data);
+ if (length <= capacity) {
+ // ??? could check there is no null byte from ptr to ptr+length-1
+ // ??? and that there is a null byte at ptr+length.
+ // ???
+ // ??? could check that ch->allockind is MC_AllocNew ???
+ // ??? probably not a good idea, as I guess stdstring
+ // ??? allocator can be done via custom allocator
+ // ??? or even a call to malloc ????
+ return LchStdString;
+ }
}
}
}
@@ -718,7 +724,8 @@
// 0-sized block. This trick does not work for 'new MyClass[0]'
// because a chunk "word-sized" is allocated to store the (0) nr
// of elements.
- if ( ptr == ch->data + sizeof(SizeT)) {
+ if ( ptr == ch->data + sizeof(SizeT)
+ && MC_(is_valid_aligned_word)(ch->data)) {
const SizeT nr_elts = *((SizeT*)ch->data);
if (nr_elts > 0 && (ch->szB - sizeof(SizeT)) % nr_elts == 0) {
// ??? could check that ch->allockind is MC_AllocNewVec ???
@@ -730,7 +737,8 @@
if (HiS(LchMultipleInheritance, heur_set)) {
// Detect inner pointer used for multiple inheritance.
// Assumption is that the vtable pointers are before the object.
- if (VG_IS_WORD_ALIGNED(ptr)) {
+ if (VG_IS_WORD_ALIGNED(ptr)
+ && MC_(is_valid_aligned_word)(ptr)) {
Addr first_addr;
Addr inner_addr;
@@ -744,7 +752,8 @@
// in the last page.
inner_addr = *((Addr*)ptr);
if (VG_IS_WORD_ALIGNED(inner_addr)
- && inner_addr >= (Addr)VKI_PAGE_SIZE) {
+ && inner_addr >= (Addr)VKI_PAGE_SIZE
+ && MC_(is_valid_aligned_word)(ch->data)) {
first_addr = *((Addr*)ch->data);
if (VG_IS_WORD_ALIGNED(first_addr)
&& first_addr >= (Addr)VKI_PAGE_SIZE
@@ -775,15 +784,10 @@
return;
if (ex->state == Reachable) {
- // If block was considered reachable via an heuristic,
- // and it is now directly reachable via ptr, clear the
- // heuristic.
- if (ex->heuristic && ptr == ch->data) {
- // ch was up to now considered as reachable dur to
- // ex->heuristic. We have a direct ptr now => clear
- // the heuristic field.
+ if (ex->heuristic && ptr == ch->data)
+ // If block was considered reachable via an heuristic, and it is now
+ // directly reachable via ptr, clear the heuristic field.
ex->heuristic = LchNone;
- }
return;
}
|
|
From: Mark W. <mj...@re...> - 2013-10-13 09:13:04
|
> On 10/04/2013 11:44 PM, Mark Wielaard wrote:
>
> > The funny thing with valgrind is that it can emulate tm even if the host
> > doesn't (just like it emulates avx2 if you just have avx).
> >
> > But there is a typo in VEX/priv/guest_amd64_toIR.c:
> >
> > diff --git a/priv/guest_amd64_toIR.c b/priv/guest_amd64_toIR.c
> > index a29e175..c421007 100644
> > --- a/priv/guest_amd64_toIR.c
> > +++ b/priv/guest_amd64_toIR.c
> > @@ -20067,7 +20067,7 @@ Long dis_ESC_NONE (
> > }
> > /* BEGIN HACKY SUPPORT FOR xbegin */
> > if (modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 4
> > - && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
> > + && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
> > delta++; /* mod/rm byte */
> > d64 = getSDisp(4,delta);
> > delta += 4;
>
> So .. _AVX2 was what I intended, in the sense that I wanted only to provide
> TM if the host could do AVX2. But if changing to _AVX makes the prereq
> problem go away, then fine.
>
> btw I suspect I made this more complex/inaccurate/confusing than it needed
> to be by assuming that CPUs that can do AVX2 can also do TM. But that's
> not so -- all Haswell-branded CPUs can do AVX2 (IIUC) but only the higher
> spec ones can do TM.
I think we need to rethink our VEX capabilities vs host capabilities a
bit (after 3.9.0). Currently this makes the prereq problem go away since
prereq checks the host capabilities. But that does not translate
one-on-one to valgrind capabilities. Valgrind (on x86) advertises
its own capabilities through fixed emulated cpuid "families" that only
map coarsely on the host cpuid. But in guest_toIR we check against the
individual host hardware capabilities. We need to connect those
a little better (and IMHO give the user a way to select which ones
they want - e.g. we can always emulate TM currently, but the user
might not always want it, even on hardware that does have it).
Cheers,
Mark
|
|
From: Julian S. <js...@ac...> - 2013-10-13 00:34:29
|
[arriving way too late at the party ..]
On 10/04/2013 11:44 PM, Mark Wielaard wrote:
> The funny thing with valgrind is that it can emulate tm even if the host
> doesn't (just like it emulates avx2 if you just have avx).
>
> But there is a typo in VEX/priv/guest_amd64_toIR.c:
>
> diff --git a/priv/guest_amd64_toIR.c b/priv/guest_amd64_toIR.c
> index a29e175..c421007 100644
> --- a/priv/guest_amd64_toIR.c
> +++ b/priv/guest_amd64_toIR.c
> @@ -20067,7 +20067,7 @@ Long dis_ESC_NONE (
> }
> /* BEGIN HACKY SUPPORT FOR xbegin */
> if (modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 4
> - && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
> + && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
> delta++; /* mod/rm byte */
> d64 = getSDisp(4,delta);
> delta += 4;
So .. _AVX2 was what I intended, in the sense that I wanted only to provide
TM if the host could do AVX2. But if changing to _AVX makes the prereq
problem go away, then fine.
btw I suspect I made this more complex/inaccurate/confusing than it needed
to be by assuming that CPUs that can do AVX2 can also do TM. But that's
not so -- all Haswell-branded CPUs can do AVX2 (IIUC) but only the higher
spec ones can do TM.
J
|