You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
1
(16) |
2
(22) |
3
(23) |
4
(12) |
5
(24) |
6
(28) |
7
(16) |
|
8
(3) |
9
(2) |
10
(9) |
11
(22) |
12
(19) |
13
(19) |
14
(15) |
|
15
(10) |
16
(23) |
17
(27) |
18
(31) |
19
(26) |
20
(19) |
21
(17) |
|
22
(6) |
23
(4) |
24
(3) |
25
(14) |
26
(1) |
27
(20) |
28
(14) |
|
29
(10) |
30
(26) |
|
|
|
|
|
|
From: marc b. <mar...@gm...> - 2013-09-10 21:29:07
|
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN"
"http://www.w3.org/TR/html4/strict.dtd">
<html>
<head>
<title>Valgrind test runs</title>
<link rel="stylesheet" href="../summary.css" type="text/css">
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
</head>
<body>
<div class="navbar">
<a href="all_tests.index.html">all tests</a>
</div>
<div class="main">
<h2>Valgrind test runs</h2>
<table class="report"><thead><tr>
<th class="test">Revision Valgrind.Vex</th>
<th class="test">Valgrind commit date</th>
<th class="test">Vex commit date</th>
<th class="test"><a href="machine.bristolx8664Fedora11.html">bristol ( x86_64, Fedora 11 )</a></th><th class="test"><a href="machine.bristolx8664Fedora13.html">bristol ( x86_64, Fedora 13 )</a></th><th class="test"><a href="machine.bristolx8664Fedora14.html">bristol ( x86_64, Fedora 14 )</a></th><th class="test"><a href="machine.bristolx8664Fedora15.html">bristol ( x86_64, Fedora 15 )</a></th><th class="test"><a href="machine.bristolx8664Fedora16.html">bristol ( x86_64, Fedora 16 )</a></th><th class="test"><a href="machine.bristolx8664Fedora17BeefyMiracle.html">bristol ( x86_64, Fedora 17 (Beefy Miracle) )</a></th><th class="test"><a href="machine.bristolx8664Fedora18SphericalCow.html">bristol ( x86_64, Fedora 18 (Spherical Cow) )</a></th><th class="test"><a href="machine.bristolx8664Fedora19SchrdingersCat.html">bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) )</a></th><th class="test"><a href="machine.bristolx8664Fedora21.html">bristol ( x86_64, Fedora 21 )</a></th><th class="test"><a href="machine.bristolx8664Fedora9.html">bristol ( x86_64, Fedora 9 )</a></th><th class="test"><a href="machine.fedoras390Fedora17withgcc470onz196s390x.html">fedoras390 ( Fedora 17 with gcc 4.7.0 on z196 (s390x) )</a></th><th class="test"><a href="machine.gcc110Fedorarelease18SphericalCowppc64.html">gcc110 ( Fedora release 18 (Spherical Cow), ppc64 )</a></th><th class="test"><a href="machine.macamd64Darwin1080i386.html">macamd64 ( Darwin 10.8.0 i386 )</a></th><th class="test"><a href="machine.rhels390RHEL64withgcc447onzEC12s390x.html">rhels390 ( RHEL 6.4 with gcc 4.4.7 on zEC12 (s390x) )</a></th><th class="test"><a href="machine.sless390SUSELinuxEnterpriseServer11SP1gcc434onz196s390x.html">sless390 ( SUSE Linux Enterprise Server 11 SP1 gcc 4.3.4 on z196 (s390x) )</a></th><th class="test"><a href="machine.ultragcc451Linux37911desktopx8664.html">ultra ( gcc 4.5.1 Linux 3.7.9-1.1-desktop x86_64 )</a></th> </tr>
<tr><td class="result more_failures"><a href="revision.13537.2755.html">13537.2755</a></td><td class="result more_failures">2013-09-06</td><td></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24252"/>644,2,0</a></td><td class="result more_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24251"/>644,3,2</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24250"/>663,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24248"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24247"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24246"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24245"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24242"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24241"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24253"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24243"/>639,4,0</a></td><td class="result same_failures"><a title="563 tests run,nb failures,delta failure with previous revision" href="../24254"/>563,40,0</a></td><td class="note"></td><td class="note"></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24244"/>639,0,0</a></td><td class="result same_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24249"/>658,2,0</a></td></tr>
<tr><td class="result more_failures"><a href="revision.13535.2751.html">13535.2751</a></td><td class="result more_failures"><a href=../24209>2013-09-05</a></td><td class="result more_failures"><a href=../24206>2013-09-05</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24224"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24223"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24222"/>663,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24220"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24219"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24218"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24216"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24214"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24212"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24225"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24215"/>639,4,0</a></td><td class="result more_failures"><a title="563 tests run,nb failures,delta failure with previous revision" href="../24226"/>563,40,4</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24213"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24217"/>639,0,0</a></td><td class="result same_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24221"/>658,2,0</a></td></tr>
<tr><td class="result not_run"><a href="revision.13532.2750.html">13532.2750</a></td><td class="result not_run"><a href=../24227>2013-09-06</a></td><td class="result not_run"><a href=../24175>2013-09-03</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24201"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24200"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24199"/>663,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24197"/>665,1,0</a></td><td class="result less_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24196"/>665,1,-2</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24195"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24194"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24191"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24189"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24202"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24192"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24203"/>561,36,0</a></td><td class="note"></td><td class="result not_run"><a title="failure building valgrind" href="../24190"/>no test</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24193"/>639,0,0</a></td><td class="result same_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24198"/>658,2,0</a></td></tr>
<tr><td class="result same_failures"><a href="revision.13531.2750.html">13531.2750</a></td><td class="result same_failures"><a href=../24182>2013-09-04</a></td><td class="result same_failures"><a href=../24175>2013-09-03</a></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="result same_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24184"/>658,2,0</a></td></tr>
<tr><td class="result not_run"><a href="revision.13528.2750.html">13528.2750</a></td><td class="result not_run"><a href=../24170>2013-09-03</a></td><td class="result not_run"><a href=../24175>2013-09-03</a></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24177"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24179"/>561,36,0</a></td><td class="note"></td><td class="result not_run"><a title="failure building valgrind" href="../24176"/>no test</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24178"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13527.2749.html">13527.2749</a></td><td class="result more_failures"><a href=../24167>2013-09-03</a></td><td class="result more_failures"><a href=../24152>2013-09-02</a></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="note"></td><td class="result more_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24168"/>658,2,2</a></td></tr>
<tr><td class="result more_failures"><a href="revision.13526.2749.html">13526.2749</a></td><td class="result more_failures"><a href=../24151>2013-09-02</a></td><td class="result more_failures"><a href=../24152>2013-09-02</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24162"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24164"/>644,1,0</a></td><td class="result less_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24166"/>663,1,-2</a></td><td class="result less_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24165"/>665,1,-1</a></td><td class="result more_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24161"/>665,3,2</a></td><td class="result less_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24159"/>665,6,-1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24157"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24155"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24153"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24163"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24156"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24160"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24154"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24158"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13520.2747.html">13520.2747</a></td><td class="result more_failures"><a href=../24114>2013-08-31</a></td><td class="result more_failures"><a href=../24130>2013-09-01</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24139"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24141"/>644,1,0</a></td><td class="result more_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24143"/>663,3,1</a></td><td class="result more_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24142"/>665,2,1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24144"/>665,1,0</a></td><td class="result more_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24138"/>665,7,1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24136"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24133"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24131"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24140"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24134"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24137"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24132"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24135"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13520.2745.html">13520.2745</a></td><td class="result more_failures"><a href=../24114>2013-08-31</a></td><td class="result more_failures"><a href=../24050>2013-08-27</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24126"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24125"/>644,1,0</a></td><td class="result more_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24124"/>663,2,1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24123"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24122"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24121"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24120"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24117"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24115"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24127"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24118"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24128"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24116"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24119"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result less_failures"><a href="revision.13519.2745.html">13519.2745</a></td><td class="result less_failures"><a href=../24099>2013-08-30</a></td><td class="result less_failures"><a href=../24050>2013-08-27</a></td><td class="result less_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24111"/>644,2,-1</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24110"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24109"/>663,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24108"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24107"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24106"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24104"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24102"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24100"/>665,7,0</a></td><td class="result less_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24112"/>642,2,-2</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24103"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24113"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24101"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24105"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13518.2745.html">13518.2745</a></td><td class="result more_failures"><a href=../24083>2013-08-29</a></td><td class="result more_failures"><a href=../24050>2013-08-27</a></td><td class="result more_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24093"/>644,3,1</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24095"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24096"/>663,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24097"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24098"/>665,1,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24092"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24090"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24089"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24085"/>665,7,0</a></td><td class="result more_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24094"/>642,4,2</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24087"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24091"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24086"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24088"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result less_failures"><a href="revision.13517.2745.html">13517.2745</a></td><td class="result less_failures"><a href=../24067>2013-08-28</a></td><td class="result less_failures"><a href=../24050>2013-08-27</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24079"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24078"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24077"/>663,1,0</a></td><td class="result less_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24076"/>665,1,-1</a></td><td class="result less_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24075"/>665,1,-1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24074"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24072"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24070"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24068"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24080"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24071"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24081"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24069"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24073"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13516.2745.html">13516.2745</a></td><td class="result more_failures"><a href=../24052>2013-08-27</a></td><td class="result more_failures"><a href=../24050>2013-08-27</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24064"/>644,2,0</a></td><td class="result same_failures"><a title="644 tests run,nb failures,delta failure with previous revision" href="../24063"/>644,1,0</a></td><td class="result same_failures"><a title="663 tests run,nb failures,delta failure with previous revision" href="../24062"/>663,1,0</a></td><td class="result more_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24061"/>665,2,1</a></td><td class="result more_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24060"/>665,2,1</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24059"/>665,6,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24057"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24055"/>665,3,0</a></td><td class="result same_failures"><a title="665 tests run,nb failures,delta failure with previous revision" href="../24053"/>665,7,0</a></td><td class="result same_failures"><a title="642 tests run,nb failures,delta failure with previous revision" href="../24065"/>642,2,0</a></td><td class="result same_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24056"/>639,4,0</a></td><td class="result same_failures"><a title="561 tests run,nb failures,delta failure with previous revision" href="../24066"/>561,36,0</a></td><td class="note"></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24054"/>636,0,0</a></td><td class="result pass"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24058"/>639,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13513.2744.html">13513.2744</a></td><td class="result more_failures"><a href=../24033>2013-08-25</a></td><td></td><td class="result same_failures"><a title="640 tests run,nb failures,delta failure with previous revision" href="../24045"/>640,2,0</a></td><td class="result same_failures"><a title="640 tests run,nb failures,delta failure with previous revision" href="../24044"/>640,1,0</a></td><td class="result same_failures"><a title="659 tests run,nb failures,delta failure with previous revision" href="../24043"/>659,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24042"/>661,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24041"/>661,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24040"/>661,6,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24038"/>661,3,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24036"/>661,3,0</a></td><td class="result more_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24034"/>661,7,7</a></td><td class="result same_failures"><a title="638 tests run,nb failures,delta failure with previous revision" href="../24046"/>638,2,0</a></td><td class="result same_failures"><a title="637 tests run,nb failures,delta failure with previous revision" href="../24037"/>637,4,0</a></td><td class="result same_failures"><a title="559 tests run,nb failures,delta failure with previous revision" href="../24047"/>559,36,0</a></td><td class="note"></td><td class="result pass"><a title="634 tests run,nb failures,delta failure with previous revision" href="../24035"/>634,0,0</a></td><td class="result pass"><a title="637 tests run,nb failures,delta failure with previous revision" href="../24039"/>637,0,0</a></td><td class="note"></td></tr>
<tr><td class="result less_failures"><a href="revision.13512.2744.html">13512.2744</a></td><td class="result less_failures"><a href=../24019>2013-08-24</a></td><td></td><td class="result same_failures"><a title="640 tests run,nb failures,delta failure with previous revision" href="../24030"/>640,2,0</a></td><td class="result less_failures"><a title="640 tests run,nb failures,delta failure with previous revision" href="../24029"/>640,1,-2</a></td><td class="result same_failures"><a title="659 tests run,nb failures,delta failure with previous revision" href="../24028"/>659,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24027"/>661,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24026"/>661,1,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24025"/>661,6,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24024"/>661,3,0</a></td><td class="result same_failures"><a title="661 tests run,nb failures,delta failure with previous revision" href="../24021"/>661,3,0</a></td><td class="note"></td><td class="result same_failures"><a title="638 tests run,nb failures,delta failure with previous revision" href="../24031"/>638,2,0</a></td><td class="result same_failures"><a title="637 tests run,nb failures,delta failure with previous revision" href="../24022"/>637,4,0</a></td><td class="result same_failures"><a title="559 tests run,nb failures,delta failure with previous revision" href="../24032"/>559,36,0</a></td><td class="note"></td><td class="result pass"><a title="634 tests run,nb failures,delta failure with previous revision" href="../24020"/>634,0,0</a></td><td class="result pass"><a title="637 tests run,nb failures,delta failure with previous revision" href="../24023"/>637,0,0</a></td><td class="note"></td></tr>
<tr><td class="result more_failures"><a href="revision.13507.2744.html">13507.2744</a></td><td class="result more_failures">2013-08-22</td><td></td><td class="result more_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24009"/>639,2,2</a></td><td class="result more_failures"><a title="639 tests run,nb failures,delta failure with previous revision" href="../24010"/>639,3,3</a></td><td class="result more_failures"><a title="658 tests run,nb failures,delta failure with previous revision" href="../24008"/>658,1,1</a></td><td class="result more_failures"><a title="660 tests run,nb failures,delta failure with previous revision" href="../24007"/>660,1,1</a></td><td class="result more_failures"><a title="660 tests run,nb failures,delta failure with previous revision" href="../24006"/>660,1,1</a></td><td class="result more_failures"><a title="660 tests run,nb failures,delta failure with previous revision" href="../24005"/>660,6,6</a></td><td class="result more_failures"><a title="660 tests run,nb failures,delta failure with previous revision" href="../24003"/>660,3,3</a></td><td class="result more_failures"><a title="660 tests run,nb failures,delta failure with previous revision" href="../24001"/>660,3,3</a></td><td class="note"></td><td class="result more_failures"><a title="637 tests run,nb failures,delta failure with previous revision" href="../24011"/>637,2,2</a></td><td class="result more_failures"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24002"/>636,4,4</a></td><td class="result more_failures"><a title="558 tests run,nb failures,delta failure with previous revision" href="../24012"/>558,36,36</a></td><td class="result more_failures"><a title="566 tests run,nb failures,delta failure with previous revision" href="../24013"/>566,116,116</a></td><td class="result pass"><a title="633 tests run,nb failures,delta failure with previous revision" href="../24000"/>633,0,0</a></td><td class="result pass"><a title="636 tests run,nb failures,delta failure with previous revision" href="../24004"/>636,0,0</a></td><td class="note"></td></tr>
</table></div>
<div class="legend">
<h3>Legend</h3>
<p class="legend">All tests <span class="result pass">passed</span>.</p>
<p class="legend">The same tests as in previous report
<span class="result same_failures">failed</span>.</p>
<p class="legend">More tests than in the previous report
<span class="result more_failures">failed</span>.</p>
<p class="legend">Less tests than in the previous report
<span class="result less_failures">failed</span>.</p>
<p class="legend">No test run, build was
<span class="not_run">broken</span>.</p>
</div>
</body></html> |
|
From: Philippe W. <phi...@sk...> - 2013-09-10 19:44:58
|
On Tue, 2013-09-10 at 16:37 +0200, Florian Krohm wrote: > On 09/09/2013 11:32 PM, Philippe Waroquiers wrote: > > On Sun, 2013-09-08 at 23:34 +0200, Florian Krohm wrote: > > >> What if we run perf every day and send the results to e.g > >> pe...@va...? Whenever mail is received at that address a little > >> script runs that reads the perf results and collects them in some light > >> weight "data base" that we could look at at valgrind.org/perf. > > > So, maybe the valdev archive can be seen as the DB. > > I think you started to write a script to handle archived test results > > and make an html page from it. > > We could use the mailing list archive as the "data base". But accessing > it is slow. I ran that script you mentioned and it took minutes to > process 100 mails. Which means that you probably don't want to run it > yourself to figure out whether last night's build regressed performancewise. > Also, accessing the mailing list archive is "by number". E.g. mail > #20000 is a certain build that happened on Sep 8, 2012. But you don't > know that relation. So if you want to know how performance evolved since > a particular date, you either need to do some kind of bisection to > figure out the corresponding email number forat that date or you need to > store this information somewhere. > I guess a nightly cronjob on valgrind.org should do this: > (1) process the valdev emails that came in today (which implies that we > keep the largest email number that was processed the previous night) > (2) extract the performance data and write it somewhere for later query > (3) create some web page to visualise the performance data (it will use > the data collected in #2) > > > A colleague has started enhancing > > this script (e.g. taking some other ideas from what wine does for > > their night tests results). > > Let's see it :) Some significant work was done some months ago (the script is now about 1200 lines), including I think performance optimisation as it maintains a local directory with the messages, and produces an html page. It might not be very easy to summarise the performance (ie. many tools/many tests for many archs) > > > > > Maybe we could have the "conf" allowing to specify: > > to run perf test y/n > > the --reps= value > > with comparison with the previous day y/n > > That would be sufficient to do what we envision. Ok, will look at this to at least have the nrs started to be captured. Script and web page will follow :). Philippe |
|
From: Philippe W. <phi...@sk...> - 2013-09-10 19:36:21
|
On Tue, 2013-09-10 at 12:56 +0200, Julian Seward wrote: > On 09/06/2013 06:11 PM, Florian Krohm wrote: > > This patch introduces an enhancement in VEX's tree builder. > > Seems plausible. > > My main concern with this is that it doesn't change the > carefully-balanced and completely-untested (AFAIK) precise-exception > semantics, as controlled by The command line arg value -vex-iropt-register-updates=allregs-at-mem-access is used in 3 tests, but there is no explicit verification of the behaviour. I believe the 3 other values are used (implicitely): cachegrind and callgrind activates by default sp-at-mem-access memcheck uses the default unwindregs-at-mem-access --vgdb=full activates allregs-at-each-insn BTW, looking at this, it means that the --help-debug default is not ok, as the default depends on the tool (but I do not see how to make the default tool dependent) Apart of having all values used, I do not think there is somewhere a test which verifies e.g. that trapping SEGV and restarting the instruction works with a certain value and fails with e.g. sp-at-mem-access. > I haven't studied the patch + surrounding code enough to know > the answer to that. +1 to land if you can convince yourself > that PX semantics won't be changed. +2 if you can also figure > out how to test the behaviour of the --vex-iropt-register-updates > flag. > > See https://bugzilla.mozilla.org/show_bug.cgi?id=913876 for > the kinds of dirty tricks that people do, requiring precise > exceptions. > > re comments on the patch itself: > > +typedef > + struct { > + Bool present; > + Int low; > + Int high; > + } > + Interval; > > That has to be at least 12 bytes, or 16 on a 64 bit target. > struct { UShort low; UShort high; Bool present; } would make > it 8 bytes on all targets. re UShort vs Short, is there any > need to have the offsets signed? If memory is important for this type, the "present" can I guess be avoided by switching to semi-open interval semantic and use low=high to indicate not present. In other words, a write at 100, length 8 would be represented by low = 100, high = 108. A not present interval will be e.g. low = 0, high = 0. Also, the ATmpInfo components might be re-ordered maybe ? Did not look much at the rest of the patch. Philippe |
|
From: <sv...@va...> - 2013-09-10 19:01:12
|
Author: carll
Date: Tue Sep 10 19:01:00 2013
New Revision: 13539
Log:
Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM
Power ISA 2.07. The first bugzilla in the series was: 322294: Add initial
support for IBM Power ISA 2.07
Phase 2 VEX commit 2756 added support for the following new instructions to
VEX/priv/guest_ppc_toIR.c:
- lq, stq, lqarx, stqcx.
- mfvsrwz, mtvsrwz
- fmrgew, fmrgow
This commit adds the corresponding test cases for these instructions.
Added:
trunk/none/tests/ppc32/jm_fp_isa_2_07.stderr.exp
trunk/none/tests/ppc32/jm_fp_isa_2_07.stdout.exp
trunk/none/tests/ppc32/jm_fp_isa_2_07.vgtest
trunk/none/tests/ppc32/jm_int_isa_2_07.stderr.exp
trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp
trunk/none/tests/ppc32/jm_int_isa_2_07.vgtest
trunk/none/tests/ppc64/jm_fp_isa_2_07.stderr.exp
trunk/none/tests/ppc64/jm_fp_isa_2_07.stdout.exp
trunk/none/tests/ppc64/jm_fp_isa_2_07.vgtest
trunk/none/tests/ppc64/jm_int_isa_2_07.stderr.exp
trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
trunk/none/tests/ppc64/jm_int_isa_2_07.vgtest
Modified:
trunk/none/tests/ppc32/Makefile.am
trunk/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
trunk/none/tests/ppc64/test_isa_2_07_part1.c
Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Tue Sep 10 19:01:00 2013
@@ -38,6 +38,8 @@
test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
+ jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \
test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest
Added: trunk/none/tests/ppc32/jm_fp_isa_2_07.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_fp_isa_2_07.stderr.exp (added)
+++ trunk/none/tests/ppc32/jm_fp_isa_2_07.stderr.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/jm_fp_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_fp_isa_2_07.stdout.exp (added)
+++ trunk/none/tests/ppc32/jm_fp_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,51 @@
+fmrgew 0010000000000001, 0010000000000001 => 0010000000100000
+fmrgew 0010000000000001, 80100094e0000359 => 0010000080100094
+fmrgew 0010000000000001, 7ff0000000000000 => 001000007ff00000
+fmrgew 0010000000000001, fff8000000000000 => 00100000fff80000
+fmrgew 3fe00094e0000359, 0010000000000001 => 3fe0009400100000
+fmrgew 3fe00094e0000359, 80100094e0000359 => 3fe0009480100094
+fmrgew 3fe00094e0000359, 7ff0000000000000 => 3fe000947ff00000
+fmrgew 3fe00094e0000359, fff8000000000000 => 3fe00094fff80000
+fmrgew bfe0000000000001, 0010000000000001 => bfe0000000100000
+fmrgew bfe0000000000001, 80100094e0000359 => bfe0000080100094
+fmrgew bfe0000000000001, 7ff0000000000000 => bfe000007ff00000
+fmrgew bfe0000000000001, fff8000000000000 => bfe00000fff80000
+fmrgew 8000000000000000, 0010000000000001 => 8000000000100000
+fmrgew 8000000000000000, 80100094e0000359 => 8000000080100094
+fmrgew 8000000000000000, 7ff0000000000000 => 800000007ff00000
+fmrgew 8000000000000000, fff8000000000000 => 80000000fff80000
+fmrgew 7ff7ffffffffffff, 0010000000000001 => 7ff7ffff00100000
+fmrgew 7ff7ffffffffffff, 80100094e0000359 => 7ff7ffff80100094
+fmrgew 7ff7ffffffffffff, 7ff0000000000000 => 7ff7ffff7ff00000
+fmrgew 7ff7ffffffffffff, fff8000000000000 => 7ff7fffffff80000
+fmrgew fff8000000000000, 0010000000000001 => fff8000000100000
+fmrgew fff8000000000000, 80100094e0000359 => fff8000080100094
+fmrgew fff8000000000000, 7ff0000000000000 => fff800007ff00000
+fmrgew fff8000000000000, fff8000000000000 => fff80000fff80000
+
+fmrgow 0010000000000001, 0010000000000001 => 0000000100000001
+fmrgow 0010000000000001, 80100094e0000359 => 00000001e0000359
+fmrgow 0010000000000001, 7ff0000000000000 => 0000000100000000
+fmrgow 0010000000000001, fff8000000000000 => 0000000100000000
+fmrgow 3fe00094e0000359, 0010000000000001 => e000035900000001
+fmrgow 3fe00094e0000359, 80100094e0000359 => e0000359e0000359
+fmrgow 3fe00094e0000359, 7ff0000000000000 => e000035900000000
+fmrgow 3fe00094e0000359, fff8000000000000 => e000035900000000
+fmrgow bfe0000000000001, 0010000000000001 => 0000000100000001
+fmrgow bfe0000000000001, 80100094e0000359 => 00000001e0000359
+fmrgow bfe0000000000001, 7ff0000000000000 => 0000000100000000
+fmrgow bfe0000000000001, fff8000000000000 => 0000000100000000
+fmrgow 8000000000000000, 0010000000000001 => 0000000000000001
+fmrgow 8000000000000000, 80100094e0000359 => 00000000e0000359
+fmrgow 8000000000000000, 7ff0000000000000 => 0000000000000000
+fmrgow 8000000000000000, fff8000000000000 => 0000000000000000
+fmrgow 7ff7ffffffffffff, 0010000000000001 => ffffffff00000001
+fmrgow 7ff7ffffffffffff, 80100094e0000359 => ffffffffe0000359
+fmrgow 7ff7ffffffffffff, 7ff0000000000000 => ffffffff00000000
+fmrgow 7ff7ffffffffffff, fff8000000000000 => ffffffff00000000
+fmrgow fff8000000000000, 0010000000000001 => 0000000000000001
+fmrgow fff8000000000000, 80100094e0000359 => 00000000e0000359
+fmrgow fff8000000000000, 7ff0000000000000 => 0000000000000000
+fmrgow fff8000000000000, fff8000000000000 => 0000000000000000
+
+All done. Tested 2 different instructions
Added: trunk/none/tests/ppc32/jm_fp_isa_2_07.vgtest
==============================================================================
--- trunk/none/tests/ppc32/jm_fp_isa_2_07.vgtest (added)
+++ trunk/none/tests/ppc32/jm_fp_isa_2_07.vgtest Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_07_cap
+prog: test_isa_2_07_part1 -f
Added: trunk/none/tests/ppc32/jm_int_isa_2_07.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_int_isa_2_07.stderr.exp (added)
+++ trunk/none/tests/ppc32/jm_int_isa_2_07.stderr.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp (added)
+++ trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,9 @@
+stq 23456789,22446688, 0 => 0000000023456789,0000000022446688)
+
+lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 11335577,23456789)
+
+lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x11335577, 0x23456789)
+
+stqcx. 45236789,44226688, => 0000000045236789,0000000044226688; CR=20000000
+
+All done. Tested 4 different instructions
Added: trunk/none/tests/ppc32/jm_int_isa_2_07.vgtest
==============================================================================
--- trunk/none/tests/ppc32/jm_int_isa_2_07.vgtest (added)
+++ trunk/none/tests/ppc32/jm_int_isa_2_07.vgtest Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_07_cap
+prog: test_isa_2_07_part1 -i
Modified: trunk/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -3,11 +3,21 @@
mfvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mfvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+mfvsrwz: 0102030405060708 => 0000000005060708
+mfvsrwz: 090a0b0c0e0d0e0f => 000000000e0d0e0f
+mfvsrwz: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
+mfvsrwz: f9fafbfcfefdfeff => 00000000fefdfeff
+
mtvsrd: 0102030405060708 => 0000000005060708
mtvsrd: 090a0b0c0e0d0e0f => 000000000e0d0e0f
mtvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mtvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+mtvsrwz: 05060708 => 0000000005060708
+mtvsrwz: 0e0d0e0f => 000000000e0d0e0f
+mtvsrwz: f5f6f7f8 => 00000000f5f6f7f8
+mtvsrwz: fefdfeff => 00000000fefdfeff
+
mtfprwa: 05060708 => 0000000005060708
mtfprwa: 0e0d0e0f => 000000000e0d0e0f
mtfprwa: f5f6f7f8 => fffffffff5f6f7f8
@@ -31,4 +41,4 @@
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
-All done. Tested 5 different instructions
+All done. Tested 7 different instructions
Modified: trunk/none/tests/ppc64/Makefile.am
==============================================================================
--- trunk/none/tests/ppc64/Makefile.am (original)
+++ trunk/none/tests/ppc64/Makefile.am Tue Sep 10 19:01:00 2013
@@ -26,6 +26,8 @@
test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
+ jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \
test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest
check_PROGRAMS = \
Added: trunk/none/tests/ppc64/jm_fp_isa_2_07.stderr.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_fp_isa_2_07.stderr.exp (added)
+++ trunk/none/tests/ppc64/jm_fp_isa_2_07.stderr.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc64/jm_fp_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_fp_isa_2_07.stdout.exp (added)
+++ trunk/none/tests/ppc64/jm_fp_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,51 @@
+fmrgew 0010000000000001, 0010000000000001 => 0010000000100000
+fmrgew 0010000000000001, 80100094e0000359 => 0010000080100094
+fmrgew 0010000000000001, 7ff0000000000000 => 001000007ff00000
+fmrgew 0010000000000001, fff8000000000000 => 00100000fff80000
+fmrgew 3fe00094e0000359, 0010000000000001 => 3fe0009400100000
+fmrgew 3fe00094e0000359, 80100094e0000359 => 3fe0009480100094
+fmrgew 3fe00094e0000359, 7ff0000000000000 => 3fe000947ff00000
+fmrgew 3fe00094e0000359, fff8000000000000 => 3fe00094fff80000
+fmrgew bfe0000000000001, 0010000000000001 => bfe0000000100000
+fmrgew bfe0000000000001, 80100094e0000359 => bfe0000080100094
+fmrgew bfe0000000000001, 7ff0000000000000 => bfe000007ff00000
+fmrgew bfe0000000000001, fff8000000000000 => bfe00000fff80000
+fmrgew 8000000000000000, 0010000000000001 => 8000000000100000
+fmrgew 8000000000000000, 80100094e0000359 => 8000000080100094
+fmrgew 8000000000000000, 7ff0000000000000 => 800000007ff00000
+fmrgew 8000000000000000, fff8000000000000 => 80000000fff80000
+fmrgew 7ff7ffffffffffff, 0010000000000001 => 7ff7ffff00100000
+fmrgew 7ff7ffffffffffff, 80100094e0000359 => 7ff7ffff80100094
+fmrgew 7ff7ffffffffffff, 7ff0000000000000 => 7ff7ffff7ff00000
+fmrgew 7ff7ffffffffffff, fff8000000000000 => 7ff7fffffff80000
+fmrgew fff8000000000000, 0010000000000001 => fff8000000100000
+fmrgew fff8000000000000, 80100094e0000359 => fff8000080100094
+fmrgew fff8000000000000, 7ff0000000000000 => fff800007ff00000
+fmrgew fff8000000000000, fff8000000000000 => fff80000fff80000
+
+fmrgow 0010000000000001, 0010000000000001 => 0000000100000001
+fmrgow 0010000000000001, 80100094e0000359 => 00000001e0000359
+fmrgow 0010000000000001, 7ff0000000000000 => 0000000100000000
+fmrgow 0010000000000001, fff8000000000000 => 0000000100000000
+fmrgow 3fe00094e0000359, 0010000000000001 => e000035900000001
+fmrgow 3fe00094e0000359, 80100094e0000359 => e0000359e0000359
+fmrgow 3fe00094e0000359, 7ff0000000000000 => e000035900000000
+fmrgow 3fe00094e0000359, fff8000000000000 => e000035900000000
+fmrgow bfe0000000000001, 0010000000000001 => 0000000100000001
+fmrgow bfe0000000000001, 80100094e0000359 => 00000001e0000359
+fmrgow bfe0000000000001, 7ff0000000000000 => 0000000100000000
+fmrgow bfe0000000000001, fff8000000000000 => 0000000100000000
+fmrgow 8000000000000000, 0010000000000001 => 0000000000000001
+fmrgow 8000000000000000, 80100094e0000359 => 00000000e0000359
+fmrgow 8000000000000000, 7ff0000000000000 => 0000000000000000
+fmrgow 8000000000000000, fff8000000000000 => 0000000000000000
+fmrgow 7ff7ffffffffffff, 0010000000000001 => ffffffff00000001
+fmrgow 7ff7ffffffffffff, 80100094e0000359 => ffffffffe0000359
+fmrgow 7ff7ffffffffffff, 7ff0000000000000 => ffffffff00000000
+fmrgow 7ff7ffffffffffff, fff8000000000000 => ffffffff00000000
+fmrgow fff8000000000000, 0010000000000001 => 0000000000000001
+fmrgow fff8000000000000, 80100094e0000359 => 00000000e0000359
+fmrgow fff8000000000000, 7ff0000000000000 => 0000000000000000
+fmrgow fff8000000000000, fff8000000000000 => 0000000000000000
+
+All done. Tested 2 different instructions
Added: trunk/none/tests/ppc64/jm_fp_isa_2_07.vgtest
==============================================================================
--- trunk/none/tests/ppc64/jm_fp_isa_2_07.vgtest (added)
+++ trunk/none/tests/ppc64/jm_fp_isa_2_07.vgtest Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_07_cap
+prog: test_isa_2_07_part1 -f
Added: trunk/none/tests/ppc64/jm_int_isa_2_07.stderr.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stderr.exp (added)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stderr.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp (added)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -0,0 +1,9 @@
+stq abcdef0123456789,1133557722446688, 0 => abcdef0123456789,1133557722446688)
+
+lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+
+lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+
+stqcx. abefcd0145236789,1155337744226688 => abefcd0145236789,1155337744226688; CR=20000000
+
+All done. Tested 4 different instructions
Added: trunk/none/tests/ppc64/jm_int_isa_2_07.vgtest
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.vgtest (added)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.vgtest Tue Sep 10 19:01:00 2013
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_07_cap
+prog: test_isa_2_07_part1 -i
Modified: trunk/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp Tue Sep 10 19:01:00 2013
@@ -3,11 +3,21 @@
mfvsrd: f1f2f3f4f5f6f7f8 => f1f2f3f4f5f6f7f8
mfvsrd: f9fafbfcfefdfeff => f9fafbfcfefdfeff
+mfvsrwz: 0102030405060708 => 0000000005060708
+mfvsrwz: 090a0b0c0e0d0e0f => 000000000e0d0e0f
+mfvsrwz: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
+mfvsrwz: f9fafbfcfefdfeff => 00000000fefdfeff
+
mtvsrd: 0102030405060708 => 0102030405060708
mtvsrd: 090a0b0c0e0d0e0f => 090a0b0c0e0d0e0f
mtvsrd: f1f2f3f4f5f6f7f8 => f1f2f3f4f5f6f7f8
mtvsrd: f9fafbfcfefdfeff => f9fafbfcfefdfeff
+mtvsrwz: 05060708 => 0000000005060708
+mtvsrwz: 0e0d0e0f => 000000000e0d0e0f
+mtvsrwz: f5f6f7f8 => 00000000f5f6f7f8
+mtvsrwz: fefdfeff => 00000000fefdfeff
+
mtfprwa: 05060708 => 0000000005060708
mtfprwa: 0e0d0e0f => 000000000e0d0e0f
mtfprwa: f5f6f7f8 => fffffffff5f6f7f8
@@ -31,4 +41,4 @@
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
-All done. Tested 5 different instructions
+All done. Tested 7 different instructions
Modified: trunk/none/tests/ppc64/test_isa_2_07_part1.c
==============================================================================
--- trunk/none/tests/ppc64/test_isa_2_07_part1.c (original)
+++ trunk/none/tests/ppc64/test_isa_2_07_part1.c Tue Sep 10 19:01:00 2013
@@ -129,8 +129,10 @@
#ifndef __powerpc64__
typedef uint32_t HWord_t;
+#define ZERO 0
#else
typedef uint64_t HWord_t;
+#define ZERO 0ULL
#endif /* __powerpc64__ */
typedef uint64_t Word_t;
@@ -181,6 +183,8 @@
register double f16 __asm__ ("fr16");
register double f17 __asm__ ("fr17");
register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
register HWord_t r17 __asm__ ("r17");
typedef void (*test_func_t) (void);
@@ -264,6 +268,65 @@
unused uint32_t test_flags);
} special_t;
+static void test_stq(void)
+{
+ __asm__ __volatile__ ("stq %0, 0(%1)" : :"r" (r14), "r" (r16));
+}
+
+static test_t tests_istq_ops_two_i16[] = {
+ { &test_stq , "stq", },
+ { NULL, NULL, },
+};
+
+static void test_lq(void)
+{
+ __asm__ __volatile__ ("lq %0, 0(%1)" : :"r" (r14), "r" (r16));
+}
+
+static test_t tests_ildq_ops_two_i16[] = {
+ { &test_lq , "lq", },
+ { NULL, NULL, },
+};
+
+
+Word_t * mem_resv;
+static void test_stqcx(void)
+{
+ /* Have to do the lqarx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lqarx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("stqcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static test_t tests_stq_ops_three[] = {
+ { &test_stqcx , "stqcx.", },
+ { NULL, NULL, },
+};
+
+static void test_lqarx(void)
+{
+ __asm__ __volatile__ ("lqarx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static test_t tests_ldq_ops_three[] = {
+ { &test_lqarx , "lqarx", },
+ { NULL, NULL, },
+};
+
+static void test_fmrgew (void)
+{
+ __asm__ __volatile__ ("fmrgew 17,14,15");
+};
+
+static void test_fmrgow (void)
+{
+ __asm__ __volatile__ ("fmrgow 17,14,15");
+};
+
+
// VSX move instructions
static void test_mfvsrd (void)
@@ -271,11 +334,22 @@
__asm__ __volatile__ ("mfvsrd %0,%x1" : "=r" (r14) : "ws" (vec_inA));
};
+static void test_mfvsrwz (void)
+{
+ __asm__ __volatile__ ("mfvsrwz %0,%x1" : "=r" (r14) : "ws" (vec_inA));
+};
+
static void test_mtvsrd (void)
{
__asm__ __volatile__ ("mtvsrd %x0,%1" : "=ws" (vec_out) : "r" (r14));
};
+static void test_mtvsrwz (void)
+{
+ __asm__ __volatile__ ("mtvsrwz %x0,%1" : "=ws" (vec_out) : "r" (r14));
+};
+
+
static void test_mtfprwa (void)
{
__asm__ __volatile__ ("mtfprwa %x0,%1" : "=ws" (vec_out) : "r" (r14));
@@ -283,7 +357,9 @@
static test_t tests_move_ops_spe[] = {
{ &test_mfvsrd , "mfvsrd" },
+ { &test_mfvsrwz , "mfvsrwz" },
{ &test_mtvsrd , "mtvsrd" },
+ { &test_mtvsrwz , "mtvsrwz" },
{ &test_mtfprwa , "mtfprwa" },
{ NULL, NULL }
};
@@ -322,6 +398,144 @@
vdargs[3] = 0xF9FAFBFCFEFDFEFFULL;
}
+static double *fargs = NULL;
+static int nb_fargs = 0;
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table (void)
+{
+ /* Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * +SNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -SNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * (8 values)
+
+ * Ref only:
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -QNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ * +SNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -SNaN : 1 0xFF 0x400000 => 0xFFC00000
+ */
+ uint64_t mant;
+ uint16_t _exp, e0, e1;
+ int s;
+ int i=0;
+
+ /* Note: VEX isn't so hot with denormals, so don't bother
+ testing them: set _exp > 0
+ */
+
+ if ( arg_list_size == 1 ) { // Large
+ fargs = malloc(200 * sizeof(double));
+ for (s=0; s<2; s++) {
+ for (e0=0; e0<2; e0++) {
+ for (e1=0x001; ; e1 = ((e1 + 1) << 2) + 6) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = (e0 << 10) | e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 13) + 0x359) {
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ }
+ } else { // Default
+ fargs = malloc(16 * sizeof(double));
+ for (s=0; s<2; s++) { // x2
+ for (e1=0x001; ; e1 = ((e1 + 1) << 13) + 7) { // x2
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) { // x2
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ }
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ AB_DPRINTF("Registered %d fargs values\n", i);
+
+ nb_fargs = i;
+}
+
+
+
static int check_filter (char *filter)
{
char *c;
@@ -371,6 +585,39 @@
int cr;
} insn_sel_flags_t;
+static void test_float_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ double res;
+ Word_t u0, u1, ur;
+ volatile uint32_t flags;
+ int i, j;
+
+ for (i=0; i<nb_fargs; i+=3) {
+ for (j=0; j<nb_fargs; j+=5) {
+ u0 = *(Word_t *)(&fargs[i]);
+ u1 = *(Word_t *)(&fargs[j]);
+ f14 = fargs[i];
+ f15 = fargs[j];
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f17;
+ ur = *(uint64_t *)(&res);
+
+ printf("%s %016llx, %016llx => %016llx",
+ name, u0, u1, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
+#endif
+ printf("\n");
+ }
+ if (verbose) printf("\n");
+ }
+}
+
static void mfvs(const char* name, test_func_t func,
unused uint32_t test_flags)
@@ -380,9 +627,10 @@
*/
int i;
volatile Word_t result;
+ result = 0ULL;
for (i=0; i < NB_VDARGS; i++) {
- r14 = 0ULL;
+ r14 = ZERO;
vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
(*func)();
@@ -452,17 +700,25 @@
static special_t special_move_ops[] = {
{
- "mfvsrd", /* move from vector to scalar reg */
+ "mfvsrd", /* move from vector to scalar reg doubleword */
&mfvs,
},
{
- "mtvsrd", /* move from scalar to vector reg */
+ "mtvsrd", /* move from scalar to vector reg doubleword */
&mtvs,
},
{
"mtfprwa", /* (extended mnemonic for mtvsrwa) move from scalar to vector reg with twoâs-complement */
&mtvs2s,
},
+ {
+ "mfvsrwz", /* move from vector to scalar reg word */
+ &mfvs,
+ },
+ {
+ "mtvsrwz", /* move from scalar to vector reg word */
+ &mtvs2s,
+ }
};
static void test_move_special(const char* name, test_func_t func,
@@ -514,17 +770,201 @@
}
}
+static void test_int_stq_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* Store quad word from register pair */
+ int offs, k;
+ HWord_t base;
+ Word_t *iargs_priv;
+
+ // private iargs table to store to, note storing pair of regs
+ iargs_priv = memalign16(2 * sizeof(Word_t));
+
+ base = (HWord_t)&iargs_priv[0];
+ for (k = 0; k < 2; k++) // clear array
+ iargs_priv[k] = 0;
+
+ offs = 0;
+
+ /* setup source register pair */
+ r14 = (HWord_t) 0xABCDEF0123456789ULL;
+ r15 = (HWord_t) 0x1133557722446688ULL;
+
+ r16 = base; // store to r16 + offs
+
+ (*func_IN)();
+
+#ifndef __powerpc64__
+ printf("%s %08x,%08x, %2d => "
+#else
+ printf("%s %016llx,%016llx, %3d => "
+#endif
+ "%016llx,%016llx)\n",
+ name, r14, r15, offs, iargs_priv[0], iargs_priv[1]);
+
+ if (verbose) printf("\n");
+ free(iargs_priv);
+}
+
+
+static void test_int_stq_three_regs (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* Store quad word from register pair */
+ volatile uint32_t flags, xer;
+ int k;
+ HWord_t base;
+
+ base = (HWord_t)&mem_resv[0];
+ for (k = 0; k < 2; k++) // setup array for lqarx inst
+ mem_resv[k] = k;
+
+ /* setup source register pair for store */
+ r14 = ZERO;
+ r15 = ZERO;
+ r16 = base; // store to r16 + r17
+ r17 = ZERO;
+
+ /* In order for the store to occur, the lqarx instruction must first
+ * be used to load from the address thus creating a reservation at the
+ * memory address. The lqarx instruction is done in the test_stqcx(),
+ * then registers 14, r15 are changed to the data to be stored in memory
+ * by the stqcx instruction.
+ */
+ SET_CR_XER_ZERO;
+ (*func_IN)();
+ GET_CR_XER(flags,xer);
+#ifndef __powerpc64__
+ printf("%s %08x,%08x, => "
+#else
+ printf("%s %016llx,%016llx => "
+#endif
+ "%016llx,%016llx; CR=%08x\n",
+ name, r14, r15, mem_resv[0], mem_resv[1], flags);
+
+ if (verbose) printf("\n");
+}
+
+static void test_int_ldq_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* load quad word from register pair */
+ volatile uint32_t flags, xer;
+ Word_t * mem_priv;
+ HWord_t base;
+
+ // private iargs table to store to, note storing pair of regs
+ mem_priv = memalign16(2 * sizeof(Word_t)); // want 128-bits
+
+ base = (HWord_t)&mem_priv[0];
+
+ mem_priv[0] = 0xAACCEE0011335577ULL;
+ mem_priv[1] = 0xABCDEF0123456789ULL;
+
+ r14 = 0;
+ r15 = 0;
+ r16 = base; // fetch from r16 + offs
+ SET_CR_XER_ZERO;
+ (*func_IN)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = %08x,%08x)\n",
+#else
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%016llx, 0x%016llx)\n",
+#endif
+ name, mem_priv[0], mem_priv[1], r14, r15);
+
+ if (verbose) printf("\n");
+
+ free(mem_priv);
+}
+
+static void test_int_ldq_three_regs (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* load quad word from register pair */
+ HWord_t base;
+
+ base = (HWord_t)&mem_resv[0];
+
+ mem_resv[0] = 0xAACCEE0011335577ULL;
+ mem_resv[1] = 0xABCDEF0123456789ULL;
+
+ r14 = 0;
+ r15 = 0;
+ r16 = base; // fetch from r16 + r17
+ r17 = 0;
+
+ (*func_IN)();
+
+#ifndef __powerpc64__
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%08x, 0x%08x)\n",
+#else
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%016llx, 0x%016llx)\n",
+#endif
+ name, mem_resv[0], mem_resv[1], r14, r15);
+ if (verbose) printf("\n");
+
+}
+
+
+
+/* Used in do_tests */
+enum ALTIVEC_LOOPS {
+ ALTV_MOV,
+ ALTV_INT
+};
+static test_loop_t altivec_loops[] = {
+ &test_move_special,
+ &test_av_dint_two_args,
+ NULL
+};
+
/* Used in do_tests, indexed by flags->nb_args
Elements correspond to enum test_flags::num args
*/
-static test_loop_t altivec_mov_loops[] = {
- &test_move_special,
- NULL
+static test_loop_t int_loops[] = {
+ /* The #defines for the family, number registers need the array
+ * to be properly indexed. This test is for the new ISA 2.0.7
+ * instructions. The infrastructure has been left for the momemnt
+ */
+ NULL, //&test_int_one_arg,
+ NULL, //&test_int_two_args,
+ NULL, //&test_int_three_args,
+ NULL, //&test_int_two_args,
+ NULL, //&test_int_one_reg_imm16,
+ NULL, //&test_int_one_reg_imm16,
+ NULL, //&test_int_special,
+ NULL, //&test_int_ld_one_reg_imm16,
+ NULL, //&test_int_ld_two_regs,
+ NULL, //&test_int_st_two_regs_imm16,
+ NULL, //&test_int_st_three_regs,
+ &test_int_stq_two_regs_imm16,
+ &test_int_ldq_two_regs_imm16,
+ &test_int_stq_three_regs,
+ &test_int_ldq_three_regs,
};
-static test_loop_t altivec_dint_loops[] = {
- &test_av_dint_two_args,
- NULL
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+ Must have NULL for last entry.
+ */
+static test_loop_t float_loops[] = {
+ NULL,
+ &test_float_two_args,
+};
+
+
+static test_t tests_fa_ops_two[] = {
+ { &test_fmrgew , "fmrgew", },
+ { &test_fmrgow , "fmrgow", },
+ { NULL, NULL, },
};
static test_table_t all_tests[] = {
@@ -538,6 +978,31 @@
"PC altivec double word integer insns with two args",
PPC_ALTIVEC | PPC_ARITH | PPC_TWO_ARGS,
},
+ {
+ tests_istq_ops_two_i16,
+ "PPC store quadword insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0001050c,
+ },
+ {
+ tests_ildq_ops_two_i16,
+ "PPC load quadword insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0001050d,
+ },
+ {
+ tests_ldq_ops_three,
+ "PPC load quadword insns\n with three register args",
+ 0x0001050f,
+ },
+ {
+ tests_stq_ops_three,
+ "PPC store quadword insns\n with three register args",
+ 0x0001050e,
+ },
+ {
+ tests_fa_ops_two,
+ "PPC floating point arith insns with two args",
+ 0x00020102,
+ },
{ NULL, NULL, 0x00000000, },
};
@@ -593,20 +1058,21 @@
/* Select the test loop */
switch (family) {
case PPC_INTEGER:
- printf("Currently there are no integer tests enabled in this testsuite.\n");
+ mem_resv = memalign16(2 * sizeof(HWord_t)); // want 128-bits
+ loop = &int_loops[nb_args - 1];
break;
case PPC_FLOAT:
- printf("Currently there are no float tests enabled in this testsuite.\n");
+ loop = &float_loops[nb_args - 1];
break;
case PPC_ALTIVEC:
switch (type) {
case PPC_MOV:
- loop = &altivec_mov_loops[0];
+ loop = &altivec_loops[ALTV_MOV];
break;
case PPC_ARITH:
- loop = &altivec_dint_loops[0];
+ loop = &altivec_loops[ALTV_INT];
break;
default:
printf("No altivec test defined for type %x\n", type);
@@ -689,6 +1155,7 @@
flags.integer = 1;
break;
case 'f':
+ build_fargs_table();
flags.floats = 1;
break;
case 'a':
|
|
From: <sv...@va...> - 2013-09-10 18:46:49
|
Author: carll
Date: Tue Sep 10 18:46:40 2013
New Revision: 2756
Log:
Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM
Power ISA 2.07. The first bugzilla in the series was: 322294: Add initial
support for IBM Power ISA 2.07
Phase 2 adds support for the following new instructions to
VEX/priv/guest_ppc_toIR.c:
- lq, stq, lqarx, stqcx.
- mfvsrwz, mtvsrwz
- fmrgew, fmrgow
There is a corresponding test case for these instructions, see the bugzilla
for the commit number.
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Sep 10 18:46:40 2013
@@ -1531,7 +1531,7 @@
restart of the current insn. */
static void gen_SIGBUS_if_misaligned ( IRTemp addr, UChar align )
{
- vassert(align == 4 || align == 8);
+ vassert(align == 4 || align == 8 || align == 16);
if (mode64) {
vassert(typeOfIRTemp(irsb->tyenv, addr) == Ity_I64);
stmt(
@@ -4553,9 +4553,16 @@
case 0x1F: // register offset
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
break;
+ case 0x38: // immediate offset: 64bit: lq: maskoff
+ // lowest 4 bits of immediate before forming EA
+ simm16 = simm16 & 0xFFFFFFF0;
+ assign( EA, ea_rAor0_simm( rA_addr, simm16 ) );
+ break;
case 0x3A: // immediate offset: 64bit: ld/ldu/lwa: mask off
// lowest 2 bits of immediate before forming EA
simm16 = simm16 & 0xFFFFFFFC;
+ assign( EA, ea_rAor0_simm( rA_addr, simm16 ) );
+ break;
default: // immediate offset
assign( EA, ea_rAor0_simm( rA_addr, simm16 ) );
break;
@@ -4777,6 +4784,33 @@
}
break;
+ case 0x38: {
+ IRTemp high = newTemp(ty);
+ IRTemp low = newTemp(ty);
+ /* DQ Form - 128bit Loads. Lowest bits [1:0] are the PT field. */
+ DIP("lq r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+ /* NOTE: there are some changes to XER[41:42] that have not been
+ * implemented.
+ */
+ // trap if EA misaligned on 16 byte address
+ if (mode64) {
+ assign(high, loadBE(ty, mkexpr( EA ) ) );
+ assign(low, loadBE(ty, binop( Iop_Add64,
+ mkexpr( EA ),
+ mkU64( 8 ) ) ) );
+ } else {
+ assign(high, loadBE(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+ mkU32( 4 ) ) ) );
+ assign(low, loadBE(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+ mkU32( 12 ) ) ) );
+ }
+ gen_SIGBUS_if_misaligned( EA, 16 );
+ putIReg( rD_addr, mkexpr( high) );
+ putIReg( rD_addr+1, mkexpr( low) );
+ break;
+ }
default:
vex_printf("dis_int_load(ppc)(opc1)\n");
return False;
@@ -4814,7 +4848,7 @@
case 0x1F: // register offset
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
break;
- case 0x3E: // immediate offset: 64bit: std/stdu: mask off
+ case 0x3E: // immediate offset: 64bit: std/stdu/stq: mask off
// lowest 2 bits of immediate before forming EA
simm16 = simm16 & 0xFFFFFFFC;
default: // immediate offset
@@ -4965,6 +4999,30 @@
storeBE( mkexpr(EA), mkexpr(rS) );
break;
+ case 0x2: { // stq (Store QuadWord, Update, PPC64 p583)
+ IRTemp EA_hi = newTemp(ty);
+ IRTemp EA_lo = newTemp(ty);
+ DIP("stq r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+
+ if (mode64) {
+ /* upper 64-bits */
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+
+ /* lower 64-bits */
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) );
+ } else {
+ /* upper half of upper 64-bits */
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+4 ) );
+
+ /* lower half of upper 64-bits */
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) );
+ }
+ putIReg( rA_addr, mkexpr(EA_hi) );
+ storeBE( mkexpr(EA_hi), mkexpr(rS) );
+ putIReg( rA_addr, mkexpr( EA_lo) );
+ storeBE( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
+ break;
+ }
default:
vex_printf("dis_int_load(ppc)(0x3A, opc2)\n");
return False;
@@ -6032,6 +6090,81 @@
break;
}
+ /* 128bit Memsync */
+ case 0x114: { // lqarx (Load QuadWord and Reserve Indexed)
+ IRTemp res_hi = newTemp(ty);
+ IRTemp res_lo = newTemp(ty);
+
+ /* According to the PowerPC ISA version 2.07, b0 (called EH
+ in the documentation) is merely a hint bit to the
+ hardware, I think as to whether or not contention is
+ likely. So we can just ignore it. */
+ DIP("lqarx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0);
+
+ // trap if misaligned
+ gen_SIGBUS_if_misaligned( EA, 16 );
+
+ // and actually do the load
+ if (mode64) {
+ stmt( IRStmt_LLSC( Iend_BE, res_hi,
+ mkexpr(EA), NULL/*this is a load*/) );
+ stmt( IRStmt_LLSC( Iend_BE, res_lo,
+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+ NULL/*this is a load*/) );
+ } else {
+ stmt( IRStmt_LLSC( Iend_BE, res_hi,
+ binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
+ NULL/*this is a load*/) );
+ stmt( IRStmt_LLSC( Iend_BE, res_lo,
+ binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
+ NULL/*this is a load*/) );
+ }
+ putIReg( rD_addr, mkexpr(res_hi) );
+ putIReg( rD_addr+1, mkexpr(res_lo) );
+ break;
+ }
+
+ case 0x0B6: { // stqcx. (Store QuadWord Condition Indexd, PPC64)
+ // A marginally simplified version of the stwcx. case
+ IRTemp rS_hi = newTemp(ty);
+ IRTemp rS_lo = newTemp(ty);
+ IRTemp resSC;
+ if (b0 != 1) {
+ vex_printf("dis_memsync(ppc)(stqcx.,b0)\n");
+ return False;
+ }
+
+ DIP("stqcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+
+ // trap if misaligned
+ gen_SIGBUS_if_misaligned( EA, 16 );
+ // Get the data to be stored
+ assign( rS_hi, getIReg(rS_addr) );
+ assign( rS_lo, getIReg(rS_addr+1) );
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+
+ if (mode64) {
+ stmt( IRStmt_LLSC( Iend_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+ storeBE(binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
+ } else {
+ stmt( IRStmt_LLSC( Iend_BE, resSC, binop( Iop_Add32,
+ mkexpr(EA),
+ mkU32(4) ),
+ mkexpr(rS_hi) ) );
+ storeBE(binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
+ }
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+ putCR321(0, binop( Iop_Shl8,
+ unop(Iop_1Uto8, mkexpr(resSC) ),
+ mkU8(1)));
+ putCR0(0, getXER_SO());
+ break;
+ }
+
default:
vex_printf("dis_memsync(ppc)(opc2)\n");
return False;
@@ -6647,7 +6780,7 @@
DIP("mtvrsave r%u\n", rS_addr);
putGST( PPC_GST_VRSAVE, mkNarrowTo32(ty, mkexpr(rS)) );
break;
-
+
default:
vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR);
return False;
@@ -6667,7 +6800,7 @@
* instruction in terms of resource availability.
* For SX=1, mfvsrd is treated as a Vector instruction in
* terms of resource availability.
- *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
+ * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
*/
assign( vS, getVSReg( XS ) );
high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
@@ -6676,6 +6809,31 @@
break;
}
+ case 0x73: // mfvsrwz
+ {
+ UChar XS = ifieldRegXS( theInstr );
+ UChar rA_addr = ifieldRegA(theInstr);
+ IRExpr * high64;
+ IRTemp vS = newTemp( Ity_V128 );
+ DIP("mfvsrwz r%u,vsr%d\n", rA_addr, (UInt)XS);
+ /* XS = SX || S
+ * For SX=0, mfvsrwz is treated as a Floating-Point
+ * instruction in terms of resource availability.
+ * For SX=1, mfvsrwz is treated as a Vector instruction in
+ * terms of resource availability.
+ * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
+ */
+
+ assign( vS, getVSReg( XS ) );
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+ /* move value to the destination setting the upper 32-bits to zero */
+ putIReg( rA_addr, (mode64) ?
+ binop( Iop_And64, high64, mkU64( 0xFFFFFFFF ) ) :
+ unop( Iop_64to32,
+ binop( Iop_And64, high64, mkU64( 0xFFFFFFFF ) ) ) );
+ break;
+ }
+
case 0xB3: // mtvsrd
{
UChar XT = ifieldRegXT( theInstr );
@@ -6687,7 +6845,7 @@
* instruction in terms of resource availability.
* For SX=1, mfvsrd is treated as a Vector instruction in
* terms of resource availability.
- *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
+ * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
*/
assign( rA, getIReg(rA_addr) );
@@ -6713,7 +6871,7 @@
* instruction in terms of resource availability.
* For SX=1, mtvsrwa is treated as a Vector instruction in
* terms of resource availability.
- *NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
+ * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
*/
if (mode64)
assign( rA, unop( Iop_64to32, getIReg( rA_addr ) ) );
@@ -6726,6 +6884,30 @@
break;
}
+ case 0xF3: // mtvsrwz
+ {
+ UChar XT = ifieldRegXT( theInstr );
+ UChar rA_addr = ifieldRegA(theInstr);
+ IRTemp rA = newTemp( Ity_I32 );
+ DIP("mtvsrwz vsr%d,r%u\n", rA_addr, (UInt)XT);
+ /* XS = SX || S
+ * For SX=0, mtvsrwz is treated as a Floating-Point
+ * instruction in terms of resource availability.
+ * For SX=1, mtvsrwz is treated as a Vector instruction in
+ * terms of resource availability.
+ * FIXME: NEED TO FIGURE OUT HOW TO IMPLEMENT THE RESOURCE AVAILABILITY PART
+ */
+ if (mode64)
+ assign( rA, unop( Iop_64to32, getIReg( rA_addr ) ) );
+ else
+ assign( rA, getIReg(rA_addr) );
+
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ binop( Iop_32HLto64, mkU32( 0 ), mkexpr ( rA ) ),
+ mkU64( 0 ) ) );
+ break;
+ }
+
default:
vex_printf("dis_proc_ctl(ppc)(opc2)\n");
return False;
@@ -8483,6 +8665,60 @@
/*
+ Floating Point Merge Instructions
+*/
+static Bool dis_fp_merge ( UInt theInstr )
+{
+ /* X-Form */
+ UInt opc2 = ifieldOPClo10(theInstr);
+ UChar frD_addr = ifieldRegDS(theInstr);
+ UChar frA_addr = ifieldRegA(theInstr);
+ UChar frB_addr = ifieldRegB(theInstr);
+
+ IRTemp frD = newTemp(Ity_F64);
+ IRTemp frA = newTemp(Ity_F64);
+ IRTemp frB = newTemp(Ity_F64);
+
+ assign( frA, getFReg(frA_addr));
+ assign( frB, getFReg(frB_addr));
+
+ switch (opc2) {
+ case 0x3c6: // fmrgew floating merge even word
+ DIP("fmrgew fr%u,fr%u,fr%u\n", frD_addr, frA_addr, frB_addr);
+
+ assign( frD, unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ mkexpr(frA) ) ),
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ mkexpr(frB) ) ) ) ) );
+ break;
+
+ case 0x346: // fmrgow floating merge odd word
+ DIP("fmrgow fr%u,fr%u,fr%u\n", frD_addr, frA_addr, frB_addr);
+
+ assign( frD, unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ unop( Iop_64to32,
+ unop( Iop_ReinterpF64asI64,
+ mkexpr(frA) ) ),
+ unop( Iop_64to32,
+ unop( Iop_ReinterpF64asI64,
+ mkexpr(frB) ) ) ) ) );
+ break;
+
+ default:
+ vex_printf("dis_fp_merge(ppc)(opc2)\n");
+ return False;
+ }
+
+ putFReg( frD_addr, mkexpr(frD) );
+ return True;
+}
+
+/*
Floating Point Move Instructions
*/
static Bool dis_fp_move ( UInt theInstr )
@@ -16930,6 +17166,11 @@
if (dis_fp_pair( theInstr )) goto decode_success;
goto decode_failure;
+ /* 128-bit Integer Load */
+ case 0x38: // lq
+ if (dis_int_load( theInstr )) goto decode_success;
+ goto decode_failure;
+
/* 64bit Integer Loads */
case 0x3A: // ld, ldu, lwa
if (!mode64) goto decode_failure;
@@ -17209,7 +17450,7 @@
}
/* 64bit Integer Stores */
- case 0x3E: // std, stdu
+ case 0x3E: // std, stdu, stq
if (dis_int_store( theInstr, abiinfo )) goto decode_success;
goto decode_failure;
@@ -17347,6 +17588,10 @@
if (dis_fp_move( theInstr )) goto decode_success;
goto decode_failure;
+ case 0x3c6: case 0x346: // fmrgew, fmrgow
+ if (dis_fp_merge( theInstr )) goto decode_success;
+ goto decode_failure;
+
/* Floating Point Status/Control Register Instructions */
case 0x026: // mtfsb1
case 0x040: // mcrfs
@@ -17431,7 +17676,7 @@
case 0x096: // isync
if (dis_memsync( theInstr )) goto decode_success;
goto decode_failure;
-
+
default:
goto decode_failure;
}
@@ -17593,11 +17838,16 @@
if (dis_memsync( theInstr )) goto decode_success;
goto decode_failure;
+ case 0x114: case 0x0B6: // lqarx, stqcx.
+ if (dis_memsync( theInstr )) goto decode_success;
+ goto decode_failure;
+
/* Processor Control Instructions */
- case 0x33: // mfvsrd
- case 0xB3: case 0xD3: // mtvsrd, mtvsrwa
+ case 0x33: case 0x73: // mfvsrd, mfvsrwz
+ case 0xB3: case 0xD3: case 0xF3: // mtvsrd, mtvsrwa, mtvsrwz
case 0x200: case 0x013: case 0x153: // mcrxr, mfcr, mfspr
case 0x173: case 0x090: case 0x1D3: // mftb, mtcrf, mtspr
+ case 0x220: // mcrxrt
if (dis_proc_ctl( abiinfo, theInstr )) goto decode_success;
goto decode_failure;
|
|
From: Florian K. <fl...@ei...> - 2013-09-10 18:29:51
|
On 09/10/2013 12:56 PM, Julian Seward wrote: > > My main concern with this is that it doesn't change the > carefully-balanced and completely-untested (AFAIK) precise-exception > semantics, as controlled by > > --vex-iropt-register-updates=sp-at-mem-access > |unwindregs-at-mem-access [default] > |allregs-at-mem-access > |allregs-at-each-insn > > In particular, need to verify that (1) the patch does not remove any > PUTs, loads or stores, and (2) it does not reorder any PUTs with > respect to loads or stores, and (3) it doesn not reorder any stores > with respect to loads or other stores. The patch does none of those things. What is changed is the logic to decide whether or not an expression containing one or more GET[I]s and preceding a PUT statement can be substituted into a statement following the PUT. Doing such a substitution eliminates a WrTmp statement but otherwise does not remove or reorder any statement. > > IOW .. imagine we chop up the post-treebuild IRStmts into groups, > in which each group contains a single Store, a single Put, or > arbitrary Loads, Gets and arithmetic, but no Stores or Puts. > (ignoring IRDirty and other complexities). Then, the question is: > does the patch change the sequence? I cannot imagine how it could. > > +2 if you can also figure > out how to test the behaviour of the --vex-iropt-register-updates > flag. We need some way to feed an insn sequence into VEX, run it through the pipeline with various options and observe the output. https://bugs.kde.org/show_bug.cgi?id=272405 has some thoughts on that. See the run-insn.c attachment there. But one would also need a much more flexible testing harness for that. vg-regtest is not flexible enough. The BZ discusses that also to some extent. > > See https://bugzilla.mozilla.org/show_bug.cgi?id=913876 for > the kinds of dirty tricks that people do, requiring precise > exceptions. Yikes > > re comments on the patch itself: > > +typedef > + struct { > + Bool present; > + Int low; > + Int high; > + } > + Interval; > > That has to be at least 12 bytes, or 16 on a 64 bit target. Did you test your hypothesis ? :) That struct uses 12 bytes on ILP32 and LP64. > struct { UShort low; UShort high; Bool present; } would make > it 8 bytes on all targets. .. would make it 6 bytes on all targets. > re UShort vs Short, is there any > need to have the offsets signed? I use an "Int" because that is what is used for "offset into guest state" and I was attempting to be consistent. Cf. libvex_ir.h - definition of the Get and Put variants and many other places elsewhere. IMNSHO those offsets should all be unsigned entities. And, yes, a "short" would be more than enough. > > + /* Assume all guest state */ > > A bit cryptic, but from reading the lines after, you mean something > like "Assume all guest state is written" (or some such). Yes, I'll change that. Florian |
|
From: Florian K. <fl...@ei...> - 2013-09-10 14:38:15
|
On 09/09/2013 11:32 PM, Philippe Waroquiers wrote: > On Sun, 2013-09-08 at 23:34 +0200, Florian Krohm wrote: >> What if we run perf every day and send the results to e.g >> pe...@va...? Whenever mail is received at that address a little >> script runs that reads the perf results and collects them in some light >> weight "data base" that we could look at at valgrind.org/perf. > So, maybe the valdev archive can be seen as the DB. > I think you started to write a script to handle archived test results > and make an html page from it. We could use the mailing list archive as the "data base". But accessing it is slow. I ran that script you mentioned and it took minutes to process 100 mails. Which means that you probably don't want to run it yourself to figure out whether last night's build regressed performancewise. Also, accessing the mailing list archive is "by number". E.g. mail #20000 is a certain build that happened on Sep 8, 2012. But you don't know that relation. So if you want to know how performance evolved since a particular date, you either need to do some kind of bisection to figure out the corresponding email number forat that date or you need to store this information somewhere. I guess a nightly cronjob on valgrind.org should do this: (1) process the valdev emails that came in today (which implies that we keep the largest email number that was processed the previous night) (2) extract the performance data and write it somewhere for later query (3) create some web page to visualise the performance data (it will use the data collected in #2) > A colleague has started enhancing > this script (e.g. taking some other ideas from what wine does for > their night tests results). Let's see it :) > > Maybe we could have the "conf" allowing to specify: > to run perf test y/n > the --reps= value > with comparison with the previous day y/n That would be sufficient to do what we envision. Florian |
|
From: <sv...@va...> - 2013-09-10 14:00:54
|
Author: florian
Date: Tue Sep 10 14:00:45 2013
New Revision: 13538
Log:
Fix a bug introduced in the previous revision.
Modified:
trunk/auxprogs/nightly-build-summary
Modified: trunk/auxprogs/nightly-build-summary
==============================================================================
--- trunk/auxprogs/nightly-build-summary (original)
+++ trunk/auxprogs/nightly-build-summary Tue Sep 10 14:00:45 2013
@@ -104,7 +104,7 @@
my %hash = ();
# 1) Locate the section with the info about the environment of this nightly run
- for ($i = $i + 1; $i < $n; ++$i) {
+ for ($i = 0; $i < $n; ++$i) {
last if ($lines[$i] =~ /^valgrind revision:/);
}
die "no info block in message $msgno" if ($i == $n);
|
|
From: Julian S. <js...@ac...> - 2013-09-10 10:57:21
|
On 09/06/2013 06:11 PM, Florian Krohm wrote:
> This patch introduces an enhancement in VEX's tree builder.
Seems plausible.
My main concern with this is that it doesn't change the
carefully-balanced and completely-untested (AFAIK) precise-exception
semantics, as controlled by
--vex-iropt-register-updates=sp-at-mem-access
|unwindregs-at-mem-access [default]
|allregs-at-mem-access
|allregs-at-each-insn
In particular, need to verify that (1) the patch does not remove any
PUTs, loads or stores, and (2) it does not reorder any PUTs with
respect to loads or stores, and (3) it doesn not reorder any stores
with respect to loads or other stores.
IOW .. imagine we chop up the post-treebuild IRStmts into groups,
in which each group contains a single Store, a single Put, or
arbitrary Loads, Gets and arithmetic, but no Stores or Puts.
(ignoring IRDirty and other complexities). Then, the question is:
does the patch change the sequence?
I haven't studied the patch + surrounding code enough to know
the answer to that. +1 to land if you can convince yourself
that PX semantics won't be changed. +2 if you can also figure
out how to test the behaviour of the --vex-iropt-register-updates
flag.
See https://bugzilla.mozilla.org/show_bug.cgi?id=913876 for
the kinds of dirty tricks that people do, requiring precise
exceptions.
re comments on the patch itself:
+typedef
+ struct {
+ Bool present;
+ Int low;
+ Int high;
+ }
+ Interval;
That has to be at least 12 bytes, or 16 on a 64 bit target.
struct { UShort low; UShort high; Bool present; } would make
it 8 bytes on all targets. re UShort vs Short, is there any
need to have the offsets signed?
+ /* Assume all guest state */
A bit cryptic, but from reading the lines after, you mean something
like "Assume all guest state is written" (or some such).
J
|