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From: <sv...@va...> - 2012-11-25 15:33:50
|
sewardj 2012-11-25 15:33:42 +0000 (Sun, 25 Nov 2012)
New Revision: 13142
Log:
Initial Memcheck support for instrumenting guarded loads and stores.
Still to do:
* origin tracking
* reinstate the two NULLed-out 3rd args to complainIfUndefined,
once the complication pertaining to setting the shadow tmp to
'defined' is resolved
Modified files:
branches/COMEM/memcheck/mc_translate.c
Modified: branches/COMEM/memcheck/mc_translate.c (+218 -59)
===================================================================
--- branches/COMEM/memcheck/mc_translate.c 2012-11-25 12:56:10 +00:00 (rev 13141)
+++ branches/COMEM/memcheck/mc_translate.c 2012-11-25 15:33:42 +00:00 (rev 13142)
@@ -1090,15 +1090,18 @@
}
-/* Check the supplied **original** atom for undefinedness, and emit a
+/* Check the supplied *original* |atom| for undefinedness, and emit a
complaint if so. Once that happens, mark it as defined. This is
possible because the atom is either a tmp or literal. If it's a
tmp, it will be shadowed by a tmp, and so we can set the shadow to
be defined. In fact as mentioned above, we will have to allocate a
new tmp to carry the new 'defined' shadow value, and update the
original->tmp mapping accordingly; we cannot simply assign a new
- value to an existing shadow tmp as this breaks SSAness -- resulting
- in the post-instrumentation sanity checker spluttering in disapproval.
+ value to an existing shadow tmp as this breaks SSAness.
+
+ It may be that any resulting complaint should only be emitted
+ conditionally, as defined by |guard|. If |guard| is NULL then it
+ is assumed to be always-true.
*/
static void complainIfUndefined ( MCEnv* mce, IRAtom* atom, IRExpr *guard )
{
@@ -1233,14 +1236,13 @@
VG_(fnptr_to_fnentry)( fn ), args );
di->guard = cond;
- /* If the complaint is to be issued under a guard condition, AND that
- guard condition. */
+ /* If the complaint is to be issued under a guard condition, AND
+ that into the guard condition for the helper call. */
if (guard) {
- IRAtom *g1 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, di->guard));
- IRAtom *g2 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, guard));
- IRAtom *e = assignNew('V', mce, Ity_I32, binop(Iop_And32, g1, g2));
-
- di->guard = assignNew('V', mce, Ity_I1, unop(Iop_32to1, e));
+ IRAtom *g1 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, di->guard));
+ IRAtom *g2 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, guard));
+ IRAtom *e = assignNew('V', mce, Ity_I32, binop(Iop_And32, g1, g2));
+ di->guard = assignNew('V', mce, Ity_I1, unop(Iop_32to1, e));
}
setHelperAnns( mce, di );
@@ -3617,6 +3619,11 @@
static
IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
{
+ /* For the widening operations {8,16,32}{U,S}to{16,32,64}, the
+ selection of shadow operation implicitly duplicates the logic in
+ do_shadow_LoadG and should be kept in sync (in the very unlikely
+ event that the interpretation of such widening ops changes in
+ future). See comment in do_shadow_LoadG. */
IRAtom* vatom = expr2vbits( mce, atom );
tl_assert(isOriginalAtom(mce,atom));
switch (op) {
@@ -3915,11 +3922,12 @@
}
-/* Worker function; do not call directly. */
+/* Worker function; do not call directly. See comments on
+ expr2vbits_Load for the meaning of 'guard'. */
static
IRAtom* expr2vbits_Load_WRK ( MCEnv* mce,
IREndness end, IRType ty,
- IRAtom* addr, UInt bias )
+ IRAtom* addr, UInt bias, IRAtom* guard )
{
void* helper;
const HChar* hname;
@@ -3995,16 +4003,27 @@
hname, VG_(fnptr_to_fnentry)( helper ),
mkIRExprVec_1( addrAct ));
setHelperAnns( mce, di );
+ if (guard)
+ di->guard = guard;
stmt( 'V', mce, IRStmt_Dirty(di) );
return mkexpr(datavbits);
}
+/* Generate IR to do a shadow load. The helper is expected to check
+ the validity of the address and return the V bits for that address.
+ This can optionally be controlled by a guard, which is assumed to
+ be True if NULL. In the case where the guard is False at runtime,
+ the helper will return the didn't-do-the-call value of all-ones, as
+ specified by the IRDirty semantics. Since all ones means
+ "completely undefined result", the caller of this function will
+ need to fix up the result somehow in that case. */
static
IRAtom* expr2vbits_Load ( MCEnv* mce,
IREndness end, IRType ty,
- IRAtom* addr, UInt bias )
+ IRAtom* addr, UInt bias,
+ IRAtom* guard )
{
tl_assert(end == Iend_LE || end == Iend_BE);
switch (shadowTypeV(ty)) {
@@ -4012,15 +4031,15 @@
case Ity_I16:
case Ity_I32:
case Ity_I64:
- return expr2vbits_Load_WRK(mce, end, ty, addr, bias);
+ return expr2vbits_Load_WRK(mce, end, ty, addr, bias, guard);
case Ity_V128: {
IRAtom *v64hi, *v64lo;
if (end == Iend_LE) {
- v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
- v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
+ v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0, guard);
+ v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8, guard);
} else {
- v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
- v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
+ v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0, guard);
+ v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8, guard);
}
return assignNew( 'V', mce,
Ity_V128,
@@ -4030,10 +4049,14 @@
/* V256-bit case -- phrased in terms of 64 bit units (Qs),
with Q3 being the most significant lane. */
if (end == Iend_BE) goto unhandled;
- IRAtom* v64Q0 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
- IRAtom* v64Q1 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
- IRAtom* v64Q2 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+16);
- IRAtom* v64Q3 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+24);
+ IRAtom* v64Q0
+ = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0, guard);
+ IRAtom* v64Q1
+ = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8, guard);
+ IRAtom* v64Q2
+ = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+16, guard);
+ IRAtom* v64Q3
+ = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+24, guard);
return assignNew( 'V', mce,
Ity_V256,
IRExpr_Qop(Iop_64x4toV256,
@@ -4046,29 +4069,86 @@
}
-/* If there is no guard expression or the guard is always TRUE this function
- behaves like expr2vbits_Load. If the guard is not true at runtime, an
- all-bits-defined bit pattern will be returned.
- It is assumed that definedness of GUARD has already been checked at the call
- site. */
+/* The most general handler for guarded loads. Assumes the
+ definedness of GUARD and ADDR have already been checked by the
+ caller. A GUARD of NULL it is assumed to mean "always True".
+
+ Generate IR to do a shadow load from ADDR and return the V bits.
+ The loaded type is TY. The loaded data is then (shadow) widened by
+ using VWIDEN, which can be Iop_INVALID to denote a no-op. If GUARD
+ evaluates to False at run time then the returned Vbits are simply
+ VALT instead. Note therefore that the argument type of VWIDEN must
+ be TY and the result type of VWIDEN must equal the type of VALT.
+*/
static
-IRAtom* expr2vbits_guarded_Load ( MCEnv* mce,
- IREndness end, IRType ty,
- IRAtom* addr, UInt bias, IRAtom *guard )
+IRAtom* expr2vbits_Load_guarded_General ( MCEnv* mce,
+ IREndness end, IRType ty,
+ IRAtom* addr, UInt bias,
+ IRAtom* guard,
+ IROp vwiden, IRAtom* valt )
{
- if (guard) {
- IRAtom *cond, *iffalse, *iftrue;
+ /* Sanity check the conversion operation, and also set TYWIDE. */
+ IRType tyWide = Ity_INVALID;
+ switch (vwiden) {
+ case Iop_INVALID:
+ tyWide = ty;
+ break;
+ case Iop_16Uto32: case Iop_16Sto32: case Iop_8Uto32: case Iop_8Sto32:
+ tyWide = Ity_I32;
+ break;
+ default:
+ VG_(tool_panic)("memcheck:expr2vbits_Load_guarded_General");
+ }
- cond = assignNew('V', mce, Ity_I8, unop(Iop_1Uto8, guard));
- iftrue = assignNew('V', mce, ty,
- expr2vbits_Load(mce, end, ty, addr, bias));
- iffalse = assignNew('V', mce, ty, definedOfType(ty));
+ /* If the guard evaluates to True, this will hold the loaded V bits
+ at TY. If the guard evaluates to False, this will be all
+ ones, meaning "all undefined", in which case we will have to
+ replace it using a Mux0X below. */
+ IRAtom* iftrue1
+ = assignNew('V', mce, ty,
+ expr2vbits_Load(mce, end, ty, addr, bias, guard));
+ /* Now (shadow-) widen the loaded V bits to the desired width. In
+ the guard-is-False case, the allowable widening operators will
+ in the worst case (unsigned widening) at least leave the
+ pre-widened part as being marked all-undefined, and in the best
+ case (signed widening) mark the whole widened result as
+ undefined. Anyway, it doesn't matter really, since in this case
+ we will replace said value with the default value |valt| using a
+ Mux0X. */
+ IRAtom* iftrue2
+ = vwiden == Iop_INVALID
+ ? iftrue1
+ : assignNew('V', mce, tyWide, unop(vwiden, iftrue1));
+ /* These are the V bits we will return if the load doesn't take
+ place. */
+ IRAtom* iffalse
+ = valt;
+ /* Prepare the cond for the Mux0X. Convert a NULL cond into
+ something that iropt knows how to fold out later. */
+ IRAtom* cond
+ = guard == NULL
+ ? mkU8(1)
+ : assignNew('V', mce, Ity_I8, unop(Iop_1Uto8, guard));
+ /* And assemble the final result. */
+ return assignNew('V', mce, tyWide, IRExpr_Mux0X(cond, iffalse, iftrue2));
+}
- return assignNew('V', mce, ty, IRExpr_Mux0X(cond, iffalse, iftrue));
- }
- /* No guard expression or unconditional load */
- return expr2vbits_Load(mce, end, ty, addr, bias);
+/* A simpler handler for guarded loads, in which there is no
+ conversion operation, and the default V bit return (when the guard
+ evaluates to False at runtime) is "all defined". If there is no
+ guard expression or the guard is always TRUE this function behaves
+ like expr2vbits_Load. It is assumed that definedness of GUARD and
+ ADDR has already been checked at the call site. */
+static
+IRAtom* expr2vbits_Load_guarded_Simple ( MCEnv* mce,
+ IREndness end, IRType ty,
+ IRAtom* addr, UInt bias,
+ IRAtom *guard )
+{
+ return expr2vbits_Load_guarded_General(
+ mce, end, ty, addr, bias, guard, Iop_INVALID, definedOfType(ty)
+ );
}
@@ -4147,7 +4227,8 @@
case Iex_Load:
return expr2vbits_Load( mce, e->Iex.Load.end,
e->Iex.Load.ty,
- e->Iex.Load.addr, 0/*addr bias*/ );
+ e->Iex.Load.addr, 0/*addr bias*/,
+ NULL/* guard == "always True"*/ );
case Iex_CCall:
return mkLazyN( mce, e->Iex.CCall.args,
@@ -4217,13 +4298,17 @@
}
-/* Generate a shadow store. addr is always the original address atom.
- You can pass in either originals or V-bits for the data atom, but
- obviously not both. guard :: Ity_I1 controls whether the store
- really happens; NULL means it unconditionally does. Note that
- guard itself is not checked for definedness; the caller of this
- function must do that if necessary. */
+/* Generate a shadow store. |addr| is always the original address
+ atom. You can pass in either originals or V-bits for the data
+ atom, but obviously not both. This function generates a check for
+ the definedness of |addr|. That check is performed regardless of
+ whether |guard| is true or not.
+ |guard| :: Ity_I1 controls whether the store really happens; NULL
+ means it unconditionally does. Note that |guard| itself is not
+ checked for definedness; the caller of this function must do that
+ if necessary.
+*/
static
void do_shadow_Store ( MCEnv* mce,
IREndness end,
@@ -4281,7 +4366,7 @@
/* First, emit a definedness test for the address. This also sets
the address (shadow) to 'defined' following the test. */
- complainIfUndefined( mce, addr, guard );
+ complainIfUndefined( mce, addr, NULL );
/* Now decide which helper function to call to write the data V
bits into shadow memory. */
@@ -4582,7 +4667,7 @@
should remove all but this test. */
IRType tyAddr;
tl_assert(d->mAddr);
- complainIfUndefined(mce, d->mAddr, d->guard);
+ complainIfUndefined(mce, d->mAddr, NULL);
tyAddr = typeOfIRExpr(mce->sb->tyenv, d->mAddr);
tl_assert(tyAddr == Ity_I32 || tyAddr == Ity_I64);
@@ -4599,8 +4684,8 @@
while (toDo >= 4) {
here = mkPCastTo(
mce, Ity_I32,
- expr2vbits_guarded_Load ( mce, end, Ity_I32, d->mAddr,
- d->mSize - toDo, d->guard )
+ expr2vbits_Load_guarded_Simple(
+ mce, end, Ity_I32, d->mAddr, d->mSize - toDo, d->guard )
);
curr = mkUifU32(mce, here, curr);
toDo -= 4;
@@ -4609,8 +4694,8 @@
while (toDo >= 2) {
here = mkPCastTo(
mce, Ity_I32,
- expr2vbits_guarded_Load ( mce, end, Ity_I16, d->mAddr,
- d->mSize - toDo, d->guard )
+ expr2vbits_Load_guarded_Simple(
+ mce, end, Ity_I16, d->mAddr, d->mSize - toDo, d->guard )
);
curr = mkUifU32(mce, here, curr);
toDo -= 2;
@@ -4619,8 +4704,8 @@
if (toDo == 1) {
here = mkPCastTo(
mce, Ity_I32,
- expr2vbits_guarded_Load ( mce, end, Ity_I8, d->mAddr,
- d->mSize - toDo, d->guard )
+ expr2vbits_Load_guarded_Simple(
+ mce, end, Ity_I8, d->mAddr, d->mSize - toDo, d->guard )
);
curr = mkUifU32(mce, here, curr);
toDo -= 1;
@@ -4990,7 +5075,8 @@
'V', mce, elemTy,
expr2vbits_Load(
mce,
- cas->end, elemTy, cas->addr, 0/*Addr bias*/
+ cas->end, elemTy, cas->addr, 0/*Addr bias*/,
+ NULL/*always happens*/
));
bind_shadow_tmp_to_orig('V', mce, mkexpr(cas->oldLo), voldLo);
if (otrak) {
@@ -5118,14 +5204,16 @@
'V', mce, elemTy,
expr2vbits_Load(
mce,
- cas->end, elemTy, cas->addr, memOffsHi/*Addr bias*/
+ cas->end, elemTy, cas->addr, memOffsHi/*Addr bias*/,
+ NULL/*always happens*/
));
voldLo
= assignNew(
'V', mce, elemTy,
expr2vbits_Load(
mce,
- cas->end, elemTy, cas->addr, memOffsLo/*Addr bias*/
+ cas->end, elemTy, cas->addr, memOffsLo/*Addr bias*/,
+ NULL/*always happens*/
));
bind_shadow_tmp_to_orig('V', mce, mkexpr(cas->oldHi), voldHi);
bind_shadow_tmp_to_orig('V', mce, mkexpr(cas->oldLo), voldLo);
@@ -5212,7 +5300,8 @@
|| resTy == Ity_I16 || resTy == Ity_I8);
assign( 'V', mce, resTmp,
expr2vbits_Load(
- mce, stEnd, resTy, stAddr, 0/*addr bias*/));
+ mce, stEnd, resTy, stAddr, 0/*addr bias*/,
+ NULL/*always happens*/) );
} else {
/* Store Conditional */
/* Stay sane */
@@ -5246,6 +5335,58 @@
}
+/* ---- Dealing with LoadG/StoreG (not entirely simple) ---- */
+
+static void do_shadow_StoreG ( MCEnv* mce, IRStoreG* sg )
+{
+ if (0) VG_(printf)("XXXX StoreG\n");
+ complainIfUndefined(mce, sg->guard, NULL);
+ /* do_shadow_Store will check the definedness of sg->addr. */
+ do_shadow_Store( mce, sg->end,
+ sg->addr, 0/* addr bias */,
+ sg->data,
+ NULL /* shadow data */,
+ sg->guard );
+}
+
+static void do_shadow_LoadG ( MCEnv* mce, IRLoadG* lg )
+{
+ if (0) VG_(printf)("XXXX LoadG\n");
+ complainIfUndefined(mce, lg->guard, NULL);
+ /* expr2vbits_Load_guarded_General will check the definedness of
+ lg->addr. */
+
+ /* Look at the LoadG's built-in conversion operation, to determine
+ the source (actual loaded data) type, and the equivalent IROp.
+ NOTE that implicitly we are taking a widening operation to be
+ applied to original atoms and producing one that applies to V
+ bits. Since signed and unsigned widening are self-shadowing,
+ this is a straight copy of the op (modulo swapping from the
+ IRLoadGOp form to the IROp form). Note also therefore that this
+ implicitly duplicates the logic to do with said widening ops in
+ expr2vbits_Unop. See comment at the start of expr2vbits_Unop. */
+ IROp vwiden = Iop_INVALID;
+ IRType loadedTy = Ity_INVALID;
+ switch (lg->cvt) {
+ case ILGop_Ident32: loadedTy = Ity_I32; vwiden = Iop_INVALID; break;
+ case ILGop_16Uto32: loadedTy = Ity_I16; vwiden = Iop_16Uto32; break;
+ case ILGop_16Sto32: loadedTy = Ity_I16; vwiden = Iop_16Sto32; break;
+ case ILGop_8Uto32: loadedTy = Ity_I8; vwiden = Iop_8Uto32; break;
+ case ILGop_8Sto32: loadedTy = Ity_I8; vwiden = Iop_8Sto32; break;
+ default: VG_(tool_panic)("do_shadow_LoadG");
+ }
+
+ IRAtom* vbits_alt
+ = expr2vbits( mce, lg->alt );
+ IRAtom* vbits_final
+ = expr2vbits_Load_guarded_General(mce, lg->end, loadedTy,
+ lg->addr, 0/*addr bias*/,
+ lg->guard, vwiden, vbits_alt );
+ /* And finally, bind the V bits to the destination temporary. */
+ assign( 'V', mce, findShadowTmpV(mce, lg->dst), vbits_final );
+}
+
+
/*------------------------------------------------------------*/
/*--- Memcheck main ---*/
/*------------------------------------------------------------*/
@@ -5348,6 +5489,16 @@
case Ist_Store:
return isBogusAtom(st->Ist.Store.addr)
|| isBogusAtom(st->Ist.Store.data);
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ return isBogusAtom(sg->addr) || isBogusAtom(sg->data)
+ || isBogusAtom(sg->guard);
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ return isBogusAtom(lg->addr) || isBogusAtom(lg->alt)
+ || isBogusAtom(lg->guard);
+ }
case Ist_Exit:
return isBogusAtom(st->Ist.Exit.guard);
case Ist_AbiHint:
@@ -5585,6 +5736,14 @@
NULL/*guard*/ );
break;
+ case Ist_StoreG:
+ do_shadow_StoreG( &mce, st->Ist.StoreG.details );
+ break;
+
+ case Ist_LoadG:
+ do_shadow_LoadG( &mce, st->Ist.LoadG.details );
+ break;
+
case Ist_Exit:
complainIfUndefined( &mce, st->Ist.Exit.guard, NULL );
break;
|
|
From: <sv...@va...> - 2012-11-25 15:26:56
|
sewardj 2012-11-25 15:26:48 +0000 (Sun, 25 Nov 2012)
New Revision: 2572
Log:
Initial front changes for ARM, to generate direct IR for at least some
conditional loads and stores. Very incomplete -- most load-store
cases still use the old scheme.
Modified files:
branches/COMEM/priv/guest_arm_toIR.c
Modified: branches/COMEM/priv/guest_arm_toIR.c (+72 -27)
===================================================================
--- branches/COMEM/priv/guest_arm_toIR.c 2012-11-25 15:17:42 +00:00 (rev 2571)
+++ branches/COMEM/priv/guest_arm_toIR.c 2012-11-25 15:26:48 +00:00 (rev 2572)
@@ -329,6 +329,49 @@
stmt( IRStmt_Store(Iend_LE, addr, data) );
}
+static void storeGuardedLE ( IRExpr* addr, IRExpr* data, IRTemp guardT )
+{
+ if (guardT == IRTemp_INVALID) {
+ /* unconditional */
+ storeLE(addr, data);
+ } else {
+ stmt( IRStmt_StoreG(Iend_LE, addr, data,
+ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) );
+ }
+}
+
+static void loadGuardedLE ( IRTemp dst, IRLoadGOp cvt,
+ IRExpr* addr, IRExpr* alt,
+ IRTemp guardT /* :: Ity_I32, 0 or 1 */ )
+{
+ if (guardT == IRTemp_INVALID) {
+ /* unconditional */
+ IRExpr* loaded = NULL;
+ switch (cvt) {
+ case ILGop_Ident32:
+ loaded = loadLE(Ity_I32, addr); break;
+ case ILGop_8Uto32:
+ loaded = unop(Iop_8Uto32, loadLE(Ity_I8, addr)); break;
+ case ILGop_8Sto32:
+ loaded = unop(Iop_8Sto32, loadLE(Ity_I8, addr)); break;
+ case ILGop_16Uto32:
+ loaded = unop(Iop_16Uto32, loadLE(Ity_I16, addr)); break;
+ case ILGop_16Sto32:
+ loaded = unop(Iop_16Sto32, loadLE(Ity_I16, addr)); break;
+ default:
+ vassert(0);
+ }
+ vassert(loaded != NULL);
+ assign(dst, loaded);
+ } else {
+ /* Generate a guarded load into 'dst', but apply 'cvt' to the
+ loaded data before putting the data in 'dst'. If the load
+ does not take place, 'alt' is placed directly in 'dst'. */
+ stmt( IRStmt_LoadG(Iend_LE, cvt, dst, addr, alt,
+ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) );
+ }
+}
+
/* Generate a new temporary of the given type. */
static IRTemp newTemp ( IRType ty )
{
@@ -17521,16 +17564,16 @@
}
if (bP == 1 && bW == 0) {
- DIP("%s.w r%u, [r%u, #%c%u]\n",
+ DIP("%s.wQQQ1 r%u, [r%u, #%c%u]\n",
nm, rT, rN, bU ? '+' : '-', imm8);
}
else if (bP == 1 && bW == 1) {
- DIP("%s.w r%u, [r%u, #%c%u]!\n",
+ DIP("%s.wQQQ2 r%u, [r%u, #%c%u]!\n",
nm, rT, rN, bU ? '+' : '-', imm8);
}
else {
vassert(bP == 0 && bW == 1);
- DIP("%s.w r%u, [r%u], #%c%u\n",
+ DIP("%s.wQQQ3 r%u, [r%u], #%c%u\n",
nm, rT, rN, bU ? '+' : '-', imm8);
}
@@ -17740,12 +17783,15 @@
if (valid) {
// if it's a branch, it can't happen in the middle of an IT block
- if (loadsPC)
+ // Also, if it is a branch, make it unconditional at this point.
+ // Doing conditional branches in-line is too complex (for now)
+ if (loadsPC) {
gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
- // go uncond
- mk_skip_over_T32_if_cond_is_false(condT);
- condT = IRTemp_INVALID;
- // now uncond
+ // go uncond
+ mk_skip_over_T32_if_cond_is_false(condT);
+ condT = IRTemp_INVALID;
+ // now uncond
+ }
IRTemp rNt = newTemp(Ity_I32);
if (rN == 15) {
@@ -17759,53 +17805,52 @@
assign(transAddr,
binop( Iop_Add32, mkexpr(rNt), mkU32(imm12) ));
+ IRTemp oldRt = newTemp(Ity_I32);
+ assign(oldRt, getIRegT(rT));
+
if (isST) {
- IRTemp oldRt = newTemp(Ity_I32);
- assign(oldRt, getIRegT(rT));
+ IRExpr* data = NULL;
switch (ty) {
case Ity_I8:
- storeLE(mkexpr(transAddr),
- unop(Iop_32to8, mkexpr(oldRt)));
+ data = unop(Iop_32to8, mkexpr(oldRt));
break;
case Ity_I16:
- storeLE(mkexpr(transAddr),
- unop(Iop_32to16, mkexpr(oldRt)));
+ data = unop(Iop_32to16, mkexpr(oldRt));
break;
case Ity_I32:
- storeLE(mkexpr(transAddr), mkexpr(oldRt));
+ data = mkexpr(oldRt);
break;
default:
vassert(0);
}
+ storeGuardedLE(mkexpr(transAddr), data, condT);
} else {
- IRTemp newRt = newTemp(Ity_I32);
- IROp widen = Iop_INVALID;
+ IRTemp newRt = newTemp(Ity_I32);
+ IRLoadGOp widen = ILGop_INVALID;
switch (ty) {
case Ity_I8:
- widen = syned ? Iop_8Sto32 : Iop_8Uto32; break;
+ widen = syned ? ILGop_8Sto32 : ILGop_8Uto32; break;
case Ity_I16:
- widen = syned ? Iop_16Sto32 : Iop_16Uto32; break;
+ widen = syned ? ILGop_16Sto32 : ILGop_16Uto32; break;
case Ity_I32:
- break;
+ widen = ILGop_Ident32; break;
default:
vassert(0);
}
- if (widen == Iop_INVALID) {
- assign(newRt, loadLE(ty, mkexpr(transAddr)));
- } else {
- assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr))));
- }
- putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
+ loadGuardedLE(newRt, widen,
+ mkexpr(transAddr), mkexpr(oldRt), condT);
+ putIRegT(rT, mkexpr(newRt), condT);
if (loadsPC) {
/* Presumably this is an interworking branch. */
+ vassert(condT == IRTemp_INVALID); /* due to check above */
irsb->next = mkexpr(newRt);
irsb->jumpkind = Ijk_Boring; /* or _Ret ? */
dres.whatNext = Dis_StopHere;
}
}
- DIP("%s.w r%u, [r%u, +#%u]\n", nm, rT, rN, imm12);
+ DIP("%s.wQQQ9 r%u, [r%u, +#%u]\n", nm, rT, rN, imm12);
goto decode_success;
}
|
|
From: <sv...@va...> - 2012-11-25 15:17:53
|
sewardj 2012-11-25 15:17:42 +0000 (Sun, 25 Nov 2012)
New Revision: 2571
Log:
ARM back end changes, to support code generation for IR guarded loads
and stores.
Modified files:
branches/COMEM/priv/host_arm_defs.c
branches/COMEM/priv/host_arm_defs.h
branches/COMEM/priv/host_arm_isel.c
branches/COMEM/priv/host_generic_regs.c
branches/COMEM/priv/host_generic_regs.h
Modified: branches/COMEM/priv/host_generic_regs.h (+21 -0)
===================================================================
--- branches/COMEM/priv/host_generic_regs.h 2012-11-25 15:14:44 +00:00 (rev 2570)
+++ branches/COMEM/priv/host_generic_regs.h 2012-11-25 15:17:42 +00:00 (rev 2571)
@@ -234,6 +234,27 @@
/*---------------------------------------------------------*/
+/*--- C-Call return-location descriptions ---*/
+/*---------------------------------------------------------*/
+
+/* This is common to all back ends. It describes where the return
+ value from a C call is located. This is important in the case that
+ the call is conditional, since the return locations will need to be
+ set to all-ones in the case that the call does not happen. */
+
+typedef
+ enum {
+ RetLocINVALID, /* INVALID */
+ RetLocNone, /* no return value (a.k.a C "void") */
+ RetLocInt, /* in the primary int return reg */
+ RetLoc2Int /* in both primary and secondary int ret regs */
+ }
+ RetLoc;
+
+extern void ppRetLoc ( RetLoc rloc );
+
+
+/*---------------------------------------------------------*/
/*--- Reg alloc: TODO: move somewhere else ---*/
/*---------------------------------------------------------*/
Modified: branches/COMEM/priv/host_generic_regs.c (+16 -0)
===================================================================
--- branches/COMEM/priv/host_generic_regs.c 2012-11-25 15:14:44 +00:00 (rev 2570)
+++ branches/COMEM/priv/host_generic_regs.c 2012-11-25 15:17:42 +00:00 (rev 2571)
@@ -218,6 +218,22 @@
}
+/*---------------------------------------------------------*/
+/*--- C-Call return-location actions ---*/
+/*---------------------------------------------------------*/
+
+void ppRetLoc ( RetLoc ska )
+{
+ switch (ska) {
+ case RetLocINVALID: vex_printf("RetLocINVALID"); return;
+ case RetLocNone: vex_printf("RetLocNone"); return;
+ case RetLocInt: vex_printf("RetLocInt"); return;
+ case RetLoc2Int: vex_printf("RetLoc2Int"); return;
+ default: vpanic("ppRetLoc");
+ }
+}
+
+
/*---------------------------------------------------------------*/
/*--- end host_generic_regs.c ---*/
/*---------------------------------------------------------------*/
Modified: branches/COMEM/priv/host_arm_isel.c (+152 -61)
===================================================================
--- branches/COMEM/priv/host_arm_isel.c 2012-11-25 15:14:44 +00:00 (rev 2570)
+++ branches/COMEM/priv/host_arm_isel.c 2012-11-25 15:17:42 +00:00 (rev 2571)
@@ -378,7 +378,8 @@
static
Bool doHelperCall ( ISelEnv* env,
Bool passBBP,
- IRExpr* guard, IRCallee* cee, IRExpr** args )
+ IRExpr* guard, IRCallee* cee, IRExpr** args,
+ RetLoc rloc )
{
ARMCondCode cc;
HReg argregs[ARM_N_ARGREGS];
@@ -615,7 +616,7 @@
values. But that's too much hassle. */
/* Finally, the call itself. */
- addInstr(env, ARMInstr_Call( cc, target, nextArgReg ));
+ addInstr(env, ARMInstr_Call( cc, target, nextArgReg, rloc ));
return True; /* success */
}
@@ -1087,7 +1088,6 @@
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
-// vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
switch (e->tag) {
@@ -1105,29 +1105,21 @@
if (ty == Ity_I32) {
ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
- addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, dst, amode));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, dst, amode));
return dst;
}
if (ty == Ity_I16) {
ARMAMode2* amode = iselIntExpr_AMode2 ( env, e->Iex.Load.addr );
- addInstr(env, ARMInstr_LdSt16(True/*isLoad*/, False/*!signedLoad*/,
+ addInstr(env, ARMInstr_LdSt16(ARMcc_AL,
+ True/*isLoad*/, False/*!signedLoad*/,
dst, amode));
return dst;
}
if (ty == Ity_I8) {
ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
- addInstr(env, ARMInstr_LdSt8U(True/*isLoad*/, dst, amode));
+ addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, True/*isLoad*/, dst, amode));
return dst;
}
-
-//zz if (ty == Ity_I16) {
-//zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
-//zz return dst;
-//zz }
-//zz if (ty == Ity_I8) {
-//zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
-//zz return dst;
-//zz }
break;
}
@@ -1378,7 +1370,8 @@
HReg res = newVRegI(env);
addInstr(env, mk_iMOVds_RR(hregARM_R0(), regL));
addInstr(env, mk_iMOVds_RR(hregARM_R1(), regR));
- addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 2 ));
+ addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn),
+ 2, RetLocInt ));
addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
return res;
}
@@ -1665,7 +1658,8 @@
HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
HReg res = newVRegI(env);
addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg));
- addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 1 ));
+ addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn),
+ 1, RetLocInt ));
addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
return res;
}
@@ -1680,7 +1674,7 @@
&& e->Iex.Get.offset < 4096-4) {
HReg dst = newVRegI(env);
addInstr(env, ARMInstr_LdSt32(
- True/*isLoad*/,
+ ARMcc_AL, True/*isLoad*/,
dst,
ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset)));
return dst;
@@ -1719,14 +1713,16 @@
HReg dst = newVRegI(env);
vassert(ty == e->Iex.CCall.retty);
- /* be very restrictive for now. Only 32/64-bit ints allowed
- for args, and 32 bits for return type. */
+ /* be very restrictive for now. Only 32/64-bit ints allowed for
+ args, and 32 bits for return type. Don't forget to change
+ the RetLoc if more types are allowed in future. */
if (e->Iex.CCall.retty != Ity_I32)
goto irreducible;
/* Marshal args, do the call, clear stack. */
Bool ok = doHelperCall( env, False,
- NULL, e->Iex.CCall.cee, e->Iex.CCall.args );
+ NULL, e->Iex.CCall.cee, e->Iex.CCall.args,
+ RetLocInt );
if (ok) {
addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
return dst;
@@ -1858,8 +1854,10 @@
rA = iselIntExpr_R(env, e->Iex.Load.addr);
tHi = newVRegI(env);
tLo = newVRegI(env);
- addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, ARMAMode1_RI(rA, 4)));
- addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, ARMAMode1_RI(rA, 0)));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
+ tHi, ARMAMode1_RI(rA, 4)));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
+ tLo, ARMAMode1_RI(rA, 0)));
*rHi = tHi;
*rLo = tLo;
return;
@@ -1871,8 +1869,8 @@
ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 4);
HReg tHi = newVRegI(env);
HReg tLo = newVRegI(env);
- addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, am4));
- addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, am0));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tHi, am4));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tLo, am0));
*rHi = tHi;
*rLo = tLo;
return;
@@ -4257,13 +4255,17 @@
/* Store the less significant 64 bits */
iselInt64Expr(&w1, &w0, env, e->Iex.Binop.arg2);
- addInstr(env, ARMInstr_LdSt32(False/*store*/, w0, sp_0));
- addInstr(env, ARMInstr_LdSt32(False/*store*/, w1, sp_4));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
+ w0, sp_0));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
+ w1, sp_4));
/* Store the more significant 64 bits */
iselInt64Expr(&w3, &w2, env, e->Iex.Binop.arg1);
- addInstr(env, ARMInstr_LdSt32(False/*store*/, w2, sp_8));
- addInstr(env, ARMInstr_LdSt32(False/*store*/, w3, sp_12));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
+ w2, sp_8));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
+ w3, sp_12));
/* Load result back from stack. */
addInstr(env, ARMInstr_NLdStQ(True/*load*/, res,
@@ -5641,20 +5643,21 @@
if (tyd == Ity_I32) {
HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
- addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, rD, am));
return;
}
if (tyd == Ity_I16) {
HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
- addInstr(env, ARMInstr_LdSt16(False/*!isLoad*/,
+ addInstr(env, ARMInstr_LdSt16(ARMcc_AL,
+ False/*!isLoad*/,
False/*!isSignedLoad*/, rD, am));
return;
}
if (tyd == Ity_I8) {
HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
- addInstr(env, ARMInstr_LdSt8U(False/*!isLoad*/, rD, am));
+ addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, False/*!isLoad*/, rD, am));
return;
}
if (tyd == Ity_I64) {
@@ -5666,9 +5669,9 @@
HReg rDhi, rDlo, rA;
iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
- addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDhi,
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDhi,
ARMAMode1_RI(rA,4)));
- addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDlo,
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDlo,
ARMAMode1_RI(rA,0)));
}
return;
@@ -5695,6 +5698,88 @@
break;
}
+ /* --------- CONDITIONAL STORE --------- */
+ /* conditional little-endian write to memory */
+ case Ist_StoreG: {
+ IRStoreG* sg = stmt->Ist.StoreG.details;
+ IRType tya = typeOfIRExpr(env->type_env, sg->addr);
+ IRType tyd = typeOfIRExpr(env->type_env, sg->data);
+ IREndness end = sg->end;
+
+ if (tya != Ity_I32 || end != Iend_LE)
+ goto stmt_fail;
+
+ switch (tyd) {
+ case Ity_I8:
+ case Ity_I32: {
+ HReg rD = iselIntExpr_R(env, sg->data);
+ ARMAMode1* am = iselIntExpr_AMode1(env, sg->addr);
+ ARMCondCode cc = iselCondCode(env, sg->guard);
+ addInstr(env, (tyd == Ity_I32 ? ARMInstr_LdSt32 : ARMInstr_LdSt8U)
+ (cc, False/*!isLoad*/, rD, am));
+ return;
+ }
+ case Ity_I16: {
+ HReg rD = iselIntExpr_R(env, sg->data);
+ ARMAMode2* am = iselIntExpr_AMode2(env, sg->addr);
+ ARMCondCode cc = iselCondCode(env, sg->guard);
+ addInstr(env, ARMInstr_LdSt16(cc,
+ False/*!isLoad*/,
+ False/*!isSignedLoad*/, rD, am));
+ return;
+ }
+ default:
+ break;
+ }
+ break;
+ }
+
+ /* --------- CONDITIONAL LOAD --------- */
+ /* conditional little-endian load from memory */
+ case Ist_LoadG: {
+ IRLoadG* lg = stmt->Ist.LoadG.details;
+ IRType tya = typeOfIRExpr(env->type_env, lg->addr);
+ IREndness end = lg->end;
+
+ if (tya != Ity_I32 || end != Iend_LE)
+ goto stmt_fail;
+
+ switch (lg->cvt) {
+ case ILGop_8Uto32:
+ case ILGop_Ident32: {
+ HReg rAlt = iselIntExpr_R(env, lg->alt);
+ ARMAMode1* am = iselIntExpr_AMode1(env, lg->addr);
+ HReg rD = lookupIRTemp(env, lg->dst);
+ addInstr(env, mk_iMOVds_RR(rD, rAlt));
+ ARMCondCode cc = iselCondCode(env, lg->guard);
+ addInstr(env, (lg->cvt == ILGop_Ident32 ? ARMInstr_LdSt32
+ : ARMInstr_LdSt8U)
+ (cc, True/*isLoad*/, rD, am));
+ return;
+ }
+ case ILGop_16Sto32:
+ case ILGop_16Uto32:
+ case ILGop_8Sto32: {
+ HReg rAlt = iselIntExpr_R(env, lg->alt);
+ ARMAMode2* am = iselIntExpr_AMode2(env, lg->addr);
+ HReg rD = lookupIRTemp(env, lg->dst);
+ addInstr(env, mk_iMOVds_RR(rD, rAlt));
+ ARMCondCode cc = iselCondCode(env, lg->guard);
+ if (lg->cvt == ILGop_8Sto32) {
+ addInstr(env, ARMInstr_Ld8S(cc, rD, am));
+ } else {
+ vassert(lg->cvt == ILGop_16Sto32 || lg->cvt == ILGop_16Uto32);
+ Bool sx = lg->cvt == ILGop_16Sto32;
+ addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+ break;
+ }
+
/* --------- PUT --------- */
/* write guest state, fixed offset */
case Ist_Put: {
@@ -5703,7 +5788,7 @@
if (tyd == Ity_I32) {
HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
ARMAMode1* am = ARMAMode1_RI(hregARM_R8(), stmt->Ist.Put.offset);
- addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, rD, am));
return;
}
if (tyd == Ity_I64) {
@@ -5720,8 +5805,10 @@
ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(),
stmt->Ist.Put.offset + 4);
iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
- addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDhi, am4));
- addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDlo, am0));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
+ rDhi, am4));
+ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
+ rDlo, am0));
}
return;
}
@@ -5752,25 +5839,6 @@
break;
}
-//zz /* --------- Indexed PUT --------- */
-//zz /* write guest state, run-time offset */
-//zz case Ist_PutI: {
-//zz ARMAMode2* am2
-//zz = genGuestArrayOffset(
-//zz env, stmt->Ist.PutI.descr,
-//zz stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
-//zz
-//zz IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
-//zz
-//zz if (tyd == Ity_I8) {
-//zz HReg reg = iselIntExpr_R(env, stmt->Ist.PutI.data);
-//zz addInstr(env, ARMInstr_StoreB(reg, am2));
-//zz return;
-//zz }
-//zz// CAB: Ity_I32, Ity_I16 ?
-//zz break;
-//zz }
-
/* --------- TMP --------- */
/* assign value to temporary */
case Ist_WrTmp: {
@@ -5829,7 +5897,6 @@
/* --------- Call to DIRTY helper --------- */
/* call complex ("dirty") helper function */
case Ist_Dirty: {
- IRType retty;
IRDirty* d = stmt->Ist.Dirty.details;
Bool passBBP = False;
@@ -5838,8 +5905,31 @@
passBBP = toBool(d->nFxState > 0 && d->needsBBP);
- /* Marshal args, do the call, clear stack. */
- Bool ok = doHelperCall( env, passBBP, d->guard, d->cee, d->args );
+ /* Figure out the return type, if any. */
+ IRType retty = Ity_INVALID;
+ if (d->tmp != IRTemp_INVALID)
+ retty = typeOfIRTemp(env->type_env, d->tmp);
+
+ /* Marshal args, do the call, clear stack, set the return value
+ to all-ones if this is a conditional call that returns a
+ value and the call is skipped. We need to set the ret-loc
+ correctly in order to implement the IRDirty semantics that
+ the return value is all-ones if the call doesn't happen. */
+ RetLoc rloc = RetLocINVALID;
+ switch (retty) {
+ case Ity_INVALID: /* function doesn't return anything */
+ rloc = RetLocNone; break;
+ case Ity_I64:
+ rloc = RetLoc2Int; break;
+ case Ity_I32: case Ity_I16: case Ity_I8:
+ rloc = RetLocInt; break;
+ default:
+ break;
+ }
+ if (rloc == RetLocINVALID)
+ break; /* will go to stmt_fail: */
+
+ Bool ok = doHelperCall( env, passBBP, d->guard, d->cee, d->args, rloc );
if (!ok)
break; /* will go to stmt_fail: */
@@ -5848,8 +5938,6 @@
/* No return value. Nothing to do. */
return;
- retty = typeOfIRTemp(env->type_env, d->tmp);
-
if (retty == Ity_I64) {
if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg tmp = lookupIRTemp(env, d->tmp);
@@ -6164,6 +6252,9 @@
/* sanity ... */
vassert(arch_host == VexArchARM);
+ /* guard against unexpected space regressions */
+ vassert(sizeof(ARMInstr) <= 28);
+
/* hwcaps should not change from one ISEL call to another. */
arm_hwcaps = hwcaps_host; // JRS 2012 Mar 31: FIXME (RM)
Modified: branches/COMEM/priv/host_arm_defs.h (+30 -21)
===================================================================
--- branches/COMEM/priv/host_arm_defs.h 2012-11-25 15:14:44 +00:00 (rev 2570)
+++ branches/COMEM/priv/host_arm_defs.h 2012-11-25 15:17:42 +00:00 (rev 2571)
@@ -659,29 +659,33 @@
HReg dst;
UInt imm32;
} Imm32;
- /* 32-bit load or store */
+ /* 32-bit load or store, may be conditional */
struct {
- Bool isLoad;
- HReg rD;
- ARMAMode1* amode;
+ ARMCondCode cc; /* ARMcc_NV is not allowed */
+ Bool isLoad;
+ HReg rD;
+ ARMAMode1* amode;
} LdSt32;
- /* 16-bit load or store */
+ /* 16-bit load or store, may be conditional */
struct {
- Bool isLoad;
- Bool signedLoad;
- HReg rD;
- ARMAMode2* amode;
+ ARMCondCode cc; /* ARMcc_NV is not allowed */
+ Bool isLoad;
+ Bool signedLoad;
+ HReg rD;
+ ARMAMode2* amode;
} LdSt16;
- /* 8-bit (unsigned) load or store */
+ /* 8-bit (unsigned) load or store, may be conditional */
struct {
- Bool isLoad;
- HReg rD;
- ARMAMode1* amode;
+ ARMCondCode cc; /* ARMcc_NV is not allowed */
+ Bool isLoad;
+ HReg rD;
+ ARMAMode1* amode;
} LdSt8U;
- /* 8-bit signed load */
+ /* 8-bit signed load, may be conditional */
struct {
- HReg rD;
- ARMAMode2* amode;
+ ARMCondCode cc; /* ARMcc_NV is not allowed */
+ HReg rD;
+ ARMAMode2* amode;
} Ld8S;
/* Update the guest R15T value, then exit requesting to chain
to it. May be conditional. Urr, use of Addr32 implicitly
@@ -720,6 +724,7 @@
ARMCondCode cond;
HWord target;
Int nArgRegs; /* # regs carrying args: 0 .. 4 */
+ RetLoc rloc; /* where the return value will be */
} Call;
/* (PLAIN) 32 * 32 -> 32: r0 = r2 * r3
(ZX) 32 *u 32 -> 64: r1:r0 = r2 *u r3
@@ -949,11 +954,14 @@
extern ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg, ARMRI84* );
extern ARMInstr* ARMInstr_Mov ( HReg, ARMRI84* );
extern ARMInstr* ARMInstr_Imm32 ( HReg, UInt );
-extern ARMInstr* ARMInstr_LdSt32 ( Bool isLoad, HReg, ARMAMode1* );
-extern ARMInstr* ARMInstr_LdSt16 ( Bool isLoad, Bool signedLoad,
+extern ARMInstr* ARMInstr_LdSt32 ( ARMCondCode,
+ Bool isLoad, HReg, ARMAMode1* );
+extern ARMInstr* ARMInstr_LdSt16 ( ARMCondCode,
+ Bool isLoad, Bool signedLoad,
HReg, ARMAMode2* );
-extern ARMInstr* ARMInstr_LdSt8U ( Bool isLoad, HReg, ARMAMode1* );
-extern ARMInstr* ARMInstr_Ld8S ( HReg, ARMAMode2* );
+extern ARMInstr* ARMInstr_LdSt8U ( ARMCondCode,
+ Bool isLoad, HReg, ARMAMode1* );
+extern ARMInstr* ARMInstr_Ld8S ( ARMCondCode, HReg, ARMAMode2* );
extern ARMInstr* ARMInstr_XDirect ( Addr32 dstGA, ARMAMode1* amR15T,
ARMCondCode cond, Bool toFastEP );
extern ARMInstr* ARMInstr_XIndir ( HReg dstGA, ARMAMode1* amR15T,
@@ -961,7 +969,8 @@
extern ARMInstr* ARMInstr_XAssisted ( HReg dstGA, ARMAMode1* amR15T,
ARMCondCode cond, IRJumpKind jk );
extern ARMInstr* ARMInstr_CMov ( ARMCondCode, HReg dst, ARMRI84* src );
-extern ARMInstr* ARMInstr_Call ( ARMCondCode, HWord, Int nArgRegs );
+extern ARMInstr* ARMInstr_Call ( ARMCondCode, HWord, Int nArgRegs,
+ RetLoc rloc );
extern ARMInstr* ARMInstr_Mul ( ARMMulOp op );
extern ARMInstr* ARMInstr_LdrEX ( Int szB );
extern ARMInstr* ARMInstr_StrEX ( Int szB );
Modified: branches/COMEM/priv/host_arm_defs.c (+193 -41)
===================================================================
--- branches/COMEM/priv/host_arm_defs.c 2012-11-25 15:14:44 +00:00 (rev 2570)
+++ branches/COMEM/priv/host_arm_defs.c 2012-11-25 15:17:42 +00:00 (rev 2571)
@@ -1144,32 +1144,50 @@
i->ARMin.Imm32.imm32 = imm32;
return i;
}
-ARMInstr* ARMInstr_LdSt32 ( Bool isLoad, HReg rD, ARMAMode1* amode ) {
+ARMInstr* ARMInstr_LdSt32 ( ARMCondCode cc,
+ Bool isLoad, HReg rD, ARMAMode1* amode ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
i->tag = ARMin_LdSt32;
+ i->ARMin.LdSt32.cc = cc;
i->ARMin.LdSt32.isLoad = isLoad;
i->ARMin.LdSt32.rD = rD;
i->ARMin.LdSt32.amode = amode;
+ vassert(cc != ARMcc_NV);
return i;
}
-ARMInstr* ARMInstr_LdSt16 ( Bool isLoad, Bool signedLoad,
+ARMInstr* ARMInstr_LdSt16 ( ARMCondCode cc,
+ Bool isLoad, Bool signedLoad,
HReg rD, ARMAMode2* amode ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
i->tag = ARMin_LdSt16;
+ i->ARMin.LdSt16.cc = cc;
i->ARMin.LdSt16.isLoad = isLoad;
i->ARMin.LdSt16.signedLoad = signedLoad;
i->ARMin.LdSt16.rD = rD;
i->ARMin.LdSt16.amode = amode;
+ vassert(cc != ARMcc_NV);
return i;
}
-ARMInstr* ARMInstr_LdSt8U ( Bool isLoad, HReg rD, ARMAMode1* amode ) {
+ARMInstr* ARMInstr_LdSt8U ( ARMCondCode cc,
+ Bool isLoad, HReg rD, ARMAMode1* amode ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
i->tag = ARMin_LdSt8U;
+ i->ARMin.LdSt8U.cc = cc;
i->ARMin.LdSt8U.isLoad = isLoad;
i->ARMin.LdSt8U.rD = rD;
i->ARMin.LdSt8U.amode = amode;
+ vassert(cc != ARMcc_NV);
return i;
}
+ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_Ld8S;
+ i->ARMin.Ld8S.cc = cc;
+ i->ARMin.Ld8S.rD = rD;
+ i->ARMin.Ld8S.amode = amode;
+ vassert(cc != ARMcc_NV);
+ return i;
+}
ARMInstr* ARMInstr_XDirect ( Addr32 dstGA, ARMAMode1* amR15T,
ARMCondCode cond, Bool toFastEP ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
@@ -1208,12 +1226,15 @@
vassert(cond != ARMcc_AL);
return i;
}
-ARMInstr* ARMInstr_Call ( ARMCondCode cond, HWord target, Int nArgRegs ) {
+ARMInstr* ARMInstr_Call ( ARMCondCode cond, HWord target, Int nArgRegs,
+ RetLoc rloc ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
i->tag = ARMin_Call;
i->ARMin.Call.cond = cond;
i->ARMin.Call.target = target;
i->ARMin.Call.nArgRegs = nArgRegs;
+ i->ARMin.Call.rloc = rloc;
+ vassert(rloc != RetLocINVALID);
return i;
}
ARMInstr* ARMInstr_Mul ( ARMMulOp op ) {
@@ -1559,12 +1580,14 @@
return;
case ARMin_LdSt32:
if (i->ARMin.LdSt32.isLoad) {
- vex_printf("ldr ");
+ vex_printf("ldr%s ", i->ARMin.LdSt32.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt32.cc));
ppHRegARM(i->ARMin.LdSt32.rD);
vex_printf(", ");
ppARMAMode1(i->ARMin.LdSt32.amode);
} else {
- vex_printf("str ");
+ vex_printf("str%s ", i->ARMin.LdSt32.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt32.cc));
ppARMAMode1(i->ARMin.LdSt32.amode);
vex_printf(", ");
ppHRegARM(i->ARMin.LdSt32.rD);
@@ -1572,13 +1595,18 @@
return;
case ARMin_LdSt16:
if (i->ARMin.LdSt16.isLoad) {
- vex_printf("%s", i->ARMin.LdSt16.signedLoad
- ? "ldrsh " : "ldrh " );
+ vex_printf("%s%s%s",
+ i->ARMin.LdSt16.signedLoad ? "ldrsh" : "ldrh",
+ i->ARMin.LdSt16.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt16.cc),
+ i->ARMin.LdSt16.signedLoad ? " " : " ");
ppHRegARM(i->ARMin.LdSt16.rD);
vex_printf(", ");
ppARMAMode2(i->ARMin.LdSt16.amode);
} else {
- vex_printf("strh ");
+ vex_printf("strh%s ",
+ i->ARMin.LdSt16.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt16.cc));
ppARMAMode2(i->ARMin.LdSt16.amode);
vex_printf(", ");
ppHRegARM(i->ARMin.LdSt16.rD);
@@ -1586,19 +1614,26 @@
return;
case ARMin_LdSt8U:
if (i->ARMin.LdSt8U.isLoad) {
- vex_printf("ldrb ");
+ vex_printf("ldrb%s ", i->ARMin.LdSt8U.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt8U.cc));
ppHRegARM(i->ARMin.LdSt8U.rD);
vex_printf(", ");
ppARMAMode1(i->ARMin.LdSt8U.amode);
} else {
- vex_printf("strb ");
+ vex_printf("strb%s ", i->ARMin.LdSt8U.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.LdSt8U.cc));
ppARMAMode1(i->ARMin.LdSt8U.amode);
vex_printf(", ");
ppHRegARM(i->ARMin.LdSt8U.rD);
}
return;
case ARMin_Ld8S:
- goto unhandled;
+ vex_printf("ldrsb%s ", i->ARMin.Ld8S.cc == ARMcc_AL ? " "
+ : showARMCondCode(i->ARMin.Ld8S.cc));
+ ppARMAMode2(i->ARMin.Ld8S.amode);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.Ld8S.rD);
+ return;
case ARMin_XDirect:
vex_printf("(xDirect) ");
vex_printf("if (%%cpsr.%s) { ",
@@ -1651,8 +1686,10 @@
vex_printf("call%s ",
i->ARMin.Call.cond==ARMcc_AL
? "" : showARMCondCode(i->ARMin.Call.cond));
- vex_printf("0x%lx [nArgRegs=%d]",
+ vex_printf("0x%lx [nArgRegs=%d, ",
i->ARMin.Call.target, i->ARMin.Call.nArgRegs);
+ ppRetLoc(i->ARMin.Call.rloc);
+ vex_printf("]");
return;
case ARMin_Mul:
vex_printf("%-5s ", showARMMulOp(i->ARMin.Mul.op));
@@ -1951,7 +1988,6 @@
"str r11,[r12+4]");
return;
default:
- unhandled:
vex_printf("ppARMInstr: unhandled case (tag %d)", (Int)i->tag);
vpanic("ppARMInstr(1)");
return;
@@ -1995,6 +2031,8 @@
addRegUsage_ARMAMode1(u, i->ARMin.LdSt32.amode);
if (i->ARMin.LdSt32.isLoad) {
addHRegUse(u, HRmWrite, i->ARMin.LdSt32.rD);
+ if (i->ARMin.LdSt32.cc != ARMcc_AL)
+ addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
} else {
addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
}
@@ -2003,6 +2041,8 @@
addRegUsage_ARMAMode2(u, i->ARMin.LdSt16.amode);
if (i->ARMin.LdSt16.isLoad) {
addHRegUse(u, HRmWrite, i->ARMin.LdSt16.rD);
+ if (i->ARMin.LdSt16.cc != ARMcc_AL)
+ addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
} else {
addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
}
@@ -2011,12 +2051,18 @@
addRegUsage_ARMAMode1(u, i->ARMin.LdSt8U.amode);
if (i->ARMin.LdSt8U.isLoad) {
addHRegUse(u, HRmWrite, i->ARMin.LdSt8U.rD);
+ if (i->ARMin.LdSt8U.cc != ARMcc_AL)
+ addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
} else {
addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
}
return;
case ARMin_Ld8S:
- goto unhandled;
+ addRegUsage_ARMAMode2(u, i->ARMin.Ld8S.amode);
+ addHRegUse(u, HRmWrite, i->ARMin.Ld8S.rD);
+ if (i->ARMin.Ld8S.cc != ARMcc_AL)
+ addHRegUse(u, HRmRead, i->ARMin.Ld8S.rD);
+ return;
/* XDirect/XIndir/XAssisted are also a bit subtle. They
conditionally exit the block. Hence we only need to list (1)
the registers that they read, and (2) the registers that they
@@ -2246,7 +2292,6 @@
addHRegUse(u, HRmWrite, hregARM_R12());
addHRegUse(u, HRmWrite, hregARM_R11());
return;
- unhandled:
default:
ppARMInstr(i);
vpanic("getRegUsage_ARMInstr");
@@ -2296,7 +2341,9 @@
mapRegs_ARMAMode1(m, i->ARMin.LdSt8U.amode);
return;
case ARMin_Ld8S:
- goto unhandled;
+ i->ARMin.Ld8S.rD = lookupHRegRemap(m, i->ARMin.Ld8S.rD);
+ mapRegs_ARMAMode2(m, i->ARMin.Ld8S.amode);
+ return;
case ARMin_XDirect:
mapRegs_ARMAMode1(m, i->ARMin.XDirect.amR15T);
return;
@@ -2437,7 +2484,6 @@
case ARMin_ProfInc:
/* hardwires r11 and r12 -- nothing to modify. */
return;
- unhandled:
default:
ppARMInstr(i);
vpanic("mapRegs_ARMInstr");
@@ -2504,7 +2550,7 @@
switch (rclass) {
case HRcInt32:
vassert(offsetB <= 4095);
- *i1 = ARMInstr_LdSt32( False/*!isLoad*/,
+ *i1 = ARMInstr_LdSt32( ARMcc_AL, False/*!isLoad*/,
rreg,
ARMAMode1_RI(hregARM_R8(), offsetB) );
return;
@@ -2559,7 +2605,7 @@
switch (rclass) {
case HRcInt32:
vassert(offsetB <= 4095);
- *i1 = ARMInstr_LdSt32( True/*isLoad*/,
+ *i1 = ARMInstr_LdSt32( ARMcc_AL, True/*isLoad*/,
rreg,
ARMAMode1_RI(hregARM_R8(), offsetB) );
return;
@@ -3006,20 +3052,24 @@
}
case ARMin_LdSt32:
case ARMin_LdSt8U: {
- UInt bL, bB;
- HReg rD;
- ARMAMode1* am;
+ UInt bL, bB;
+ HReg rD;
+ ARMAMode1* am;
+ ARMCondCode cc;
if (i->tag == ARMin_LdSt32) {
bB = 0;
bL = i->ARMin.LdSt32.isLoad ? 1 : 0;
am = i->ARMin.LdSt32.amode;
rD = i->ARMin.LdSt32.rD;
+ cc = i->ARMin.LdSt32.cc;
} else {
bB = 1;
bL = i->ARMin.LdSt8U.isLoad ? 1 : 0;
am = i->ARMin.LdSt8U.amode;
rD = i->ARMin.LdSt8U.rD;
+ cc = i->ARMin.LdSt8U.cc;
}
+ vassert(cc != ARMcc_NV);
if (am->tag == ARMam1_RI) {
Int simm12;
UInt instr, bP;
@@ -3031,7 +3081,7 @@
simm12 = am->ARMam1.RI.simm13;
}
vassert(simm12 >= 0 && simm12 <= 4095);
- instr = XXXXX___(X1110,X0101,BITS4(bP,bB,0,bL),
+ instr = XXXXX___(cc,X0101,BITS4(bP,bB,0,bL),
iregNo(am->ARMam1.RI.reg),
iregNo(rD));
instr |= simm12;
@@ -3043,10 +3093,12 @@
}
}
case ARMin_LdSt16: {
- HReg rD = i->ARMin.LdSt16.rD;
- UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0;
- UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0;
- ARMAMode2* am = i->ARMin.LdSt16.amode;
+ HReg rD = i->ARMin.LdSt16.rD;
+ UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0;
+ UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0;
+ ARMAMode2* am = i->ARMin.LdSt16.amode;
+ ARMCondCode cc = i->ARMin.LdSt16.cc;
+ vassert(cc != ARMcc_NV);
if (am->tag == ARMam2_RI) {
HReg rN = am->ARMam2.RI.reg;
Int simm8;
@@ -3064,20 +3116,24 @@
vassert(!(bL == 0 && bS == 1)); // "! signed store"
/**/ if (bL == 0 && bS == 0) {
// strh
- instr = XXXXXXXX(X1110,X0001, BITS4(bP,1,0,0), iregNo(rN),
+ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,0), iregNo(rN),
iregNo(rD), imm8hi, X1011, imm8lo);
*p++ = instr;
goto done;
}
else if (bL == 1 && bS == 0) {
// ldrh
- instr = XXXXXXXX(X1110,X0001, BITS4(bP,1,0,1), iregNo(rN),
+ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
iregNo(rD), imm8hi, X1011, imm8lo);
*p++ = instr;
goto done;
}
else if (bL == 1 && bS == 1) {
- goto bad;
+ // ldrsh
+ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
+ iregNo(rD), imm8hi, X1111, imm8lo);
+ *p++ = instr;
+ goto done;
}
else vassert(0); // ill-constructed insn
} else {
@@ -3085,8 +3141,35 @@
goto bad;
}
}
- case ARMin_Ld8S:
- goto bad;
+ case ARMin_Ld8S: {
+ HReg rD = i->ARMin.Ld8S.rD;
+ ARMAMode2* am = i->ARMin.Ld8S.amode;
+ ARMCondCode cc = i->ARMin.Ld8S.cc;
+ vassert(cc != ARMcc_NV);
+ if (am->tag == ARMam2_RI) {
+ HReg rN = am->ARMam2.RI.reg;
+ Int simm8;
+ UInt bP, imm8hi, imm8lo, instr;
+ if (am->ARMam2.RI.simm9 < 0) {
+ bP = 0;
+ simm8 = -am->ARMam2.RI.simm9;
+ } else {
+ bP = 1;
+ simm8 = am->ARMam2.RI.simm9;
+ }
+ vassert(simm8 >= 0 && simm8 <= 255);
+ imm8hi = (simm8 >> 4) & 0xF;
+ imm8lo = simm8 & 0xF;
+ // ldrsb
+ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN),
+ iregNo(rD), imm8hi, X1101, imm8lo);
+ *p++ = instr;
+ goto done;
+ } else {
+ // RR case
+ goto bad;
+ }
+ }
case ARMin_XDirect: {
/* NB: what goes on here has to be very closely coordinated
@@ -3267,6 +3350,7 @@
*p++ = instr;
goto done;
}
+
case ARMin_Call: {
UInt instr;
/* Decide on a scratch reg used to hold to the call address.
@@ -3280,14 +3364,82 @@
case 4: scratchNo = 11; break;
default: vassert(0);
}
- // r"scratchNo" = &target
- p = imm32_to_iregNo( (UInt*)p,
- scratchNo, (UInt)i->ARMin.Call.target );
- // blx{cond} r"scratchNo"
- instr = XXX___XX(i->ARMin.Call.cond, X0001, X0010, /*___*/
- X0011, scratchNo);
- instr |= 0xFFF << 8; // stick in the SBOnes
- *p++ = instr;
+ /* If we don't need to do any fixup actions in the case that
+ the call doesn't happen, just do the simple thing and emit
+ straight-line code. We hope this is the common case. */
+ if (i->ARMin.Call.cond == ARMcc_AL/*call always happens*/
+ || i->ARMin.Call.rloc == RetLocNone/*no fixup action*/) {
+ // r"scratchNo" = &target
+ p = imm32_to_iregNo( (UInt*)p,
+ scratchNo, (UInt)i->ARMin.Call.target );
+ // blx{cond} r"scratchNo"
+ instr = XXX___XX(i->ARMin.Call.cond, X0001, X0010, /*___*/
+ X0011, scratchNo);
+ instr |= 0xFFF << 8; // stick in the SBOnes
+ *p++ = instr;
+ } else {
+ Int delta;
+ /* Complex case. We have to generate an if-then-else
+ diamond. */
+ // before:
+ // b{!cond} else:
+ // r"scratchNo" = &target
+ // blx{AL} r"scratchNo"
+ // preElse:
+ // b after:
+ // else:
+ // mvn r0, #0 // possibly
+ // mvn r1, #0 // possibly
+ // after:
+
+ // before:
+ UInt* pBefore = p;
+
+ // b{!cond} else: // ptmp1 points here
+ *p++ = 0; // filled in later
+
+ // r"scratchNo" = &target
+ p = imm32_to_iregNo( (UInt*)p,
+ scratchNo, (UInt)i->ARMin.Call.target );
+
+ // blx{AL} r"scratchNo"
+ instr = XXX___XX(ARMcc_AL, X0001, X0010, /*___*/
+ X0011, scratchNo);
+ instr |= 0xFFF << 8; // stick in the SBOnes
+ *p++ = instr;
+
+ // preElse:
+ UInt* pPreElse = p;
+
+ // b after:
+ *p++ = 0; // filled in later
+
+ // else:
+ delta = (UChar*)p - (UChar*)pBefore;
+ delta = (delta >> 2) - 2;
+ *pBefore
+ = XX______(1 ^ i->ARMin.Call.cond, X1010) | (delta & 0xFFFFFF);
+
+ /* Do the 'else' actions */
+ switch (i->ARMin.Call.rloc) {
+ case RetLocInt:
+ *p++ = 0xE3E00000; break; // mvn r0, #0
+ case RetLoc2Int:
+ // mvn r0, #0 ; mvn r1, #0
+ vassert(0); //ATC
+ *p++ = 0xE3E00000; *p++ = 0xE3E01000; break;
+ case RetLocNone:
+ case RetLocINVALID:
+ default:
+ vassert(0);
+ }
+
+ // after:
+ delta = (UChar*)p - (UChar*)pPreElse;
+ delta = (delta >> 2) - 2;
+ *pPreElse = XX______(ARMcc_AL, X1010) | (delta & 0xFFFFFF);
+ }
+
goto done;
}
case ARMin_Mul: {
|
|
From: <sv...@va...> - 2012-11-25 15:14:52
|
sewardj 2012-11-25 15:14:44 +0000 (Sun, 25 Nov 2012)
New Revision: 2570
Log:
Add IR level definitions and associated iropt hackery, to support
direct representation of conditional (guarded) loads and stores in IR.
Modified files:
branches/COMEM/priv/ir_defs.c
branches/COMEM/priv/ir_opt.c
branches/COMEM/pub/libvex_ir.h
Modified: branches/COMEM/pub/libvex_ir.h (+138 -25)
===================================================================
--- branches/COMEM/pub/libvex_ir.h 2012-11-25 12:48:39 +00:00 (rev 2569)
+++ branches/COMEM/pub/libvex_ir.h 2012-11-25 15:14:44 +00:00 (rev 2570)
@@ -218,7 +218,7 @@
float, or a vector (SIMD) value. */
typedef
enum {
- Ity_INVALID=0x11000,
+ Ity_INVALID=0x1100,
Ity_I1,
Ity_I8,
Ity_I16,
@@ -248,7 +248,7 @@
/* IREndness is used in load IRExprs and store IRStmts. */
typedef
enum {
- Iend_LE=0x12000, /* little endian */
+ Iend_LE=0x1200, /* little endian */
Iend_BE /* big endian */
}
IREndness;
@@ -261,7 +261,7 @@
/* The various kinds of constant. */
typedef
enum {
- Ico_U1=0x13000,
+ Ico_U1=0x1300,
Ico_U8,
Ico_U16,
Ico_U32,
@@ -412,7 +412,7 @@
/* -- Do not change this ordering. The IR generators rely on
(eg) Iop_Add64 == IopAdd8 + 3. -- */
- Iop_INVALID=0x14000,
+ Iop_INVALID=0x1400,
Iop_Add8, Iop_Add16, Iop_Add32, Iop_Add64,
Iop_Sub8, Iop_Sub16, Iop_Sub32, Iop_Sub64,
/* Signless mul. MullS/MullU is elsewhere. */
@@ -1543,7 +1543,7 @@
in the comments for IRExpr. */
typedef
enum {
- Iex_Binder=0x15000,
+ Iex_Binder=0x1900,
Iex_Get,
Iex_GetI,
Iex_RdTmp,
@@ -1752,7 +1752,7 @@
} Iex;
};
-/* ------------------ A ternary expression ---------------------- */
+/* Expression auxiliaries: a ternary expression. */
struct _IRTriop {
IROp op; /* op-code */
IRExpr* arg1; /* operand 1 */
@@ -1760,7 +1760,7 @@
IRExpr* arg3; /* operand 3 */
};
-/* ------------------ A quarternary expression ------------------ */
+/* Expression auxiliaries: a quarternary expression. */
struct _IRQop {
IROp op; /* op-code */
IRExpr* arg1; /* operand 1 */
@@ -1865,7 +1865,7 @@
*/
typedef
enum {
- Ijk_INVALID=0x16000,
+ Ijk_INVALID=0x1A00,
Ijk_Boring, /* not interesting; just goto next */
Ijk_Call, /* guest is doing a call */
Ijk_Ret, /* guest is doing a return */
@@ -1912,19 +1912,21 @@
Dirty calls are statements rather than expressions for obvious
reasons. If a dirty call is marked as writing guest state, any
- values derived from the written parts of the guest state are
- invalid. Similarly, if the dirty call is stated as writing
- memory, any loaded values are invalidated by it.
+ pre-existing values derived from the written parts of the guest
+ state are invalid. Similarly, if the dirty call is stated as
+ writing memory, any pre-existing loaded values are invalidated by
+ it.
In order that instrumentation is possible, the call must state, and
state correctly:
- * whether it reads, writes or modifies memory, and if so where
- (only one chunk can be stated)
+ * whether it reads, writes or modifies memory, and if so where Only
+ one chunk can be stated, although it is allowed to repeat some
+ number of times at a fixed interval.
* whether it reads, writes or modifies guest state, and if so which
- pieces (several pieces may be stated, and currently their extents
- must be known at translation-time).
+ pieces. Several pieces may be stated, and their extents must be
+ known at translation-time.
Normally, code is generated to pass just the args to the helper.
However, if .needsBBP is set, then an extra first argument is
@@ -1934,9 +1936,11 @@
call does not access guest state.
IMPORTANT NOTE re GUARDS: Dirty calls are strict, very strict. The
- arguments are evaluated REGARDLESS of the guard value. The order of
- argument evaluation is unspecified. The guard expression is evaluated
- AFTER the arguments have been evaluated.
+ arguments, and 'mFx' are evaluated REGARDLESS of the guard value.
+ The order of argument evaluation is unspecified. The guard
+ expression is evaluated AFTER the arguments and 'mFx' have been
+ evaluated. 'mFx' is expected (by Memcheck) to be a defined value
+ even if the guard evaluates to false.
*/
#define VEX_N_FXSTATE 7 /* enough for FXSAVE/FXRSTOR on x86 */
@@ -1944,7 +1948,7 @@
/* Effects on resources (eg. registers, memory locations) */
typedef
enum {
- Ifx_None = 0x1700, /* no effect */
+ Ifx_None=0x1B00, /* no effect */
Ifx_Read, /* reads the resource */
Ifx_Write, /* writes the resource */
Ifx_Modify, /* modifies the resource */
@@ -1958,10 +1962,10 @@
typedef
struct _IRDirty {
/* What to call, and details of args/results. .guard must be
- non-NULL. If .tmp is not IRTemp_INVALID (that is, the call
- returns a result) then .guard must be demonstrably (at
- JIT-time) always true, that is, the call must be
- unconditional. Conditional calls that assign .tmp are not
+ non-NULL. If .tmp is not IRTemp_INVALID, then the call
+ returns a result which is placed in .tmp. If at runtime the
+ guard evaluates to false, .tmp has an all-ones bit pattern
+ written to it. Hence conditional calls that assign .tmp are
allowed. */
IRCallee* cee; /* where to call */
IRExpr* guard; /* :: Ity_Bit. Controls whether call happens */
@@ -2031,7 +2035,7 @@
typedef
enum {
- Imbe_Fence=0x18000,
+ Imbe_Fence=0x1C00,
/* Needed only on ARM. It cancels a reservation made by a
preceding Linked-Load, and needs to be handed through to the
back end, just as LL and SC themselves are. */
@@ -2131,6 +2135,7 @@
/* ------------------ Circular Array Put ------------------ */
+
typedef
struct {
IRRegArray* descr; /* Part of guest state treated as circular */
@@ -2147,6 +2152,85 @@
extern IRPutI* deepCopyIRPutI ( IRPutI* );
+/* --------------- Guarded loads and stores --------------- */
+
+/* Conditional stores are straightforward. They are the same as
+ normal stores, with an extra 'guard' field :: Ity_I1 that
+ determines whether or not the store actually happens. If not,
+ memory is unmodified.
+
+ The semantics of this is that 'addr' and 'data' are fully evaluated
+ even in the case where 'guard' evaluates to zero (false).
+*/
+typedef
+ struct {
+ IREndness end; /* Endianness of the store */
+ IRExpr* addr; /* store address */
+ IRExpr* data; /* value to write */
+ IRExpr* guard; /* Guarding value */
+ }
+ IRStoreG;
+
+/* Conditional loads are a little more complex. 'addr' is the
+ address, 'guard' is the guarding condition. If the load takes
+ place, the loaded value is placed in 'dst'. If it does not take
+ place, 'alt' is copied to 'dst'. However, the loaded value is not
+ placed directly in 'dst' -- it is first subjected to the conversion
+ specified by 'cvt'.
+
+ For example, imagine doing a conditional 8-bit load, in which the
+ loaded value is zero extended to 32 bits. Hence:
+ * 'dst' and 'alt' must have type I32
+ * 'cvt' must be a unary op which converts I8 to I32. In this
+ example, it would be ILGop_8Uto32.
+
+ There is no explicit indication of the type at which the load is
+ done, since that is inferrable from the arg type of 'cvt'. Note
+ that the types of 'alt' and 'dst' and the result type of 'cvt' must
+ all be the same.
+
+ Semantically, 'addr' is evaluated even in the case where 'guard'
+ evaluates to zero (false), and 'alt' is evaluated even when 'guard'
+ evaluates to one (true). That is, 'addr' and 'alt' are always
+ evaluated.
+*/
+typedef
+ enum {
+ ILGop_INVALID=0x1D00,
+ ILGop_Ident32, /* 32 bit, no conversion */
+ ILGop_16Uto32, /* 16 bit load, Z-widen to 32 */
+ ILGop_16Sto32, /* 16 bit load, S-widen to 32 */
+ ILGop_8Uto32, /* 8 bit load, Z-widen to 32 */
+ ILGop_8Sto32 /* 8 bit load, S-widen to 32 */
+ }
+ IRLoadGOp;
+
+typedef
+ struct {
+ IREndness end; /* Endianness of the load */
+ IRLoadGOp cvt; /* Conversion to apply to the loaded value */
+ IRTemp dst; /* Destination (LHS) of assignment */
+ IRExpr* addr; /* Address being loaded from */
+ IRExpr* alt; /* Value if load is not done. */
+ IRExpr* guard; /* Guarding value */
+ }
+ IRLoadG;
+
+extern void ppIRStoreG ( IRStoreG* sg );
+
+extern void ppIRLoadGOp ( IRLoadGOp cvt );
+
+extern void ppIRLoadG ( IRLoadG* lg );
+
+extern IRStoreG* mkIRStoreG ( IREndness end,
+ IRExpr* addr, IRExpr* data,
+ IRExpr* guard );
+
+extern IRLoadG* mkIRLoadG ( IREndness end, IRLoadGOp cvt,
+ IRTemp dst, IRExpr* addr, IRExpr* alt,
+ IRExpr* guard );
+
+
/* ------------------ Statements ------------------ */
/* The different kinds of statements. Their meaning is explained
@@ -2161,13 +2245,15 @@
typedef
enum {
- Ist_NoOp=0x19000,
+ Ist_NoOp=0x1E00,
Ist_IMark, /* META */
Ist_AbiHint, /* META */
Ist_Put,
Ist_PutI,
Ist_WrTmp,
Ist_Store,
+ Ist_LoadG,
+ Ist_StoreG,
Ist_CAS,
Ist_LLSC,
Ist_Dirty,
@@ -2288,6 +2374,24 @@
IRExpr* data; /* value to write */
} Store;
+ /* Guarded store. Note that this is defined to evaluate all
+ expression fields (addr, data) even if the guard evaluates
+ to false.
+ ppIRStmt output:
+ if (<guard>) ST<end>(<addr>) = <data> */
+ struct {
+ IRStoreG* details;
+ } StoreG;
+
+ /* Guarded load. Note that this is defined to evaluate all
+ expression fields (addr, alt) even if the guard evaluates
+ to false.
+ ppIRStmt output:
+ t<tmp> = if (<guard>) <cvt>(LD<end>(<addr>)) else <alt> */
+ struct {
+ IRLoadG* details;
+ } LoadG;
+
/* Do an atomic compare-and-swap operation. Semantics are
described above on a comment at the definition of IRCAS.
@@ -2407,6 +2511,10 @@
extern IRStmt* IRStmt_PutI ( IRPutI* details );
extern IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data );
extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data );
+extern IRStmt* IRStmt_StoreG ( IREndness end, IRExpr* addr, IRExpr* data,
+ IRExpr* guard );
+extern IRStmt* IRStmt_LoadG ( IREndness end, IRLoadGOp cvt, IRTemp dst,
+ IRExpr* addr, IRExpr* alt, IRExpr* guard );
extern IRStmt* IRStmt_CAS ( IRCAS* details );
extern IRStmt* IRStmt_LLSC ( IREndness end, IRTemp result,
IRExpr* addr, IRExpr* storedata );
@@ -2504,6 +2612,11 @@
extern IRType typeOfIRTemp ( IRTypeEnv*, IRTemp );
extern IRType typeOfIRExpr ( IRTypeEnv*, IRExpr* );
+/* What are the arg and result type for this IRLoadGOp? */
+extern void typeOfIRLoadGOp ( IRLoadGOp cvt,
+ /*OUT*/IRType* t_res,
+ /*OUT*/IRType* t_arg );
+
/* Sanity check a BB of IR */
extern void sanityCheckIRSB ( IRSB* bb,
const HChar* caller,
Modified: branches/COMEM/priv/ir_defs.c (+192 -20)
===================================================================
--- branches/COMEM/priv/ir_defs.c 2012-11-25 12:48:39 +00:00 (rev 2569)
+++ branches/COMEM/priv/ir_defs.c 2012-11-25 15:14:44 +00:00 (rev 2570)
@@ -1217,6 +1217,42 @@
ppIRExpr(puti->data);
}
+void ppIRStoreG ( IRStoreG* sg )
+{
+ vex_printf("if (");
+ ppIRExpr(sg->guard);
+ vex_printf(") ST%s(", sg->end==Iend_LE ? "le" : "be");
+ ppIRExpr(sg->addr);
+ vex_printf(") = ");
+ ppIRExpr(sg->data);
+}
+
+void ppIRLoadGOp ( IRLoadGOp cvt )
+{
+ switch (cvt) {
+ case ILGop_INVALID: vex_printf("ILGop_INVALID"); break;
+ case ILGop_Ident32: vex_printf("Ident32"); break;
+ case ILGop_16Uto32: vex_printf("16Uto32"); break;
+ case ILGop_16Sto32: vex_printf("16Sto32"); break;
+ case ILGop_8Uto32: vex_printf("8Uto32"); break;
+ case ILGop_8Sto32: vex_printf("8Sto32"); break;
+ default: vpanic("ppIRLoadGOp");
+ }
+}
+
+void ppIRLoadG ( IRLoadG* lg )
+{
+ ppIRTemp(lg->dst);
+ vex_printf(" = if-strict (");
+ ppIRExpr(lg->guard);
+ vex_printf(") ");
+ ppIRLoadGOp(lg->cvt);
+ vex_printf("(LD%s(", lg->end==Iend_LE ? "le" : "be");
+ ppIRExpr(lg->addr);
+ vex_printf(")) else ");
+ ppIRExpr(lg->alt);
+}
+
void ppIRJumpKind ( IRJumpKind kind )
{
switch (kind) {
@@ -1298,6 +1334,12 @@
vex_printf( ") = ");
ppIRExpr(s->Ist.Store.data);
break;
+ case Ist_StoreG:
+ ppIRStoreG(s->Ist.StoreG.details);
+ break;
+ case Ist_LoadG:
+ ppIRLoadG(s->Ist.LoadG.details);
+ break;
case Ist_CAS:
ppIRCAS(s->Ist.CAS.details);
break;
@@ -1738,6 +1780,33 @@
}
+/* Constructors -- IRStoreG and IRLoadG */
+
+IRStoreG* mkIRStoreG ( IREndness end,
+ IRExpr* addr, IRExpr* data, IRExpr* guard )
+{
+ IRStoreG* sg = LibVEX_Alloc(sizeof(IRStoreG));
+ sg->end = end;
+ sg->addr = addr;
+ sg->data = data;
+ sg->guard = guard;
+ return sg;
+}
+
+IRLoadG* mkIRLoadG ( IREndness end, IRLoadGOp cvt,
+ IRTemp dst, IRExpr* addr, IRExpr* alt, IRExpr* guard )
+{
+ IRLoadG* lg = LibVEX_Alloc(sizeof(IRLoadG));
+ lg->end = end;
+ lg->cvt = cvt;
+ lg->dst = dst;
+ lg->addr = addr;
+ lg->alt = alt;
+ lg->guard = guard;
+ return lg;
+}
+
+
/* Constructors -- IRStmt */
IRStmt* IRStmt_NoOp ( void )
@@ -1792,6 +1861,21 @@
vassert(end == Iend_LE || end == Iend_BE);
return s;
}
+IRStmt* IRStmt_StoreG ( IREndness end, IRExpr* addr, IRExpr* data,
+ IRExpr* guard ) {
+ IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
+ s->tag = Ist_StoreG;
+ s->Ist.StoreG.details = mkIRStoreG(end, addr, data, guard);
+ vassert(end == Iend_LE || end == Iend_BE);
+ return s;
+}
+IRStmt* IRStmt_LoadG ( IREndness end, IRLoadGOp cvt, IRTemp dst,
+ IRExpr* addr, IRExpr* alt, IRExpr* guard ) {
+ IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
+ s->tag = Ist_LoadG;
+ s->Ist.LoadG.details = mkIRLoadG(end, cvt, dst, addr, alt, guard);
+ return s;
+}
IRStmt* IRStmt_CAS ( IRCAS* cas ) {
IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
s->tag = Ist_CAS;
@@ -2043,6 +2127,20 @@
return IRStmt_Store(s->Ist.Store.end,
deepCopyIRExpr(s->Ist.Store.addr),
deepCopyIRExpr(s->Ist.Store.data));
+ case Ist_StoreG: {
+ IRStoreG* sg = s->Ist.StoreG.details;
+ return IRStmt_StoreG(sg->end,
+ deepCopyIRExpr(sg->addr),
+ deepCopyIRExpr(sg->data),
+ deepCopyIRExpr(sg->guard));
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = s->Ist.LoadG.details;
+ return IRStmt_LoadG(lg->end, lg->cvt, lg->dst,
+ deepCopyIRExpr(lg->addr),
+ deepCopyIRExpr(lg->alt),
+ deepCopyIRExpr(lg->guard));
+ }
case Ist_CAS:
return IRStmt_CAS(deepCopyIRCAS(s->Ist.CAS.details));
case Ist_LLSC:
@@ -2929,7 +3027,6 @@
return env->types[tmp];
}
-
IRType typeOfIRConst ( IRConst* con )
{
switch (con->tag) {
@@ -2948,6 +3045,21 @@
}
}
+void typeOfIRLoadGOp ( IRLoadGOp cvt,
+ /*OUT*/IRType* t_res, /*OUT*/IRType* t_arg )
+{
+ switch (cvt) {
+ case ILGop_Ident32:
+ *t_res = Ity_I32; *t_arg = Ity_I32; break;
+ case ILGop_16Uto32: case ILGop_16Sto32:
+ *t_res = Ity_I32; *t_arg = Ity_I16; break;
+ case ILGop_8Uto32: case ILGop_8Sto32:
+ *t_res = Ity_I32; *t_arg = Ity_I8; break;
+ default:
+ vpanic("typeOfIRLoadGOp");
+ }
+}
+
IRType typeOfIRExpr ( IRTypeEnv* tyenv, IRExpr* e )
{
IRType t_dst, t_arg1, t_arg2, t_arg3, t_arg4;
@@ -3086,6 +3198,16 @@
case Ist_Store:
return toBool( isIRAtom(st->Ist.Store.addr)
&& isIRAtom(st->Ist.Store.data) );
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ return toBool( isIRAtom(sg->addr)
+ && isIRAtom(sg->data) && isIRAtom(sg->guard) );
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ return toBool( isIRAtom(lg->addr)
+ && isIRAtom(lg->alt) && isIRAtom(lg->guard) );
+ }
case Ist_CAS:
cas = st->Ist.CAS.details;
return toBool( isIRAtom(cas->addr)
@@ -3258,10 +3380,12 @@
static
void useBeforeDef_Stmt ( IRSB* bb, IRStmt* stmt, Int* def_counts )
{
- Int i;
- IRDirty* d;
- IRCAS* cas;
- IRPutI* puti;
+ Int i;
+ IRDirty* d;
+ IRCAS* cas;
+ IRPutI* puti;
+ IRLoadG* lg;
+ IRStoreG* sg;
switch (stmt->tag) {
case Ist_IMark:
break;
@@ -3284,6 +3408,18 @@
useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.addr,def_counts);
useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.data,def_counts);
break;
+ case Ist_StoreG:
+ sg = stmt->Ist.StoreG.details;
+ useBeforeDef_Expr(bb,stmt,sg->addr,def_counts);
+ useBeforeDef_Expr(bb,stmt,sg->data,def_counts);
+ useBeforeDef_Expr(bb,stmt,sg->guard,def_counts);
+ break;
+ case Ist_LoadG:
+ lg = stmt->Ist.LoadG.details;
+ useBeforeDef_Expr(bb,stmt,lg->addr,def_counts);
+ useBeforeDef_Expr(bb,stmt,lg->alt,def_counts);
+ useBeforeDef_Expr(bb,stmt,lg->guard,def_counts);
+ break;
case Ist_CAS:
cas = stmt->Ist.CAS.details;
useBeforeDef_Expr(bb,stmt,cas->addr,def_counts);
@@ -3571,18 +3707,54 @@
tcExpr( bb, stmt, stmt->Ist.WrTmp.data, gWordTy );
if (typeOfIRTemp(tyenv, stmt->Ist.WrTmp.tmp)
!= typeOfIRExpr(tyenv, stmt->Ist.WrTmp.data))
- sanityCheckFail(bb,stmt,"IRStmt.Put.Tmp: tmp and expr do not match");
+ sanityCheckFail(bb,stmt,
+ "IRStmt.Put.Tmp: tmp and expr do not match");
break;
case Ist_Store:
tcExpr( bb, stmt, stmt->Ist.Store.addr, gWordTy );
tcExpr( bb, stmt, stmt->Ist.Store.data, gWordTy );
if (typeOfIRExpr(tyenv, stmt->Ist.Store.addr) != gWordTy)
- sanityCheckFail(bb,stmt,"IRStmt.Store.addr: not :: guest word type");
+ sanityCheckFail(bb,stmt,
+ "IRStmt.Store.addr: not :: guest word type");
if (typeOfIRExpr(tyenv, stmt->Ist.Store.data) == Ity_I1)
- sanityCheckFail(bb,stmt,"IRStmt.Store.data: cannot Store :: Ity_I1");
+ sanityCheckFail(bb,stmt,
+ "IRStmt.Store.data: cannot Store :: Ity_I1");
if (stmt->Ist.Store.end != Iend_LE && stmt->Ist.Store.end != Iend_BE)
sanityCheckFail(bb,stmt,"Ist.Store.end: bogus endianness");
break;
+ case Ist_StoreG: {
+ IRStoreG* sg = stmt->Ist.StoreG.details;
+ tcExpr( bb, stmt, sg->addr, gWordTy );
+ tcExpr( bb, stmt, sg->data, gWordTy );
+ tcExpr( bb, stmt, sg->guard, gWordTy );
+ if (typeOfIRExpr(tyenv, sg->addr) != gWordTy)
+ sanityCheckFail(bb,stmt,"IRStmtG...addr: not :: guest word type");
+ if (typeOfIRExpr(tyenv, sg->data) == Ity_I1)
+ sanityCheckFail(bb,stmt,"IRStmtG...data: cannot Store :: Ity_I1");
+ if (typeOfIRExpr(tyenv, sg->guard) != Ity_I1)
+ sanityCheckFail(bb,stmt,"IRStmtG...guard: not :: Ity_I1");
+ if (sg->end != Iend_LE && sg->end != Iend_BE)
+ sanityCheckFail(bb,stmt,"IRStmtG...end: bogus endianness");
+ break;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = stmt->Ist.LoadG.details;
+ tcExpr( bb, stmt, lg->addr, gWordTy );
+ tcExpr( bb, stmt, lg->alt, gWordTy );
+ tcExpr( bb, stmt, lg->guard, gWordTy );
+ if (typeOfIRExpr(tyenv, lg->guard) != Ity_I1)
+ sanityCheckFail(bb,stmt,"IRStmt.LoadG.guard: not :: Ity_I1");
+ if (typeOfIRExpr(tyenv, lg->addr) != gWordTy)
+ sanityCheckFail(bb,stmt,"IRStmt.LoadG.addr: not "
+ ":: guest word type");
+ if (typeOfIRExpr(tyenv, lg->alt) != typeOfIRTemp(tyenv, lg->dst))
+ sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/alt type mismatch");
+ IRTemp cvtRes = Ity_INVALID, cvtArg = Ity_INVALID;
+ typeOfIRLoadGOp(lg->cvt, &cvtRes, &cvtArg);
+ if (cvtRes != typeOfIRTemp(tyenv, lg->dst))
+ sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/loaded type mismatch");
+ break;
+ }
case Ist_CAS:
cas = stmt->Ist.CAS.details;
/* make sure it's definitely either a CAS or a DCAS */
@@ -3692,15 +3864,6 @@
tcExpr( bb, stmt, d->guard, gWordTy );
if (typeOfIRExpr(tyenv, d->guard) != Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.Dirty.guard not :: Ity_I1");
- /* A dirty helper that is executed conditionally (or not at
- all) may not return a value. Hence if .tmp is not
- IRTemp_INVALID, .guard must be manifestly True at JIT
- time. */
- if (d->tmp != IRTemp_INVALID
- && (d->guard->tag != Iex_Const
- || d->guard->Iex.Const.con->Ico.U1 == 0))
- sanityCheckFail(bb,stmt,"IRStmt.Dirty with a return value"
- " is executed under a condition");
/* check types, minimally */
if (d->tmp != IRTemp_INVALID
&& typeOfIRTemp(tyenv, d->tmp) == Ity_I1)
@@ -3793,6 +3956,7 @@
for (i = 0; i < bb->stmts_used; i++) {
IRDirty* d;
IRCAS* cas;
+ IRLoadG* lg;
stmt = bb->stmts[i];
/* Check any temps used by this statement. */
useBeforeDef_Stmt(bb,stmt,def_counts);
@@ -3808,11 +3972,19 @@
sanityCheckFail(bb, stmt,
"IRStmt.Tmp: destination tmp is assigned more than once");
break;
- case Ist_Store:
+ case Ist_LoadG:
+ lg = stmt->Ist.LoadG.details;
+ if (lg->dst < 0 || lg->dst >= n_temps)
+ sanityCheckFail(bb, stmt,
+ "IRStmt.LoadG: destination tmp is out of range");
+ def_counts[lg->dst]++;
+ if (def_counts[lg->dst] > 1)
+ sanityCheckFail(bb, stmt,
+ "IRStmt.LoadG: destination tmp is assigned more than once");
break;
case Ist_Dirty:
- if (stmt->Ist.Dirty.details->tmp != IRTemp_INVALID) {
- d = stmt->Ist.Dirty.details;
+ d = stmt->Ist.Dirty.details;
+ if (d->tmp != IRTemp_INVALID) {
if (d->tmp < 0 || d->tmp >= n_temps)
sanityCheckFail(bb, stmt,
"IRStmt.Dirty: destination tmp is out of range");
Modified: branches/COMEM/priv/ir_opt.c (+274 -27)
===================================================================
--- branches/COMEM/priv/ir_opt.c 2012-11-25 12:48:39 +00:00 (rev 2569)
+++ branches/COMEM/priv/ir_opt.c 2012-11-25 15:14:44 +00:00 (rev 2570)
@@ -400,10 +400,12 @@
static void flatten_Stmt ( IRSB* bb, IRStmt* st )
{
Int i;
- IRExpr *e1, *e2, *e3, *e4, *e5;
- IRDirty *d, *d2;
- IRCAS *cas, *cas2;
- IRPutI *puti, *puti2;
+ IRExpr *e1, *e2, *e3, *e4, *e5;
+ IRDirty *d, *d2;
+ IRCAS *cas, *cas2;
+ IRPutI *puti, *puti2;
+ IRLoadG *lg;
+ IRStoreG *sg;
switch (st->tag) {
case Ist_Put:
if (isIRAtom(st->Ist.Put.data)) {
@@ -439,6 +441,21 @@
e2 = flatten_Expr(bb, st->Ist.Store.data);
addStmtToIRSB(bb, IRStmt_Store(st->Ist.Store.end, e1,e2));
break;
+ case Ist_StoreG:
+ sg = st->Ist.StoreG.details;
+ e1 = flatten_Expr(bb, sg->addr);
+ e2 = flatten_Expr(bb, sg->data);
+ e3 = flatten_Expr(bb, sg->guard);
+ addStmtToIRSB(bb, IRStmt_StoreG(sg->end, e1, e2, e3));
+ break;
+ case Ist_LoadG:
+ lg = st->Ist.LoadG.details;
+ e1 = flatten_Expr(bb, lg->addr);
+ e2 = flatten_Expr(bb, lg->alt);
+ e3 = flatten_Expr(bb, lg->guard);
+ addStmtToIRSB(bb, IRStmt_LoadG(lg->end, lg->cvt, lg->dst,
+ e1, e2, e3));
+ break;
case Ist_CAS:
cas = st->Ist.CAS.details;
e1 = flatten_Expr(bb, cas->addr);
@@ -763,7 +780,22 @@
vassert(isIRAtom(st->Ist.Store.data));
memRW = True;
break;
-
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ vassert(isIRAtom(sg->addr));
+ vassert(isIRAtom(sg->data));
+ vassert(isIRAtom(sg->guard));
+ memRW = True;
+ break;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ vassert(isIRAtom(lg->addr));
+ vassert(isIRAtom(lg->alt));
+ vassert(isIRAtom(lg->guard));
+ memRW = True;
+ break;
+ }
case Ist_Exit:
vassert(isIRAtom(st->Ist.Exit.guard));
break;
@@ -2407,6 +2439,62 @@
fold_Expr(env, subst_Expr(env, st->Ist.Store.data))
);
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ vassert(isIRAtom(sg->addr));
+ vassert(isIRAtom(sg->data));
+ vassert(isIRAtom(sg->guard));
+ IRExpr* faddr = fold_Expr(env, subst_Expr(env, sg->addr));
+ IRExpr* fdata = fold_Expr(env, subst_Expr(env, sg->data));
+ IRExpr* fguard = fold_Expr(env, subst_Expr(env, sg->guard));
+ if (fguard->tag == Iex_Const) {
+ /* The condition on this store has folded down to a constant. */
+ vassert(fguard->Iex.Const.con->tag == Ico_U1);
+ if (fguard->Iex.Const.con->Ico.U1 == False) {
+ return IRStmt_NoOp();
+ } else {
+ vassert(fguard->Iex.Const.con->Ico.U1 == True);
+ return IRStmt_Store(sg->end, faddr, fdata);
+ }
+ }
+ return IRStmt_StoreG(sg->end, faddr, fdata, fguard);
+ }
+
+ case Ist_LoadG: {
+ /* This is complicated. If the guard folds down to 'false',
+ we can replace it with a NoOp, but if the guard folds down
+ to 'true', we can't conveniently replace it with an
+ unconditional load, because doing so requires generating a
+ new temporary, and that is not easy to do at this
+ point. */
+ IRLoadG* lg = st->Ist.LoadG.details;
+ vassert(isIRAtom(lg->addr));
+ vassert(isIRAtom(lg->alt));
+ vassert(isIRAtom(lg->guard));
+ IRExpr* faddr = fold_Expr(env, subst_Expr(env, lg->addr));
+ IRExpr* falt = fold_Expr(env, subst_Expr(env, lg->alt));
+ IRExpr* fguard = fold_Expr(env, subst_Expr(env, lg->guard));
+ if (fguard->tag == Iex_Const) {
+ /* The condition on this load has folded down to a constant. */
+ vassert(fguard->Iex.Const.con->tag == Ico_U1);
+ if (fguard->Iex.Const.con->Ico.U1 == False) {
+ /* The load is not going to happen -- instead 'alt' is
+ assigned to 'dst'. */
+ return IRStmt_WrTmp(lg->dst, falt);
+ } else {
+ vassert(fguard->Iex.Const.con->Ico.U1 == True);
+ /* The load is always going to happen. We want to
+ convert to an unconditional load and assign to 'dst'
+ (IRStmt_WrTmp). Problem is we need an extra temp to
+ hold the loaded value, but none is available.
+ Instead, reconstitute the conditional load (with
+ folded args, of course) and let the caller of this
+ routine deal with the problem. */
+ }
+ }
+ return IRStmt_LoadG(lg->end, lg->cvt, lg->dst, faddr, falt, fguard);
+ }
+
case Ist_CAS: {
IRCAS *cas, *cas2;
cas = st->Ist.CAS.details;
@@ -2480,8 +2568,6 @@
/* Interesting. The condition on this exit has folded down to
a constant. */
vassert(fcond->Iex.Const.con->tag == Ico_U1);
- vassert(fcond->Iex.Const.con->Ico.U1 == False
- || fcond->Iex.Const.con->Ico.U1 == True);
if (fcond->Iex.Const.con->Ico.U1 == False) {
/* exit is never going to happen, so dump the statement. */
return IRStmt_NoOp();
@@ -2515,6 +2601,11 @@
IRStmt* st2;
Int n_tmps = in->tyenv->types_used;
IRExpr** env = LibVEX_Alloc(n_tmps * sizeof(IRExpr*));
+ /* Keep track of IRStmt_LoadGs that we need to revisit after
+ processing all the other statements. */
+ const Int N_FIXUPS = 16;
+ Int fixups[N_FIXUPS]; /* indices in the stmt array of 'out' */
+ Int n_fixups = 0;
out = emptyIRSB();
out->tyenv = deepCopyIRTypeEnv( in->tyenv );
@@ -2542,40 +2633,124 @@
st2 = subst_and_fold_Stmt( env, st2 );
- /* If the statement has been folded into a no-op, forget it. */
- if (st2->tag == Ist_NoOp) continue;
+ /* Deal with some post-folding special cases. */
+ switch (st2->tag) {
- /* If the statement assigns to an IRTemp add it to the running
- environment. This is for the benefit of copy propagation
- and to allow sameIRExpr look through IRTemps. */
- if (st2->tag == Ist_WrTmp) {
- vassert(env[(Int)(st2->Ist.WrTmp.tmp)] == NULL);
- env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
+ /* If the statement has been folded into a no-op, forget
+ it. */
+ case Ist_NoOp:
+ continue;
- /* 't1 = t2' -- don't add to BB; will be optimized out */
- if (st2->Ist.WrTmp.data->tag == Iex_RdTmp) continue;
+ /* If the statement assigns to an IRTemp add it to the
+ running environment. This is for the benefit of copy
+ propagation and to allow sameIRExpr look through
+ IRTemps. */
+ case Ist_WrTmp: {
+ vassert(env[(Int)(st2->Ist.WrTmp.tmp)] == NULL);
+ env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
- /* 't = const' && 'const != F64i' -- don't add to BB
- Note, we choose not to propagate const when const is an
- F64i, so that F64i literals can be CSE'd later. This helps
- x86 floating point code generation. */
- if (st2->Ist.WrTmp.data->tag == Iex_Const
- && st2->Ist.WrTmp.data->Iex.Const.con->tag != Ico_F64i) continue;
+ /* 't1 = t2' -- don't add to BB; will be optimized out */
+ if (st2->Ist.WrTmp.data->tag == Iex_RdTmp)
+ continue;
+
+ /* 't = const' && 'const != F64i' -- don't add to BB
+ Note, we choose not to propagate const when const is an
+ F64i, so that F64i literals can be CSE'd later. This
+ helps x86 floating point code generation. */
+ if (st2->Ist.WrTmp.data->tag == Iex_Const
+ && st2->Ist.WrTmp.data->Iex.Const.con->tag != Ico_F64i) {
+ continue;
+ }
+ /* else add it to the output, as normal */
+ break;
+ }
+
+ case Ist_LoadG: {
+ IRLoadG* lg = st2->Ist.LoadG.details;
+ IRExpr* guard = lg->guard;
+ if (guard->tag == Iex_Const) {
+ /* The guard has folded to a constant, and that
+ constant must be 1:I1, since subst_and_fold_Stmt
+ folds out the case 0:I1 by itself. */
+ vassert(guard->Iex.Const.con->tag == Ico_U1);
+ vassert(guard->Iex.Const.con->Ico.U1 == True);
+ /* Add a NoOp here as a placeholder, and make a note of
+ where it is in the output block. Afterwards we'll
+ come back here and transform the NoOp and the LoadG
+ into a load-convert pair. The fixups[] entry
+ refers to the inserted NoOp, and we expect to find
+ the relevant LoadG immediately after it. */
+ vassert(n_fixups >= 0 && n_fixups <= N_FIXUPS);
+ if (n_fixups < N_FIXUPS) {
+ fixups[n_fixups++] = out->stmts_used;
+ addStmtToIRSB( out, IRStmt_NoOp() );
+ }
+ }
+ /* And always add the LoadG to the output, regardless. */
+ break;
+ }
+
+ default:
+ break;
}
/* Not interesting, copy st2 into the output block. */
addStmtToIRSB( out, st2 );
}
-#if STATS_IROPT
+# if STATS_IROPT
vex_printf("sameIRExpr: invoked = %u/%u equal = %u/%u max_nodes = %u\n",
invocation_count, recursion_count, success_count,
recursion_success_count, max_nodes_visited);
-#endif
+# endif
out->next = subst_Expr( env, in->next );
out->jumpkind = in->jumpkind;
out->offsIP = in->offsIP;
+
+ /* Process any leftover unconditional LoadGs that we noticed
+ in the main pass. */
+ vassert(n_fixups >= 0 && n_fixups <= N_FIXUPS);
+ for (i = 0; i < n_fixups; i++) {
+ Int ix = fixups[i];
+ /* Carefully verify that the LoadG has the expected form. */
+ vassert(ix >= 0 && ix+1 < out->stmts_used);
+ IRStmt* nop = out->stmts[ix];
+ IRStmt* lgu = out->stmts[ix+1];
+ vassert(nop->tag == Ist_NoOp);
+ vassert(lgu->tag == Ist_LoadG);
+ IRLoadG* lg = lgu->Ist.LoadG.details;
+ IRExpr* guard = lg->guard;
+ vassert(guard->Iex.Const.con->tag == Ico_U1);
+ vassert(guard->Iex.Const.con->Ico.U1 == True);
+ /* Figure out the load and result types, and the implied
+ conversion operation. */
+ IRType cvtRes = Ity_INVALID, cvtArg = Ity_INVALID;
+ typeOfIRLoadGOp(lg->cvt, &cvtRes, &cvtArg);
+ IROp cvtOp = Iop_INVALID;
+ switch (lg->cvt) {
+ case ILGop_Ident32: break;
+ case ILGop_8Uto32: cvtOp = Iop_8Uto32; break;
+ case ILGop_8Sto32: cvtOp = Iop_8Sto32; break;
+ case ILGop_16Uto32: cvtOp = Iop_16Uto32; break;
+ case ILGop_16Sto32: cvtOp = Iop_16Sto32; break;
+ default: vpanic("cprop_BB: unhandled ILGOp");
+ }
+ /* Replace the placeholder NoOp by the required unconditional
+ load. */
+ IRTemp tLoaded = newIRTemp(out->tyenv, cvtArg);
+ out->stmts[ix]
+ = IRStmt_WrTmp(tLoaded,
+ IRExpr_Load(lg->end, cvtArg, lg->addr));
+ /* Replace the LoadG by a conversion from the loaded value's
+ type to the required result type. */
+ out->stmts[ix+1]
+ = IRStmt_WrTmp(
+ lg->dst, cvtOp == Iop_INVALID
+ ? IRExpr_RdTmp(tLoaded)
+ : IRExpr_Unop(cvtOp, IRExpr_RdTmp(tLoaded)));
+ }
+
return out;
}
@@ -2671,6 +2846,20 @@
addUses_Expr(set, st->Ist.Store.addr);
addUses_Expr(set, st->Ist.Store.data);
return;
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ addUses_Expr(set, sg->addr);
+ addUses_Expr(set, sg->data);
+ addUses_Expr(set, sg->guard);
+ return;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ addUses_Expr(set, lg->addr);
+ addUses_Expr(set, lg->alt);
+ addUses_Expr(set, lg->guard);
+ return;
+ }
case Ist_CAS:
cas = st->Ist.CAS.details;
addUses_Expr(set, cas->addr);
@@ -3477,7 +3666,7 @@
if (0) { ppIRSB(bb); vex_printf("\n\n"); }
/* Iterate forwards over the stmts.
- On seeing "t = E", where E is one of the 5 AvailExpr forms:
+ On seeing "t = E", where E is one of the AvailExpr forms:
let E' = apply tenv substitution to E
search aenv for E'
if a mapping E' -> q is found,
@@ -3507,11 +3696,12 @@
switch (st->tag) {
case Ist_Dirty: case Ist_Store: case Ist_MBE:
case Ist_CAS: case Ist_LLSC:
+ case Ist_StoreG:
paranoia = 2; break;
case Ist_Put: case Ist_PutI:
paranoia = 1; break;
case Ist_NoOp: case Ist_IMark: case Ist_AbiHint:
- case Ist_WrTmp: case Ist_Exit:
+ case Ist_WrTmp: case Ist_Exit: case Ist_LoadG:
paranoia = 0; break;
default:
vpanic("do_cse_BB(1)");
@@ -4212,6 +4402,21 @@
deltaIRExpr(st->Ist.Store.addr, delta);
deltaIRExpr(st->Ist.Store.data, delta);
break;
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ deltaIRExpr(sg->addr, delta);
+ deltaIRExpr(sg->data, delta);
+ deltaIRExpr(sg->guard, delta);
+ break;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ lg->dst += delta;
+ deltaIRExpr(lg->addr, delta);
+ deltaIRExpr(lg->alt, delta);
+ deltaIRExpr(lg->guard, delta);
+ break;
+ }
case Ist_CAS:
if (st->Ist.CAS.details->oldHi != IRTemp_INVALID)
st->Ist.CAS.details->oldHi += delta;
@@ -4684,6 +4889,20 @@
aoccCount_Expr(uses, st->Ist.Store.addr);
aoccCount_Expr(uses, st->Ist.Store.data);
return;
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ aoccCount_Expr(uses, sg->addr);
+ aoccCount_Expr(uses, sg->data);
+ aoccCount_Expr(uses, sg->guard);
+ return;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ aoccCount_Expr(uses, lg->addr);
+ aoccCount_Expr(uses, lg->alt);
+ aoccCount_Expr(uses, lg->guard);
+ return;
+ }
case Ist_CAS:
cas = st->Ist.CAS.details;
aoccCount_Expr(uses, cas->addr);
@@ -5000,6 +5219,20 @@
atbSubst_Expr(env, st->Ist.Store.addr),
atbSubst_Expr(env, st->Ist.Store.data)
);
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ return IRStmt_StoreG(sg->end,
+ atbSubst_Expr(env, sg->addr),
+ atbSubst_Expr(env, sg->data),
+ atbSubst_Expr(env, sg->guard));
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ return IRStmt_LoadG(lg->end, lg->cvt, lg->dst,
+ atbSubst_Expr(env, lg->addr),
+ atbSubst_Expr(env, lg->alt),
+ atbSubst_Expr(env, lg->guard));
+ }
case Ist_WrTmp:
return IRStmt_WrTmp(
st->Ist.WrTmp.tmp,
@@ -5411,6 +5644,20 @@
vassert(isIRAtom(st->Ist.Store.addr));
vassert(isIRAtom(st->Ist.Store.data));
break;
+ case Ist_StoreG: {
+ IRStoreG* sg = st->Ist.StoreG.details;
+ vassert(isIRAtom(sg->addr));
+ vassert(isIRAtom(sg->data));
+ vassert(isIRAtom(sg->guard));
+ break;
+ }
+ case Ist_LoadG: {
+ IRLoadG* lg = st->Ist.LoadG.details;
+ vassert(isIRAtom(lg->addr));
+ vassert(isIRAtom(lg->alt));
+ vassert(isIRAtom(lg->guard));
+ break;
+ }
case Ist_CAS:
cas = st->Ist.CAS.details;
vassert(isIRAtom(cas->addr));
|
|
From: <sv...@va...> - 2012-11-25 12:56:17
|
sewardj 2012-11-25 12:56:10 +0000 (Sun, 25 Nov 2012)
New Revision: 13141
Log:
Swizzle external.
Modified directories:
branches/COMEM/
Modified: branches/COMEM/
Property changed: branches/COMEM (+0 -0)
___________________________________________________________________
Name: svn:externals
- VEX svn://svn.valgrind.org/vex/trunk
+ VEX svn://svn.valgrind.org/vex/branches/COMEM
|
|
From: <sv...@va...> - 2012-11-25 12:51:13
|
sewardj 2012-11-25 12:51:04 +0000 (Sun, 25 Nov 2012)
New Revision: 13140
Log:
Move this directory to the right place. Duh.
Copied directories:
branches/COMEM/ (from rev 13139, COMEM/)
Removed directories:
COMEM/
Copied: branches/COMEM/
(from rev 13139, COMEM/)
Deleted: COMEM/
% svn ls COMEM/@13139
|
|
From: <sv...@va...> - 2012-11-25 12:48:45
|
sewardj 2012-11-25 12:48:39 +0000 (Sun, 25 Nov 2012)
New Revision: 2569
Log:
Move this directory to the right place. Duh.
Copied directories:
branches/COMEM/ (from rev 2568, COMEM/)
Removed directories:
COMEM/
Copied: branches/COMEM/
(from rev 2568, COMEM/)
Deleted: COMEM/
% svn ls COMEM/@2568
|
|
From: <sv...@va...> - 2012-11-25 12:42:42
|
sewardj 2012-11-25 12:42:27 +0000 (Sun, 25 Nov 2012)
New Revision: 13139
Log:
Create a copy of trunk r13138 to hold work on adding direct support
for conditional loads and stores to IR ("COnditional MEMory")
Copied directories:
COMEM/ (from rev 13138, trunk/)
Copied: COMEM/
(from rev 13138, trunk/)
|
|
From: <sv...@va...> - 2012-11-25 12:35:51
|
sewardj 2012-11-25 12:35:42 +0000 (Sun, 25 Nov 2012)
New Revision: 2568
Log:
Create a copy of trunk r2567 to hold work on adding direct support
for conditional loads and stores to IR ("COnditional MEMory")
Copied directories:
COMEM/ (from rev 2567, trunk/)
Copied: COMEM/
(from rev 2567, trunk/)
|
|
From: Philippe W. <phi...@sk...> - 2012-11-25 04:46:46
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.3.1-3.fc16.ppc64 ppc64 Vendor version: Fedora release 16 (Verne) Nightly build on gcc110 ( Fedora release 16 (Verne), ppc64 ) Started at 2012-11-24 20:00:14 PST Ended at 2012-11-24 20:45:06 PST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 538 tests, 8 stderr failures, 3 stdout failures, 1 stderrB failure, 1 stdoutB failure, 2 post failures == gdbserver_tests/mcmain_pic (stdout) gdbserver_tests/mcmain_pic (stderr) gdbserver_tests/mcmain_pic (stdoutB) gdbserver_tests/mcmain_pic (stderrB) memcheck/tests/linux/getregset (stdout) memcheck/tests/linux/getregset (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/trivialleak (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) massif/tests/big-alloc (post) massif/tests/deep-D (post) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc20_verifywrap (stderr) |
|
From: Tom H. <to...@co...> - 2012-11-25 04:11:47
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2012-11-25 03:41:26 GMT Ended at 2012-11-25 04:11:32 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 613 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Rich C. <rc...@wi...> - 2012-11-25 04:02:23
|
valgrind revision: 13138
VEX revision: 2567
C compiler: gcc (SUSE Linux) 4.5.1 20101208 [gcc-4_5-branch revision 167585]
Assembler: GNU assembler (GNU Binutils; openSUSE 11.4) 2.21
C library: GNU C Library stable release version 2.11.3 (20110203)
uname -mrs: Linux 2.6.37.6-0.7-desktop x86_64
Vendor version: Welcome to openSUSE 11.4 "Celadon" - Kernel %r (%t).
Nightly build on ultra ( gcc 4.5.1 Linux 2.6.37.6-0.7-desktop x86_64 )
Started at 2012-11-24 21:30:02 CST
Ended at 2012-11-24 22:02:10 CST
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 628 tests, 2 stderr failures, 0 stdout failures, 6 stderrB failures, 0 stdoutB failures, 0 post failures ==
gdbserver_tests/mcbreak (stderrB)
gdbserver_tests/mcclean_after_fork (stderrB)
gdbserver_tests/mcleak (stderrB)
gdbserver_tests/mcmain_pic (stderrB)
gdbserver_tests/mcvabits (stderrB)
gdbserver_tests/mssnapshot (stderrB)
memcheck/tests/linux/timerfd-syscall (stderr)
memcheck/tests/origin5-bz2 (stderr)
=================================================
./valgrind-new/gdbserver_tests/mcbreak.stderrB.diff
=================================================
--- mcbreak.stderrB.exp 2012-11-24 21:45:32.229383137 -0600
+++ mcbreak.stderrB.out 2012-11-24 21:53:02.543546907 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
vgdb-error value changed from 999999 to 0
n_errs_found 1 n_errs_shown 1 (vgdb-error 0)
vgdb-error value changed from 0 to 0
=================================================
./valgrind-new/gdbserver_tests/mcclean_after_fork.stderrB.diff
=================================================
--- mcclean_after_fork.stderrB.exp 2012-11-24 21:45:32.228383021 -0600
+++ mcclean_after_fork.stderrB.out 2012-11-24 21:53:04.255744833 -0600
@@ -1,4 +1,6 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
monitor command request to kill this process
Remote connection closed
=================================================
./valgrind-new/gdbserver_tests/mcleak.stderrB.diff
=================================================
--- mcleak.stderrB.exp 2012-11-24 21:45:32.223382441 -0600
+++ mcleak.stderrB.out 2012-11-24 21:53:22.465849885 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
10 bytes in 1 blocks are still reachable in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: f (leak-delta.c:14)
=================================================
./valgrind-new/gdbserver_tests/mcmain_pic.stderrB.diff
=================================================
--- mcmain_pic.stderrB.exp 2012-11-24 21:45:32.232383485 -0600
+++ mcmain_pic.stderrB.out 2012-11-24 21:53:24.081036598 -0600
@@ -1,2 +1,4 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
=================================================
./valgrind-new/gdbserver_tests/mcvabits.stderrB.diff
=================================================
--- mcvabits.stderrB.exp 2012-11-24 21:45:32.233383601 -0600
+++ mcvabits.stderrB.out 2012-11-24 21:53:28.832585871 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
Address 0x........ len 10 addressable
Address 0x........ is 0 bytes inside data symbol "undefined"
Address 0x........ len 10 defined
=================================================
./valgrind-new/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2012-11-24 21:45:32.232383485 -0600
+++ mssnapshot.stderrB.out 2012-11-24 21:53:31.908941491 -0600
@@ -1,5 +1,9 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=92ec8fe859846a62345f74696ab349721415587a"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-new/memcheck/tests/linux/timerfd-syscall.stderr.diff
=================================================
--- timerfd-syscall.stderr.exp 2012-11-24 21:45:38.435102461 -0600
+++ timerfd-syscall.stderr.out 2012-11-24 21:54:42.948153636 -0600
@@ -33,7 +33,7 @@
got timer ticks (1) after 0.5 s
absolute timer test (at 500 ms) ...
waiting timer ...
-got timer ticks (1) after 0.5 s
+got timer ticks (1) after 0.0 s
sequential timer test (100 ms clock) ...
sleeping one second ...
timerfd_gettime returned:
=================================================
./valgrind-new/memcheck/tests/origin5-bz2.stderr.diff-glibc212-s390x
=================================================
--- origin5-bz2.stderr.exp-glibc212-s390x 2012-11-24 21:45:49.542389938 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:54:58.381937809 -0600
@@ -75,17 +75,6 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
- at 0x........: mainSort (origin5-bz2.c:2859)
- by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
- by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
- by 0x........: handle_compress (origin5-bz2.c:4753)
- by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
- by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
- by 0x........: main (origin5-bz2.c:6484)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
-Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -131,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-new/memcheck/tests/origin5-bz2.stderr.diff-glibc234-s390x
=================================================
--- origin5-bz2.stderr.exp-glibc234-s390x 2012-11-24 21:45:49.525387968 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:54:58.381937809 -0600
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-new/memcheck/tests/origin5-bz2.stderr.diff-glibc25-amd64
=================================================
--- origin5-bz2.stderr.exp-glibc25-amd64 2012-11-24 21:45:49.468381360 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:54:58.381937809 -0600
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-new/memcheck/tests/origin5-bz2.stderr.diff-glibc25-x86
=================================================
--- origin5-bz2.stderr.exp-glibc25-x86 2012-11-24 21:45:49.498384838 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:54:58.381937809 -0600
@@ -12,7 +12,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
@@ -21,7 +21,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
@@ -30,7 +30,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2820)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -41,7 +41,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2823)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -52,7 +52,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2854)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -63,7 +63,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2858)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -74,7 +74,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -85,7 +85,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2964)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -96,7 +96,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2269)
by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -107,7 +107,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2275)
by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
<truncated beyond 100 lines>
=================================================
./valgrind-new/memcheck/tests/origin5-bz2.stderr.diff-glibc27-ppc64
=================================================
--- origin5-bz2.stderr.exp-glibc27-ppc64 2012-11-24 21:45:49.511386344 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:54:58.381937809 -0600
@@ -1,7 +1,7 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6481)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Conditional jump or move depends on uninitialised value(s)
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -10,7 +10,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -19,7 +19,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -28,7 +28,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2820)
@@ -39,7 +39,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2823)
@@ -50,7 +50,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2854)
@@ -61,7 +61,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2858)
@@ -72,7 +72,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
@@ -83,7 +83,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2964)
@@ -94,7 +94,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2269)
@@ -105,7 +105,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
<truncated beyond 100 lines>
=================================================
./valgrind-old/gdbserver_tests/mcbreak.stderrB.diff
=================================================
--- mcbreak.stderrB.exp 2012-11-24 21:31:14.744983514 -0600
+++ mcbreak.stderrB.out 2012-11-24 21:35:27.098237615 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
vgdb-error value changed from 999999 to 0
n_errs_found 1 n_errs_shown 1 (vgdb-error 0)
vgdb-error value changed from 0 to 0
=================================================
./valgrind-old/gdbserver_tests/mcclean_after_fork.stderrB.diff
=================================================
--- mcclean_after_fork.stderrB.exp 2012-11-24 21:31:14.744983514 -0600
+++ mcclean_after_fork.stderrB.out 2012-11-24 21:35:28.804435401 -0600
@@ -1,4 +1,6 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
monitor command request to kill this process
Remote connection closed
=================================================
./valgrind-old/gdbserver_tests/mcleak.stderrB.diff
=================================================
--- mcleak.stderrB.exp 2012-11-24 21:31:14.740983050 -0600
+++ mcleak.stderrB.out 2012-11-24 21:35:47.532606422 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
10 bytes in 1 blocks are still reachable in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: f (leak-delta.c:14)
=================================================
./valgrind-old/gdbserver_tests/mcmain_pic.stderrB.diff
=================================================
--- mcmain_pic.stderrB.exp 2012-11-24 21:31:14.748983978 -0600
+++ mcmain_pic.stderrB.out 2012-11-24 21:35:49.135792268 -0600
@@ -1,2 +1,4 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
=================================================
./valgrind-old/gdbserver_tests/mcvabits.stderrB.diff
=================================================
--- mcvabits.stderrB.exp 2012-11-24 21:31:14.749984094 -0600
+++ mcvabits.stderrB.out 2012-11-24 21:35:53.880342268 -0600
@@ -1,5 +1,7 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
Address 0x........ len 10 addressable
Address 0x........ is 0 bytes inside data symbol "undefined"
Address 0x........ len 10 defined
=================================================
./valgrind-old/gdbserver_tests/mssnapshot.stderrB.diff
=================================================
--- mssnapshot.stderrB.exp 2012-11-24 21:31:14.748983978 -0600
+++ mssnapshot.stderrB.out 2012-11-24 21:35:56.950698192 -0600
@@ -1,5 +1,9 @@
relaying data between gdb and process ....
vgdb-error value changed from 0 to 999999
+
+
+Missing separate debuginfo for /lib64/libc.so.6
+Try: zypper install -C "debuginfo(build-id)=92ec8fe859846a62345f74696ab349721415587a"
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
=================================================
./valgrind-old/memcheck/tests/linux/timerfd-syscall.stderr.diff
=================================================
--- timerfd-syscall.stderr.exp 2012-11-24 21:31:23.627013186 -0600
+++ timerfd-syscall.stderr.out 2012-11-24 21:37:08.070942579 -0600
@@ -33,7 +33,7 @@
got timer ticks (1) after 0.5 s
absolute timer test (at 500 ms) ...
waiting timer ...
-got timer ticks (1) after 0.5 s
+got timer ticks (1) after 0.0 s
sequential timer test (100 ms clock) ...
sleeping one second ...
timerfd_gettime returned:
=================================================
./valgrind-old/memcheck/tests/origin5-bz2.stderr.diff-glibc212-s390x
=================================================
--- origin5-bz2.stderr.exp-glibc212-s390x 2012-11-24 21:31:28.796612483 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:37:23.487729708 -0600
@@ -75,17 +75,6 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
- at 0x........: mainSort (origin5-bz2.c:2859)
- by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
- by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
- by 0x........: handle_compress (origin5-bz2.c:4753)
- by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
- by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
- by 0x........: main (origin5-bz2.c:6484)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
-Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -131,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-old/memcheck/tests/origin5-bz2.stderr.diff-glibc234-s390x
=================================================
--- origin5-bz2.stderr.exp-glibc234-s390x 2012-11-24 21:31:28.779610512 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:37:23.487729708 -0600
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-old/memcheck/tests/origin5-bz2.stderr.diff-glibc25-amd64
=================================================
--- origin5-bz2.stderr.exp-glibc25-amd64 2012-11-24 21:31:28.722603903 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:37:23.487729708 -0600
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: g_serviceFn (origin5-bz2.c:6429)
+ by 0x........: default_bzalloc (origin5-bz2.c:4470)
+ by 0x........: BZ2_decompress (origin5-bz2.c:1578)
+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192)
+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678)
+ by 0x........: main (origin5-bz2.c:6498)
=================================================
./valgrind-old/memcheck/tests/origin5-bz2.stderr.diff-glibc25-x86
=================================================
--- origin5-bz2.stderr.exp-glibc25-x86 2012-11-24 21:31:28.752607381 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:37:23.487729708 -0600
@@ -12,7 +12,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
@@ -21,7 +21,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
@@ -30,7 +30,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2820)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -41,7 +41,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2823)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -52,7 +52,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2854)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -63,7 +63,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2858)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -74,7 +74,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -85,7 +85,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2964)
by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -96,7 +96,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2269)
by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -107,7 +107,7 @@
Uninitialised value was created by a client request
at 0x........: main (origin5-bz2.c:6479)
-Use of uninitialised value of size 4
+Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2275)
by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
@@ -120,6 +120,12 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
+ Uninitialised value was created by a heap allocation
+ at 0x........: malloc (vg_replace_malloc.c:...)
<truncated beyond 100 lines>
=================================================
./valgrind-old/memcheck/tests/origin5-bz2.stderr.diff-glibc27-ppc64
=================================================
--- origin5-bz2.stderr.exp-glibc27-ppc64 2012-11-24 21:31:28.765608889 -0600
+++ origin5-bz2.stderr.out 2012-11-24 21:37:23.487729708 -0600
@@ -1,7 +1,7 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (origin5-bz2.c:6481)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Conditional jump or move depends on uninitialised value(s)
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -10,7 +10,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -19,7 +19,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
@@ -28,7 +28,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2820)
@@ -39,7 +39,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2823)
@@ -50,7 +50,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2854)
@@ -61,7 +61,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2858)
@@ -72,7 +72,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2963)
@@ -83,7 +83,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: mainSort (origin5-bz2.c:2964)
@@ -94,7 +94,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
at 0x........: fallbackSort (origin5-bz2.c:2269)
@@ -105,7 +105,7 @@
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6481)
+ at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
<truncated beyond 100 lines>
|
|
From: Tom H. <to...@co...> - 2012-11-25 03:58:55
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.4.1 20090725 (Red Hat 4.4.1-2) Assembler: GNU assembler version 2.19.51.0.14-3.fc11 20090722 C library: GNU C Library stable release version 2.10.2 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 11 (Leonidas) Nightly build on bristol ( x86_64, Fedora 11 ) Started at 2012-11-25 03:31:08 GMT Ended at 2012-11-25 03:58:42 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 617 tests, 1 stderr failure, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/long_namespace_xml (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Tom H. <to...@co...> - 2012-11-25 03:49:47
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.4.5 20101112 (Red Hat 4.4.5-2) Assembler: GNU assembler version 2.20.51.0.2-20.fc13 20091009 C library: GNU C Library stable release version 2.12.2 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 13 (Goddard) Nightly build on bristol ( x86_64, Fedora 13 ) Started at 2012-11-25 03:21:32 GMT Ended at 2012-11-25 03:49:34 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 617 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == helgrind/tests/pth_barrier3 (stderr) |
|
From: Tom H. <to...@co...> - 2012-11-25 03:40:44
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.5.1 20100924 (Red Hat 4.5.1-4) Assembler: GNU assembler version 2.20.51.0.7-8.fc14 20100318 C library: GNU C Library stable release version 2.13 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 14 (Laughlin) Nightly build on bristol ( x86_64, Fedora 14 ) Started at 2012-11-25 03:11:37 GMT Ended at 2012-11-25 03:40:31 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 635 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) |
|
From: Tom H. <to...@co...> - 2012-11-25 03:33:26
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2012-11-25 03:03:04 GMT Ended at 2012-11-25 03:33:09 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 637 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) |
|
From: Tom H. <to...@co...> - 2012-11-25 03:23:38
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2012-11-25 02:52:11 GMT Ended at 2012-11-25 03:23:27 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 637 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) |
|
From: Christian B. <bor...@de...> - 2012-11-25 03:13:51
|
valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.21.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.42-0.7-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP2 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP1 gcc 4.3.4 on z196 (s390x) ) Started at 2012-11-25 03:45:01 CET Ended at 2012-11-25 04:13:42 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 610 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == |
|
From: Tom H. <to...@co...> - 2012-11-25 03:13:04
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valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2012-11-25 02:41:13 GMT Ended at 2012-11-25 03:12:52 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 637 tests, 5 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) memcheck/tests/origin5-bz2 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
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From: Tom H. <to...@co...> - 2012-11-25 03:03:33
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valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) Assembler: GNU assembler version 2.23.51.0.1-3.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2012-11-25 02:31:14 GMT Ended at 2012-11-25 03:03:21 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 637 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
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From: Tom H. <to...@co...> - 2012-11-25 02:48:07
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valgrind revision: 13138 VEX revision: 2567 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) Assembler: GNU assembler version 2.23.51.0.5-1.fc19 20121110 C library: GNU C Library development release version 2.16.90 uname -mrs: Linux 3.5.3-1.fc17.x86_64 x86_64 Vendor version: Fedora release 19 (Rawhide) Nightly build on bristol ( x86_64, Fedora 19 ) Started at 2012-11-25 02:21:15 GMT Ended at 2012-11-25 02:47:55 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 637 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) |
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From: <sv...@va...> - 2012-11-25 01:22:35
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florian 2012-11-25 01:22:27 +0000 (Sun, 25 Nov 2012)
New Revision: 2567
Log:
Formatting only change.
Modified files:
trunk/priv/guest_s390_helpers.c
Modified: trunk/priv/guest_s390_helpers.c (+5 -4)
===================================================================
--- trunk/priv/guest_s390_helpers.c 2012-11-24 21:07:14 +00:00 (rev 2566)
+++ trunk/priv/guest_s390_helpers.c 2012-11-25 01:22:27 +00:00 (rev 2567)
@@ -1534,11 +1534,12 @@
return unop(Iop_1Uto32, binop(Iop_CmpLT64S, mkU64(0), cc_dep1));
}
if (cond == 8 + 2 || cond == 8 + 2 + 1) {
- /* special case =0 || >0 to handle some gcc magic that only checks
- * the first bit. Fixes 308427
+ /* Special case cc_dep >= 0. Only check the MSB to avoid bogus
+ memcheck complaints due to gcc magic. Fixes 308427
*/
- return unop(Iop_64to32, binop(Iop_Xor64, binop(Iop_Shr64,cc_dep1,mkU8(63)),
- mkU64(1)));
+ return unop(Iop_64to32, binop(Iop_Xor64,
+ binop(Iop_Shr64, cc_dep1, mkU8(63)),
+ mkU64(1)));
}
if (cond == 8 + 4 + 2 || cond == 8 + 4 + 2 + 1) {
return mkU32(1);
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