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From: Petar J. <mip...@gm...> - 2012-09-17 22:52:45
|
On Mon, Sep 17, 2012 at 8:39 PM, Florian Krohm <br...@ac...> wrote: > So this is a 64-bit architecture, right? I am addressing its 32-bit mode, so from that point of view, it's 32-bit. It should behave like all other MIPS32 implementation, but it does not. Petar |
|
From: <sv...@va...> - 2012-09-17 21:23:33
|
sewardj 2012-09-17 22:26:42 +0100 (Mon, 17 Sep 2012)
New Revision: 12992
Log:
Commit some left-over merge metadata.
Modified directories:
branches/VALGRIND_3_8_BRANCH/
branches/VALGRIND_3_8_BRANCH/coregrind/
branches/VALGRIND_3_8_BRANCH/coregrind/m_syswrap/
Modified files:
branches/VALGRIND_3_8_BRANCH/Makefile.am
branches/VALGRIND_3_8_BRANCH/coregrind/m_syswrap/syswrap-generic.c
Modified: branches/VALGRIND_3_8_BRANCH/
Modified: branches/VALGRIND_3_8_BRANCH/coregrind/
Modified: branches/VALGRIND_3_8_BRANCH/coregrind/m_syswrap/
Property changed: branches/VALGRIND_3_8_BRANCH/coregrind/m_syswrap/syswrap-generic.c (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN/coregrind/m_syswrap/syswrap-generic.c:12477-12516
/trunk/coregrind/m_syswrap/syswrap-generic.c:12874,12878-12879,12881-12883,12885,12887,12891-12894,12897-12898,12923,12947
+ /branches/TCHAIN/coregrind/m_syswrap/syswrap-generic.c:12477-12516
/trunk/coregrind/m_syswrap/syswrap-generic.c:12874,12878-12879,12881-12883,12885,12887,12891-12894,12897-12898,12923,12947,12980,12982
Property changed: branches/VALGRIND_3_8_BRANCH/Makefile.am (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN/Makefile.am:12477-12516
/trunk/Makefile.am:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964,12983
+ /branches/TCHAIN/Makefile.am:12477-12516
/trunk/Makefile.am:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964,12980,12982-12983
Property changed: branches/VALGRIND_3_8_BRANCH/coregrind/m_syswrap (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN/coregrind/m_syswrap:12477-12516
/trunk/coregrind/m_syswrap:12873,12881-12883,12885,12887,12891-12894,12897-12898,12923,12947
+ /branches/TCHAIN/coregrind/m_syswrap:12477-12516
/trunk/coregrind/m_syswrap:12873,12881-12883,12885,12887,12891-12894,12897-12898,12923,12947,12980,12982
Property changed: branches/VALGRIND_3_8_BRANCH (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN:12477-12516
/trunk:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947
+ /branches/TCHAIN:12477-12516
/trunk:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12980,12982
Property changed: branches/VALGRIND_3_8_BRANCH/coregrind (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN/coregrind:12477-12516
/trunk/coregrind:12873,12881,12885,12887,12891-12894,12897-12898,12923,12947
+ /branches/TCHAIN/coregrind:12477-12516
/trunk/coregrind:12873,12881,12885,12887,12891-12894,12897-12898,12923,12947,12980,12982
|
|
From: <sv...@va...> - 2012-09-17 21:16:58
|
florian 2012-09-17 22:20:06 +0100 (Mon, 17 Sep 2012)
New Revision: 12991
Log:
Upon successful run, remove temporary files.
Modified files:
trunk/perf/vg_perf.in
Modified: trunk/perf/vg_perf.in (+6 -0)
===================================================================
--- trunk/perf/vg_perf.in 2012-09-17 19:54:44 +01:00 (rev 12990)
+++ trunk/perf/vg_perf.in 2012-09-17 22:20:06 +01:00 (rev 12991)
@@ -252,6 +252,12 @@
die "\n*** missing usertime in perf.stderr\n";
$tmin = $1 if ($1 < $tmin);
}
+
+ # Successful run; cleanup
+ unlink("perf.cmd");
+ unlink("perf.stderr");
+ unlink("perf.stdout");
+
# Avoid divisions by zero!
return (0 == $tmin ? 0.01 : $tmin);
}
|
|
From: <sv...@va...> - 2012-09-17 18:51:35
|
florian 2012-09-17 19:54:44 +0100 (Mon, 17 Sep 2012)
New Revision: 12990
Log:
Add missing header files. Building from tarball works again.
Modified files:
trunk/memcheck/tests/vbit-test/Makefile.am
Modified: trunk/memcheck/tests/vbit-test/Makefile.am (+1 -1)
===================================================================
--- trunk/memcheck/tests/vbit-test/Makefile.am 2012-09-17 19:20:29 +01:00 (rev 12989)
+++ trunk/memcheck/tests/vbit-test/Makefile.am 2012-09-17 19:54:44 +01:00 (rev 12990)
@@ -9,7 +9,7 @@
#----------------------------------------------------------------------------
pkginclude_HEADERS =
-noinst_HEADERS =
+noinst_HEADERS = vtest.h vbits.h
#----------------------------------------------------------------------------
# vbit_test
|
|
From: Florian K. <br...@ac...> - 2012-09-17 18:39:36
|
On 09/17/2012 08:18 AM, Petar Jovanovic wrote: > Hi everyone, > > Loongson platform has some specifics which diverge from MIPS32 spec. > This mostly relates to usage of odd registers in FPU instructions, and thus > we should (mostly) avoid use of odd single precision FP registers for Loongson. > > Thus, a fix (see down below) for this can be made in getAllocableRegs_MIPS. > It would be, however, nice to have that change conditional to Loongson platform, > but VexArchInfo is not available at that point. > So this is a 64-bit architecture, right? Then you would have another architecture entry: VexArchMIPS64 -- similar to what is done for PPC. If you do that then you can have a specific getAllocableRegs function for that architecture and use that in main_main.c Florian |
|
From: <sv...@va...> - 2012-09-17 18:17:20
|
sewardj 2012-09-17 19:20:29 +0100 (Mon, 17 Sep 2012)
New Revision: 12989
Log:
Update.
Modified files:
trunk/NEWS
trunk/docs/internals/3_8_BUGSTATUS.txt
Modified: trunk/docs/internals/3_8_BUGSTATUS.txt (+12 -25)
===================================================================
--- trunk/docs/internals/3_8_BUGSTATUS.txt 2012-09-17 19:20:06 +01:00 (rev 12988)
+++ trunk/docs/internals/3_8_BUGSTATUS.txt 2012-09-17 19:20:29 +01:00 (rev 12989)
@@ -22,7 +22,7 @@
(B38=12938) 12885 (Iop_DPBtoBCD and Iop_BCDtoDPB fix)
(B38=2502) 2475 (289584: Handle a reg-reg encoding of MOVAPS)
(B38=2503) 2476 (305042: Implement 0F 7F encoding of movq reg-reg)
-(B38=12940) 12887 (n-i-bz libmpiwrap.c fixes)
+(B38=12940) 12887 (n-i-bz: libmpiwrap.c fixes)
(B38=2504) 2477 (305321: Re-enable 'prefetch m8' and 'prefetchw m8')
(B38=2505) 2478 (295617: Fix LZCNT and TZCNT properly)
(B38=2506) 2479 (305199: Implement QDADD and QDSUB)
@@ -34,12 +34,16 @@
(B38=12945) 12897/8 (305690: andle non-zero sem_*wait() return values correctly)
(B38=2508) 2499 (305926: Invalid alignment checks for some AVX instructions)
(B38=12946) 12923 (304980: Guard against negative symbol sizes)
-(B38=12948) 12947 (n-i-bz: volatile in stack check, re clang)
-(B38=?????) 12964 (306310 3.8.0 release tarball missing some files)
+(B38=12948) 12947 (n-i-bz: volatile in stack check, re clang)
+(B38=12984) 12964 (306310 3.8.0 release tarball missing some files)
+(B38=2534) 2517/8 (n-i-bz: fix a couple of union tag-vs-field mixups)
+(B38=2535) 2531 (306297: ARM: STM<c>.W <Rn>{!}, <registers> too strict)
+(B38=2536) 2532 (306664: AMD64: Fix PCMPxSTRx variant $0x46)
+(B38=12985) 12982 (306612: Intercept __GI_memmove)
+(B38=2537,12986)
+ 2533,12980
+ (304035: ARM: uqsub16 shadd16 uhsub8 uhsub16)
-VEX r2517, 2518
-#306310 (12964)
-
-------- Bugs brought forward from 3_7_BUGSTATUS.txt --------
291310 FXSAVE instruction marks memory as undefined on amd64
@@ -58,10 +62,6 @@
303877 valgrind doesn't support compressed debuginfo sections.
-304035 disInstr(arm): unhandled instruction 0xE1023053
- UQSUB16 QADD QSUB QDADD SHADD16 UHSUB16
- (but based on 3.6.1; unclear which are still problematic)
-
304259 support Darwin 12 (Mac OS 10.8, Mountain Lion)
Canonical OSX 10.8
@@ -79,9 +79,6 @@
probably related to 301281 et al
QUERIED
-304744 valgrind hangs on munmap()
- probably invalid
-
304832 ppc32: build failure
probably invalid
@@ -96,6 +93,7 @@
305957 m_debuginfo/d3basics.c:965 (vgModuleLocal_evaluate_GX):
Assertion 'aMin == (Addr)0' failed.
+ QUERIED -- no info so far
306004 Wishlist: port valgrind to sparc
@@ -109,31 +107,20 @@
306235 unhandled syscall: 429 (freebsd)
-306297 disInstr(thumb): unhandled instruction 0xE883 0x000C
-
306299 Internal error when running a winelib application
306310 3.8.0 release tarball missing some files
306340 parse_var_DIE confused by DWARF from clang-3.1
-306360 vex x86->IR: 0x66 0xF 0x3A 0x1
-
306535 massif: force dump result every X minutes
306587 data cache line size is 128 and instruction cache line size is 32
-306588 data cache line size is 128 and instruction cache line size is 32
-306590 not support e500v2 spe 0x216 command
+306590 not support e500v2 spe 0x216 command
-306612 RHEL 6 glibc-2.X default suppressions need /lib*/libc-*patterns
-
286864 strlen function redirection error
-306664 vex amd64->IR: 0x66 0xF 0x3A 0x62 0xD1 0x46 0x66 0xF
-
-306721 vex amd64->IR: 0xC5 0xFB 0x10 0x5 0x1B 0xE8 0x1 0x0
-
306783 Mips unhandled syscall : 4025 / 4079 / 4182
-- Mon 17 Sept 2012, 10 am
Modified: trunk/NEWS (+5 -0)
===================================================================
--- trunk/NEWS 2012-09-17 19:20:06 +01:00 (rev 12988)
+++ trunk/NEWS 2012-09-17 19:20:29 +01:00 (rev 12989)
@@ -56,8 +56,13 @@
n-i-bz m [381] exp-sgcheck's memcpy causes programs to segfault
n-i-bz m [381] volatile in stack check, re clang
n-i-bz m [381] Incorrect undef'dness prop for Iop_DPBtoBCD and Iop_BCDtoDPB
+306297 [381] disInstr(thumb): unhandled instruction 0xE883 0x000C
+306664 [381] vex amd64->IR: 0x66 0xF 0x3A 0x62 0xD1 0x46 0x66 0xF
+304035 [381] disInstr(arm): unhandled instruction 0xE1023053
+306612 [381] RHEL 6 glibc-2.X default suppressions need /lib*/libc-*patterns
+
Release 3.8.0 (10 August 2012)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3.8.0 is a feature release with many improvements and the usual
|
|
From: <sv...@va...> - 2012-09-17 18:16:57
|
sewardj 2012-09-17 19:20:06 +0100 (Mon, 17 Sep 2012)
New Revision: 12988
Log:
Fix inconsistent comment (== BRANCH_3_8 r12987)
Modified files:
trunk/README.android
Modified: trunk/README.android (+0 -1)
===================================================================
--- trunk/README.android 2012-09-17 19:18:33 +01:00 (rev 12987)
+++ trunk/README.android 2012-09-17 19:20:06 +01:00 (rev 12988)
@@ -79,7 +79,6 @@
# The below re-generates configure, Makefiles, ...
# This is not needed if you start from a release tarball.
-# (in any case, the release tarball does not contain the autogen.sh file).
./autogen.sh
# for ARM
|
|
From: <sv...@va...> - 2012-09-17 18:15:23
|
sewardj 2012-09-17 19:18:33 +0100 (Mon, 17 Sep 2012)
New Revision: 12987
Log:
Fix now-inconsistent comment.
Modified files:
branches/VALGRIND_3_8_BRANCH/README.android
Property changed: branches/VALGRIND_3_8_BRANCH/README.android (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN/README.android:12477-12516
/trunk/README.android:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964
+ /branches/TCHAIN/README.android:12477-12516
/trunk/README.android:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964,12980,12982
Modified: branches/VALGRIND_3_8_BRANCH/README.android (+0 -1)
===================================================================
--- branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 19:11:28 +01:00 (rev 12986)
+++ branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 19:18:33 +01:00 (rev 12987)
@@ -79,7 +79,6 @@
# The below re-generates configure, Makefiles, ...
# This is not needed if you start from a release tarball.
-# (in any case, the release tarball does not contain the autogen.sh file).
./autogen.sh
# for ARM
|
|
From: Julian S. <js...@ac...> - 2012-09-17 18:13:22
|
> So why are we adding autogen.sh to the tar ball at the same time as > adding this comment? Yeah, that's kinda stupid. I'll fix the comment. > Certainly in normal autotools use it shouldn't be in the release tar > ball and users shouldn't need to run it. Indeed. But it could be argued that it is nice if users can rebuild the tarball from the tarball (so to speak) if they want, for whatever reason. So I'm inclined to leave autogen.sh in there, unless there's some reason why it's a bad idea. J |
|
From: <sv...@va...> - 2012-09-17 18:08:19
|
sewardj 2012-09-17 19:11:28 +0100 (Mon, 17 Sep 2012)
New Revision: 12986
Log:
Merge from trunk, r12980 (Add support for: uqsub16 shadd16 uhsub8
uhsub16, #304035, valgrind side).
Modified files:
branches/VALGRIND_3_8_BRANCH/memcheck/mc_translate.c
Modified: branches/VALGRIND_3_8_BRANCH/memcheck/mc_translate.c (+1 -0)
===================================================================
--- branches/VALGRIND_3_8_BRANCH/memcheck/mc_translate.c 2012-09-17 19:02:38 +01:00 (rev 12985)
+++ branches/VALGRIND_3_8_BRANCH/memcheck/mc_translate.c 2012-09-17 19:11:28 +01:00 (rev 12986)
@@ -2554,6 +2554,7 @@
case Iop_HSub16Sx2:
case Iop_QAdd16Sx2:
case Iop_QSub16Sx2:
+ case Iop_QSub16Ux2:
return binary16Ix2(mce, vatom1, vatom2);
case Iop_Add8x4:
|
|
From: Tom H. <to...@co...> - 2012-09-17 18:07:59
|
On 17/09/12 18:47, sv...@va... wrote: > Modified: branches/VALGRIND_3_8_BRANCH/README.android (+3 -0) > =================================================================== > --- branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 18:17:00 +01:00 (rev 12983) > +++ branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 18:47:58 +01:00 (rev 12984) > @@ -77,6 +77,9 @@ > # different if /sdcard doesn't work on the device -- this is > # a known cause of difficulties. > > +# The below re-generates configure, Makefiles, ... > +# This is not needed if you start from a release tarball. > +# (in any case, the release tarball does not contain the autogen.sh file). > ./autogen.sh So why are we adding autogen.sh to the tar ball at the same time as adding this comment? Certainly in normal autotools use it shouldn't be in the release tar ball and users shouldn't need to run it. Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
|
From: <sv...@va...> - 2012-09-17 18:04:56
|
sewardj 2012-09-17 19:08:00 +0100 (Mon, 17 Sep 2012)
New Revision: 2537
Log:
Merge from trunk, r2533 (Add support for: uqsub16 shadd16 uhsub8
uhsub16, #304035, vex side).
Modified directories:
branches/VEX_3_8_BRANCH/
Modified files:
branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c
branches/VEX_3_8_BRANCH/priv/host_arm_isel.c
Modified: branches/VEX_3_8_BRANCH/
Modified: branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c (+180 -0)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c 2012-09-17 19:00:06 +01:00 (rev 2536)
+++ branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c 2012-09-17 19:08:00 +01:00 (rev 2537)
@@ -10490,6 +10490,186 @@
/* fall through */
}
+ /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF050) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_QSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uqsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF020) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,0,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HAdd16Sx2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("shadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(1,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub8Ux4, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
Modified: branches/VEX_3_8_BRANCH/priv/host_arm_isel.c (+2 -0)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/host_arm_isel.c 2012-09-17 19:00:06 +01:00 (rev 2536)
+++ branches/VEX_3_8_BRANCH/priv/host_arm_isel.c 2012-09-17 19:08:00 +01:00 (rev 2537)
@@ -1366,6 +1366,8 @@
fn = &h_generic_calc_QAdd32S; break;
case Iop_QSub32S:
fn = &h_generic_calc_QSub32S; break;
+ case Iop_QSub16Ux2:
+ fn = &h_generic_calc_QSub16Ux2; break;
default:
break;
}
Property changed: branches/VEX_3_8_BRANCH (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518,2531-2532
+ /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518,2531-2533
|
|
From: <sv...@va...> - 2012-09-17 17:59:28
|
sewardj 2012-09-17 19:02:38 +0100 (Mon, 17 Sep 2012)
New Revision: 12985
Log:
Merge from trunk, r12982 (Intercept __GI_memmove, #306612)
Modified files:
branches/VALGRIND_3_8_BRANCH/memcheck/mc_replace_strmem.c
Modified: branches/VALGRIND_3_8_BRANCH/memcheck/mc_replace_strmem.c (+1 -0)
===================================================================
--- branches/VALGRIND_3_8_BRANCH/memcheck/mc_replace_strmem.c 2012-09-17 18:47:58 +01:00 (rev 12984)
+++ branches/VALGRIND_3_8_BRANCH/memcheck/mc_replace_strmem.c 2012-09-17 19:02:38 +01:00 (rev 12985)
@@ -1020,6 +1020,7 @@
#if defined(VGO_linux)
MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+ MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove)
#elif defined(VGO_darwin)
# if DARWIN_VERS <= DARWIN_10_6
|
|
From: <sv...@va...> - 2012-09-17 17:56:57
|
sewardj 2012-09-17 19:00:06 +0100 (Mon, 17 Sep 2012)
New Revision: 2536
Log:
Merge from trunk, r2532 (AMD64: Fix PCMPxSTRx variant $0x46, #306664)
Modified directories:
branches/VEX_3_8_BRANCH/
Modified files:
branches/VEX_3_8_BRANCH/priv/guest_amd64_toIR.c
branches/VEX_3_8_BRANCH/priv/guest_generic_x87.c
Modified: branches/VEX_3_8_BRANCH/
Property changed: branches/VEX_3_8_BRANCH (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518,2531
+ /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518,2531-2532
Modified: branches/VEX_3_8_BRANCH/priv/guest_generic_x87.c (+41 -0)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/guest_generic_x87.c 2012-09-17 18:57:26 +01:00 (rev 2535)
+++ branches/VEX_3_8_BRANCH/priv/guest_generic_x87.c 2012-09-17 19:00:06 +01:00 (rev 2536)
@@ -798,6 +798,7 @@
case 0x00:
case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
default:
return False;
@@ -960,6 +961,46 @@
return True;
}
+ /*----------------------------------------*/
+ /*-- ranges, signed byte data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 2/*sb*/) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ Char* argL = (Char*)argLV;
+ Char* argR = (Char*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 16; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 16; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFFFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
return False;
}
Modified: branches/VEX_3_8_BRANCH/priv/guest_amd64_toIR.c (+1 -0)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/guest_amd64_toIR.c 2012-09-17 18:57:26 +01:00 (rev 2535)
+++ branches/VEX_3_8_BRANCH/priv/guest_amd64_toIR.c 2012-09-17 19:00:06 +01:00 (rev 2536)
@@ -16919,6 +16919,7 @@
case 0x00:
case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
case 0x01: // the 16-bit character versions of the above
case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
|
|
From: <sv...@va...> - 2012-09-17 17:54:17
|
sewardj 2012-09-17 18:57:26 +0100 (Mon, 17 Sep 2012)
New Revision: 2535
Log:
Merge from trunk, r2531 (ARM: STM<c>.W <Rn>{!}, <registers> too
strict, #306297)
Modified directories:
branches/VEX_3_8_BRANCH/
Modified files:
branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c
Modified: branches/VEX_3_8_BRANCH/
Property changed: branches/VEX_3_8_BRANCH (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518
+ /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518,2531
Modified: branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c (+0 -9)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c 2012-09-17 18:51:44 +01:00 (rev 2534)
+++ branches/VEX_3_8_BRANCH/priv/guest_arm_toIR.c 2012-09-17 18:57:26 +01:00 (rev 2535)
@@ -16399,15 +16399,6 @@
if (rN == 15) valid = False;
if (popcount32(regList) < 2) valid = False;
if (bW == 1 && (regList & (1<<rN))) valid = False;
- if (regList & (1<<rN)) {
- UInt i;
- /* if Rn is in the list, then it must be the
- lowest numbered entry */
- for (i = 0; i < rN; i++) {
- if (regList & (1<<i))
- valid = False;
- }
- }
}
if (valid) {
|
|
From: <sv...@va...> - 2012-09-17 17:48:35
|
sewardj 2012-09-17 18:51:44 +0100 (Mon, 17 Sep 2012)
New Revision: 2534
Log:
Merge from trunk, r2517 and 2518 (Fix a couple of union tag-vs-field
mixups, n-i-bz)
Modified directories:
branches/VEX_3_8_BRANCH/
Modified files:
branches/VEX_3_8_BRANCH/priv/host_s390_defs.c
branches/VEX_3_8_BRANCH/priv/host_s390_isel.c
Modified: branches/VEX_3_8_BRANCH/
Modified: branches/VEX_3_8_BRANCH/priv/host_s390_isel.c (+2 -2)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/host_s390_isel.c 2012-09-17 16:27:58 +01:00 (rev 2533)
+++ branches/VEX_3_8_BRANCH/priv/host_s390_isel.c 2012-09-17 18:51:44 +01:00 (rev 2534)
@@ -1635,7 +1635,7 @@
/* --------- UNARY OP --------- */
case Iex_Unop: {
- IRExpr *left = expr->Iex.Binop.arg1;
+ IRExpr *left = expr->Iex.Unop.arg;
s390_bfp_unop_t bfpop;
s390_round_t rounding_mode;
HReg op_hi, op_lo, op, f12, f13, f14, f15;
@@ -1646,7 +1646,7 @@
f14 = make_fpr(14);
f15 = make_fpr(15);
- switch (expr->Iex.Binop.op) {
+ switch (expr->Iex.Unop.op) {
case Iop_NegF128: bfpop = S390_BFP_NEG; goto float128_opnd;
case Iop_AbsF128: bfpop = S390_BFP_ABS; goto float128_opnd;
case Iop_I32StoF128: bfpop = S390_BFP_I32_TO_F128; goto convert_int;
Property changed: branches/VEX_3_8_BRANCH (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
- /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499
+ /branches/TCHAIN:2272-2295
/trunk:2469,2475-2480,2499,2517-2518
Modified: branches/VEX_3_8_BRANCH/priv/host_s390_defs.c (+1 -1)
===================================================================
--- branches/VEX_3_8_BRANCH/priv/host_s390_defs.c 2012-09-17 16:27:58 +01:00 (rev 2533)
+++ branches/VEX_3_8_BRANCH/priv/host_s390_defs.c 2012-09-17 18:51:44 +01:00 (rev 2534)
@@ -7372,7 +7372,7 @@
UInt r1 = hregNumber(insn->variant.bfp128_unop.dst_hi);
UInt r2_hi = hregNumber(insn->variant.bfp128_unop.op_hi);
UInt r2_lo = hregNumber(insn->variant.bfp128_unop.op_lo);
- s390_round_t rounding_mode = insn->variant.bfp_binop.rounding_mode;
+ s390_round_t rounding_mode = insn->variant.bfp128_unop.rounding_mode;
/* Paranoia */
vassert(insn->size != 16);
|
|
From: <sv...@va...> - 2012-09-17 17:44:49
|
sewardj 2012-09-17 18:47:58 +0100 (Mon, 17 Sep 2012)
New Revision: 12984
Log:
Merge from trunk, r12964 (partial) and r12983 (3.8.0 release tarball
missing some files, #306310).
Modified files:
branches/VALGRIND_3_8_BRANCH/Makefile.am
branches/VALGRIND_3_8_BRANCH/README.android
Property changed: branches/VALGRIND_3_8_BRANCH/README.android (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
+ /branches/TCHAIN/README.android:12477-12516
/trunk/README.android:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964
Modified: branches/VALGRIND_3_8_BRANCH/README.android (+3 -0)
===================================================================
--- branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 18:17:00 +01:00 (rev 12983)
+++ branches/VALGRIND_3_8_BRANCH/README.android 2012-09-17 18:47:58 +01:00 (rev 12984)
@@ -77,6 +77,9 @@
# different if /sdcard doesn't work on the device -- this is
# a known cause of difficulties.
+# The below re-generates configure, Makefiles, ...
+# This is not needed if you start from a release tarball.
+# (in any case, the release tarball does not contain the autogen.sh file).
./autogen.sh
# for ARM
Property changed: branches/VALGRIND_3_8_BRANCH/Makefile.am (+0 -0)
___________________________________________________________________
Name: svn:mergeinfo
+ /branches/TCHAIN/Makefile.am:12477-12516
/trunk/Makefile.am:12873,12878-12879,12885,12887,12891-12894,12897-12898,12923,12947,12964,12983
Modified: branches/VALGRIND_3_8_BRANCH/Makefile.am (+3 -1)
===================================================================
--- branches/VALGRIND_3_8_BRANCH/Makefile.am 2012-09-17 18:17:00 +01:00 (rev 12983)
+++ branches/VALGRIND_3_8_BRANCH/Makefile.am 2012-09-17 18:47:58 +01:00 (rev 12984)
@@ -99,11 +99,13 @@
README_MISSING_SYSCALL_OR_IOCTL \
README.s390 \
README.android \
+ README.android_emulator \
README.mips \
NEWS.old \
valgrind.pc.in \
valgrind.spec.in \
- valgrind.spec
+ valgrind.spec \
+ autogen.sh
dist_noinst_SCRIPTS = \
vg-in-place
|
|
From: <sv...@va...> - 2012-09-17 17:13:56
|
sewardj 2012-09-17 18:17:00 +0100 (Mon, 17 Sep 2012)
New Revision: 12983
Log:
Include autogen.sh in the tarfile. See #306310.
Modified files:
trunk/Makefile.am
Modified: trunk/Makefile.am (+2 -1)
===================================================================
--- trunk/Makefile.am 2012-09-17 16:44:15 +01:00 (rev 12982)
+++ trunk/Makefile.am 2012-09-17 18:17:00 +01:00 (rev 12983)
@@ -105,7 +105,8 @@
NEWS.old \
valgrind.pc.in \
valgrind.spec.in \
- valgrind.spec
+ valgrind.spec \
+ autogen.sh
dist_noinst_SCRIPTS = \
vg-in-place
|
|
From: <sv...@va...> - 2012-09-17 15:41:10
|
sewardj 2012-09-17 16:44:15 +0100 (Mon, 17 Sep 2012)
New Revision: 12982
Log:
Intercept __GI_memmove on Linux. Fixes #306612.
Modified files:
trunk/memcheck/mc_replace_strmem.c
Modified: trunk/memcheck/mc_replace_strmem.c (+1 -0)
===================================================================
--- trunk/memcheck/mc_replace_strmem.c 2012-09-17 16:29:53 +01:00 (rev 12981)
+++ trunk/memcheck/mc_replace_strmem.c 2012-09-17 16:44:15 +01:00 (rev 12982)
@@ -1020,6 +1020,7 @@
#if defined(VGO_linux)
MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+ MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove)
#elif defined(VGO_darwin)
# if DARWIN_VERS <= DARWIN_10_6
|
|
From: <sv...@va...> - 2012-09-17 15:26:51
|
sewardj 2012-09-17 16:29:53 +0100 (Mon, 17 Sep 2012)
New Revision: 12981
Log:
Add tests for: uqsub16 shadd16 uhsub8 uhsub16. See #304035.
Modified files:
trunk/none/tests/arm/v6media.c
trunk/none/tests/arm/v6media.stdout.exp
Modified: trunk/none/tests/arm/v6media.stdout.exp (+240 -0)
===================================================================
--- trunk/none/tests/arm/v6media.stdout.exp 2012-09-17 16:28:46 +01:00 (rev 12980)
+++ trunk/none/tests/arm/v6media.stdout.exp 2012-09-17 16:29:53 +01:00 (rev 12981)
@@ -3459,3 +3459,243 @@
qdsub r0, r1, r2 :: rd 0x4bbfa85f rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
qdsub r0, r1, r2 :: rd 0xe805dd64 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
qdsub r0, r1, r2 :: rd 0x1832d2e2 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+------------ UQSUB16 -----------------------------------
+uqsub16 r0, r1, r2 :: rd 0x0000fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x000f0000 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x0000000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0xff05fbf1 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00003299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x0000a51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x1e2e0000 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x72a40000 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00003f6a rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x4fa20000 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000bdd rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x02e00ee4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x49521d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x2f6e4f7e rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x5ff30000 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x48180000 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x091d815b rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00004213 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x378207c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x0000baee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x46ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x44be0000 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x56f59001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x29620000 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x10670000 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x2ccf41e6 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x19273080 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00006cc2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x3423a486 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00003743 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00007afa rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x0000b0f8 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x70c30000 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x34fa0000 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x36d35289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x9965947f rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00003add rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00001a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x27f10000 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x28470000 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x6b3c0000 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x000013e3 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x426415f1 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uqsub16 r0, r1, r2 :: rd 0x00000000 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+------------ SHADD16 -----------------------------------
+shadd16 r0, r1, r2 :: rd 0x00100001 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x00100001 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x00010010 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x00010010 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x00004000 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xbfffbfff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xc3071ea4 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xdfa25c8b rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x2f80d324 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xc8d014ce rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x1a19e6e0 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xf78011a7 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xd9c73cdd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x080ee7ea rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x06c2fde1 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xd0ac059a rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xdb4ea5c7 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3c4a09f2 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xb5a291cc rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x0cf8e3af rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe9aa4554 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x085dc98e rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xc1e6ffcd rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3c28257c rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xec463ee6 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe0c3e118 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3910c352 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x0083eb0b rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x4f531ee3 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x0a4cf680 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe21f244b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x117a69bc rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe6e4ff42 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe487f42f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xa9f00c4b rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xf8312a6f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x282428c4 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x6b014b1d rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe852e591 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3d241b03 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xf2acc179 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x0c5df486 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x357fda8e rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3c5bceec rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xbf6598a8 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x1a48fb28 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x49393caa rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x2afde6fe rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x45943f3a rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x08d69c45 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xe188b17f rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x963aa611 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x306948d3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xfd28066e rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0xeee51ce2 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+shadd16 r0, r1, r2 :: rd 0x0029edf1 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+------------ UHSUB8 -----------------------------------
+uhsub8 r0, r1, r2 :: rd 0x00f87f7e rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x00078082 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x80820007 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x7f7e00f8 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x3f7f3f7f rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xff7fc07f rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x40004000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xc080c080 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xf5fbbdb7 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xb5bf194c rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xfd86520f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x4607132e rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x0f17a1d6 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x3952f6d0 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xfc36f1e6 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x95d81f35 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x28d18cb9 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xcf51ce3f rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xeb3006ee rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x01f007f2 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x25a90e0f rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xf229f2f7 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x18b728bf rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x00ebd734 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x30f9bd30 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x240ce211 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x040e402d rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xde17f51e rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xccc7032a rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xfffc2109 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x1cc10363 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xb2fe5d77 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xdca4b3b5 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x23670132 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x22dff0c6 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x2bfa4800 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x143195df rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x08b3d2d0 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x16e721f3 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x0c1318c0 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xfc463661 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x1a1152c3 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xddf01ca1 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xcb083dfd rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xcc9358fc rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x38e1b3b7 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xca37f9e9 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x1afd95ff rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x1be92944 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x4c324abf rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xff4a1dee rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xa0460d2a rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x14f8db7b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x1423eeb2 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x369efbf0 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xf61a0af1 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0x21320bf8 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xdff8eafe rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub8 r0, r1, r2 :: rd 0xa110c142 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+------------ UHSUB16 -----------------------------------
+uhsub16 r0, r1, r2 :: rd 0xfff87ffe rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x00078002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x80020007 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x7ffefff8 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xffffc0ff rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x40004000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xf4fbbcb7 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xb4bf194c rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xfc86528f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x460713ae rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x0f17a156 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x3952f5d0 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xfc36f0e6 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x95581fb5 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x27d18c39 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xcf51ce3f rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xebb005ee rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x01700772 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x24a90e8f rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xf2a9f1f7 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x17b727bf rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xffebd734 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x2ff9bdb0 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x240ce211 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x048e40ad rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xde17f59e rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xcc4703aa rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xfefc2109 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x1bc103e3 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xb27e5d77 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xdc24b2b5 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x236701b2 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x225ff046 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x2b7a4800 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x14b1955f rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x0833d1d0 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x166720f3 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x0c931840 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xfc463661 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x1a115243 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xdcf01ba1 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xcb083d7d rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xcb93587c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x3861b337 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xca37f8e9 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x1a7d957f rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x1b692944 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x4cb24a3f rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xff4a1d6e rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xa0c60d2a rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x13f8db7b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x1423ee32 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x359efaf0 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xf69a09f1 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0x21320af8 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xdf78ea7e rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhsub16 r0, r1, r2 :: rd 0xa190c1c2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
Modified: trunk/none/tests/arm/v6media.c (+244 -0)
===================================================================
--- trunk/none/tests/arm/v6media.c 2012-09-17 16:28:46 +01:00 (rev 12980)
+++ trunk/none/tests/arm/v6media.c 2012-09-17 16:29:53 +01:00 (rev 12981)
@@ -4366,6 +4366,250 @@
TESTINST3("qdsub r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
TESTINST3("qdsub r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
+ printf("------------ UQSUB16 -----------------------------------\n");
+ TESTINST3("uqsub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0);
+ TESTINST3("uqsub16 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
+TESTINST3("uqsub16 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+
+ printf("------------ SHADD16 -----------------------------------\n");
+ TESTINST3("shadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("shadd16 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
+TESTINST3("shadd16 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+
+ printf("------------ UHSUB8 -----------------------------------\n");
+ TESTINST3("uhsub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhsub8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
+TESTINST3("uhsub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+
+ printf("------------ UHSUB16 -----------------------------------\n");
+ TESTINST3("uhsub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhsub16 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
+TESTINST3("uhsub16 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+
/*
TESTINST3("theinsn", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
TESTINST3("theinsn", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
|
|
From: <sv...@va...> - 2012-09-17 15:25:41
|
sewardj 2012-09-17 16:28:46 +0100 (Mon, 17 Sep 2012)
New Revision: 12980
Log:
Handle Iop_QSub16Ux2, needed in fix for #304035.
Modified files:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c (+1 -0)
===================================================================
--- trunk/memcheck/mc_translate.c 2012-09-17 14:43:57 +01:00 (rev 12979)
+++ trunk/memcheck/mc_translate.c 2012-09-17 16:28:46 +01:00 (rev 12980)
@@ -2554,6 +2554,7 @@
case Iop_HSub16Sx2:
case Iop_QAdd16Sx2:
case Iop_QSub16Sx2:
+ case Iop_QSub16Ux2:
return binary16Ix2(mce, vatom1, vatom2);
case Iop_Add8x4:
|
|
From: <sv...@va...> - 2012-09-17 15:24:54
|
sewardj 2012-09-17 16:27:58 +0100 (Mon, 17 Sep 2012)
New Revision: 2533
Log:
Add support for: uqsub16 shadd16 uhsub8 uhsub16. Fixes #304035.
Modified files:
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm_isel.c
Modified: trunk/priv/host_arm_isel.c (+2 -0)
===================================================================
--- trunk/priv/host_arm_isel.c 2012-09-17 14:40:11 +01:00 (rev 2532)
+++ trunk/priv/host_arm_isel.c 2012-09-17 16:27:58 +01:00 (rev 2533)
@@ -1366,6 +1366,8 @@
fn = &h_generic_calc_QAdd32S; break;
case Iop_QSub32S:
fn = &h_generic_calc_QSub32S; break;
+ case Iop_QSub16Ux2:
+ fn = &h_generic_calc_QSub16Ux2; break;
default:
break;
}
Modified: trunk/priv/guest_arm_toIR.c (+180 -0)
===================================================================
--- trunk/priv/guest_arm_toIR.c 2012-09-17 14:40:11 +01:00 (rev 2532)
+++ trunk/priv/guest_arm_toIR.c 2012-09-17 16:27:58 +01:00 (rev 2533)
@@ -10494,6 +10494,186 @@
/* fall through */
}
+ /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF050) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_QSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uqsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF020) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,0,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HAdd16Sx2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("shadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(1,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub8Ux4, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
|
|
From: <sv...@va...> - 2012-09-17 13:40:51
|
sewardj 2012-09-17 14:43:57 +0100 (Mon, 17 Sep 2012)
New Revision: 12979
Log:
Add test cases for PCMPxSTRx variant $0x46. See #306664.
Modified files:
trunk/none/tests/amd64/pcmpstr64.c
trunk/none/tests/amd64/pcmpstr64.stdout.exp
Modified: trunk/none/tests/amd64/pcmpstr64.stdout.exp (+28 -0)
===================================================================
--- trunk/none/tests/amd64/pcmpstr64.stdout.exp 2012-09-17 09:37:33 +01:00 (rev 12978)
+++ trunk/none/tests/amd64/pcmpstr64.stdout.exp 2012-09-17 14:43:57 +01:00 (rev 12979)
@@ -208,6 +208,10 @@
istri 44 123456789abcdef1 000000fecb975421 -> 0881000f 0881000f
istri 44 0123456789abcdef 00000000dca86532 -> 00c1000d 00c1000d
istri 44 123456789abcdef1 00000000dca86532 -> 0081000e 0081000e
+istri 44 163887ec041a9b72 fcd75adb9b3e895a -> 00410004 00410004
+istri 44 fc937cbfbf53f8e2 0d136bcb024d3fb7 -> 0081000d 0081000d
+istri 44 2ca34182c29a82ab 302ebd646775ab54 -> 0081000b 0081000b
+istri 44 3f2987608c11be6f a9ecb661f8e0a8cb -> 00c10007 00c10007
istri 00 abcdacbdabcdabcd 000000000000000a -> 00810003 00810003
istri 00 abcdabcdabcdabcd 000000000000000b -> 00810002 00810002
istri 00 abcdabcdabcdabcd 00000000000000ab -> 00810002 00810002
@@ -260,3 +264,27 @@
istri 38 0000000000000001 aaaaaaaa0aaaaaaa -> 08c10000 08c10000
istri 38 0000000000000000 aaaaaaaaaaaaaaaa -> 00400010 00400010
istri 38 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
+istri 46 aaaabbbbccccdddd 00000000000000bc -> 00800010 00800010
+istri 46 aaaabbbbccccdddd 00000000000000cb -> 0081000b 0081000b
+istri 46 baaabbbbccccdddd 00000000000000cb -> 0081000f 0081000f
+istri 46 baaabbbbccccdddc 00000000000000cb -> 0881000f 0881000f
+istri 46 bbbbbbbbbbbbbbbb 00000000000000cb -> 0881000f 0881000f
+istri 46 bbbbbbbb0bbbbbbb 00000000000000cb -> 08c10006 08c10006
+istri 46 bbbbbbbbbbbbbb0b 00000000000000cb -> 08c10000 08c10000
+istri 46 bbbbbbbbbbbbbbb0 00000000000000cb -> 00c00010 00c00010
+istri 46 0000000000000000 00000000000000cb -> 00c00010 00c00010
+istri 46 0000000000000000 0000000000000000 -> 00c00010 00c00010
+istri 46 bbbbbbbbbbbbbbbb 00000000000000cb -> 0881000f 0881000f
+istri 46 bbbbbbbbbbbbbbbb 000000000000000b -> 00800010 00800010
+istri 46 b4b4b4b4b4b4b4b4 00000000000062cb -> 0881000f 0881000f
+istri 46 b4b4b4b4b4b4b4b4 00000000000002cb -> 0081000f 0081000f
+istri 46 b4b4b4b4b4b4b4b4 00000000000000cb -> 0081000f 0081000f
+istri 46 b4b4b4b4b4b4b4b4 000000000000000b -> 00800010 00800010
+istri 46 0123456789abcdef 000000fecb975421 -> 08c1000e 08c1000e
+istri 46 123456789abcdef1 000000fecb975421 -> 0881000f 0881000f
+istri 46 0123456789abcdef 00000000dca86532 -> 00c1000d 00c1000d
+istri 46 123456789abcdef1 00000000dca86532 -> 0081000e 0081000e
+istri 46 163887ec041a9b72 fcd75adb9b3e895a -> 08410006 08410006
+istri 46 fc937cbfbf53f8e2 0d136bcb024d3fb7 -> 0881000f 0881000f
+istri 46 2ca34182c29a82ab 302ebd646775ab54 -> 0081000f 0081000f
+istri 46 3f2987608c11be6f a9ecb661f8e0a8cb -> 00c10007 00c10007
Modified: trunk/none/tests/amd64/pcmpstr64.c (+132 -1)
===================================================================
--- trunk/none/tests/amd64/pcmpstr64.c 2012-09-17 09:37:33 +01:00 (rev 12978)
+++ trunk/none/tests/amd64/pcmpstr64.c 2012-09-17 14:43:57 +01:00 (rev 12979)
@@ -10,6 +10,7 @@
typedef unsigned int UInt;
typedef signed int Int;
typedef unsigned char UChar;
+typedef signed char Char;
typedef unsigned long long int ULong;
typedef UChar Bool;
#define False ((Bool)0)
@@ -204,7 +205,7 @@
switch (imm8) {
case 0x00:
case 0x02: case 0x08: case 0x0C: case 0x12: case 0x1A:
- case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x38: case 0x3A: case 0x44: case 0x46: case 0x4A:
break;
default:
return False;
@@ -371,6 +372,47 @@
return True;
}
+ /*----------------------------------------*/
+ /*-- ranges, signed byte data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 2/*sb*/
+ && !isSTRM) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ Char* argL = (Char*)argLV;
+ Char* argR = (Char*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 16; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 16; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFFFF;
+
+ // generate I-format output
+ pcmpXstrX_WRK_gen_output_fmt_I(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx
+ );
+
+ return True;
+ }
+
return False;
}
@@ -1075,6 +1117,11 @@
try_istri(wot,h,s, "0123456789abcdef", "00000000dca86532");
try_istri(wot,h,s, "123456789abcdef1", "00000000dca86532");
+
+ try_istri(wot,h,s, "163887ec041a9b72", "fcd75adb9b3e895a");
+ try_istri(wot,h,s, "fc937cbfbf53f8e2", "0d136bcb024d3fb7");
+ try_istri(wot,h,s, "2ca34182c29a82ab", "302ebd646775ab54");
+ try_istri(wot,h,s, "3f2987608c11be6f", "a9ecb661f8e0a8cb");
}
@@ -1255,6 +1302,89 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_46 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_46 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x46, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_46 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x46, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_46 ( void )
+{
+ char* wot = "46";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_46;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_46;
+
+ try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000bc");
+ try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000cb");
+ try_istri(wot,h,s, "baaabbbbccccdddd", "00000000000000cb");
+ try_istri(wot,h,s, "baaabbbbccccdddc", "00000000000000cb");
+
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb");
+ try_istri(wot,h,s, "bbbbbbbb0bbbbbbb", "00000000000000cb");
+ try_istri(wot,h,s, "bbbbbbbbbbbbbb0b", "00000000000000cb");
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbb0", "00000000000000cb");
+ try_istri(wot,h,s, "0000000000000000", "00000000000000cb");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb");
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000000b");
+ try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000062cb");
+
+ try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000002cb");
+ try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000000cb");
+ try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "000000000000000b");
+
+ try_istri(wot,h,s, "0123456789abcdef", "000000fecb975421");
+ try_istri(wot,h,s, "123456789abcdef1", "000000fecb975421");
+
+ try_istri(wot,h,s, "0123456789abcdef", "00000000dca86532");
+ try_istri(wot,h,s, "123456789abcdef1", "00000000dca86532");
+
+ try_istri(wot,h,s, "163887ec041a9b72", "fcd75adb9b3e895a");
+ try_istri(wot,h,s, "fc937cbfbf53f8e2", "0d136bcb024d3fb7");
+ try_istri(wot,h,s, "2ca34182c29a82ab", "302ebd646775ab54");
+ try_istri(wot,h,s, "3f2987608c11be6f", "a9ecb661f8e0a8cb");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -1271,5 +1401,6 @@
istri_44();
istri_00();
istri_38();
+ istri_46();
return 0;
}
|
|
From: <sv...@va...> - 2012-09-17 13:37:08
|
sewardj 2012-09-17 14:40:11 +0100 (Mon, 17 Sep 2012)
New Revision: 2532
Log:
Fix PCMPxSTRx variant $0x46. Fixes #306664.
Modified files:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_generic_x87.c
Modified: trunk/priv/guest_amd64_toIR.c (+1 -0)
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2012-09-17 12:37:43 +01:00 (rev 2531)
+++ trunk/priv/guest_amd64_toIR.c 2012-09-17 14:40:11 +01:00 (rev 2532)
@@ -16919,6 +16919,7 @@
case 0x00:
case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
case 0x01: // the 16-bit character versions of the above
case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
Modified: trunk/priv/guest_generic_x87.c (+41 -0)
===================================================================
--- trunk/priv/guest_generic_x87.c 2012-09-17 12:37:43 +01:00 (rev 2531)
+++ trunk/priv/guest_generic_x87.c 2012-09-17 14:40:11 +01:00 (rev 2532)
@@ -798,6 +798,7 @@
case 0x00:
case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
default:
return False;
@@ -960,6 +961,46 @@
return True;
}
+ /*----------------------------------------*/
+ /*-- ranges, signed byte data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 2/*sb*/) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ Char* argL = (Char*)argLV;
+ Char* argR = (Char*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 16; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 16; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFFFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
return False;
}
|
|
From: Petar J. <mip...@gm...> - 2012-09-17 12:18:56
|
Hi everyone,
Loongson platform has some specifics which diverge from MIPS32 spec.
This mostly relates to usage of odd registers in FPU instructions, and thus
we should (mostly) avoid use of odd single precision FP registers for Loongson.
Thus, a fix (see down below) for this can be made in getAllocableRegs_MIPS.
It would be, however, nice to have that change conditional to Loongson platform,
but VexArchInfo is not available at that point.
So, does anybody think there is a clean way to get VexArchInfo at
getAllocableRegs_PLATFORM, or we should just apply the change to fit
Loongson in this case (we measured it, and no performance impact has been
seen on any of the benchmarks we ran)? Or this could be resolved differently?
Thanks for the feedback.
Petar
Index: VEX/priv/host_mips_defs.c
===================================================================
--- VEX/priv/host_mips_defs.c (revision 2491)
+++ VEX/priv/host_mips_defs.c (working copy)
@@ -552,9 +552,9 @@
void getAllocableRegs_MIPS(Int * nregs, HReg ** arr, Bool mode64)
{
if (mode64)
- *nregs = 27;
+ *nregs = 24;
else
- *nregs = 34;
+ *nregs = 29;
UInt i = 0;
*arr = LibVEX_Alloc(*nregs * sizeof(HReg));
@@ -595,16 +595,13 @@
// FP = frame pointer
// RA = link register
// + PC, HI and LO
+ (*arr)[i++] = hregMIPS_F16(mode64);
+ (*arr)[i++] = hregMIPS_F18(mode64);
(*arr)[i++] = hregMIPS_F20(mode64);
- (*arr)[i++] = hregMIPS_F21(mode64);
(*arr)[i++] = hregMIPS_F22(mode64);
- (*arr)[i++] = hregMIPS_F23(mode64);
(*arr)[i++] = hregMIPS_F24(mode64);
- (*arr)[i++] = hregMIPS_F25(mode64);
(*arr)[i++] = hregMIPS_F26(mode64);
- (*arr)[i++] = hregMIPS_F27(mode64);
(*arr)[i++] = hregMIPS_F28(mode64);
- (*arr)[i++] = hregMIPS_F29(mode64);
(*arr)[i++] = hregMIPS_F30(mode64);
if (!mode64) {
/* Fake double floating point */
@@ -616,8 +613,6 @@
(*arr)[i++] = hregMIPS_D5();
(*arr)[i++] = hregMIPS_D6();
(*arr)[i++] = hregMIPS_D7();
- (*arr)[i++] = hregMIPS_D8();
- (*arr)[i++] = hregMIPS_D9();
}
vassert(i == *nregs);
|