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From: Tom H. <th...@cy...> - 2011-04-28 02:54:02
|
Nightly build on vauxhall ( x86_64, Fedora 14 ) Started at 2011-04-28 03:20:04 BST Ended at 2011-04-28 03:53:40 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 569 tests, 4 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/linux/stack_switch (stderr) memcheck/tests/origin5-bz2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) drd/tests/pth_detached2 (stdout) exp-ptrcheck/tests/bad_percentify (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 569 tests, 4 stderr failures, 0 stdout failures, 0 post failures == memcheck/tests/linux/stack_switch (stderr) memcheck/tests/origin5-bz2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) exp-ptrcheck/tests/bad_percentify (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Thu Apr 28 03:36:35 2011 --- new.short Thu Apr 28 03:53:40 2011 *************** *** 8,10 **** ! == 569 tests, 4 stderr failures, 0 stdout failures, 0 post failures == memcheck/tests/linux/stack_switch (stderr) --- 8,10 ---- ! == 569 tests, 4 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/linux/stack_switch (stderr) *************** *** 12,13 **** --- 12,14 ---- helgrind/tests/tc06_two_races_xml (stderr) + drd/tests/pth_detached2 (stdout) exp-ptrcheck/tests/bad_percentify (stderr) |
|
From: Tom H. <th...@cy...> - 2011-04-28 02:39:22
|
Nightly build on mg ( x86_64, Fedora 9 ) Started at 2011-04-28 03:10:04 BST Ended at 2011-04-28 03:38:59 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 573 tests, 3 stderr failures, 4 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/amd64/sse4-64 (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc23_bogus_condwait (stderr) |
|
From: Florian K. <br...@ac...> - 2011-04-28 02:07:18
|
On 04/27/2011 08:19 PM, Maynard Johnson wrote:
> ------- host_ppc_isel.c ----------
> if (e->tag == Iex_Qop) {
> if (e->Iex.Qop.op == Iop_MAdd64Fx2) {
> HReg dst = iselVecExpr(env, e->Iex.Qop.arg2);
> HReg xA = iselVecExpr(env, e->Iex.Qop.arg3);
> HReg xB = iselVecExpr(env, e->Iex.Qop.arg4);
> set_FPU_rounding_mode( env, e->Iex.Qop.arg1 );
> addInstr(env, PPCInstr_VxQop(Pavfp_MADD, True, dst, xA, xB));
> return dst;
> }
> }
> ---------------------------------
I believe this is the culprit. Rewrite this like so:
HReg xT = iselVecExpr(env, e->Iex.Qop.arg2); /* I presume this is xT */
HReg xA = iselVecExpr(env, e->Iex.Qop.arg3);
HReg xB = iselVecExpr(env, e->Iex.Qop.arg4);
set_FPU_rounding_mode( env, e->Iex.Qop.arg1 );
dst = newVreg.... /* allocate a new Vreg here */
addInstr(env, /* copy contents of xT to dst */);
addInstr(env, PPCInstr_VxQop(Pavfp_MADD, True, dst, xA, xB));
return dst;
That should do the trick.
Florian
|
|
From: Maynard J. <may...@us...> - 2011-04-28 00:19:50
|
Julian Seward wrote:
> On Thursday, April 28, 2011, Florian Krohm wrote:
>> On 04/27/2011 06:40 PM, Maynard Johnson wrote:
>>> My "dst" register has the same value it did as when it was used as input.
>>
>> This sounds familiar. I think something like this happened to me once,
>> and the problem was in insn selection where my isel_int_expr_wrk was
>> returning a register that was modified before. And that's not allowed.
>> Perhaps that is what's happening. But I'm just guessing.
>
> Maynard needs to say whether he's talking about front end stuff
> (_toIR.c) or back end stuff (_isel.c). I can't guess from the
> original posting.
>
Here are some details to clarify the question . . .
In the frontend (guest_ppc_toIR.c):
---------------------
case 0x184: case 0x1A4: // xvmaddadp
{
DIP("xvmaddadp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
putVSReg( XT,
qop( Iop_MAdd64Fx2,
rm,
getVSReg( XT ),
getVSReg( XA ),
getVSReg( XB ) ) );
break;
}
---------------------
The new operation is a "Vector multiply add double precision". All three registers are vector regs, each holding two double precision floating point input values. The arithmetic that's done is (XA * XB) + XT. Special rules apply to both the intermediate and final results such that I can't simply break the vector registers in two and operate on the constituent FPs with Iop_MulF64 and Iop_AddF64. So I defined Iop_MAdd64Fx2 and implemented the backend for this new Iop. So the backend looks like this:
------- host_ppc_isel.c ----------
if (e->tag == Iex_Qop) {
if (e->Iex.Qop.op == Iop_MAdd64Fx2) {
HReg dst = iselVecExpr(env, e->Iex.Qop.arg2);
HReg xA = iselVecExpr(env, e->Iex.Qop.arg3);
HReg xB = iselVecExpr(env, e->Iex.Qop.arg4);
set_FPU_rounding_mode( env, e->Iex.Qop.arg1 );
addInstr(env, PPCInstr_VxQop(Pavfp_MADD, True, dst, xA, xB));
return dst;
}
}
---------------------------------
------- host_ppc_defs.c ----------
case Pin_VxQopFP: {
UInt v_dst = vregNo(i->Pin.VxQopFP.xT);
UInt v_srcL = vregNo(i->Pin.VxQopFP.xA);
UInt v_srcR = vregNo(i->Pin.VxQopFP.xB);
if (i->Pin.VxQopFP.op == Pavfp_MADD) {
if (i->Pin.VxQopFP.d_prec)
p = mkFormVX3( p, 60, v_dst, v_srcL, v_srcR, 97 );
}
goto done;
}
---------------------------------
NOTE: Not shown above, but I also updated the "mapRegs" and getRegUsage" functions of host_ppc_defs.c.
When my testcase executes the xvmaddadp insn and prints out the XT register, it has the same value as its input value versus the expected output value. I know the xvmaddadp insn is being executed because I ran the testcase under valgrind with ' --trace-notbelow' and '--trace-flags=10000001' to show assembly code, and I see the xvmaddadp.
So I'm obviously missing something, but I just can't see what. Hopefully this is enough detail that someone can point me in the right direction. Thanks in advance for any help!
-Maynard
> J
|
|
From: Julian S. <js...@ac...> - 2011-04-27 23:29:32
|
On Thursday, April 28, 2011, Florian Krohm wrote: > On 04/27/2011 06:40 PM, Maynard Johnson wrote: > > My "dst" register has the same value it did as when it was used as input. > > This sounds familiar. I think something like this happened to me once, > and the problem was in insn selection where my isel_int_expr_wrk was > returning a register that was modified before. And that's not allowed. > Perhaps that is what's happening. But I'm just guessing. Maynard needs to say whether he's talking about front end stuff (_toIR.c) or back end stuff (_isel.c). I can't guess from the original posting. J |
|
From: <sv...@va...> - 2011-04-27 23:25:22
|
Author: sewardj
Date: 2011-04-28 00:25:15 +0100 (Thu, 28 Apr 2011)
New Revision: 11715
Log:
Change the default (minimum) client malloc alignment from 8 to 16
on ppc32-linux. This is needed to make Altivec-using code work
correctly. Noticed when running ./auxprogs/gsl16test with gcc-4.6
with args -mcpu=970 -g -O3 -ftree-vectorize on Memcheck, in
which case a few of the tests failed because malloc() returns
8 byte aligned memory when it should return 16-aligned memory.
Modified:
trunk/coregrind/pub_core_mallocfree.h
Modified: trunk/coregrind/pub_core_mallocfree.h
===================================================================
--- trunk/coregrind/pub_core_mallocfree.h 2011-04-27 19:04:31 UTC (rev 11714)
+++ trunk/coregrind/pub_core_mallocfree.h 2011-04-27 23:25:15 UTC (rev 11715)
@@ -70,12 +70,14 @@
// minimum alignment. Must be a power of 2 greater than 4, and should be
// greater than 8.
#if defined(VGP_x86_linux) || \
- defined(VGP_ppc32_linux) || \
defined(VGP_arm_linux)
# define VG_MIN_MALLOC_SZB 8
// Nb: We always use 16 bytes for Darwin, even on 32-bits, so it can be used
// for any AltiVec- or SSE-related type. This matches the Darwin libc.
+// Also, use 16 bytes for any PPC variant, since 16 is required to make
+// Altiveccery work right.
#elif defined(VGP_amd64_linux) || \
+ defined(VGP_ppc32_linux) || \
defined(VGP_ppc64_linux) || \
defined(VGP_s390x_linux) || \
defined(VGP_ppc64_aix5) || \
|
|
From: Florian K. <br...@ac...> - 2011-04-27 23:21:11
|
On 04/27/2011 06:40 PM, Maynard Johnson wrote: > My "dst" register has the same value it did as when it was used as input. This sounds familiar. I think something like this happened to me once, and the problem was in insn selection where my isel_int_expr_wrk was returning a register that was modified before. And that's not allowed. Perhaps that is what's happening. But I'm just guessing. Florian |
|
From: Julian S. <js...@ac...> - 2011-04-27 23:04:06
|
> this "input/output type" of operation fails. My "dst" register has the > same value it did as when it was used as input. Is there a trick I'm > missing or is this concept not supported in VEX? Assuming you're referring to front end stuff, viz, how to translate the instruction into IR. Euh, the vast majority of x86 and x86_64 instructions have one of the register arguments as both input and output. So it's a supported concept. Imagine you have some 2-argument add instruction add r2, r5 meaning "r2 += r5" Then you'd generate IR like this (for ppc32) PUT(8) = Add32( GET(8), GET(20) ) No new Iops required. Iops seem completely unrelated to this discussion: they are just forms of math. What you appear to be talking about is simulation of guest register accesses, and that is done by IR Gets and Puts. J |
|
From: Maynard J. <may...@us...> - 2011-04-27 22:40:43
|
Hi, I'm implementing an instruction for a new IBM Power processor where one of the register arguments is used as both input and output. Having no straightforward way of implementing this instruction with existing emulation for the ppc64 architecture, I attempted to add a new Iop and associated cruf. I've added new Iops a few times before, so I *thought* I knew what I was doing. However, the end result of my attempt to support this "input/output type" of operation fails. My "dst" register has the same value it did as when it was used as input. Is there a trick I'm missing or is this concept not supported in VEX? Thanks. -Maynard |
|
From: Christian B. <bor...@de...> - 2011-04-27 20:31:12
|
Nightly build on fedora390 ( Fedora 13/14/15 mix with gcc 3.5.3 on z196 (s390x) ) Started at 2011-04-27 22:10:01 CEST Ended at 2011-04-27 22:30:26 CEST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 460 tests, 6 stderr failures, 0 stdout failures, 0 post failures == helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc23_bogus_condwait (stderr) drd/tests/tc04_free_lock (stderr) drd/tests/tc09_bad_unlock (stderr) drd/tests/tc23_bogus_condwait (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 459 tests, 6 stderr failures, 0 stdout failures, 0 post failures == helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc23_bogus_condwait (stderr) drd/tests/tc04_free_lock (stderr) drd/tests/tc09_bad_unlock (stderr) drd/tests/tc23_bogus_condwait (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Apr 27 22:20:09 2011 --- new.short Wed Apr 27 22:30:26 2011 *************** *** 8,10 **** ! == 459 tests, 6 stderr failures, 0 stdout failures, 0 post failures == helgrind/tests/tc06_two_races_xml (stderr) --- 8,10 ---- ! == 460 tests, 6 stderr failures, 0 stdout failures, 0 post failures == helgrind/tests/tc06_two_races_xml (stderr) |
|
From: Christian B. <bor...@de...> - 2011-04-27 20:30:10
|
Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP1 gcc 4.3.4 on z196 (s390x) ) Started at 2011-04-27 22:10:01 CEST Ended at 2011-04-27 22:30:02 CEST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 461 tests, 6 stderr failures, 0 stdout failures, 0 post failures == none/tests/faultstatus (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc23_bogus_condwait (stderr) drd/tests/tc04_free_lock (stderr) drd/tests/tc09_bad_unlock (stderr) drd/tests/tc23_bogus_condwait (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 460 tests, 6 stderr failures, 1 stdout failure, 0 post failures == none/tests/faultstatus (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc23_bogus_condwait (stderr) drd/tests/pth_detached2 (stdout) drd/tests/tc04_free_lock (stderr) drd/tests/tc09_bad_unlock (stderr) drd/tests/tc23_bogus_condwait (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Apr 27 22:19:57 2011 --- new.short Wed Apr 27 22:30:02 2011 *************** *** 8,10 **** ! == 460 tests, 6 stderr failures, 1 stdout failure, 0 post failures == none/tests/faultstatus (stderr) --- 8,10 ---- ! == 461 tests, 6 stderr failures, 0 stdout failures, 0 post failures == none/tests/faultstatus (stderr) *************** *** 12,14 **** helgrind/tests/tc23_bogus_condwait (stderr) - drd/tests/pth_detached2 (stdout) drd/tests/tc04_free_lock (stderr) --- 12,13 ---- |
|
From: <sv...@va...> - 2011-04-27 19:04:40
|
Author: rjwalsh
Date: 2011-04-27 20:04:31 +0100 (Wed, 27 Apr 2011)
New Revision: 11714
Log:
Fix no-arg ioctls on Darwin.
Modified:
trunk/coregrind/
trunk/coregrind/m_syswrap/syswrap-darwin.c
trunk/exp-dhat/
trunk/exp-ptrcheck/
Property changes on: trunk/coregrind
___________________________________________________________________
Name: svn:ignore
- *.a
*.dSYM
*.so
.deps
link_tool_exe_aix5
link_tool_exe_darwin
link_tool_exe_linux
Makefile
Makefile.in
no_op_client_for_valgrind
stage2
stage2.lds
valgrind
vgpreload_core-x86-darwin.so.dSYM
vg_intercept.c
vg_replace_malloc.c
vg_toolint.c
vg_toolint.h
+ *.a
*.dSYM
*.so
.deps
link_tool_exe_aix5
link_tool_exe_darwin
link_tool_exe_linux
Makefile
Makefile.in
no_op_client_for_valgrind
stage2
stage2.lds
valgrind
vgpreload_core-x86-darwin.so.dSYM
vg_intercept.c
vg_replace_malloc.c
vg_toolint.c
vg_toolint.h
fixup_macho_loadcmds
Modified: trunk/coregrind/m_syswrap/syswrap-darwin.c
===================================================================
--- trunk/coregrind/m_syswrap/syswrap-darwin.c 2011-04-27 12:00:51 UTC (rev 11713)
+++ trunk/coregrind/m_syswrap/syswrap-darwin.c 2011-04-27 19:04:31 UTC (rev 11714)
@@ -690,11 +690,25 @@
PRE(ioctl)
{
*flags |= SfMayBlock;
- PRINT("ioctl ( %ld, 0x%lx, %#lx )",ARG1,ARG2,ARG3);
- PRE_REG_READ3(long, "ioctl",
- unsigned int, fd, unsigned int, request, unsigned long, arg);
+ /* Handle ioctls that don't take an arg first */
switch (ARG2 /* request */) {
+ case VKI_TIOCSCTTY:
+ case VKI_TIOCEXCL:
+ case VKI_TIOCPTYGRANT:
+ case VKI_TIOCPTYUNLK:
+ case VKI_DTRACEHIOC_REMOVE:
+ PRINT("ioctl ( %ld, 0x%lx )",ARG1,ARG2);
+ PRE_REG_READ2(long, "ioctl",
+ unsigned int, fd, unsigned int, request);
+ return;
+ default:
+ PRINT("ioctl ( %ld, 0x%lx, %#lx )",ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "ioctl",
+ unsigned int, fd, unsigned int, request, unsigned long, arg);
+ }
+
+ switch (ARG2 /* request */) {
case VKI_TIOCGWINSZ:
PRE_MEM_WRITE( "ioctl(TIOCGWINSZ)", ARG3, sizeof(struct vki_winsize) );
break;
@@ -721,9 +735,6 @@
/* Set a process group ID? */
PRE_MEM_WRITE( "ioctl(TIOCGPGRP)", ARG3, sizeof(vki_pid_t) );
break;
- case VKI_TIOCSCTTY:
- /* Just takes an int value. */
- break;
case VKI_FIONBIO:
PRE_MEM_READ( "ioctl(FIONBIO)", ARG3, sizeof(int) );
break;
@@ -846,7 +857,6 @@
PRE_MEM_WRITE( "ioctl(FIONREAD)", ARG3, sizeof(int) );
break;
- case VKI_DTRACEHIOC_REMOVE:
case VKI_DTRACEHIOC_ADDDOF:
break;
@@ -866,9 +876,6 @@
case VKI_TIOCPTYGNAME:
PRE_MEM_WRITE( "ioctl(TIOCPTYGNAME)", ARG3, 128 );
break;
- case VKI_TIOCPTYGRANT:
- case VKI_TIOCPTYUNLK:
- break;
default:
ML_(PRE_unknown_ioctl)(tid, ARG2, ARG3);
Property changes on: trunk/exp-dhat
___________________________________________________________________
Name: svn:ignore
- *.dSYM
.deps
exp-dhat-*-darwin
exp-dhat-*-linux
Makefile
Makefile.in
vgpreload_exp-dhat-*-linux.so
+ *.dSYM
.deps
exp-dhat-*-darwin
exp-dhat-*-linux
Makefile
Makefile.in
vgpreload_exp-dhat-*-linux.so
vgpreload_exp-dhat-*-darwin.so
Property changes on: trunk/exp-ptrcheck
___________________________________________________________________
Name: svn:ignore
- *.dSYM
.deps
exp-ptrcheck-*-darwin
exp-ptrcheck-*-linux
Makefile
Makefile.in
preen_invars
vgpreload_exp-ptrcheck-*-linux.so
vgpreload_exp-ptrcheck-x86-darwin.so
vgpreload_exp-ptrcheck-x86-darwin.so.dSYM
+ *.dSYM
.deps
exp-ptrcheck-*-darwin
exp-ptrcheck-*-linux
Makefile
Makefile.in
preen_invars
vgpreload_exp-ptrcheck-*-linux.so
vgpreload_exp-ptrcheck-*-darwin.so
vgpreload_exp-ptrcheck-*-darwin.so.dSYM
|
|
From: <sv...@va...> - 2011-04-27 12:07:12
|
Author: sewardj
Date: 2011-04-27 13:07:01 +0100 (Wed, 27 Apr 2011)
New Revision: 2132
Log:
s390x: invalid use of R0 as base register
When emitting code for a shift operation with the shift amount operand being in
memory we load the shift amount into R0 and use that register in SLAG etc..
That won't work because the contents of R0 will be ignored when used as a base
reg.
So, let's choose some other register and save/restore it.
Fixes #270959. (Florian Krohm, br...@ac...)
Modified:
trunk/priv/host_s390_defs.c
Modified: trunk/priv/host_s390_defs.c
===================================================================
--- trunk/priv/host_s390_defs.c 2011-04-27 11:58:22 UTC (rev 2131)
+++ trunk/priv/host_s390_defs.c 2011-04-27 12:07:01 UTC (rev 2132)
@@ -5208,30 +5208,56 @@
d = src->d;
/* Shift operands are special here as there are no opcodes that
- allow a memory operand. So we first load the 2nd operand to R0. */
+ allow a memory operand. So we first load the 2nd operand into
+ some register. R0 is used to save restore the contents of the
+ chosen register.. */
- /* fixs390: NO. Using R0 as the base will ignore the register contents. */
if (insn->variant.alu.tag == S390_ALU_LSH ||
insn->variant.alu.tag == S390_ALU_RSH ||
insn->variant.alu.tag == S390_ALU_RSHA) {
+ UInt b2;
- buf = s390_emit_load_mem(buf, insn->size, R0, src);
+ /* Choose a register (other than DST or R0) into which to stick the
+ shift amount. The following works because r15 is reserved and
+ thusly dst != 15. */
+ vassert(dst != 15); /* extra paranoia */
+ b2 = (dst + 1) % 16;
+
+ buf = s390_emit_LGR(buf, R0, b2); /* save */
+ /* Loading SRC to B2 does not modify R0. */
+ buf = s390_emit_load_mem(buf, insn->size, b2, src);
+
if (insn->size == 8) {
- if (insn->variant.alu.tag == S390_ALU_LSH)
- return s390_emit_SLLG(buf, dst, dst, R0, DISP20(0));
- if (insn->variant.alu.tag == S390_ALU_RSH)
- return s390_emit_SRLG(buf, dst, dst, R0, DISP20(0));
- if (insn->variant.alu.tag == S390_ALU_RSHA)
- return s390_emit_SRAG(buf, dst, dst, R0, DISP20(0));
+ switch (insn->variant.alu.tag) {
+ case S390_ALU_LSH:
+ buf = s390_emit_SLLG(buf, dst, dst, b2, DISP20(0));
+ break;
+ case S390_ALU_RSH:
+ buf = s390_emit_SRLG(buf, dst, dst, b2, DISP20(0));
+ break;
+ case S390_ALU_RSHA:
+ buf = s390_emit_SRAG(buf, dst, dst, b2, DISP20(0));
+ break;
+ default: /* unreachable */
+ goto fail;
+ }
} else {
- if (insn->variant.alu.tag == S390_ALU_LSH)
- return s390_emit_SLL(buf, dst, R0, 0);
- if (insn->variant.alu.tag == S390_ALU_RSH)
- return s390_emit_SRL(buf, dst, R0, 0);
- if (insn->variant.alu.tag == S390_ALU_RSHA)
- return s390_emit_SRA(buf, dst, R0, 0);
+ switch (insn->variant.alu.tag) {
+ case S390_ALU_LSH:
+ buf = s390_emit_SLL(buf, dst, b2, 0);
+ break;
+ case S390_ALU_RSH:
+ buf = s390_emit_SRL(buf, dst, b2, 0);
+ break;
+ case S390_ALU_RSHA:
+ buf = s390_emit_SRA(buf, dst, b2, 0);
+ break;
+ default: /* unreachable */
+ goto fail;
+ }
}
+ return s390_emit_LGR(buf, b2, R0); /* restore */
}
switch (insn->size) {
|
|
From: <sv...@va...> - 2011-04-27 12:01:02
|
Author: sewardj
Date: 2011-04-27 13:00:51 +0100 (Wed, 27 Apr 2011)
New Revision: 11713
Log:
s390x: fpr - gpr transfer facility -- valgrind side fixes,
and test cases. Fixes #268619.
(Florian Krohm, br...@ac...)
Added:
trunk/none/tests/s390x/fgx.c
trunk/none/tests/s390x/fgx.stderr.exp
trunk/none/tests/s390x/fgx.stdout.exp
trunk/none/tests/s390x/fgx.vgtest
Modified:
trunk/coregrind/m_machine.c
trunk/none/tests/s390x/Makefile.am
Modified: trunk/coregrind/m_machine.c
===================================================================
--- trunk/coregrind/m_machine.c 2011-04-27 11:33:44 UTC (rev 11712)
+++ trunk/coregrind/m_machine.c 2011-04-27 12:00:51 UTC (rev 11713)
@@ -1000,7 +1000,7 @@
vki_sigaction_fromK_t saved_sigill_act;
vki_sigaction_toK_t tmp_sigill_act;
- volatile Bool have_LDISP, have_EIMM, have_GIE, have_DFP;
+ volatile Bool have_LDISP, have_EIMM, have_GIE, have_DFP, have_FGX;
Int r, model;
/* Unblock SIGILL and stash away the old action for that signal */
@@ -1061,6 +1061,13 @@
: : : "r0", "cc", "memory"); /* adtr r0,r0,r0 */
}
+ have_FGX = True;
+ if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
+ have_FGX = False;
+ } else {
+ __asm__ __volatile__(".long 0xb3cd0000" : : : "r0"); /* lgdr r0,f0 */
+ }
+
/* Restore signals */
r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
vg_assert(r == 0);
@@ -1070,8 +1077,9 @@
model = VG_(get_machine_model)();
- VG_(debugLog)(1, "machine", "machine %d LDISP %d EIMM %d GIE %d DFP %d\n",
- model, have_LDISP, have_EIMM, have_GIE, have_DFP);
+ VG_(debugLog)(1, "machine", "machine %d LDISP %d EIMM %d GIE %d DFP %d "
+ "FGX %d\n", model, have_LDISP, have_EIMM, have_GIE,
+ have_DFP, have_FGX);
if (model == VEX_S390X_MODEL_INVALID) return False;
@@ -1085,6 +1093,7 @@
if (have_EIMM) vai.hwcaps |= VEX_HWCAPS_S390X_EIMM;
if (have_GIE) vai.hwcaps |= VEX_HWCAPS_S390X_GIE;
if (have_DFP) vai.hwcaps |= VEX_HWCAPS_S390X_DFP;
+ if (have_FGX) vai.hwcaps |= VEX_HWCAPS_S390X_FGX;
VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps);
Modified: trunk/none/tests/s390x/Makefile.am
===================================================================
--- trunk/none/tests/s390x/Makefile.am 2011-04-27 11:33:44 UTC (rev 11712)
+++ trunk/none/tests/s390x/Makefile.am 2011-04-27 12:00:51 UTC (rev 11713)
@@ -5,7 +5,7 @@
INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
and or xor insert div srst fold_And16 flogr sub_EI add_EI \
and_EI or_EI xor_EI insert_EI mul_GE add_GE condloadstore \
- op_exception
+ op_exception fgx
check_PROGRAMS = $(INSN_TESTS) \
ex_sig \
Added: trunk/none/tests/s390x/fgx.c
===================================================================
--- trunk/none/tests/s390x/fgx.c (rev 0)
+++ trunk/none/tests/s390x/fgx.c 2011-04-27 12:00:51 UTC (rev 11713)
@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include "opcodes.h"
+
+int main()
+{
+ register long g asm("r7");
+ register double f asm("f8");
+ double f1;
+
+ memset(&f1, 0x0f, sizeof(double));
+ f = f1;
+ g = 42;
+ printf("test LGDR\n\n");
+ printf("before g = %ld\n", g);
+ printf("before f = %a\n", f);
+ printf("copy f to g\n");
+ asm volatile ( LGDR(7,8) : "=d"(g) : "f"(f));
+ printf("after g = %16.16lx\n", g); /* 0x0x0x0...... */
+ printf("after f = %a\n", f);
+
+ printf("\ntest LDGR\n\n");
+ f = 3.14;
+ printf("before g = %16.16lx\n", g); /* 0x0x0x0...... */
+ printf("before f = %a\n", f);
+ printf("copy g to f\n");
+ asm volatile ( LDGR(8,7) : "=f"(f) : "d"(g));
+ printf("after g = %16.16lx\n", g); /* 0x0x0x0...... */
+ printf("after f = %a\n", f);
+
+ return 0;
+}
+
Added: trunk/none/tests/s390x/fgx.stderr.exp
===================================================================
--- trunk/none/tests/s390x/fgx.stderr.exp (rev 0)
+++ trunk/none/tests/s390x/fgx.stderr.exp 2011-04-27 12:00:51 UTC (rev 11713)
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/s390x/fgx.stdout.exp
===================================================================
--- trunk/none/tests/s390x/fgx.stdout.exp (rev 0)
+++ trunk/none/tests/s390x/fgx.stdout.exp 2011-04-27 12:00:51 UTC (rev 11713)
@@ -0,0 +1,15 @@
+test LGDR
+
+before g = 42
+before f = 0x1.f0f0f0f0f0f0fp-783
+copy f to g
+after g = 0f0f0f0f0f0f0f0f
+after f = 0x1.f0f0f0f0f0f0fp-783
+
+test LDGR
+
+before g = 0f0f0f0f0f0f0f0f
+before f = 0x1.91eb851eb851fp+1
+copy g to f
+after g = 0f0f0f0f0f0f0f0f
+after f = 0x1.f0f0f0f0f0f0fp-783
Added: trunk/none/tests/s390x/fgx.vgtest
===================================================================
--- trunk/none/tests/s390x/fgx.vgtest (rev 0)
+++ trunk/none/tests/s390x/fgx.vgtest 2011-04-27 12:00:51 UTC (rev 11713)
@@ -0,0 +1 @@
+prog: fgx
|
|
From: <sv...@va...> - 2011-04-27 11:58:33
|
Author: sewardj
Date: 2011-04-27 12:58:22 +0100 (Wed, 27 Apr 2011)
New Revision: 2131
Log:
s390x: fpr - gpr transfer facility
We need to introduce a new hwcap to model the presence of the fpr - gpr
transfer facility. If it is not available, we cannot use the LDGR and LGDR
insns and need to use a trick similar to what ppc does (write/read stack
location).
Fixes #268619 (vex side).
(Florian Krohm, br...@ac...)
Modified:
trunk/priv/host_s390_defs.c
trunk/priv/host_s390_defs.h
trunk/priv/main_main.c
trunk/pub/libvex.h
Modified: trunk/priv/host_s390_defs.c
===================================================================
--- trunk/priv/host_s390_defs.c 2011-04-27 10:07:42 UTC (rev 2130)
+++ trunk/priv/host_s390_defs.c 2011-04-27 11:58:22 UTC (rev 2131)
@@ -2794,7 +2794,8 @@
static UChar *
s390_emit_LDGR(UChar *p, UChar r1, UChar r2)
{
- /* fixs390: PR 268619 */
+ vassert(s390_host_has_fgx);
+
if (unlikely(vex_traceflags & VEX_TRACE_ASM))
s390_disasm(ENC3(MNM, FPR, GPR), "ldgr", r1, r2);
@@ -2805,7 +2806,8 @@
static UChar *
s390_emit_LGDR(UChar *p, UChar r1, UChar r2)
{
- /* fixs390: PR 268619 */
+ vassert(s390_host_has_fgx);
+
if (unlikely(vex_traceflags & VEX_TRACE_ASM))
s390_disasm(ENC3(MNM, GPR, FPR), "lgdr", r1, r2);
@@ -3875,6 +3877,55 @@
return s390_emit_CLR(p, r1, R0);
}
+
+static UChar *
+s390_emit_LGDRw(UChar *p, UChar r1, UChar r2)
+{
+ if (s390_host_has_fgx) {
+ return s390_emit_LGDR(p, r1, r2);
+ }
+
+ /* Store the FPR at memory[sp - 8]. This is safe because SP grows towards
+ smaller addresses and is 8-byte aligned. Then load the GPR from that
+ memory location/ */
+ if (s390_host_has_ldisp) {
+ p = s390_emit_STDY(p, r2, R0, S390_REGNO_STACK_POINTER, DISP20(-8));
+ return s390_emit_LG(p, r1, R0, S390_REGNO_STACK_POINTER, DISP20(-8));
+ }
+
+ /* No long displacement. Need to adjust SP explicitly as to avoid negative
+ displacements. */
+ p = s390_emit_AGHI(p, S390_REGNO_STACK_POINTER, -8);
+ p = s390_emit_STD(p, r2, R0, S390_REGNO_STACK_POINTER, 0);
+ p = s390_emit_LG(p, r1, R0, S390_REGNO_STACK_POINTER, DISP20(0));
+ return s390_emit_AGHI(p, S390_REGNO_STACK_POINTER, 8);
+}
+
+
+static UChar *
+s390_emit_LDGRw(UChar *p, UChar r1, UChar r2)
+{
+ if (s390_host_has_fgx) {
+ return s390_emit_LDGR(p, r1, r2);
+ }
+
+ /* Store the GPR at memory[sp - 8]. This is safe because SP grows towards
+ smaller addresses and is 8-byte aligned. Then load the FPR from that
+ memory location/ */
+ if (s390_host_has_ldisp) {
+ p = s390_emit_STG(p, r2, R0, S390_REGNO_STACK_POINTER, DISP20(-8));
+ return s390_emit_LDY(p, r1, R0, S390_REGNO_STACK_POINTER, DISP20(-8));
+ }
+
+ /* No long displacement. Need to adjust SP explicitly as to avoid negative
+ displacements. */
+ p = s390_emit_AGHI(p, S390_REGNO_STACK_POINTER, -8);
+ p = s390_emit_STG(p, r2, R0, S390_REGNO_STACK_POINTER, DISP20(0));
+ p = s390_emit_LD(p, r1, R0, S390_REGNO_STACK_POINTER, 0);
+ return s390_emit_AGHI(p, S390_REGNO_STACK_POINTER, 8);
+}
+
+
/* Split up a 20-bit displacement into its high and low piece
suitable for passing as function arguments */
#define DISP20(d) ((d) & 0xFFF), (((d) >> 12) & 0xFF)
@@ -5051,9 +5102,9 @@
return s390_emit_LDR(buf, dst, src);
} else {
if (dst_class == HRcFlt64 && src_class == HRcInt64)
- return s390_emit_LDGR(buf, dst, src); /* fixs390: PR 268619 */
+ return s390_emit_LDGRw(buf, dst, src);
if (dst_class == HRcInt64 && src_class == HRcFlt64)
- return s390_emit_LGDR(buf, dst, src); /* fixs390: PR 268619 */
+ return s390_emit_LGDRw(buf, dst, src);
/* A move between floating point registers and general purpose
registers of different size should never occur and indicates
an error elsewhere. */
Modified: trunk/priv/host_s390_defs.h
===================================================================
--- trunk/priv/host_s390_defs.h 2011-04-27 10:07:42 UTC (rev 2130)
+++ trunk/priv/host_s390_defs.h 2011-04-27 11:58:22 UTC (rev 2131)
@@ -491,6 +491,8 @@
(s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_GIE))
#define s390_host_has_dfp \
(s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_DFP))
+#define s390_host_has_fgx \
+ (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_FGX))
#endif /* ndef __VEX_HOST_S390_DEFS_H */
Modified: trunk/priv/main_main.c
===================================================================
--- trunk/priv/main_main.c 2011-04-27 10:07:42 UTC (rev 2130)
+++ trunk/priv/main_main.c 2011-04-27 11:58:22 UTC (rev 2131)
@@ -933,23 +933,38 @@
static HChar* show_hwcaps_s390x ( UInt hwcaps )
{
- const UInt LD = VEX_HWCAPS_S390X_LDISP;
- const UInt EI = VEX_HWCAPS_S390X_EIMM;
- const UInt GE = VEX_HWCAPS_S390X_GIE;
- const UInt DF = VEX_HWCAPS_S390X_DFP;
+ static const HChar prefix[] = "s390x";
+ static const HChar facilities[][6] = {
+ { "ldisp" },
+ { "eimm" },
+ { "gie" },
+ { "dfp" },
+ { "fgx" },
+ };
+ static HChar buf[sizeof facilities + sizeof prefix + 1];
+ static HChar *p;
+ if (buf[0] != '\0') return buf; /* already constructed */
+
hwcaps = VEX_HWCAPS_S390X(hwcaps);
- if (hwcaps == (LD)) return "s390x-ldisp";
- if (hwcaps == (LD|EI)) return "s390x-ldisp-eimm";
- if (hwcaps == (LD|GE)) return "s390x-ldisp-gie";
- if (hwcaps == (LD|DF)) return "s390x-ldisp-dfp";
- if (hwcaps == (LD|EI|GE)) return "s390x-ldisp-eimm-gie";
- if (hwcaps == (LD|EI|DF)) return "s390x-ldisp-eimm-dfp";
- if (hwcaps == (LD|GE|DF)) return "s390x-ldisp-gie-dfp";
- if (hwcaps == (LD|EI|GE|DF)) return "s390x-ldisp-eimm-gie-dfp";
+ p = buf + vex_sprintf(buf, "%s", prefix);
+ if (hwcaps & VEX_HWCAPS_S390X_LDISP)
+ p = p + vex_sprintf(p, "-%s", facilities[0]);
+ if (hwcaps & VEX_HWCAPS_S390X_EIMM)
+ p = p + vex_sprintf(p, "-%s", facilities[1]);
+ if (hwcaps & VEX_HWCAPS_S390X_GIE)
+ p = p + vex_sprintf(p, "-%s", facilities[2]);
+ if (hwcaps & VEX_HWCAPS_S390X_DFP)
+ p = p + vex_sprintf(p, "-%s", facilities[3]);
+ if (hwcaps & VEX_HWCAPS_S390X_FGX)
+ p = p + vex_sprintf(p, "-%s", facilities[4]);
- return "s390-zarch";
+ /* If there are no facilities, add "zarch" */
+ if (hwcaps == 0)
+ vex_sprintf(p, "-%s", "zarch");
+
+ return buf;
}
/* ---- */
Modified: trunk/pub/libvex.h
===================================================================
--- trunk/pub/libvex.h 2011-04-27 10:07:42 UTC (rev 2130)
+++ trunk/pub/libvex.h 2011-04-27 11:58:22 UTC (rev 2131)
@@ -104,7 +104,8 @@
[24] Extended-immediate facility
[23] General-instruction-extension facility
[22] Decimal floating point facility
- [0:21] Currently unused; reserved for future use
+ [21] FPR-GR transfer facility
+ [0:20] Currently unused; reserved for future use
*/
/* Model numbers must be assigned in chronological order.
@@ -121,16 +122,18 @@
#define VEX_S390X_MODEL_INVALID 9
#define VEX_S390X_MODEL_MASK 0x3F
-#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
-#define VEX_HWCAPS_S390X_EIMM (1<<7) /* Extended-immediate facility */
-#define VEX_HWCAPS_S390X_GIE (1<<8) /* General-instruction-extension facility */
-#define VEX_HWCAPS_S390X_DFP (1<<9) /* Decimal floating point facility */
+#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
+#define VEX_HWCAPS_S390X_EIMM (1<<7) /* Extended-immediate facility */
+#define VEX_HWCAPS_S390X_GIE (1<<8) /* General-instruction-extension facility */
+#define VEX_HWCAPS_S390X_DFP (1<<9) /* Decimal floating point facility */
+#define VEX_HWCAPS_S390X_FGX (1<<10) /* FPR-GR transfer facility */
/* Special value representing all available s390x hwcaps */
#define VEX_HWCAPS_S390X_ALL (VEX_HWCAPS_S390X_LDISP | \
VEX_HWCAPS_S390X_EIMM | \
VEX_HWCAPS_S390X_GIE | \
- VEX_HWCAPS_S390X_DFP)
+ VEX_HWCAPS_S390X_DFP | \
+ VEX_HWCAPS_S390X_FGX)
#define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK)
#define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK)
|
|
From: <sv...@va...> - 2011-04-27 11:33:53
|
Author: sewardj
Date: 2011-04-27 12:33:44 +0100 (Wed, 27 Apr 2011)
New Revision: 11712
Log:
Fix bogus asm constraints in jm-insns.c. Fixes #263919.
(Maynard Johnson, may...@us...)
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
===================================================================
--- trunk/none/tests/ppc32/jm-insns.c 2011-04-27 11:11:22 UTC (rev 11711)
+++ trunk/none/tests/ppc32/jm-insns.c 2011-04-27 11:33:44 UTC (rev 11712)
@@ -6092,9 +6092,9 @@
volatile vector unsigned int v2 =
// (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF };
(vector unsigned int){ 0x01010101,0x01010101,0x01010101,0x01010101 };
- //__asm__ __volatile__ ("vcmpequw. 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets CR[6]
- //__asm__ __volatile__ ("vpkswss 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets VSCR[SAT]
- __asm__ __volatile__ ("vsubsbs 31,%0,%1" : : "vr" (v1), "vr" (v2)); // sets VSCR[SAT]
+ //__asm__ __volatile__ ("vcmpequw. 31,%0,%1" : : "v" (v1), "v" (v2)); // sets CR[6]
+ //__asm__ __volatile__ ("vpkswss 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
+ __asm__ __volatile__ ("vsubsbs 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
*/
//#define DEFAULT_VSCR 0x00010000
@@ -6123,11 +6123,11 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load input -> r14
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
// do stuff
(*func)();
@@ -6141,7 +6141,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
@@ -6184,12 +6184,12 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
// do stuff
(*func)();
@@ -6203,7 +6203,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
@@ -6252,13 +6252,13 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15,r16
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2));
- __asm__ __volatile__ ("vor 16,%0,%0" : : "vr" (vec_in3));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+ __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
// do stuff
(*func)();
@@ -6272,7 +6272,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
@@ -6326,12 +6326,12 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_shft));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_shft));
// do stuff
(*func)();
@@ -6345,7 +6345,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_shft;
@@ -6399,11 +6399,11 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load input -> r14
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
// do stuff
(*func)();
@@ -6417,7 +6417,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
dst = (unsigned int*)&vec_out;
@@ -6466,7 +6466,7 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// do stuff
@@ -6481,7 +6481,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
dst = (unsigned int*)&vec_out;
@@ -6528,12 +6528,12 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
// do stuff
(*func)();
@@ -6547,7 +6547,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
@@ -6599,7 +6599,7 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// do stuff
@@ -6614,7 +6614,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
dst = (unsigned int*)&vec_out;
@@ -6712,7 +6712,7 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// do stuff
@@ -6727,7 +6727,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
vec_in = (vector unsigned int)viargs[i];
src = (unsigned int*)&vec_in;
@@ -6798,11 +6798,11 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
// do stuff
(*func)();
@@ -6815,7 +6815,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
vec_out = (vector unsigned int)viargs_priv[i];
src = (unsigned int*)&vec_in;
@@ -6879,11 +6879,11 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load input -> r14
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
// do stuff
(*func)();
@@ -6897,7 +6897,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
@@ -6941,12 +6941,12 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
// do stuff
(*func)();
@@ -6960,7 +6960,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
@@ -7010,13 +7010,13 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load inputs -> r14,r15,r16
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in1));
- __asm__ __volatile__ ("vor 15,%0,%0" : : "vr" (vec_in2));
- __asm__ __volatile__ ("vor 16,%0,%0" : : "vr" (vec_in3));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+ __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
// do stuff
(*func)();
@@ -7030,7 +7030,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
@@ -7086,11 +7086,11 @@
// reset VSCR and CR
vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
flags = 0;
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (vscr) );
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
__asm__ __volatile__ ("mtcr %0" : : "r" (flags));
// load input -> r14
- __asm__ __volatile__ ("vor 14,%0,%0" : : "vr" (vec_in));
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
// do stuff
(*func)();
@@ -7104,7 +7104,7 @@
/* Restore flags */
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
- __asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
|
|
From: <sv...@va...> - 2011-04-27 11:11:34
|
Author: sewardj Date: 2011-04-27 12:11:22 +0100 (Wed, 27 Apr 2011) New Revision: 11711 Log: Add alternative expected output cases for more recent glibcs (eg, 2.12), which print a minus sign for NaNs. Fixes #262989. (Maynard Johnson, may...@us...) Added: trunk/none/tests/ppc32/jm-vmx.stdout.exp_Minus_nan trunk/none/tests/ppc32/test_fx.stdout.exp_Minus_nan trunk/none/tests/ppc32/test_gx.stdout.exp_Minus_nan trunk/none/tests/ppc64/jm-vmx.stdout.exp_Minus_nan Modified: trunk/none/tests/ppc32/Makefile.am trunk/none/tests/ppc64/Makefile.am [... diff too large to include ...] |
|
From: <sv...@va...> - 2011-04-27 10:07:50
|
Author: sewardj
Date: 2011-04-27 11:07:42 +0100 (Wed, 27 Apr 2011)
New Revision: 2130
Log:
Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back
ends. Partial fix for #270851.
Modified:
trunk/priv/guest_ppc_toIR.c
trunk/priv/host_ppc_isel.c
trunk/priv/ir_defs.c
Modified: trunk/priv/guest_ppc_toIR.c
===================================================================
--- trunk/priv/guest_ppc_toIR.c 2011-04-27 07:02:44 UTC (rev 2129)
+++ trunk/priv/guest_ppc_toIR.c 2011-04-27 10:07:42 UTC (rev 2130)
@@ -7256,7 +7256,7 @@
case 0x3Ce: // fcfidus (Float convert from unsigned DWord to single precision)
DIP("fcfidus%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr);
assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) );
- assign( frD, binop( Iop_I64UtoF32, rm, mkexpr( r_tmp64 ) ) );
+ assign( frD, unop( Iop_F32toF64, binop( Iop_I64UtoF32, rm, mkexpr( r_tmp64 ) ) ) );
goto putFR;
}
}
Modified: trunk/priv/host_ppc_isel.c
===================================================================
--- trunk/priv/host_ppc_isel.c 2011-04-27 07:02:44 UTC (rev 2129)
+++ trunk/priv/host_ppc_isel.c 2011-04-27 10:07:42 UTC (rev 2130)
@@ -3190,8 +3190,7 @@
return r_dst;
}
- if (e->Iex.Binop.op == Iop_I64StoF64 || e->Iex.Binop.op == Iop_I64UtoF64
- || e->Iex.Binop.op == Iop_I64UtoF32) {
+ if (e->Iex.Binop.op == Iop_I64StoF64 || e->Iex.Binop.op == Iop_I64UtoF64) {
if (mode64) {
HReg fdst = newVRegF(env);
HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2);
@@ -3206,8 +3205,8 @@
addInstr(env, PPCInstr_Store(8, zero_r1, isrc, True/*mode64*/));
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
- e->Iex.Binop.op == Iop_I64StoF64 ? True : False,
- e->Iex.Binop.op == Iop_I64UtoF32 ? False : True,
+ e->Iex.Binop.op == Iop_I64StoF64,
+ True/*fdst is 64 bit*/,
fdst, fdst));
add_to_sp( env, 16 );
@@ -3234,8 +3233,8 @@
addInstr(env, PPCInstr_Store(4, four_r1, isrcLo, False/*mode32*/));
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
- e->Iex.Binop.op == Iop_I64StoF64 ? True : False,
- e->Iex.Binop.op == Iop_I64UtoF32 ? False : True,
+ e->Iex.Binop.op == Iop_I64StoF64,
+ True/*fdst is 64 bit*/,
fdst, fdst));
add_to_sp( env, 16 );
Modified: trunk/priv/ir_defs.c
===================================================================
--- trunk/priv/ir_defs.c 2011-04-27 07:02:44 UTC (rev 2129)
+++ trunk/priv/ir_defs.c 2011-04-27 10:07:42 UTC (rev 2130)
@@ -2265,7 +2265,7 @@
case Iop_I32StoF64: UNARY(Ity_I32, Ity_F64);
case Iop_I64StoF64: BINARY(ity_RMode,Ity_I64, Ity_F64);
case Iop_I64UtoF64: BINARY(ity_RMode,Ity_I64, Ity_F64);
- case Iop_I64UtoF32: BINARY(ity_RMode,Ity_I64, Ity_F64);
+ case Iop_I64UtoF32: BINARY(ity_RMode,Ity_I64, Ity_F32);
case Iop_I32UtoF64: UNARY(Ity_I32, Ity_F64);
|
|
From: Bart V. A. <bva...@ac...> - 2011-04-27 08:23:36
|
Nightly build on cellbuzz-native ( cellbuzz, ppc64, Fedora 7, native ) Started at 2011-04-27 02:47:23 EDT Ended at 2011-04-27 04:23:24 EDT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 457 tests, 12 stderr failures, 9 stdout failures, 0 post failures == memcheck/tests/deep_templates (stdout) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) callgrind/tests/simwork-both (stdout) callgrind/tests/simwork-both (stderr) callgrind/tests/simwork-branch (stdout) callgrind/tests/simwork-branch (stderr) none/tests/empty-exe (stderr) none/tests/faultstatus (stderr) none/tests/linux/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/round (stdout) none/tests/ppc32/test_gx (stdout) none/tests/ppc64/jm-fp (stdout) none/tests/ppc64/round (stdout) none/tests/shell_valid2 (stderr) none/tests/shell_valid3 (stderr) none/tests/shell_zerolength (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc23_bogus_condwait (stderr) |
|
From: <sv...@va...> - 2011-04-27 08:09:45
|
Author: sewardj
Date: 2011-04-27 09:09:37 +0100 (Wed, 27 Apr 2011)
New Revision: 11710
Log:
Fix a bunch of printf format-string warnings when compiling this "-m64".
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
===================================================================
--- trunk/none/tests/ppc32/jm-insns.c 2011-04-26 10:23:54 UTC (rev 11709)
+++ trunk/none/tests/ppc32/jm-insns.c 2011-04-27 08:09:37 UTC (rev 11710)
@@ -181,7 +181,7 @@
#undef uint32_t
#undef uint64_t
#define uint32_t unsigned int
-#define uint64_t unsigned long long
+#define uint64_t unsigned long long int
#ifndef __powerpc64__
typedef uint32_t HWord_t;
@@ -4614,7 +4614,7 @@
#ifndef __powerpc64__
printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
#else
- printf("%s %016lx, %016lx, %016lx => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %016llx, %016llx => %016llx (%08x %08x)\n",
#endif
name, iargs[i], iargs[j], iargs[k], res, flags, xer);
}
@@ -4658,7 +4658,7 @@
printf("%s %08x, %08x => %08x (%08x %08x)\n",
#else
if (zap_hi32) res &= 0xFFFFFFFFULL;
- printf("%s %016lx, %016lx => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %016llx => %016llx (%08x %08x)\n",
#endif
name, iargs[i], iargs[j], res, flags, xer);
}
@@ -4690,7 +4690,7 @@
#ifndef __powerpc64__
printf("%s %08x => %08x (%08x %08x)\n",
#else
- printf("%s %016lx => %016lx (%08x %08x)\n",
+ printf("%s %016llx => %016llx (%08x %08x)\n",
#endif
name, iargs[i], res, flags, xer);
}
@@ -4790,7 +4790,7 @@
#ifndef __powerpc64__
printf("%s %08x, %08x => %08x (%08x %08x)\n",
#else
- printf("%s %016lx, %08x => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %08x => %016llx (%08x %08x)\n",
#endif
name, iargs[i], ii16[j], res, flags, xer);
}
@@ -4855,7 +4855,7 @@
#ifndef __powerpc64__
printf("%s %08x, %2d, %2d, %2d => %08x (%08x %08x)\n",
#else
- printf("%s %016lx, %2d, %2d, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %2d, %2d, %2d => %016llx (%08x %08x)\n",
#endif
name, iargs[i], j, k, l, res, flags, xer);
}
@@ -4896,7 +4896,7 @@
#ifndef __powerpc64__
printf("%s %08x, %08x, %2d, %2d => %08x (%08x %08x)\n",
#else
- printf("%s %016lx, %016lx, %2d, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %016llx, %2d, %2d => %016llx (%08x %08x)\n",
#endif
name, iargs[i], iargs[j], k, l, res, flags, xer);
}
@@ -4933,7 +4933,7 @@
#ifndef __powerpc64__
printf("%s %08x, %2d => %08x (%08x %08x)\n",
#else
- printf("%s %016lx, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
#endif
name, iargs[i], j, res, flags, xer);
}
@@ -4969,7 +4969,7 @@
#ifndef __powerpc64__
printf("%s %d, %d (%08x) => (%08x %08x)\n",
#else
- printf("%s %d, %d (%016lx) => (%08x %08x)\n",
+ printf("%s %d, %d (%016llx) => (%08x %08x)\n",
#endif
name, j, k, iargs[i], flags, xer);
}
@@ -5029,7 +5029,7 @@
#ifndef __powerpc64__
printf("%s (%08x) => %08x (%08x %08x)\n",
#else
- printf("%s (%016lx) => %016lx (%08x %08x)\n",
+ printf("%s (%016llx) => %016llx (%08x %08x)\n",
#endif
name, iargs[i], res, flags, xer);
}
@@ -5057,7 +5057,7 @@
#ifndef __powerpc64__
printf("%s 1 (%08x) -> mtxer -> mfxer => %08x\n",
#else
- printf("%s 1 (%08x) -> mtxer -> mfxer => %016lx\n",
+ printf("%s 1 (%08x) -> mtxer -> mfxer => %016llx\n",
#endif
name, j, res);
}
@@ -5074,7 +5074,7 @@
#ifndef __powerpc64__
printf("%s 8 (%08x) -> mtlr -> mflr => %08x\n",
#else
- printf("%s 8 (%08x) -> mtlr -> mflr => %016lx\n",
+ printf("%s 8 (%08x) -> mtlr -> mflr => %016llx\n",
#endif
name, j, res);
}
@@ -5091,7 +5091,7 @@
#ifndef __powerpc64__
printf("%s 9 (%08x) -> mtctr -> mfctr => %08x\n",
#else
- printf("%s 9 (%08x) -> mtctr -> mfctr => %016lx\n",
+ printf("%s 9 (%08x) -> mtctr -> mfctr => %016llx\n",
#endif
name, j, res);
}
@@ -5122,7 +5122,7 @@
#ifndef __powerpc64__
printf("%s %3d, %08x => (%08x %08x)\n",
#else
- printf("%s %3d, %016lx => (%08x %08x)\n",
+ printf("%s %3d, %016llx => (%08x %08x)\n",
#endif
name, j, iargs[i], flags, xer);
}
@@ -5163,7 +5163,7 @@
GET_CR_XER(flags,xer);
res = r17;
- printf("%s %016lx, %016lx, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %016llx, %2d => %016llx (%08x %08x)\n",
name, iargs[i], iargs[j], k, res, flags, xer);
}
if (verbose) printf("\n");
@@ -5198,7 +5198,7 @@
GET_CR_XER(flags,xer);
res = r17;
- printf("%s %016lx, %2d, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %2d, %2d => %016llx (%08x %08x)\n",
name, iargs[i], j, k, res, flags, xer);
}
if (verbose) printf("\n");
@@ -5231,7 +5231,7 @@
GET_CR_XER(flags,xer);
res = r17;
- printf("%s %016lx, %2d => %016lx (%08x %08x)\n",
+ printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
name, iargs[i], j, res, flags, xer);
}
if (verbose) printf("\n");
@@ -5446,7 +5446,7 @@
#ifndef __powerpc64__
printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
#else
- printf("%s %3d, (%016lx) => %016lx, %3ld (%08x %08x)\n",
+ printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
#endif
name, offs, iargs[i], res, r14-base, flags, xer);
}
@@ -5471,7 +5471,7 @@
#ifndef __powerpc64__
printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
#else
- printf("%s %3d, (%016lx) => %016lx, %3ld (%08x %08x)\n",
+ printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
#endif
name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer);
}
@@ -5500,7 +5500,7 @@
#ifndef __powerpc64__
printf("%s %d (%08x) => %08x, %d (%08x %08x)\n",
#else
- printf("%s %3d, (%016lx) => %016lx, %2ld (%08x %08x)\n",
+ printf("%s %3d, (%016llx) => %016llx, %2lld (%08x %08x)\n",
#endif
name, offs, iargs[i], res, r14-base, flags, xer);
}
@@ -5541,7 +5541,7 @@
#ifndef __powerpc64__
printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
#else
- printf("%s %016lx, %3d => %016lx, %3ld (%08x %08x)\n",
+ printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
#endif
name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
@@ -5569,7 +5569,7 @@
#ifndef __powerpc64__
printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
#else
- printf("%s %016lx, %3d => %016lx, %3ld (%08x %08x)\n",
+ printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
#endif
name, iargs[nb_iargs-1+i], offs, iargs_priv[nb_iargs-1+i],
r15-base, flags, xer);
@@ -5605,7 +5605,7 @@
#ifndef __powerpc64__
printf("%s %08x, %d => %08x, %d (%08x %08x)\n",
#else
- printf("%s %016lx, %3d => %016lx, %2ld (%08x %08x)\n",
+ printf("%s %016llx, %3d => %016llx, %2lld (%08x %08x)\n",
#endif
name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
@@ -5667,7 +5667,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %016llx, %016llx => %016llx",
#else
- printf("%s %016lx, %016lx, %016lx => %016lx",
+ printf("%s %016llx, %016llx, %016llx => %016llx",
#endif
name, u0, u1, u2, ur);
#if defined TEST_FLOAT_FLAGS
@@ -5705,7 +5705,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %016llx => %016llx",
#else
- printf("%s %016lx, %016lx => %016lx",
+ printf("%s %016llx, %016llx => %016llx",
#endif
name, u0, u1, ur);
#if defined TEST_FLOAT_FLAGS
@@ -5746,7 +5746,7 @@
#ifndef __powerpc64__
printf("%s %016llx => %016llx",
#else
- printf("%s %016lx => %016lx",
+ printf("%s %016llx => %016llx",
#endif
name, u0, ur);
#if defined TEST_FLOAT_FLAGS
@@ -5854,7 +5854,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %4d => %016llx, %4d",
#else
- printf("%s %016lx, %4d => %016lx, %4ld",
+ printf("%s %016llx, %4d => %016llx, %4lld",
#endif
name, double_to_bits(src), offs,
double_to_bits(res), r14-base);
@@ -5897,7 +5897,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %4d => %016llx, %4d",
#else
- printf("%s %016lx, %4ld => %016lx, %4ld",
+ printf("%s %016llx, %4lld => %016llx, %4lld",
#endif
name, double_to_bits(src), r15/*offs*/,
double_to_bits(res), r14-base);
@@ -5965,7 +5965,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %4d => %016llx, %4d",
#else
- printf("%s %016lx, %4d => %016lx, %4ld",
+ printf("%s %016llx, %4d => %016llx, %4lld",
#endif
name, double_to_bits(src), offs,
double_to_bits(*p_dst), r15-base);
@@ -6028,7 +6028,7 @@
#ifndef __powerpc64__
printf("%s %016llx, %4d => %016llx, %4d",
#else
- printf("%s %016lx, %4ld => %016lx, %4ld",
+ printf("%s %016llx, %4lld => %016llx, %4lld",
#endif
name, double_to_bits(src), r16/*offs*/,
double_to_bits(*p_dst), r15-base);
@@ -6043,7 +6043,7 @@
#ifndef __powerpc64__
printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
#else
- printf("%s %016lx (%014e), %4d => %016lx (%014e), %08x (%08x %08x)\n",
+ printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
#endif
name, double_to_bits(src), src, offs,
double_to_bits(*p_dst), *p_dst, r15, flags, xer);
@@ -6052,7 +6052,7 @@
#ifndef __powerpc64__
printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
#else
- printf("%s %016lx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
+ printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
#endif
name, double_to_bits(src), src, offs,
(uint32_t)(double_to_bits(*p_dst) >> 32),
|
|
From: <sv...@va...> - 2011-04-27 07:02:55
|
Author: sewardj
Date: 2011-04-27 08:02:44 +0100 (Wed, 27 Apr 2011)
New Revision: 2129
Log:
Fix up some enum confusion to do with ARMNeonUnOp and ARMNeonUnOpS, as
found by "the IBM checker", and also by clang-2.9. Fixes #271820.
(Florian Krohm, br...@ac...)
Modified:
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
Modified: trunk/priv/host_arm_defs.c
===================================================================
--- trunk/priv/host_arm_defs.c 2011-04-26 21:36:09 UTC (rev 2128)
+++ trunk/priv/host_arm_defs.c 2011-04-27 07:02:44 UTC (rev 2129)
@@ -1369,7 +1369,7 @@
return i;
}
-ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp op, ARMNRS* dst, ARMNRS* src,
+ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS op, ARMNRS* dst, ARMNRS* src,
UInt size, Bool Q ) {
ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
i->tag = ARMin_NUnaryS;
@@ -1799,8 +1799,8 @@
return;
case ARMin_NUnaryS:
vex_printf("%s%s%s ",
- showARMNeonUnOpS(i->ARMin.NUnary.op),
- showARMNeonUnOpSDataType(i->ARMin.NUnary.op),
+ showARMNeonUnOp(i->ARMin.NUnary.op),
+ showARMNeonUnOpDataType(i->ARMin.NUnary.op),
showARMNeonDataSize(i));
ppARMNRS(i->ARMin.NUnaryS.dst);
vex_printf(", ");
Modified: trunk/priv/host_arm_defs.h
===================================================================
--- trunk/priv/host_arm_defs.h 2011-04-26 21:36:09 UTC (rev 2128)
+++ trunk/priv/host_arm_defs.h 2011-04-27 07:02:44 UTC (rev 2129)
@@ -940,7 +940,7 @@
extern ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg, ARMAModeN* );
extern ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg, ARMAModeN* );
extern ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp, HReg, HReg, UInt, Bool );
-extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp, ARMNRS*, ARMNRS*,
+extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS, ARMNRS*, ARMNRS*,
UInt, Bool );
extern ARMInstr* ARMInstr_NDual ( ARMNeonDualOp, HReg, HReg, UInt, Bool );
extern ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp, HReg, HReg, HReg,
|
|
From: Manoj <man...@gm...> - 2011-04-27 03:38:05
|
Any plans to support MIPS in near future. TIA Manoj On Apr 27, 2011, at 8:40 AM, Florian Krohm <br...@ac...> wrote: > On 04/20/2011 06:12 AM, Julian Seward wrote: >> >> Greetings. >> >> It's time to think a bit about a 3.7.0 release. The following are >> proposals, for contemplation/discussion. >> > [snip] >> >> Other stuff that I forgot / missed? >> > > There were a few bug reports since 3.6.1 that we should take a look at > and possibly fix, time permitting. I remember at least the following > which are easy to reproduce and/or have testcases/patches: > > 269144 - missing "Bad option" error message > V fails to complain about the invalid option syntax and silently does > the wrong thing > > 267020 - hardwired directory name /tmp > > 270326 - valgrind segfault.. > > I'm going to triage these and perhaps some more that were opened since > 3.6.1. > > Florian > > ------------------------------------------------------------------------------ > WhatsUp Gold - Download Free Network Management Software > The most intuitive, comprehensive, and cost-effective network > management toolset available today. Delivers lowest initial > acquisition cost and overall TCO of any competing solution. > http://p.sf.net/sfu/whatsupgold-sd > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
|
From: Florian K. <br...@ac...> - 2011-04-27 03:10:27
|
On 04/20/2011 06:12 AM, Julian Seward wrote: > > Greetings. > > It's time to think a bit about a 3.7.0 release. The following are > proposals, for contemplation/discussion. > [snip] > > Other stuff that I forgot / missed? > There were a few bug reports since 3.6.1 that we should take a look at and possibly fix, time permitting. I remember at least the following which are easy to reproduce and/or have testcases/patches: 269144 - missing "Bad option" error message V fails to complain about the invalid option syntax and silently does the wrong thing 267020 - hardwired directory name /tmp 270326 - valgrind segfault.. I'm going to triage these and perhaps some more that were opened since 3.6.1. Florian |
|
From: Tom H. <th...@cy...> - 2011-04-27 02:55:09
|
Nightly build on vauxhall ( x86_64, Fedora 14 ) Started at 2011-04-27 03:20:05 BST Ended at 2011-04-27 03:54:48 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 569 tests, 4 stderr failures, 0 stdout failures, 0 post failures == memcheck/tests/linux/stack_switch (stderr) memcheck/tests/origin5-bz2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) exp-ptrcheck/tests/bad_percentify (stderr) |
|
From: Tom H. <th...@cy...> - 2011-04-27 02:47:03
|
Nightly build on mg ( x86_64, Fedora 9 ) Started at 2011-04-27 03:10:08 BST Ended at 2011-04-27 03:46:43 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 573 tests, 3 stderr failures, 4 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/amd64/sse4-64 (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc23_bogus_condwait (stderr) |