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From: <sv...@va...> - 2010-08-01 16:45:50
|
Author: sewardj
Date: 2010-08-01 17:45:42 +0100 (Sun, 01 Aug 2010)
New Revision: 1999
Log:
Support a couple more Thumb insns. Fix PC alignment problem for ADR.
Modified:
branches/THUMB/priv/guest_arm_toIR.c
Modified: branches/THUMB/priv/guest_arm_toIR.c
===================================================================
--- branches/THUMB/priv/guest_arm_toIR.c 2010-08-01 13:24:56 UTC (rev 1998)
+++ branches/THUMB/priv/guest_arm_toIR.c 2010-08-01 16:45:42 UTC (rev 1999)
@@ -6566,9 +6566,12 @@
case BITS5(1,0,1,0,0): {
/* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
/* a.k.a. ADR */
+ /* rD = align4(PC) + imm8 * 4 */
UInt rD = INSN0(10,8);
UInt imm8 = INSN0(7,0);
- putIRegT(rD, binop(Iop_Add32, getIRegT(15), mkU32(imm8 * 4)),
+ putIRegT(rD, binop(Iop_Add32,
+ binop(Iop_And32, getIRegT(15), mkU32(~3UL)),
+ mkU32(imm8 * 4)),
condT);
DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
goto decode_success;
@@ -7201,7 +7204,8 @@
if (INSN0(15,11) == BITS5(1,1,1,1,0)
&& ( INSN0(9,5) == BITS5(0,0,0,1,0) // ORR
|| INSN0(9,5) == BITS5(0,0,0,0,0) // AND
- || INSN0(9,5) == BITS5(0,0,0,0,1)) // BIC
+ || INSN0(9,5) == BITS5(0,0,0,0,1) // BIC
+ || INSN0(9,5) == BITS5(0,0,1,0,0)) // EOR
&& INSN1(15,15) == 0) {
UInt bS = INSN0(4,4);
UInt rN = INSN0(3,0);
@@ -7211,10 +7215,11 @@
IROp op = Iop_INVALID;
HChar* nm = "???";
switch (INSN0(9,5)) {
+ case BITS5(0,0,0,1,0): op = Iop_Or32; nm = "orr"; break;
case BITS5(0,0,0,0,0): op = Iop_And32; nm = "and"; break;
- case BITS5(0,0,0,1,0): op = Iop_Or32; nm = "orr"; break;
case BITS5(0,0,0,0,1): op = Iop_And32; nm = "bic";
isBIC = True; break;
+ case BITS5(0,0,1,0,0): op = Iop_Xor32; nm = "eor"; break;
default: vassert(0);
}
IRTemp argL = newTemp(Ity_I32);
@@ -7308,6 +7313,59 @@
}
}
+ /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
+ // also SBC
+ if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+ && ( INSN0(8,5) == BITS4(1,0,1,0) // adc subopc
+ /* || INSN0(8,5) == BITS4(?,?,?,?*/ ) // sbc subopc
+ && INSN1(15,15) == 0) {
+ /* ADC: Rd = Rn + shifter_operand + oldC */
+ /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
+ UInt rN = INSN0(3,0);
+ UInt rD = INSN1(11,8);
+ UInt rM = INSN1(3,0);
+ if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+ UInt bS = INSN0(4,4);
+ UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6);
+ UInt how = INSN1(5,4);
+
+ IRTemp argL = newTemp(Ity_I32);
+ assign(argL, getIRegT(rN));
+
+ IRTemp rMt = newTemp(Ity_I32);
+ assign(rMt, getIRegT(rM));
+
+ IRTemp argR = newTemp(Ity_I32);
+ IRTemp oldC = newTemp(Ity_I32);
+ compute_result_and_C_after_shift_by_imm5(
+ dis_buf, &argR, &oldC, rMt, how, imm5, rM
+ );
+
+ HChar* nm = "???";
+ IRTemp res = newTemp(Ity_I32);
+ switch (INSN0(8,5)) {
+ case BITS4(1,0,1,0): // ADC
+ nm = "adc";
+ assign(res,
+ binop(Iop_Add32,
+ binop(Iop_Add32, mkexpr(argL), mkexpr(argR)),
+ mkexpr(oldC) ));
+ putIRegT(rD, mkexpr(res), condT);
+ if (bS)
+ setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
+ argL, argR, oldC, condT );
+
+ break;
+ default:
+ vassert(0);
+ }
+
+ DIP("%s%s.w r%u, r%u, %s\n",
+ nm, bS ? "s" : "", rD, rN, dis_buf);
+ goto decode_success;
+ }
+ }
+
/* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
/* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
/* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
@@ -8248,21 +8306,35 @@
}
/* ------------------ UXTB ------------------ */
- if (INSN0(15,0) == 0xFA5F
+ if ((INSN0(15,0) == 0xFA5F || INSN0(15,0) == 0xFA1F)
&& INSN1(15,12) == BITS4(1,1,1,1)
&& INSN1(7,6) == BITS2(1,0)) {
UInt rD = INSN1(11,8);
UInt rM = INSN1(3,0);
UInt rot = INSN1(5,4);
if (!isBadRegT(rD) && !isBadRegT(rM)) {
+ HChar* nm = "???";
IRTemp srcT = newTemp(Ity_I32);
IRTemp rotT = newTemp(Ity_I32);
IRTemp dstT = newTemp(Ity_I32);
assign(srcT, getIRegT(rM));
assign(rotT, genROR32(srcT, 8 * rot));
- assign(dstT, unop(Iop_8Uto32, unop(Iop_32to8, mkexpr(rotT))));
+ switch (INSN0(15,0)) {
+ case 0xFA5F: // UXTB
+ nm = "uxtb";
+ assign(dstT, unop(Iop_8Uto32,
+ unop(Iop_32to8, mkexpr(rotT))));
+ break;
+ case 0xFA1F: // UXTH
+ nm = "uxth";
+ assign(dstT, unop(Iop_16Uto32,
+ unop(Iop_32to16, mkexpr(rotT))));
+ break;
+ default:
+ vassert(0);
+ }
putIRegT(rD, mkexpr(dstT), condT);
- DIP("uxtb r%u, r%u, ror #%u\n", rD, rM, 8 * rot);
+ DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
goto decode_success;
}
}
|
|
From: <sv...@va...> - 2010-08-01 13:25:05
|
Author: sewardj
Date: 2010-08-01 14:24:56 +0100 (Sun, 01 Aug 2010)
New Revision: 1998
Log:
Fix up the IR optimiser a bit and the ARM spechelper for
armg_calculate_condition in particular. This is so it can
successfully fold out the all the boilerplate IR guff inserted at the
start of translation of all Thumb instructions, in most circumstances.
Modified:
branches/THUMB/priv/guest_amd64_defs.h
branches/THUMB/priv/guest_amd64_helpers.c
branches/THUMB/priv/guest_arm_defs.h
branches/THUMB/priv/guest_arm_helpers.c
branches/THUMB/priv/guest_arm_toIR.c
branches/THUMB/priv/guest_ppc_defs.h
branches/THUMB/priv/guest_ppc_helpers.c
branches/THUMB/priv/guest_x86_defs.h
branches/THUMB/priv/guest_x86_helpers.c
branches/THUMB/priv/ir_opt.c
branches/THUMB/priv/ir_opt.h
branches/THUMB/priv/main_main.c
Modified: branches/THUMB/priv/guest_amd64_defs.h
===================================================================
--- branches/THUMB/priv/guest_amd64_defs.h 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_amd64_defs.h 2010-08-01 13:24:56 UTC (rev 1998)
@@ -61,8 +61,10 @@
/* Used by the optimiser to specialise calls to helpers. */
extern
-IRExpr* guest_amd64_spechelper ( HChar* function_name,
- IRExpr** args );
+IRExpr* guest_amd64_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts );
/* Describes to the optimiser which part of the guest state require
precise memory exceptions. This is logically part of the guest
Modified: branches/THUMB/priv/guest_amd64_helpers.c
===================================================================
--- branches/THUMB/priv/guest_amd64_helpers.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_amd64_helpers.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -867,7 +867,9 @@
}
IRExpr* guest_amd64_spechelper ( HChar* function_name,
- IRExpr** args )
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts )
{
# define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
Modified: branches/THUMB/priv/guest_arm_defs.h
===================================================================
--- branches/THUMB/priv/guest_arm_defs.h 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_arm_defs.h 2010-08-01 13:24:56 UTC (rev 1998)
@@ -55,8 +55,10 @@
/* Used by the optimiser to specialise calls to helpers. */
extern
-IRExpr* guest_arm_spechelper ( HChar* function_name,
- IRExpr** args );
+IRExpr* guest_arm_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts );
/* Describes to the optimser which part of the guest state require
precise memory exceptions. This is logically part of the guest
Modified: branches/THUMB/priv/guest_arm_helpers.c
===================================================================
--- branches/THUMB/priv/guest_arm_helpers.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_arm_helpers.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -215,11 +215,16 @@
{
UInt cond = cond_n_op >> 4;
UInt cc_op = cond_n_op & 0xF;
- UInt nf, zf, vf, cf;
- UInt inv = cond & 1;
- // vex_printf("XXXXXXXX %x %x %x %x\n", cond_n_op, cc_dep1, cc_dep2, cc_dep3);
- UInt nzcv = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3);
+ UInt nf, zf, vf, cf, nzcv, inv;
+ // vex_printf("XXXXXXXX %x %x %x %x\n",
+ // cond_n_op, cc_dep1, cc_dep2, cc_dep3);
+ // skip flags computation in this case
+ if (cond == ARMCondAL) return 1;
+
+ inv = cond & 1;
+ nzcv = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3);
+
switch (cond) {
case ARMCondEQ: // Z=1 => z
case ARMCondNE: // Z=0
@@ -260,9 +265,7 @@
zf = nzcv >> ARMG_CC_SHIFT_Z;
return 1 & (inv ^ ~(zf | (nf ^ vf)));
- case ARMCondAL:
- return 1; /* well, that bit at least was easy! */
-
+ case ARMCondAL: // handled above
case ARMCondNV: // should never get here: Illegal instr
default:
/* shouldn't really make these calls from generated code */
@@ -291,8 +294,10 @@
&& e->Iex.Const.con->Ico.U32 == n );
}
-IRExpr* guest_arm_spechelper ( HChar* function_name,
- IRExpr** args )
+IRExpr* guest_arm_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts )
{
# define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
@@ -312,7 +317,7 @@
vex_printf("\n");
# endif
- /* --------- specialising "x86g_calculate_condition" --------- */
+ /* --------- specialising "armg_calculate_condition" --------- */
if (vex_streq(function_name, "armg_calculate_condition")) {
/* specialise calls to above "armg_calculate condition" function */
@@ -343,7 +348,7 @@
}
if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) {
- /* LE after SUB --> test argL <s argR */
+ /* LT after SUB --> test argL <s argR */
return unop(Iop_1Uto32,
binop(Iop_CmpLT32S, cc_dep1, cc_dep2));
}
@@ -380,6 +385,51 @@
binop(Iop_CmpNE32, cc_dep1, mkU32(0)));
}
+ /*----------------- AL -----------------*/
+ /* A critically important case for Thumb code.
+
+ What we're trying to spot is the case where cond_n_op is an
+ expression of the form Or32(..., 0xE0) since that means the
+ caller is asking for CondAL and we can simply return 1
+ without caring what the ... part is. This is a potentially
+ dodgy kludge in that it assumes that the ... part has zeroes
+ in bits 7:4, so that the result of the Or32 is guaranteed to
+ be 0xE in bits 7:4. Given that the places where this first
+ arg are constructed (in guest_arm_toIR.c) are very
+ constrained, we can get away with this. To make this
+ guaranteed safe would require to have a new primop, Slice44
+ or some such, thusly
+
+ Slice44(arg1, arg2) = 0--(24)--0 arg1[7:4] arg2[3:0]
+
+ and we would then look for Slice44(0xE0, ...)
+ which would give the required safety property.
+
+ It would be infeasibly expensive to scan backwards through
+ the entire block looking for an assignment to the temp, so
+ just look at the previous 16 statements. That should find it
+ if it is an interesting case, as a result of how the
+ boilerplate guff at the start of each Thumb insn translation
+ is made.
+ */
+ if (cond_n_op->tag == Iex_RdTmp) {
+ Int j;
+ IRTemp look_for = cond_n_op->Iex.RdTmp.tmp;
+ Int limit = n_precedingStmts - 16;
+ if (limit < 0) limit = 0;
+ if (0) vex_printf("scanning %d .. %d\n", n_precedingStmts-1, limit);
+ for (j = n_precedingStmts - 1; j >= limit; j--) {
+ IRStmt* st = precedingStmts[j];
+ if (st->tag == Ist_WrTmp
+ && st->Ist.WrTmp.tmp == look_for
+ && st->Ist.WrTmp.data->tag == Iex_Binop
+ && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32
+ && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4)))
+ return mkU32(1);
+ }
+ /* Didn't find any useful binding to the first arg
+ in the previous 16 stmts. */
+ }
}
# undef unop
Modified: branches/THUMB/priv/guest_arm_toIR.c
===================================================================
--- branches/THUMB/priv/guest_arm_toIR.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_arm_toIR.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -32,8 +32,19 @@
that all cases where putIRegT writes r15, we generate a jump.
All uses of newTemp assign to an IRTemp and not a UInt
- */
+
+ XXXX thumb to do: improve the ITSTATE-zeroing optimisation by
+ taking into account the number of insns guarded by an IT.
+
+ remove the nasty hack, in the spechelper, of looking for Or32(...,
+ 0xE0) in as the first arg to armg_calculate_condition, and instead
+ use Slice44 as specified in comments in the spechelper.
+
+ add specialisations for armg_calculate_flag_c and _v, as they
+ are moderately often needed in Thumb code.
+*/
+
/* Limitations, etc
- pretty dodgy exception semantics for {LD,ST}Mxx, no doubt
@@ -5613,7 +5624,26 @@
that would not otherwise have happened. The saving grace is
that such skipping is pretty rare -- it only happens,
statistically, 18/4096ths of the time, so is judged unlikely to
- be a performance problems. */
+ be a performance problems.
+
+ FIXME: do better. Take into account the number of insns covered
+ by any IT insns we find, to rule out cases where an IT clearly
+ cannot cover this instruction. This would improve behaviour for
+ branch targets immediately following an IT-guarded group that is
+ not of full length. Eg, (and completely ignoring issues of 16-
+ vs 32-bit insn length):
+
+ ite cond
+ insn1
+ insn2
+ label: insn3
+ insn4
+
+ The 'it' only conditionalises insn1 and insn2. However, the
+ current analysis is conservative and considers insn3 and insn4
+ also possibly guarded. Hence if 'label:' is the start of a hot
+ loop we will get a big performance hit.
+ */
{
/* Summary result of this analysis: False == safe but
suboptimal. */
Modified: branches/THUMB/priv/guest_ppc_defs.h
===================================================================
--- branches/THUMB/priv/guest_ppc_defs.h 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_ppc_defs.h 2010-08-01 13:24:56 UTC (rev 1998)
@@ -62,12 +62,16 @@
/* Used by the optimiser to specialise calls to helpers. */
extern
-IRExpr* guest_ppc32_spechelper ( HChar* function_name,
- IRExpr** args );
+IRExpr* guest_ppc32_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts );
extern
-IRExpr* guest_ppc64_spechelper ( HChar* function_name,
- IRExpr** args );
+IRExpr* guest_ppc64_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts );
/* Describes to the optimser which part of the guest state require
precise memory exceptions. This is logically part of the guest
Modified: branches/THUMB/priv/guest_ppc_helpers.c
===================================================================
--- branches/THUMB/priv/guest_ppc_helpers.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_ppc_helpers.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -182,13 +182,17 @@
/* Helper-function specialiser. */
IRExpr* guest_ppc32_spechelper ( HChar* function_name,
- IRExpr** args )
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts )
{
return NULL;
}
IRExpr* guest_ppc64_spechelper ( HChar* function_name,
- IRExpr** args )
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts )
{
return NULL;
}
Modified: branches/THUMB/priv/guest_x86_defs.h
===================================================================
--- branches/THUMB/priv/guest_x86_defs.h 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_x86_defs.h 2010-08-01 13:24:56 UTC (rev 1998)
@@ -61,8 +61,10 @@
/* Used by the optimiser to specialise calls to helpers. */
extern
-IRExpr* guest_x86_spechelper ( HChar* function_name,
- IRExpr** args );
+IRExpr* guest_x86_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts );
/* Describes to the optimiser which part of the guest state require
precise memory exceptions. This is logically part of the guest
Modified: branches/THUMB/priv/guest_x86_helpers.c
===================================================================
--- branches/THUMB/priv/guest_x86_helpers.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/guest_x86_helpers.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -772,8 +772,10 @@
&& e->Iex.Const.con->Ico.U32 == n );
}
-IRExpr* guest_x86_spechelper ( HChar* function_name,
- IRExpr** args )
+IRExpr* guest_x86_spechelper ( HChar* function_name,
+ IRExpr** args,
+ IRStmt** precedingStmts,
+ Int n_precedingStmts )
{
# define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
Modified: branches/THUMB/priv/ir_opt.c
===================================================================
--- branches/THUMB/priv/ir_opt.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/ir_opt.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -2196,8 +2196,10 @@
/*---------------------------------------------------------------*/
static
-IRSB* spec_helpers_BB ( IRSB* bb,
- IRExpr* (*specHelper) ( HChar*, IRExpr**) )
+IRSB* spec_helpers_BB(
+ IRSB* bb,
+ IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int)
+ )
{
Int i;
IRStmt* st;
@@ -2212,7 +2214,8 @@
continue;
ex = (*specHelper)( st->Ist.WrTmp.data->Iex.CCall.cee->name,
- st->Ist.WrTmp.data->Iex.CCall.args );
+ st->Ist.WrTmp.data->Iex.CCall.args,
+ &bb->stmts[0], i );
if (!ex)
/* the front end can't think of a suitable replacement */
continue;
@@ -4358,7 +4361,7 @@
static
IRSB* cheap_transformations (
IRSB* bb,
- IRExpr* (*specHelper) (HChar*, IRExpr**),
+ IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),
Bool (*preciseMemExnsFn)(Int,Int)
)
{
@@ -4509,10 +4512,13 @@
*/
-IRSB* do_iropt_BB ( IRSB* bb0,
- IRExpr* (*specHelper) (HChar*, IRExpr**),
- Bool (*preciseMemExnsFn)(Int,Int),
- Addr64 guest_addr )
+IRSB* do_iropt_BB(
+ IRSB* bb0,
+ IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),
+ Bool (*preciseMemExnsFn)(Int,Int),
+ Addr64 guest_addr,
+ VexArch guest_arch
+ )
{
static Int n_total = 0;
static Int n_expensive = 0;
@@ -4543,6 +4549,15 @@
bb = cheap_transformations( bb, specHelper, preciseMemExnsFn );
+ if (guest_arch == VexArchARM) {
+ /* Translating Thumb2 code produces a lot of chaff. We have to
+ work extra hard to get rid of it. */
+ bb = cprop_BB(bb);
+ bb = spec_helpers_BB ( bb, specHelper );
+ redundant_put_removal_BB ( bb, preciseMemExnsFn );
+ do_deadcode_BB( bb );
+ }
+
if (vex_control.iropt_level > 1) {
/* Peer at what we have, to decide how much more effort to throw
Modified: branches/THUMB/priv/ir_opt.h
===================================================================
--- branches/THUMB/priv/ir_opt.h 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/ir_opt.h 2010-08-01 13:24:56 UTC (rev 1998)
@@ -43,10 +43,13 @@
/* Top level optimiser entry point. Returns a new BB. Operates
under the control of the global "vex_control" struct. */
extern
-IRSB* do_iropt_BB ( IRSB* bb,
- IRExpr* (*specHelper) (HChar*, IRExpr**),
- Bool (*preciseMemExnsFn)(Int,Int),
- Addr64 guest_addr );
+IRSB* do_iropt_BB(
+ IRSB* bb,
+ IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),
+ Bool (*preciseMemExnsFn)(Int,Int),
+ Addr64 guest_addr,
+ VexArch guest_arch
+ );
/* Do a constant folding/propagation pass. */
extern
Modified: branches/THUMB/priv/main_main.c
===================================================================
--- branches/THUMB/priv/main_main.c 2010-07-29 18:10:51 UTC (rev 1997)
+++ branches/THUMB/priv/main_main.c 2010-08-01 13:24:56 UTC (rev 1998)
@@ -183,7 +183,7 @@
HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
VexAbiInfo* );
Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
- IRExpr* (*specHelper) ( HChar*, IRExpr** );
+ IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int );
Bool (*preciseMemExnsFn) ( Int, Int );
DisOneInstrFn disInstrFn;
@@ -501,7 +501,8 @@
/* Clean it up, hopefully a lot. */
irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn,
- vta->guest_bytes_addr );
+ vta->guest_bytes_addr,
+ vta->arch_guest );
sanityCheckIRSB( irsb, "after initial iropt",
True/*must be flat*/, guest_word_type );
|
|
From: Bart V. A. <bva...@ac...> - 2010-08-01 07:43:02
|
Nightly build on cellbuzz-native ( cellbuzz, ppc64, Fedora 7, native ) Started at 2010-08-01 02:00:05 EDT Ended at 2010-08-01 03:42:40 EDT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 462 tests, 45 stderr failures, 12 stdout failures, 0 post failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cases-full (stderr) memcheck/tests/leak-cases-summary (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/linux/timerfd-syscall (stdout) memcheck/tests/linux-syscalls-2007 (stderr) memcheck/tests/origin5-bz2 (stderr) memcheck/tests/varinfo1 (stderr) memcheck/tests/varinfo2 (stderr) memcheck/tests/varinfo3 (stderr) memcheck/tests/varinfo4 (stderr) memcheck/tests/varinfo5 (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) callgrind/tests/simwork-both (stdout) callgrind/tests/simwork-both (stderr) callgrind/tests/simwork-branch (stdout) callgrind/tests/simwork-branch (stderr) none/tests/empty-exe (stderr) none/tests/linux/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-vmx (stdout) none/tests/ppc32/round (stdout) none/tests/ppc32/test_gx (stdout) none/tests/ppc64/jm-fp (stdout) none/tests/ppc64/jm-vmx (stdout) none/tests/ppc64/round (stdout) none/tests/shell_valid2 (stderr) none/tests/shell_valid3 (stderr) none/tests/shell_zerolength (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) helgrind/tests/tc23_bogus_condwait (stderr) exp-ptrcheck/tests/bad_percentify (stderr) exp-ptrcheck/tests/base (stderr) exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/fp (stderr) exp-ptrcheck/tests/globalerr (stderr) exp-ptrcheck/tests/hackedbz2 (stderr) exp-ptrcheck/tests/hp_bounds (stderr) exp-ptrcheck/tests/hp_dangle (stderr) exp-ptrcheck/tests/hsg (stderr) exp-ptrcheck/tests/justify (stderr) exp-ptrcheck/tests/partial_bad (stderr) exp-ptrcheck/tests/partial_good (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) exp-ptrcheck/tests/realloc (stderr) exp-ptrcheck/tests/stackerr (stderr) exp-ptrcheck/tests/strcpy (stderr) exp-ptrcheck/tests/supp (stderr) exp-ptrcheck/tests/tricky (stderr) exp-ptrcheck/tests/unaligned (stderr) exp-ptrcheck/tests/zero (stderr) |
|
From: Rich C. <rc...@wi...> - 2010-08-01 04:17:52
|
Nightly build on macbook ( Darwin 9.8.0 i386 ) Started at 2010-07-31 23:05:00 CDT Ended at 2010-07-31 23:17:29 CDT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... failed Last 20 lines of verbose log follow echo Making check in . make addressable atomic_incs badaddrvalue badfree badjump badjump2 badloop badpoll badrw brk2 buflen_check calloc-overflow clientperm custom_alloc custom-overlap deep_templates describe-block doublefree error_counts errs1 exitprog execve execve2 erringfds file_locking fprw fwrite inits inline leak-0 leak-cases leak-cycle leak-pool leak-tree linux-syslog-syscall linux-syscalls-2007 long_namespace_xml long-supps mallinfo malloc_free_fill malloc_usable malloc1 malloc2 malloc3 manuel1 manuel2 manuel3 match-overrun memalign_test memalign2 memcmptest mempool mmaptest mismatches new_override metadata nanoleak_supp nanoleak2 new_nothrow noisy_child null_socket origin1-yes origin2-not-quite origin3-no origin4-many origin5-bz2 origin6-fp overlap partiallydefinedeq partial_load pdb-realloc pdb-realloc2 pipe pointer-trace post-syscall realloc1 realloc2 realloc3 sh-mem sh-mem-random sigaltstack signal2 sigprocmask sigkill strchr str_tester supp_unknown supp1 supp2 suppfree trivialleak un it_libcbase unit_oset varinfo1 varinfo2 varinfo3 varinfo4 varinfo5 varinfo5so.so varinfo6 vcpu_fbench vcpu_fnfns xml1 wrap1 wrap2 wrap3 wrap4 wrap5 wrap6 wrap7 wrap7so.so wrap8 writev gcc -DHAVE_CONFIG_H -I. -I../.. -I../.. -I../../include -I../../coregrind -I../../include -I../../VEX/pub -DVGA_amd64=1 -DVGO_darwin=1 -DVGP_amd64_darwin=1 -Winline -Wall -Wshadow -g -arch x86_64 -Wno-long-long -Wno-pointer-sign -fno-stack-protector -MT addressable.o -MD -MP -MF .deps/addressable.Tpo -c -o addressable.o addressable.c mv -f .deps/addressable.Tpo .deps/addressable.Po gcc -Winline -Wall -Wshadow -g -arch x86_64 -Wno-long-long -Wno-pointer-sign -fno-stack-protector -o addressable addressable.o gcc -DHAVE_CONFIG_H -I. -I../.. -I../.. -I../../include -I../../coregrind -I../../include -I../../VEX/pub -DVGA_amd64=1 -DVGO_darwin=1 -DVGP_amd64_darwin=1 -Winline -Wall -Wshadow -g -arch x86_64 -mdynamic-no-pic -Wno-long-long -Wno-pointer-sign -fno-stack-protector -MT atomic_incs-atomic_incs.o -MD -MP -MF .deps/atomic_incs-atomic_incs.Tpo -c -o atomic_incs-atomic_incs.o `test -f 'atomic_incs.c' || echo './'`atomic_incs.c atomic_incs.c: In function 'atomic_add_8bit': atomic_incs.c:37: error: PIC register 'rbx' clobbered in 'asm' atomic_incs.c: In function 'atomic_add_16bit': atomic_incs.c:101: error: PIC register 'rbx' clobbered in 'asm' atomic_incs.c: In function 'atomic_add_32bit': atomic_incs.c:164: error: PIC register 'rbx' clobbered in 'asm' atomic_incs.c: In function 'atomic_add_64bit': atomic_incs.c:219: error: PIC register 'rbx' clobbered in 'asm' make[5]: *** [atomic_incs-atomic_incs.o] Error 1 make[4]: *** [check-am] Error 2 make[3]: *** [check-recursive] Error 1 make[2]: *** [check-recursive] Error 1 make[1]: *** [check-recursive] Error 1 make: *** [check] Error 2 Congratulations, all tests passed! |
|
From: Tom H. <th...@cy...> - 2010-08-01 02:50:57
|
Nightly build on lloyd ( x86_64, Fedora 7 ) Started at 2010-08-01 03:05:08 BST Ended at 2010-08-01 03:50:42 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 546 tests, 2 stderr failures, 3 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 546 tests, 3 stderr failures, 3 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sun Aug 1 03:27:33 2010 --- new.short Sun Aug 1 03:50:42 2010 *************** *** 8,11 **** ! == 546 tests, 3 stderr failures, 3 stdout failures, 0 post failures == ! memcheck/tests/x86-linux/scalar (stderr) none/tests/amd64/bug132918 (stdout) --- 8,10 ---- ! == 546 tests, 2 stderr failures, 3 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) |
|
From: Tom H. <th...@cy...> - 2010-08-01 02:37:46
|
Nightly build on mg ( x86_64, Fedora 9 ) Started at 2010-08-01 03:10:04 BST Ended at 2010-08-01 03:37:33 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 553 tests, 2 stderr failures, 3 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 553 tests, 4 stderr failures, 3 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) none/tests/amd64/bug132918 (stdout) none/tests/amd64/fxtract (stdout) none/tests/x86/fxtract (stdout) helgrind/tests/pth_spinlock (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc09_bad_unlock (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sun Aug 1 03:23:50 2010 --- new.short Sun Aug 1 03:37:33 2010 *************** *** 8,11 **** ! == 553 tests, 4 stderr failures, 3 stdout failures, 0 post failures == ! memcheck/tests/x86-linux/scalar (stderr) none/tests/amd64/bug132918 (stdout) --- 8,10 ---- ! == 553 tests, 2 stderr failures, 3 stdout failures, 0 post failures == none/tests/amd64/bug132918 (stdout) *************** *** 13,15 **** none/tests/x86/fxtract (stdout) - helgrind/tests/pth_spinlock (stderr) helgrind/tests/tc06_two_races_xml (stderr) --- 12,13 ---- |