You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
|
|
|
|
1
(25) |
2
(13) |
3
(3) |
|
4
|
5
(5) |
6
(12) |
7
(5) |
8
(16) |
9
(3) |
10
|
|
11
|
12
|
13
(4) |
14
(1) |
15
(2) |
16
(6) |
17
|
|
18
|
19
(1) |
20
(2) |
21
(10) |
22
(9) |
23
(8) |
24
(5) |
|
25
|
26
(6) |
27
(8) |
28
(8) |
29
(23) |
30
(12) |
31
(6) |
|
From: John M. <me...@ge...> - 2010-07-29 22:52:13
|
jmehaffe-lnx-1:/ws/jmehaffe/main_cge5/cles_moved_aside/vg/rpm/SOURCES
> cat valgrind-3.5.0_cross_compile.patch
--- valgrind-3.5.0/configure.in.orig Wed Aug 19 06:37:48 2009
+++ valgrind-3.5.0/configure.in Thu Jul 1 15:01:20 2010
@@ -1472,9 +1472,10 @@ fi
#----------------------------------------------------------------------------
# Check for /proc filesystem
#----------------------------------------------------------------------------
-AC_CHECK_FILES(/proc/self/fd /proc/self/exe /proc/self/maps,
- [ AC_DEFINE([HAVE_PROC], 1, [can use /proc filesystem]) ],
- [])
+# jfm AC_CHECK_FILES(/proc/self/fd /proc/self/exe /proc/self/maps,
+# jfm [ AC_DEFINE([HAVE_PROC], 1, [can use /proc filesystem]) ],
+# jfm [])
+AC_DEFINE([HAVE_PROC], 1, [can use /proc filesystem])
#----------------------------------------------------------------------------
--- valgrind-3.5.0/Makefile.am.orig Fri Jul 2 13:38:25 2010
+++ valgrind-3.5.0/Makefile.am Fri Jul 2 14:43:11 2010
@@ -66,7 +66,9 @@ CLEANFILES = default.supp
default.supp: $(DEFAULT_SUPP_FILES)
echo "# This is a generated file, composed of the following
suppression rules:" > default.supp
echo "# " $(DEFAULT_SUPP_FILES) >> default.supp
- cat $(DEFAULT_SUPP_FILES) >> default.supp
+ for f in $(DEFAULT_SUPP_FILES); do \
+ cat $(srcdir)/$$f >> default.supp; \
+ done
## Preprend @PERL@ because tests/vg_regtest isn't executable
regtest: check
--- valgrind-3.5.0/Makefile.in.orig Wed Aug 19 06:43:59 2009
+++ valgrind-3.5.0/Makefile.in Tue Jul 6 10:36:50 2010
@@ -1014,7 +1014,9 @@ clean-noinst_DSYMS:
default.supp: $(DEFAULT_SUPP_FILES)
echo "# This is a generated file, composed of the following
suppression rules:" > default.supp
echo "# " $(DEFAULT_SUPP_FILES) >> default.supp
- cat $(DEFAULT_SUPP_FILES) >> default.supp
+ for f in $(DEFAULT_SUPP_FILES); do \
+ cat $(srcdir)/$$f >> default.supp; \
+ done
regtest: check
@PERL@ tests/vg_regtest $(TEST_TOOLS) $(TEST_EXP_TOOLS)
--- valgrind-3.5.0/coregrind/Makefile.orig Tue Jul 6 11:26:17 2010
+++ valgrind-3.5.0/coregrind/Makefile.in Tue Jul 6 11:28:20 2010
@@ -712,7 +712,7 @@ AM_CFLAGS_BASE = \
#----------------------------------------------------------------------------
# Basics, flags
#----------------------------------------------------------------------------
-AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) \
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) -I.. \
-I$(top_srcdir)/include -I$(top_srcdir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
-DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
--- valgrind-3.5.0/coregrind/m_main.c.orig Wed Aug 19 06:37:47 2009
+++ valgrind-3.5.0/coregrind/m_main.c Tue Jul 6 12:02:41 2010
@@ -73,6 +73,13 @@
#endif
+/* Hack because glibc is not included, but the math lib libgcc calls
it - jfm */
+
+void abort(void)
+{
+ vg_assert(0);
+}
+
/*====================================================================*/
/*=== Counters, for profiling purposes only ===*/
/*====================================================================*/
--- valgrind-3.5.0/docs/Makefile.in.orig Wed Jul 7 08:56:50 2010
+++ valgrind-3.5.0/docs/Makefile.in Wed Jul 7 08:58:44 2010
@@ -546,24 +546,24 @@ print-docs:
# be the one to handle the else/endif parts, not GNU make
# as we intend.
install-data-hook:
- if test -r html ; then \
+ if test -r $(srcdir)/html ; then \
mkdir -p $(DESTDIR)$(datadir)/doc/valgrind; \
- cp -r html $(DESTDIR)$(datadir)/doc/valgrind; \
+ cp -r $(srcdir)/html $(DESTDIR)$(datadir)/doc/valgrind; \
fi
- for f in *.1 ; do \
+ for f in $(srcdir)/*.1 ; do \
if test -r $$f ; then \
mkdir -p $(DESTDIR)$(mandir)/man1; \
cp $$f $(DESTDIR)$(mandir)/man1; \
fi \
done
ifeq ($(BUILD_ALL_DOCS),yes)
- if test -r index.pdf ; then \
+ if test -r $(srcdir)/index.pdf ; then \
mkdir -p $(DESTDIR)$(datadir)/doc/valgrind; \
- cp index.pdf
$(DESTDIR)$(datadir)/doc/valgrind/valgrind_manual.pdf; \
+ cp $(srcdir)/index.pdf
$(DESTDIR)$(datadir)/doc/valgrind/valgrind_manual.pdf; \
fi
- if test -r index.ps ; then \
+ if test -r $(srcdir)/index.ps ; then \
mkdir -p $(DESTDIR)$(datadir)/doc/valgrind; \
- cp index.ps
$(DESTDIR)$(datadir)/doc/valgrind/valgrind_manual.ps; \
+ cp $(srcdir)/index.ps
$(DESTDIR)$(datadir)/doc/valgrind/valgrind_manual.ps; \
fi
endif
|
|
From: John M. <me...@ge...> - 2010-07-29 22:50:42
|
Try again, without html.
bash > cat valgrind-3.5.0_ppc_SPE.patch
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/guest_ppc_helpers.c
vg2/valgrind-3.5.0/VEX/priv/guest_ppc_helpers.c
--- vg1/valgrind-3.5.0/VEX/priv/guest_ppc_helpers.c Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/guest_ppc_helpers.c Tue Jul 13 10:51:16 2010
@@ -386,6 +386,39 @@ void LibVEX_GuestPPC32_initialise ( /*OU
vex_state->guest_GPR30 = 0;
vex_state->guest_GPR31 = 0;
+ vex_state->guest_GPR0_ext = 0;
+ vex_state->guest_GPR1_ext = 0;
+ vex_state->guest_GPR2_ext = 0;
+ vex_state->guest_GPR3_ext = 0;
+ vex_state->guest_GPR4_ext = 0;
+ vex_state->guest_GPR5_ext = 0;
+ vex_state->guest_GPR6_ext = 0;
+ vex_state->guest_GPR7_ext = 0;
+ vex_state->guest_GPR8_ext = 0;
+ vex_state->guest_GPR9_ext = 0;
+ vex_state->guest_GPR10_ext = 0;
+ vex_state->guest_GPR11_ext = 0;
+ vex_state->guest_GPR12_ext = 0;
+ vex_state->guest_GPR13_ext = 0;
+ vex_state->guest_GPR14_ext = 0;
+ vex_state->guest_GPR15_ext = 0;
+ vex_state->guest_GPR16_ext = 0;
+ vex_state->guest_GPR17_ext = 0;
+ vex_state->guest_GPR18_ext = 0;
+ vex_state->guest_GPR19_ext = 0;
+ vex_state->guest_GPR20_ext = 0;
+ vex_state->guest_GPR21_ext = 0;
+ vex_state->guest_GPR22_ext = 0;
+ vex_state->guest_GPR23_ext = 0;
+ vex_state->guest_GPR24_ext = 0;
+ vex_state->guest_GPR25_ext = 0;
+ vex_state->guest_GPR26_ext = 0;
+ vex_state->guest_GPR27_ext = 0;
+ vex_state->guest_GPR28_ext = 0;
+ vex_state->guest_GPR29_ext = 0;
+ vex_state->guest_GPR30_ext = 0;
+ vex_state->guest_GPR31_ext = 0;
+
vex_state->guest_FPR0 = 0;
vex_state->guest_FPR1 = 0;
vex_state->guest_FPR2 = 0;
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/guest_ppc_toIR.c
vg2/valgrind-3.5.0/VEX/priv/guest_ppc_toIR.c
--- vg1/valgrind-3.5.0/VEX/priv/guest_ppc_toIR.c Mon Jul 12 15:28:02 2010
+++ vg2/valgrind-3.5.0/VEX/priv/guest_ppc_toIR.c Mon Jul 19 18:53:21 2010
@@ -298,6 +298,11 @@ static UChar ifieldBIT0 ( UInt instr ) {
return toUChar( instr & 0x1 );
}
+/* Extract unsigned offset, instr[15:11] */
+static UChar ifieldUIMM5 ( UInt instr ) {
+ return toUChar( IFIELD( instr, 11, 5) );
+}
+
/* Extract unsigned bottom half, instr[15:0] */
static UInt ifieldUIMM16 ( UInt instr ) {
return instr & 0xFFFF;
@@ -496,6 +501,11 @@ static IRExpr* mkexpr ( IRTemp tmp )
return IRExpr_RdTmp(tmp);
}
+static IRExpr* mkU1 ( UChar i )
+{
+ return IRExpr_Const(IRConst_U1(i));
+}
+
static IRExpr* mkU8 ( UChar i )
{
return IRExpr_Const(IRConst_U8(i));
@@ -943,7 +953,6 @@ static IRExpr* getIReg ( UInt archreg )
return IRExpr_Get( integerGuestRegOffset(archreg), ty );
}
-/* Ditto, but write to a reg instead. */
static void putIReg ( UInt archreg, IRExpr* e )
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
@@ -952,6 +961,83 @@ static void putIReg ( UInt archreg, IREx
stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) );
}
+/* Get GPRnn as Single Prec. FP (SPE) */
+static IRExpr* getSPReg ( UInt archreg )
+{
+ vassert(archreg < 32);
+ return IRExpr_Get( integerGuestRegOffset(archreg), Ity_F32 );
+}
+
+/* Ditto, but write to a reg instead. */
+static void putSPReg ( UInt archreg, IRExpr* e )
+{
+ vassert(archreg < 32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32 );
+ stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) );
+}
+
+
+static Int extGuestRegOffset ( UInt archreg )
+{
+ vassert(archreg < 32);
+
+ vassert(host_is_bigendian);
+
+#define offsetofPPC32GuestState(_x) offsetof(VexGuestPPC32State, _x)
+
+ switch (archreg) {
+ case 0: return offsetofPPC32GuestState(guest_GPR0_ext);
+ case 1: return offsetofPPC32GuestState(guest_GPR1_ext);
+ case 2: return offsetofPPC32GuestState(guest_GPR2_ext);
+ case 3: return offsetofPPC32GuestState(guest_GPR3_ext);
+ case 4: return offsetofPPC32GuestState(guest_GPR4_ext);
+ case 5: return offsetofPPC32GuestState(guest_GPR5_ext);
+ case 6: return offsetofPPC32GuestState(guest_GPR6_ext);
+ case 7: return offsetofPPC32GuestState(guest_GPR7_ext);
+ case 8: return offsetofPPC32GuestState(guest_GPR8_ext);
+ case 9: return offsetofPPC32GuestState(guest_GPR9_ext);
+ case 10: return offsetofPPC32GuestState(guest_GPR10_ext);
+ case 11: return offsetofPPC32GuestState(guest_GPR11_ext);
+ case 12: return offsetofPPC32GuestState(guest_GPR12_ext);
+ case 13: return offsetofPPC32GuestState(guest_GPR13_ext);
+ case 14: return offsetofPPC32GuestState(guest_GPR14_ext);
+ case 15: return offsetofPPC32GuestState(guest_GPR15_ext);
+ case 16: return offsetofPPC32GuestState(guest_GPR16_ext);
+ case 17: return offsetofPPC32GuestState(guest_GPR17_ext);
+ case 18: return offsetofPPC32GuestState(guest_GPR18_ext);
+ case 19: return offsetofPPC32GuestState(guest_GPR19_ext);
+ case 20: return offsetofPPC32GuestState(guest_GPR20_ext);
+ case 21: return offsetofPPC32GuestState(guest_GPR21_ext);
+ case 22: return offsetofPPC32GuestState(guest_GPR22_ext);
+ case 23: return offsetofPPC32GuestState(guest_GPR23_ext);
+ case 24: return offsetofPPC32GuestState(guest_GPR24_ext);
+ case 25: return offsetofPPC32GuestState(guest_GPR25_ext);
+ case 26: return offsetofPPC32GuestState(guest_GPR26_ext);
+ case 27: return offsetofPPC32GuestState(guest_GPR27_ext);
+ case 28: return offsetofPPC32GuestState(guest_GPR28_ext);
+ case 29: return offsetofPPC32GuestState(guest_GPR29_ext);
+ case 30: return offsetofPPC32GuestState(guest_GPR30_ext);
+ case 31: return offsetofPPC32GuestState(guest_GPR31_ext);
+ default: break;
+ }
+ vpanic("extGuestRegOffset(ppc,be)"); /*notreached*/
+}
+
+/* load from an extended reg (SPE) */
+static IRExpr* getExtIReg ( UInt archreg )
+{
+ vassert(archreg < 32);
+ return IRExpr_Get( extGuestRegOffset(archreg), Ity_I32 );
+}
+
+/* Write to an extended reg (SPE) */
+static void putExtIReg ( UInt archreg, IRExpr* e )
+{
+ vassert(archreg < 32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32 );
+ stmt( IRStmt_Put(extGuestRegOffset(archreg), e) );
+}
+
static Int floatGuestRegOffset ( UInt archreg )
{
@@ -1174,6 +1260,18 @@ static IRExpr* ea_rAor0_simm ( UInt rA,
}
}
+/* Standard effective address calc: (rA|0) + uimm5*mult */
+static IRExpr* ea_rAor0_uimm5 ( UInt rA, UChar uimm5, UChar mult )
+{
+ UInt offset = uimm5 * mult;
+ vassert(rA < 32);
+ if (rA == 0) {
+ return mkU16(offset);
+ } else {
+ return ea_rA_simm( rA, offset ); // take advantage that s=0
+ }
+}
+
/* Align effective address */
static IRExpr* addr_align( IRExpr* addr, UChar align )
@@ -8875,7 +8973,217 @@ static Bool dis_av_fp_convert ( UInt the
return True;
}
+static Bool dis_sp_load ( UInt theInstr )
+{
+ UChar opc1 = ifieldOPC(theInstr);
+ UChar rD_addr = ifieldRegDS(theInstr);
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+ UChar uimm5 = ifieldUIMM5(theInstr);
+ UChar b0 = ifieldBIT0(theInstr);
+
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ IRTemp EA = newTemp(ty);
+
+ if (b0) // offset
+ assign( EA, ea_rAor0_uimm5( rA_addr, uimm5, 8 ) ); // need a
better way for ev*splat
+ else // indexed
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+ vassert (opc1==0x04);
+
+ switch (opc2) { // only handles load Dword insns for now.
+ case 0x300: // evlddx (Vector Load DWord into DWord, Indexed, SPEPEM 5-113)
+ DIP("evlddx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ break;
+ case 0x301: // evldd (Vector Load DWord into Dword, SPEPEM 5-112)
+ DIP("evldd r%u,%d(r%u)\n", rD_addr, uimm5*8, rA_addr);
+ break;
+ case 0x302: // evldwx (Vector Load DWord into two words, Indexed,
SPEPEM 5-115)
+ DIP("evldwx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ break;
+ case 0x303: // evldw (Vector Load DWord into two words, SPEPEM 5-114)
+ DIP("evldw r%u,%d(r%u)\n", rD_addr, uimm5*8, rA_addr);
+ break;
+ case 0x304: // evldhx (Vector Load DWord into four half-words,
Indexed, SPEPEM 5-117)
+ DIP("evldhx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ break;
+ case 0x305: // evldh (Vector Load DWord into four half-words, SPEPEM 5-116)
+ DIP("evldh r%u,%d(r%u)\n", rD_addr, uimm5*8, rA_addr);
+ break;
+ default:
+ vex_printf("dis_sp_load(ppc)(opc2)\n");
+ return False;
+ }
+// for BigEndian, all evld* boil down to the same thing.
+ putExtIReg( rD_addr, loadBE(Ity_I32, mkexpr(EA)) );
+ putIReg( rD_addr, loadBE( Ity_I32, binop(Iop_Add32, mkexpr(EA),
mkU32(4)) ) );
+ return True;
+}
+
+static Bool dis_sp_store ( UInt theInstr )
+{
+ UChar opc1 = ifieldOPC(theInstr);
+ UChar rS_addr = ifieldRegDS(theInstr);
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+ UChar uimm5 = ifieldUIMM5(theInstr);
+ UChar b0 = ifieldBIT0(theInstr);
+
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ IRTemp EA = newTemp(ty);
+ IRTemp rS0 = newTemp(Ity_I32);
+ IRTemp rS1 = newTemp(Ity_I32);
+
+ assign( rS0, getIReg(rS_addr) );
+ assign( rS1, getExtIReg(rS_addr) );
+
+ if (b0) // offset
+ assign( EA, ea_rAor0_uimm5( rA_addr, uimm5, 8 ) ); // need a
better way for ev*splat
+ else // indexed
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+
+ vassert (opc1==0x04);
+
+ switch (opc2) { // only handles store Double insns for now.
+ case 0x320: // evstddx (Vector Store Double of Double, Indexed,
SPEPEM 5-229)
+ DIP("evstddx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ break;
+ case 0x321: // evstdd (Vector Store Double of Double, SPEPEM 5-228)
+ DIP("evstdd r%u,%d(r%u)\n", rS_addr, uimm5*8, rA_addr);
+ break;
+ case 0x322: // evstwdx (Vector Store Double of Two Words, Indexed,
SPEPEM 5-233)
+ DIP("evstdwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ break;
+ case 0x323: // evstdw (Vector Store Double of Two Words, SPEPEM 5-232)
+ DIP("evstdw r%u,%d(r%u)\n", rS_addr, uimm5*8, rA_addr);
+ break;
+ case 0x324: // evstdhx (Vector Store Double of four halfwords,
Indexed, SPEPEM 5-231)
+ DIP("evstdhx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ break;
+ case 0x325: // evstdh (Vector Store Double of four halfwords, SPEPEM 5-230)
+ DIP("evstdh r%u,%d(r%u)\n", rS_addr, uimm5*8, rA_addr);
+ break;
+ default:
+ vex_printf("dis_sp_store(ppc)(opc2)\n");
+ return False;
+ }
+// for BigEndian, all evst* boil down to the same thing.
+ storeBE( mkexpr(EA), mkexpr(rS1) );
+ storeBE( binop(Iop_Add32, mkexpr(EA), mkU32(4)), mkexpr(rS0) );
+ return True;
+}
+
+static Bool dis_sp_fp ( UInt theInstr )
+{
+ UChar opc1 = ifieldOPC(theInstr);
+ UChar rD_addr = ifieldRegDS(theInstr);
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+
+ IRTemp frA = newTemp(Ity_F64);
+ IRTemp frB = newTemp(Ity_F64);
+ IRTemp frD = newTemp(Ity_F64);
+ IRExpr* rm = get_IR_roundingmode();
+
+ vassert (opc1==0x04);
+
+ assign( frA, unop(Iop_F32toF64, getSPReg(rA_addr)));
+ assign( frB, unop(Iop_F32toF64, getSPReg(rB_addr)));
+
+ switch (opc2) { // only handles efs* for now.
+ case 0x2C0: // efsadd (Floating-Point Add, SPEPEM 5-46)
+ DIP("efsadd r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ assign( frD, triop( Iop_AddF64r32,
+ rm, mkexpr(frA), mkexpr(frB) ));
+ break;
+ case 0x2C9: // efsdiv (Floating-Point Divide, SPEPEM 5-60)
+ DIP("efsdiv r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ assign( frD, triop( Iop_DivF64r32,
+ rm, mkexpr(frA), mkexpr(frB) ));
+ break;
+ case 0x2C8: // efsmul (Floating-Point Multiply, SPEPEM 5-61)
+ DIP("efsmul r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ assign( frD, triop( Iop_MulF64r32,
+ rm, mkexpr(frA), mkexpr(frB) ));
+ break;
+ case 0x2C1: // efssub (Floating-Point Subtract, SPEPEM 5-64)
+ DIP("efssub r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ assign( frD, triop( Iop_SubF64r32,
+ rm, mkexpr(frA), mkexpr(frB) ));
+ break;
+ default:
+ vex_printf("dis_sp_fp(ppc)(opc2)\n");
+ return False;
+ }
+ putSPReg(rD_addr, unop(Iop_TruncF64asF32, mkexpr(frD)) );
+ return True;
+}
+
+/* SPE conversion instructions */
+static Bool dis_sp_cvt ( UInt theInstr )
+{
+ UChar opc1 = ifieldOPC(theInstr);
+ UChar rD_addr = ifieldRegDS(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+
+ IRTemp rD = newTemp(Ity_I32);
+ IRTemp rB = newTemp(Ity_F32);
+ IRExpr* rm = get_IR_roundingmode();
+ IRTemp frac = newTemp(Ity_I1);
+ IRTemp syned = newTemp(Ity_I1);
+ IRTemp rmz = newTemp(Ity_I32);
+
+ vassert (opc1==0x04);
+
+ assign( rB, getSPReg(rB_addr));
+ assign( rmz, mkU32(Irrm_ZERO)); // force rounding mode "to zero" ?
+
+ switch (opc2) {
+ case 0x2D7: // efsctsf (Convert Floating-Point to Signed Fraction,
SPEPEM 5-54)
+ DIP("efsctsf r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(True)); // convert to fraction
+ assign( syned, mkU1(False)); // Signed result
+ break;
+ case 0x2D5: // efsctsi (Convert Floating-Point to Signed Integer,
SPEPEM 5-55)
+ DIP("efsctsi r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(False)); // convert to fraction
+ assign( syned, mkU1(False)); // Signed result
+ break;
+ case 0x2DA: // efsctsiz (Convert Floating-Point to Signed Integer
with Round toward Zero, SPEPEM 5-56)
+ DIP("efsctsiz r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(False)); // convert to fraction
+ assign( syned, mkU1(False)); // Signed result
+ rm = mkexpr(rmz); // force round to zero
+ break;
+ case 0x2D6: // efsctuf (Convert Floating-Point to Unsigned
Fraction, SPEPEM 5-57)
+ DIP("efsctuf r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(True)); // convert to fraction
+ assign( syned, mkU1(True)); // Unsigned result
+ break;
+ case 0x2D4: // efsctui (Convert Floating-Point to Unsigned
Integer, SPEPEM 5-58)
+ DIP("efsctui r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(True)); // convert to fraction
+ assign( syned, mkU1(True)); // Unsigned result
+ break;
+ case 0x2D8: // efsctuiz (Convert Floating-Point to Unsigned
Integer with Round toward Zero, SPEPEM 5-59)
+ DIP("efsctuiz r%u,r%u\n", rD_addr, rB_addr);
+ assign( frac, mkU1(True)); // convert to fraction
+ assign( syned, mkU1(True)); // Unsigned result
+ rm = mkexpr(rmz); // force round to zero
+ break;
+ default:
+ vex_printf("dis_sp_cvt(ppc)(opc2)\n");
+ return False;
+ }
+ assign (rD, qop( Iop_F32toI32, mkexpr(rB), rm, mkexpr(frac),
mkexpr(syned)));
+ putIReg(rD_addr, mkexpr(rD));
+ return True;
+}
/*------------------------------------------------------------*/
/*--- POWER6 Instruction Translation ---*/
@@ -8968,6 +9276,7 @@ DisResult disInstr_PPC_WRK (
Bool allow_V = False;
Bool allow_FX = False;
Bool allow_GX = False;
+ Bool allow_SP = False;
UInt hwcaps = archinfo->hwcaps;
Long delta;
@@ -8982,6 +9291,7 @@ DisResult disInstr_PPC_WRK (
allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));
allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC32_FX));
allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC32_GX));
+ allow_SP = (0 != (hwcaps & VEX_HWCAPS_PPC32_SP));
}
/* The running delta */
@@ -9534,7 +9844,60 @@ DisResult disInstr_PPC_WRK (
case 0x04:
- /* AltiVec instructions */
+ /* AltiVec or SPE instructions */
+
+ if (allow_SP) { // Altivec and SPE are mutually exclusive, as
+ // the instruction opcodes overlap
+ opc2 = IFIELD(theInstr, 0, 11);
+
+ switch (opc2) {
+ /* SPE Load */
+ case 0x300: case 0x301: // evlddx, evldd
+ case 0x302: case 0x303: // evldwx, evldw
+ case 0x304: case 0x305: // evldhx, evldh
+ case 0x308: case 0x309: // evlhhesplatx, evlhhesplat
+ case 0x30D: case 0x30C: // evlhhousplatx, evlhhousplat
+ case 0x30E: case 0x30F: // evlhhossplatx, evlhhossplat
+ case 0x310: case 0x311: // evlwhex, evlwhe
+ case 0x314: case 0x315: // evlwhoux, evlwhou
+ case 0x316: case 0x317: // evlwhosx, evlwhos
+ case 0x318: case 0x319: // evlwwsplatx, evlwwsplat
+ case 0x31C: case 0x31D: // evlwhsplatx, evlwhsplat
+ if (dis_sp_load( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* SPE Store */
+ case 0x320: case 0x321: // evstddx, evstdd
+ case 0x322: case 0x323: // evstdwx, evstdw
+ case 0x324: case 0x325: // evstdhx, evstdh
+ case 0x330: case 0x331: // evstwhex, evstwhe
+ case 0x334: case 0x335: // evstwhox, evstwho
+ case 0x338: case 0x339: // evstwwex, evstwwe
+ case 0x33C: case 0x33D: // evstwwox, evstwwo
+ if (dis_sp_store( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* SPE Arith */
+ case 0x2C0: case 0x2C1: // efsadd, efssub
+ case 0x2C8: case 0x2C9: // efsmul, efsdiv
+ if (dis_sp_fp( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* SPE Convert */
+ case 0x2D4: case 0x2D5: // efsctui, efsctsi
+ case 0x2D6: case 0x2D7: // efsctuf, efsctsf
+ case 0x2D8: case 0x2DA: // efsctuiz, efsctsiz
+ if (dis_sp_cvt( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ default:
+ vex_printf("disInstr(ppc): "
+ "declined to decode a SignalProcessing-Optional insn.\n");
+ goto decode_failure;
+ }
+ }
+
+ /* else, assume Altivec insn */
opc2 = IFIELD(theInstr, 0, 6);
switch (opc2) {
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/host_generic_regs.h
vg2/valgrind-3.5.0/VEX/priv/host_generic_regs.h
--- vg1/valgrind-3.5.0/VEX/priv/host_generic_regs.h Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/host_generic_regs.h Fri Jul 16 11:12:21 2010
@@ -104,9 +104,10 @@ typedef
HRcINVALID=1, /* NOT A VALID REGISTER CLASS */
HRcInt32=4, /* 32-bit int */
HRcInt64=5, /* 64-bit int */
- HRcFlt64=6, /* 64-bit float */
- HRcVec64=7, /* 64-bit SIMD */
- HRcVec128=8 /* 128-bit SIMD */
+ HRcFlt32=6, /* 32-bit float */
+ HRcFlt64=7, /* 64-bit float */
+ HRcVec64=8, /* 64-bit SIMD */
+ HRcVec128=9 /* 128-bit SIMD */
}
HRegClass;
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/host_ppc_defs.c
vg2/valgrind-3.5.0/VEX/priv/host_ppc_defs.c
--- vg1/valgrind-3.5.0/VEX/priv/host_ppc_defs.c Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/host_ppc_defs.c Sat Jul 17 11:16:35 2010
@@ -984,6 +984,16 @@ PPCInstr* PPCInstr_FpCftI ( Bool fromI,
vassert(!(int32 && fromI)); /* no such insn ("fcfiw"). */
return i;
}
+PPCInstr* PPCInstr_FpCstI ( Bool frac, Bool syned,
+ HReg dst, HReg src ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_FpCstI;
+ i->Pin.FpCstI.frac = frac;
+ i->Pin.FpCstI.syned = syned;
+ i->Pin.FpCstI.dst = dst;
+ i->Pin.FpCstI.src = src;
+ return i;
+}
PPCInstr* PPCInstr_FpCMov ( PPCCondCode cond, HReg dst, HReg src ) {
PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
i->tag = Pin_FpCMov;
@@ -1459,6 +1469,19 @@ void ppPPCInstr ( PPCInstr* i, Bool mode
ppHRegPPC(i->Pin.FpCftI.src);
return;
}
+ case Pin_FpCstI: {
+ HChar* str_f = "i";
+ HChar* str_s = "u";
+ if (i->Pin.FpCstI.frac)
+ str_f = "f";
+ if (i->Pin.FpCstI.syned)
+ str_s = "s";
+ vex_printf("efsct%s%s ", str_s, str_f);
+ ppHRegPPC(i->Pin.FpCstI.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.FpCstI.src);
+ return;
+ }
case Pin_FpCMov:
vex_printf("fpcmov (%s) ", showPPCCondCode(i->Pin.FpCMov.cond));
ppHRegPPC(i->Pin.FpCMov.dst);
@@ -1815,6 +1838,10 @@ void getRegUsage_PPCInstr ( HRegUsage* u
addHRegUse(u, HRmWrite, i->Pin.FpCftI.dst);
addHRegUse(u, HRmRead, i->Pin.FpCftI.src);
return;
+ case Pin_FpCstI:
+ addHRegUse(u, HRmWrite, i->Pin.FpCstI.dst);
+ addHRegUse(u, HRmRead, i->Pin.FpCstI.src);
+ return;
case Pin_FpCMov:
addHRegUse(u, HRmModify, i->Pin.FpCMov.dst);
addHRegUse(u, HRmRead, i->Pin.FpCMov.src);
@@ -2026,6 +2053,9 @@ void mapRegs_PPCInstr ( HRegRemap* m, PP
case Pin_FpCftI:
mapReg(m, &i->Pin.FpCftI.dst);
mapReg(m, &i->Pin.FpCftI.src);
+ case Pin_FpCstI:
+ mapReg(m, &i->Pin.FpCstI.dst);
+ mapReg(m, &i->Pin.FpCstI.src);
return;
case Pin_FpCMov:
mapReg(m, &i->Pin.FpCMov.dst);
@@ -3389,6 +3419,20 @@ Int emit_PPCInstr ( UChar* buf, Int nbuf
goto done;
}
goto bad;
+ }
+
+ case Pin_FpCstI: {
+ UInt opc2 = 0x16A;
+ UInt opc3 = 0;
+ UInt ir_dst = iregNo(i->Pin.FpCstI.dst, Ity_I32);
+ UInt ir_src = iregNo(i->Pin.FpCstI.src, Ity_I32);
+ if (i->Pin.FpCstI.frac)
+ opc2++;
+ if (i->Pin.FpCstI.syned)
+ opc3++;
+
+ p = mkFormX(p, 0x04, ir_dst, 0, ir_src, opc2, opc3);
+ goto done;
}
case Pin_FpCMov: {
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/host_ppc_defs.h
vg2/valgrind-3.5.0/VEX/priv/host_ppc_defs.h
--- vg1/valgrind-3.5.0/VEX/priv/host_ppc_defs.h Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/host_ppc_defs.h Sat Jul 17 10:59:31 2010
@@ -473,6 +473,7 @@ typedef
Pin_FpSTFIW, /* stfiwx */
Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */
Pin_FpCftI, /* fcfid/fctid/fctiw */
+ Pin_FpCstI, /* evfsct[sf, si, siz, uf, ui, uiz] */
Pin_FpCMov, /* FP floating point conditional move */
Pin_FpLdFPSCR, /* mtfsf */
Pin_FpCmp, /* FP compare, generating value into int reg */
@@ -681,6 +682,13 @@ typedef
HReg src;
HReg dst;
} FpCftI;
+/* evfsct[sf, si, siz, uf, ui, uiz] */
+ struct {
+ Bool frac; /* False==Integer, True==fraction */
+ Bool syned; /* True==signed conversion, False==unsigned */
+ HReg src;
+ HReg dst;
+ } FpCstI;
/* FP mov src to dst on the given condition. */
struct {
PPCCondCode cond;
@@ -823,6 +831,8 @@ extern PPCInstr* PPCInstr_FpLdSt ( B
extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data );
extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32,
+ HReg dst, HReg src );
+extern PPCInstr* PPCInstr_FpCstI ( Bool frac, Bool syned,
HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src );
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/priv/host_ppc_isel.c
vg2/valgrind-3.5.0/VEX/priv/host_ppc_isel.c
--- vg1/valgrind-3.5.0/VEX/priv/host_ppc_isel.c Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/host_ppc_isel.c Sat Jul 17 11:52:08 2010
@@ -326,6 +326,13 @@ static HReg newVRegF ( ISelEnv* env )
return reg;
}
+static HReg newVRegS ( ISelEnv* env )
+{
+ HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/);
+ env->vreg_ctr++;
+ return reg;
+}
+
static HReg newVRegV ( ISelEnv* env )
{
HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
@@ -1197,6 +1204,32 @@ static HReg iselWordExpr_R_wrk ( ISelEnv
return r_dst;
/*NOTREACHED*/
+ }
+
+ /* --------- QUAD OP --------- */
+ case Iex_Qop: {
+ if (e->Iex.Qop.op == Iop_F32toI32) {
+ HReg fsrc = iselFltExpr(env, e->Iex.Qop.arg1);
+ HReg idst = newVRegI(env);
+ IRExpr* fr = e->Iex.Qop.arg3;
+ IRExpr* sy = e->Iex.Qop.arg4;
+
+ Bool frac = fr->Iex.Const.con->Ico.U1;
+ Bool syned = sy->Iex.Const.con->Ico.U1;
+
+ vassert( fr->tag == Iex_Const );
+ vassert( fr->Iex.Const.con->tag == Ico_U1 );
+ vassert( sy->tag == Iex_Const );
+ vassert( sy->Iex.Const.con->tag == Ico_U1 );
+
+ /* Set host rounding mode */
+ set_FPU_rounding_mode( env, e->Iex.Qop.arg2 );
+
+ addInstr(env, PPCInstr_FpCstI(frac, syned, idst, fsrc));
+
+ return idst;
+ }
+ break;
}
/* --------- BINARY OP --------- */
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/VEX/priv/ir_defs.c
vg2/valgrind-3.5.0/VEX/priv/ir_defs.c
--- vg1/valgrind-3.5.0/VEX/priv/ir_defs.c Wed Aug 19 06:37:52 2009
+++ vg2/valgrind-3.5.0/VEX/priv/ir_defs.c Mon Jul 19 18:12:04 2010
@@ -291,6 +291,8 @@ void ppIROp ( IROp op )
case Iop_CmpF64: vex_printf("CmpF64"); return;
+ case Iop_F32toI32: vex_printf("F32toI32"); return;
+ case Iop_F32toUI32: vex_printf("F32toUI32"); return;
case Iop_F64toI16: vex_printf("F64toI16"); return;
case Iop_F64toI32: vex_printf("F64toI32"); return;
case Iop_F64toI64: vex_printf("F64toI64"); return;
@@ -1768,6 +1770,8 @@ void typeOfPrimop ( IROp op,
case Iop_CmpF64:
BINARY(Ity_F64,Ity_F64, Ity_I32);
+ case Iop_F32toI32: QUATERNARY(Ity_F32, Ity_I32, Ity_I1, Ity_I1, Ity_I32);
+ case Iop_F32toUI32: BINARY(ity_RMode, Ity_F32, Ity_I32);
case Iop_F64toI16: BINARY(ity_RMode,Ity_F64, Ity_I16);
case Iop_F64toI32: BINARY(ity_RMode,Ity_F64, Ity_I32);
case Iop_F64toI64: BINARY(ity_RMode,Ity_F64, Ity_I64);
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/VEX/priv/main_main.c
vg2/valgrind-3.5.0/VEX/priv/main_main.c
--- vg1/valgrind-3.5.0/VEX/priv/main_main.c Mon Jul 12 15:28:02 2010
+++ vg2/valgrind-3.5.0/VEX/priv/main_main.c Mon Jul 12 15:32:43 2010
@@ -755,17 +755,23 @@ static HChar* show_hwcaps_amd64 ( UInt h
static HChar* show_hwcaps_ppc32 ( UInt hwcaps )
{
/* Monotonic with complications. Basically V > F > baseline,
- but once you have F then you can have FX or GX too. */
+ but once you have F then you can have FX and/or GX and/or SPE too. */
+ /* I don't think you will find SPE with V, nor on PPC64 */
const UInt F = VEX_HWCAPS_PPC32_F;
const UInt V = VEX_HWCAPS_PPC32_V;
const UInt FX = VEX_HWCAPS_PPC32_FX;
const UInt GX = VEX_HWCAPS_PPC32_GX;
+ const UInt SP = VEX_HWCAPS_PPC32_SP;
UInt c = hwcaps;
if (c == 0) return "ppc32-int";
if (c == F) return "ppc32-int-flt";
if (c == (F|FX)) return "ppc32-int-flt-FX";
if (c == (F|GX)) return "ppc32-int-flt-GX";
+ if (c == (F|SP)) return "ppc32-int-flt-SPE";
if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX";
+ if (c == (F|FX|SP)) return "ppc32-int-flt-FX-SPE";
+ if (c == (F|GX|SP)) return "ppc32-int-flt-GX-SPE";
+ if (c == (F|FX|GX|SP)) return "ppc32-int-flt-FX-GX-SPE";
if (c == (F|V)) return "ppc32-int-flt-vmx";
if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX";
if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX";
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/VEX/pub/libvex.h
vg2/valgrind-3.5.0/VEX/pub/libvex.h
--- vg1/valgrind-3.5.0/VEX/pub/libvex.h Mon Jul 12 15:28:02 2010
+++ vg2/valgrind-3.5.0/VEX/pub/libvex.h Mon Jul 12 15:32:43 2010
@@ -95,11 +95,12 @@ typedef
#define VEX_HWCAPS_PPC32_FX (1<<8) /* FP extns (fsqrt, fsqrts) */
#define VEX_HWCAPS_PPC32_GX (1<<9) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
+#define VEX_HWCAPS_PPC32_SP (1<<10) /* SPE (Signal Processing extns) */
/* ppc64: baseline capability is integer and basic FP insns */
-#define VEX_HWCAPS_PPC64_V (1<<10) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC64_FX (1<<11) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC64_GX (1<<12) /* Graphics extns
+#define VEX_HWCAPS_PPC64_V (1<<11) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC64_FX (1<<12) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC64_GX (1<<13) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
/* arm: baseline capability is ARMv4 */
diff -x *~ -x cscope* -purN
vg1/valgrind-3.5.0/VEX/pub/libvex_guest_ppc32.h
vg2/valgrind-3.5.0/VEX/pub/libvex_guest_ppc32.h
--- vg1/valgrind-3.5.0/VEX/pub/libvex_guest_ppc32.h Mon Jul 12 15:28:02 2010
+++ vg2/valgrind-3.5.0/VEX/pub/libvex_guest_ppc32.h Tue Jul 13 10:55:14 2010
@@ -53,6 +53,7 @@
/*---------------------------------------------------------------*/
/*--- Vex's representation of the PPC32 CPU state ---*/
+/*--- The *_ext are register extensions to 64 bit, for SPE ---*/
/*---------------------------------------------------------------*/
#define VEX_GUEST_PPC32_REDIR_STACK_SIZE (16/*entries*/ * 2/*words per entry*/)
@@ -232,6 +233,40 @@ typedef
/* SPRG3, which AIUI is readonly in user space. Needed for
threading on AIX. */
/* ??? */ UInt guest_SPRG3_RO;
+
+ /* General Purpose Registers Extensions */
+ /* ??? */ UInt guest_GPR0_ext;
+ /* ??? */ UInt guest_GPR1_ext;
+ /* ??? */ UInt guest_GPR2_ext;
+ /* ??? */ UInt guest_GPR3_ext;
+ /* ??? */ UInt guest_GPR4_ext;
+ /* ??? */ UInt guest_GPR5_ext;
+ /* ??? */ UInt guest_GPR6_ext;
+ /* ??? */ UInt guest_GPR7_ext;
+ /* ??? */ UInt guest_GPR8_ext;
+ /* ??? */ UInt guest_GPR9_ext;
+ /* ??? */ UInt guest_GPR10_ext;
+ /* ??? */ UInt guest_GPR11_ext;
+ /* ??? */ UInt guest_GPR12_ext;
+ /* ??? */ UInt guest_GPR13_ext;
+ /* ??? */ UInt guest_GPR14_ext;
+ /* ??? */ UInt guest_GPR15_ext;
+ /* ??? */ UInt guest_GPR16_ext;
+ /* ??? */ UInt guest_GPR17_ext;
+ /* ??? */ UInt guest_GPR18_ext;
+ /* ??? */ UInt guest_GPR19_ext;
+ /* ??? */ UInt guest_GPR20_ext;
+ /* ??? */ UInt guest_GPR21_ext;
+ /* ??? */ UInt guest_GPR22_ext;
+ /* ??? */ UInt guest_GPR23_ext;
+ /* ??? */ UInt guest_GPR24_ext;
+ /* ??? */ UInt guest_GPR25_ext;
+ /* ??? */ UInt guest_GPR26_ext;
+ /* ??? */ UInt guest_GPR27_ext;
+ /* ??? */ UInt guest_GPR28_ext;
+ /* ??? */ UInt guest_GPR29_ext;
+ /* ??? */ UInt guest_GPR30_ext;
+ /* ??? */ UInt guest_GPR31_ext;
/* Padding to make it have an 8-aligned size */
/* UInt padding; */
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/VEX/pub/libvex_ir.h
vg2/valgrind-3.5.0/VEX/pub/libvex_ir.h
--- vg1/valgrind-3.5.0/VEX/pub/libvex_ir.h Wed Aug 19 06:37:53 2009
+++ vg2/valgrind-3.5.0/VEX/pub/libvex_ir.h Wed Jul 14 17:53:54 2010
@@ -582,6 +582,8 @@ typedef
represent exactly all values of the source type.
*/
Iop_F64toI16, /* IRRoundingMode(I32) x F64 -> I16 */
+ Iop_F32toUI32, /* F32 -> unsigned I32 */
+ Iop_F32toI32, /* F32 -> I32 */
Iop_F64toI32, /* IRRoundingMode(I32) x F64 -> I32 */
Iop_F64toI64, /* IRRoundingMode(I32) x F64 -> I64 */
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/coregrind/m_machine.c
vg2/valgrind-3.5.0/coregrind/m_machine.c
--- vg1/valgrind-3.5.0/coregrind/m_machine.c Mon Jul 12 15:28:02 2010
+++ vg2/valgrind-3.5.0/coregrind/m_machine.c Mon Jul 12 15:32:43 2010
@@ -444,7 +444,7 @@ Bool VG_(machine_get_hwcaps)( void )
vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act;
vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act;
- volatile Bool have_F, have_V, have_FX, have_GX;
+ volatile Bool have_F, have_V, have_FX, have_GX, have_SP;
Int r;
/* This is a kludge. Really we ought to back-convert saved_act
@@ -523,6 +523,14 @@ Bool VG_(machine_get_hwcaps)( void )
__asm__ __volatile__(".long 0xFC000034"); /* frsqrte 0,0 */
}
+ /* Signal Processing optional */
+ have_SP = True;
+ if (__builtin_setjmp(env_unsup_insn)) {
+ have_SP = False;
+ } else {
+ __asm__ __volatile__(".long 0x10000217"); /* evor 0,0,0 */
+ }
+
r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
vg_assert(r == 0);
r = VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
@@ -538,6 +546,8 @@ Bool VG_(machine_get_hwcaps)( void )
have_FX = False;
if (have_GX && !have_F)
have_GX = False;
+ if (have_SP && !have_F)
+ have_SP = False;
VG_(machine_ppc32_has_FP) = have_F ? 1 : 0;
VG_(machine_ppc32_has_VMX) = have_V ? 1 : 0;
@@ -549,6 +559,7 @@ Bool VG_(machine_get_hwcaps)( void )
if (have_V) vai.hwcaps |= VEX_HWCAPS_PPC32_V;
if (have_FX) vai.hwcaps |= VEX_HWCAPS_PPC32_FX;
if (have_GX) vai.hwcaps |= VEX_HWCAPS_PPC32_GX;
+ if (have_SP) vai.hwcaps |= VEX_HWCAPS_PPC32_SP;
/* But we're not done yet: VG_(machine_ppc32_set_clszB) must be
called before we're ready to go. */
diff -x *~ -x cscope* -purN vg1/valgrind-3.5.0/memcheck/mc_translate.c
vg2/valgrind-3.5.0/memcheck/mc_translate.c
--- vg1/valgrind-3.5.0/memcheck/mc_translate.c Wed Aug 19 06:37:02 2009
+++ vg2/valgrind-3.5.0/memcheck/mc_translate.c Tue Jul 20 02:28:21 2010
@@ -2013,6 +2013,10 @@ IRAtom* expr2vbits_Qop ( MCEnv* mce,
case Iop_MSubF64r32:
/* I32(rm) x F64 x F64 x F64 -> F64 */
return mkLazy4(mce, Ity_I64, vatom1, vatom2, vatom3, vatom4);
+ case Iop_F32toI32:
+ /* F32 x I32(rm) x U1 x U1 -> I32 */
+ /* atoms 3 & 4 are instruction selectors, not used in computation */
+ return mkLazy2(mce, Ity_I32, vatom1, vatom2);
default:
ppIROp(op);
VG_(tool_panic)("memcheck:expr2vbits_Qop");
|
|
From: <sv...@va...> - 2010-07-29 18:12:30
|
Author: bart
Date: 2010-07-29 19:12:23 +0100 (Thu, 29 Jul 2010)
New Revision: 11243
Log:
Avoid that gcc 4.5.x reports the warning "taking address of expression of type void". Tested on amd64 and on ppc64.
Modified:
trunk/coregrind/pub_core_dispatch.h
trunk/coregrind/pub_core_trampoline.h
Modified: trunk/coregrind/pub_core_dispatch.h
===================================================================
--- trunk/coregrind/pub_core_dispatch.h 2010-07-29 15:55:09 UTC (rev 11242)
+++ trunk/coregrind/pub_core_dispatch.h 2010-07-29 18:12:23 UTC (rev 11243)
@@ -68,8 +68,8 @@
following somewhat bogus decls. At least on x86 and amd64. ppc32
and ppc64 use straightforward bl-blr to get from dispatcher to
translation and back and so do not need these labels. */
-extern void VG_(run_innerloop__dispatch_unprofiled);
-extern void VG_(run_innerloop__dispatch_profiled);
+extern Addr VG_(run_innerloop__dispatch_unprofiled);
+extern Addr VG_(run_innerloop__dispatch_profiled);
#endif
@@ -86,7 +86,7 @@
/* We need to a label inside VG_(run_a_noredir_translation), so that
Vex can add branches to them from generated code. Hence the
following somewhat bogus decl. */
-extern void VG_(run_a_noredir_translation__return_point);
+extern Addr VG_(run_a_noredir_translation__return_point);
#endif
Modified: trunk/coregrind/pub_core_trampoline.h
===================================================================
--- trunk/coregrind/pub_core_trampoline.h 2010-07-29 15:55:09 UTC (rev 11242)
+++ trunk/coregrind/pub_core_trampoline.h 2010-07-29 18:12:23 UTC (rev 11243)
@@ -53,32 +53,32 @@
readable, at least. Otherwise Memcheck complains we're jumping to
invalid addresses. */
-extern void VG_(trampoline_stuff_start);
-extern void VG_(trampoline_stuff_end);
+extern Addr VG_(trampoline_stuff_start);
+extern Addr VG_(trampoline_stuff_end);
#if defined(VGP_x86_linux)
-extern void VG_(x86_linux_SUBST_FOR_sigreturn);
-extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(x86_linux_SUBST_FOR_sigreturn);
+extern Addr VG_(x86_linux_SUBST_FOR_rt_sigreturn);
extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int );
#endif
#if defined(VGP_amd64_linux)
-extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
-extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday);
-extern void VG_(amd64_linux_REDIR_FOR_vtime);
+extern Addr VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(amd64_linux_REDIR_FOR_vgettimeofday);
+extern Addr VG_(amd64_linux_REDIR_FOR_vtime);
extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
#endif
#if defined(VGP_ppc32_linux)
-extern void VG_(ppc32_linux_SUBST_FOR_sigreturn);
-extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(ppc32_linux_SUBST_FOR_sigreturn);
+extern Addr VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);
extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* );
extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
#endif
#if defined(VGP_ppc64_linux)
-extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
/* A label (sans dot) marking the ultra-magical return stub via which
@@ -88,7 +88,7 @@
restore the thread's LR and R2 registers from a small stack in the
ppc64 guest state structure, and then branch to LR. Convoluted?
Confusing? You betcha. Could I think of anything simpler? No. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);
#endif
#if defined(VGP_arm_linux)
@@ -105,22 +105,22 @@
then it cleans up the register state to be more what it really
should be at client startup, and finally it jumps to the client's
real entry point. */
-extern void VG_(ppc32_aix5_do_preloads_then_start_client);
+extern Addr VG_(ppc32_aix5_do_preloads_then_start_client);
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);
#endif
#if defined(VGP_ppc64_aix5)
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);
/* See comment for ppc32_aix5 equivalent above. */
-extern void VG_(ppc64_aix5_do_preloads_then_start_client);
+extern Addr VG_(ppc64_aix5_do_preloads_then_start_client);
#endif
#if defined(VGP_x86_darwin)
-extern void VG_(x86_darwin_SUBST_FOR_sigreturn);
+extern Addr VG_(x86_darwin_SUBST_FOR_sigreturn);
extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * );
@@ -130,7 +130,7 @@
#endif
#if defined(VGP_amd64_darwin)
-extern void VG_(amd64_darwin_SUBST_FOR_sigreturn);
+extern Addr VG_(amd64_darwin_SUBST_FOR_sigreturn);
extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * );
|
|
From: <sv...@va...> - 2010-07-29 18:11:00
|
Author: sewardj
Date: 2010-07-29 19:10:51 +0100 (Thu, 29 Jul 2010)
New Revision: 1997
Log:
Don't trash the ELF ABI redzone for amd64 when emulating BT{,S,R,C}
reg,reg. Fixes (well, at least, makes an appalling kludge a bit less
appalling) #245925.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_x86_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-07-29 16:12:41 UTC (rev 1996)
+++ trunk/priv/guest_amd64_toIR.c 2010-07-29 18:10:51 UTC (rev 1997)
@@ -7367,11 +7367,25 @@
if (epartIsReg(modrm)) {
delta++;
- /* Get it onto the client's stack. */
+ /* Get it onto the client's stack. Oh, this is a horrible
+ kludge. See https://bugs.kde.org/show_bug.cgi?id=245925.
+ Because of the ELF ABI stack redzone, there may be live data
+ up to 128 bytes below %RSP. So we can't just push it on the
+ stack, else we may wind up trashing live data, and causing
+ impossible-to-find simulation errors. (Yes, this did
+ happen.) So we need to drop RSP before at least 128 before
+ pushing it. That unfortunately means hitting Memcheck's
+ fast-case painting code. Ideally we should drop more than
+ 128, to reduce the chances of breaking buggy programs that
+ have live data below -128(%RSP). Memcheck fast-cases moves
+ of 288 bytes due to the need to handle ppc64-linux quickly,
+ so let's use 288. Of course the real fix is to get rid of
+ this kludge entirely. */
t_rsp = newTemp(Ity_I64);
t_addr0 = newTemp(Ity_I64);
- assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(sz)) );
+ vassert(vbi->guest_stack_redzone_size == 128);
+ assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(288)) );
putIReg64(R_RSP, mkexpr(t_rsp));
storeLE( mkexpr(t_rsp), getIRegE(sz, pfx, modrm) );
@@ -7470,7 +7484,7 @@
standard zero-extend rule */
if (op != BtOpNone)
putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) );
- putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(sz)) );
+ putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(288)) );
}
DIP("bt%s%c %s, %s\n",
Modified: trunk/priv/guest_x86_toIR.c
===================================================================
--- trunk/priv/guest_x86_toIR.c 2010-07-29 16:12:41 UTC (rev 1996)
+++ trunk/priv/guest_x86_toIR.c 2010-07-29 18:10:51 UTC (rev 1997)
@@ -6161,7 +6161,8 @@
static
-UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op )
+UInt dis_bt_G_E ( VexAbiInfo* vbi,
+ UChar sorb, Bool locked, Int sz, Int delta, BtOp op )
{
HChar dis_buf[50];
UChar modrm;
@@ -6191,7 +6192,12 @@
t_esp = newTemp(Ity_I32);
t_addr0 = newTemp(Ity_I32);
- assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz)) );
+ /* For the choice of the value 128, see comment in dis_bt_G_E in
+ guest_amd64_toIR.c. We point out here only that 128 is
+ fast-cased in Memcheck and is > 0, so seems like a good
+ choice. */
+ vassert(vbi->guest_stack_redzone_size == 0);
+ assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(128)) );
putIReg(4, R_ESP, mkexpr(t_esp));
storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) );
@@ -6286,7 +6292,7 @@
if (epartIsReg(modrm)) {
/* t_esp still points at it. */
putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) );
- putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(sz)) );
+ putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(128)) );
}
DIP("bt%s%c %s, %s\n",
@@ -7841,7 +7847,8 @@
Bool resteerCisOk,
void* callback_opaque,
Long delta64,
- VexArchInfo* archinfo
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi
)
{
IRType ty;
@@ -14348,16 +14355,16 @@
/* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
case 0xA3: /* BT Gv,Ev */
- delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpNone );
+ delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpNone );
break;
case 0xB3: /* BTR Gv,Ev */
- delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpReset );
+ delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpReset );
break;
case 0xAB: /* BTS Gv,Ev */
- delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpSet );
+ delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpSet );
break;
case 0xBB: /* BTC Gv,Ev */
- delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpComp );
+ delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpComp );
break;
/* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
@@ -15065,7 +15072,8 @@
expect_CAS = False;
dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
resteerCisOk,
- callback_opaque, delta, archinfo );
+ callback_opaque,
+ delta, archinfo, abiinfo );
x2 = irsb_IN->stmts_used;
vassert(x2 >= x1);
@@ -15084,7 +15092,8 @@
vex_traceflags |= VEX_TRACE_FE;
dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
resteerCisOk,
- callback_opaque, delta, archinfo );
+ callback_opaque,
+ delta, archinfo, abiinfo );
for (i = x1; i < x2; i++) {
vex_printf("\t\t");
ppIRStmt(irsb_IN->stmts[i]);
|
|
From: <sv...@va...> - 2010-07-29 16:12:49
|
Author: sewardj
Date: 2010-07-29 17:12:41 +0100 (Thu, 29 Jul 2010)
New Revision: 1996
Log:
Add a folding rule for 32Sto64.
Modified:
trunk/priv/ir_opt.c
Modified: trunk/priv/ir_opt.c
===================================================================
--- trunk/priv/ir_opt.c 2010-07-29 15:39:05 UTC (rev 1995)
+++ trunk/priv/ir_opt.c 2010-07-29 16:12:41 UTC (rev 1996)
@@ -1078,7 +1078,13 @@
0xFFFFFFFFULL
& e->Iex.Unop.arg->Iex.Const.con->Ico.U32));
break;
-
+ case Iop_32Sto64: {
+ /* signed */ Long s64 = e->Iex.Unop.arg->Iex.Const.con->Ico.U32;
+ s64 <<= 32;
+ s64 >>= 32;
+ e2 = IRExpr_Const(IRConst_U64((ULong)s64));
+ break;
+ }
case Iop_CmpNEZ8:
e2 = IRExpr_Const(IRConst_U1(toBool(
0 !=
|
|
From: <sv...@va...> - 2010-07-29 15:55:19
|
Author: sewardj
Date: 2010-07-29 16:55:09 +0100 (Thu, 29 Jul 2010)
New Revision: 11242
Log:
Test cases for LZCNT instruction support. Not wired up yet.
Added:
trunk/none/tests/amd64/test_lzcnt64.c
trunk/none/tests/x86/test_lzcnt32.c
Added: trunk/none/tests/amd64/test_lzcnt64.c
===================================================================
--- trunk/none/tests/amd64/test_lzcnt64.c (rev 0)
+++ trunk/none/tests/amd64/test_lzcnt64.c 2010-07-29 15:55:09 UTC (rev 11242)
@@ -0,0 +1,93 @@
+
+#include <stdio.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+
+__attribute__((noinline))
+void do_lzcnt64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntq 0(%0), %%r11" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntl 0(%0), %%r11d" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntw 0(%0), %%r11w" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+int main ( void )
+{
+ ULong w;
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt64(&flags, &res, w);
+ printf("lzcntq %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt32(&flags, &res, w);
+ printf("lzcntl %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt16(&flags, &res, w);
+ printf("lzcntw %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ return 0;
+}
Added: trunk/none/tests/x86/test_lzcnt32.c
===================================================================
--- trunk/none/tests/x86/test_lzcnt32.c (rev 0)
+++ trunk/none/tests/x86/test_lzcnt32.c 2010-07-29 15:55:09 UTC (rev 11242)
@@ -0,0 +1,66 @@
+
+#include <stdio.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+
+__attribute__((noinline))
+void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
+{
+ UInt block[3] = { arg, 0, 0 };
+ __asm__ __volatile__(
+ "movl $0x55555555, %%esi" "\n\t"
+ "lzcntl 0(%0), %%esi" "\n\t"
+ "movl %%esi, 4(%0)" "\n\t"
+ "pushfl" "\n\t"
+ "popl %%esi" "\n\t"
+ "movl %%esi, 8(%0)" "\n"
+ : : "r"(&block[0]) : "esi","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
+{
+ UInt block[3] = { arg, 0, 0 };
+ __asm__ __volatile__(
+ "movl $0x55555555, %%esi" "\n\t"
+ "lzcntw 0(%0), %%si" "\n\t"
+ "movl %%esi, 4(%0)" "\n\t"
+ "pushfl" "\n\t"
+ "popl %%esi" "\n\t"
+ "movl %%esi, 8(%0)" "\n"
+ : : "r"(&block[0]) : "esi","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+int main ( void )
+{
+ UInt w;
+
+ w = 0xFEDC1928;
+ while (1) {
+ UInt res;
+ UInt flags;
+ do_lzcnt32(&flags, &res, w);
+ printf("lzcntl %08x -> %08x %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17);
+ }
+
+ w = 0xFEDC1928;
+ while (1) {
+ UInt res;
+ UInt flags;
+ do_lzcnt16(&flags, &res, w);
+ printf("lzcntw %08x -> %08x %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17);
+ }
+
+ return 0;
+}
|
|
From: <sv...@va...> - 2010-07-29 15:40:40
|
Author: sewardj
Date: 2010-07-29 16:40:32 +0100 (Thu, 29 Jul 2010)
New Revision: 11241
Log:
x86/amd64: detect whether the CPU supports LZCNT. Followup to
#212335.
Modified:
trunk/coregrind/m_machine.c
Modified: trunk/coregrind/m_machine.c
===================================================================
--- trunk/coregrind/m_machine.c 2010-07-29 15:19:50 UTC (rev 11240)
+++ trunk/coregrind/m_machine.c 2010-07-29 15:40:32 UTC (rev 11241)
@@ -407,8 +407,10 @@
LibVEX_default_VexArchInfo(&vai);
#if defined(VGA_x86)
- { Bool have_sse1, have_sse2, have_cx8;
- UInt eax, ebx, ecx, edx;
+ { Bool have_sse1, have_sse2, have_cx8, have_lzcnt;
+ UInt eax, ebx, ecx, edx, max_basic, max_extended;
+ UChar vstr[13];
+ vstr[0] = 0;
if (!VG_(has_cpuid)())
/* we can't do cpuid at all. Give up. */
@@ -419,6 +421,17 @@
/* we can't ask for cpuid(x) for x > 0. Give up. */
return False;
+ /* Get processor ID string, and max basic/extended index
+ values. */
+ max_basic = eax;
+ VG_(memcpy)(&vstr[0], &ebx, 4);
+ VG_(memcpy)(&vstr[4], &edx, 4);
+ VG_(memcpy)(&vstr[8], &ecx, 4);
+ vstr[12] = 0;
+
+ VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx);
+ max_extended = eax;
+
/* get capabilities bits into edx */
VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
@@ -432,10 +445,20 @@
if (!have_cx8)
return False;
+ /* Figure out if this is an AMD that can do LZCNT. */
+ have_lzcnt = False;
+ if (0 == VG_(strcmp)(vstr, "AuthenticAMD")
+ && max_extended >= 0x80000001) {
+ VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx);
+ have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */
+ }
+
if (have_sse2 && have_sse1) {
va = VexArchX86;
vai.hwcaps = VEX_HWCAPS_X86_SSE1;
vai.hwcaps |= VEX_HWCAPS_X86_SSE2;
+ if (have_lzcnt)
+ vai.hwcaps |= VEX_HWCAPS_X86_LZCNT;
VG_(machine_x86_have_mxcsr) = 1;
return True;
}
@@ -455,7 +478,10 @@
#elif defined(VGA_amd64)
{ Bool have_sse1, have_sse2, have_sse3, have_cx8, have_cx16;
- UInt eax, ebx, ecx, edx;
+ Bool have_lzcnt;
+ UInt eax, ebx, ecx, edx, max_basic, max_extended;
+ UChar vstr[13];
+ vstr[0] = 0;
if (!VG_(has_cpuid)())
/* we can't do cpuid at all. Give up. */
@@ -466,12 +492,26 @@
/* we can't ask for cpuid(x) for x > 0. Give up. */
return False;
+ /* Get processor ID string, and max basic/extended index
+ values. */
+ max_basic = eax;
+ VG_(memcpy)(&vstr[0], &ebx, 4);
+ VG_(memcpy)(&vstr[4], &edx, 4);
+ VG_(memcpy)(&vstr[8], &ecx, 4);
+ vstr[12] = 0;
+
+ VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx);
+ max_extended = eax;
+
/* get capabilities bits into edx */
VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
have_sse1 = (edx & (1<<25)) != 0; /* True => have sse insns */
have_sse2 = (edx & (1<<26)) != 0; /* True => have sse2 insns */
have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */
+ // ssse3 is ecx:9
+ // sse41 is ecx:19
+ // sse42 is ecx:20
/* cmpxchg8b is a minimum requirement now; if we don't have it we
must simply give up. But all CPUs since Pentium-I have it, so
@@ -483,9 +523,18 @@
/* on amd64 we tolerate older cpus, which don't have cmpxchg16b */
have_cx16 = (ecx & (1<<13)) != 0; /* True => have cmpxchg16b */
+ /* Figure out if this is an AMD that can do LZCNT. */
+ have_lzcnt = False;
+ if (0 == VG_(strcmp)(vstr, "AuthenticAMD")
+ && max_extended >= 0x80000001) {
+ VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx);
+ have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */
+ }
+
va = VexArchAMD64;
vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
- | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0);
+ | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
+ | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0);
return True;
}
|
|
From: <sv...@va...> - 2010-07-29 15:39:13
|
Author: sewardj
Date: 2010-07-29 16:39:05 +0100 (Thu, 29 Jul 2010)
New Revision: 1995
Log:
Only decode LZCNT if the host supports it, since otherwise we risk
confusing it with BSR. Followup to #212335.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_x86_toIR.c
trunk/priv/host_amd64_isel.c
trunk/priv/host_x86_defs.c
trunk/priv/host_x86_isel.c
trunk/priv/main_main.c
trunk/pub/libvex.h
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/guest_amd64_toIR.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -15099,14 +15099,13 @@
goto decode_success;
}
- /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, but
- fortunately occupying opcode space which AFAICS is not occupied
- by anything else, even in Intel land. NB: 0F BD is BSR, but
- that's decoded below here, and we reject it if there's an F3
- prefix. Hence there is no possibility of confusion with this
- one. */
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
+ which we can only decode if we're sure this is an AMD cpu that
+ supports LZCNT, since otherwise it's BSR, which behaves
+ differently. */
if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
- && insn[0] == 0x0F && insn[1] == 0xBD) {
+ && insn[0] == 0x0F && insn[1] == 0xBD
+ && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
vassert(sz == 2 || sz == 4 || sz == 8);
/*IRType*/ ty = szToITy(sz);
IRTemp src = newTemp(ty);
Modified: trunk/priv/guest_x86_toIR.c
===================================================================
--- trunk/priv/guest_x86_toIR.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/guest_x86_toIR.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -12613,13 +12613,12 @@
goto decode_success;
}
- /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, but
- fortunately occupying opcode space which AFAICS is not occupied
- by anything else, even in Intel land. NB: 0F BD is BSR, but
- that's decoded below here, and it won't match there's an F3
- prefix. Hence there is no possibility of confusion with this
- one. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD) {
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
+ which we can only decode if we're sure this is an AMD cpu that
+ supports LZCNT, since otherwise it's BSR, which behaves
+ differently. */
+ if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD
+ && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) {
vassert(sz == 2 || sz == 4);
/*IRType*/ ty = szToITy(sz);
IRTemp src = newTemp(ty);
Modified: trunk/priv/host_amd64_isel.c
===================================================================
--- trunk/priv/host_amd64_isel.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/host_amd64_isel.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -4122,8 +4122,10 @@
/* sanity ... */
vassert(arch_host == VexArchAMD64);
- vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3
- |VEX_HWCAPS_AMD64_CX16)));
+ vassert(0 == (hwcaps_host
+ & ~(VEX_HWCAPS_AMD64_SSE3
+ | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_LZCNT)));
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
Modified: trunk/priv/host_x86_defs.c
===================================================================
--- trunk/priv/host_x86_defs.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/host_x86_defs.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -703,8 +703,10 @@
X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
i->tag = Xin_MFence;
i->Xin.MFence.hwcaps = hwcaps;
- vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1|VEX_HWCAPS_X86_SSE2
- |VEX_HWCAPS_X86_SSE3)));
+ vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1
+ |VEX_HWCAPS_X86_SSE2
+ |VEX_HWCAPS_X86_SSE3
+ |VEX_HWCAPS_X86_LZCNT)));
return i;
}
X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ) {
Modified: trunk/priv/host_x86_isel.c
===================================================================
--- trunk/priv/host_x86_isel.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/host_x86_isel.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -4000,9 +4000,11 @@
/* sanity ... */
vassert(arch_host == VexArchX86);
- vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_X86_SSE1
- |VEX_HWCAPS_X86_SSE2
- |VEX_HWCAPS_X86_SSE3)));
+ vassert(0 == (hwcaps_host
+ & ~(VEX_HWCAPS_X86_SSE1
+ | VEX_HWCAPS_X86_SSE2
+ | VEX_HWCAPS_X86_SSE3
+ | VEX_HWCAPS_X86_LZCNT)));
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
Modified: trunk/priv/main_main.c
===================================================================
--- trunk/priv/main_main.c 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/priv/main_main.c 2010-07-29 15:39:05 UTC (rev 1995)
@@ -754,32 +754,53 @@
static HChar* show_hwcaps_x86 ( UInt hwcaps )
{
/* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */
- if (hwcaps == 0)
- return "x86-sse0";
- if (hwcaps == VEX_HWCAPS_X86_SSE1)
- return "x86-sse1";
- if (hwcaps == (VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2))
- return "x86-sse1-sse2";
- if (hwcaps == (VEX_HWCAPS_X86_SSE1
- | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3))
- return "x86-sse1-sse2-sse3";
-
- return NULL;
+ switch (hwcaps) {
+ case 0:
+ return "x86-sse0";
+ case VEX_HWCAPS_X86_SSE1:
+ return "x86-sse1";
+ case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2:
+ return "x86-sse1-sse2";
+ case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+ | VEX_HWCAPS_X86_LZCNT:
+ return "x86-sse1-sse2-lzcnt";
+ case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+ | VEX_HWCAPS_X86_SSE3:
+ return "x86-sse1-sse2-sse3";
+ case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+ | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT:
+ return "x86-sse1-sse2-sse3-lzcnt";
+ default:
+ return NULL;
+ }
}
static HChar* show_hwcaps_amd64 ( UInt hwcaps )
{
/* SSE3 and CX16 are orthogonal and > baseline, although we really
don't expect to come across anything which can do SSE3 but can't
- do CX16. Still, we can handle that case. */
- const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3;
- const UInt CX16 = VEX_HWCAPS_AMD64_CX16;
- UInt c = hwcaps;
- if (c == 0) return "amd64-sse2";
- if (c == SSE3) return "amd64-sse3";
- if (c == CX16) return "amd64-sse2-cx16";
- if (c == (SSE3|CX16)) return "amd64-sse3-cx16";
- return NULL;
+ do CX16. Still, we can handle that case. LZCNT is similarly
+ orthogonal. */
+ switch (hwcaps) {
+ case 0:
+ return "amd64-sse2";
+ case VEX_HWCAPS_AMD64_SSE3:
+ return "amd64-sse3";
+ case VEX_HWCAPS_AMD64_CX16:
+ return "amd64-sse2-cx16";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16:
+ return "amd64-sse3-cx16";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_LZCNT:
+ return "amd64-sse3-lzcnt";
+ case VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT:
+ return "amd64-sse2-cx16-lzcnt";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_LZCNT:
+ return "amd64-sse3-cx16-lzcnt";
+
+ default:
+ return NULL;
+ }
}
static HChar* show_hwcaps_ppc32 ( UInt hwcaps )
Modified: trunk/pub/libvex.h
===================================================================
--- trunk/pub/libvex.h 2010-07-29 11:34:38 UTC (rev 1994)
+++ trunk/pub/libvex.h 2010-07-29 15:39:05 UTC (rev 1995)
@@ -69,27 +69,29 @@
/* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
cmpxchg8b. */
-#define VEX_HWCAPS_X86_SSE1 (1<<1) /* SSE1 support (Pentium III) */
-#define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */
-#define VEX_HWCAPS_X86_SSE3 (1<<3) /* SSE3 support (>= Prescott) */
+#define VEX_HWCAPS_X86_SSE1 (1<<1) /* SSE1 support (Pentium III) */
+#define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */
+#define VEX_HWCAPS_X86_SSE3 (1<<3) /* SSE3 support (>= Prescott) */
+#define VEX_HWCAPS_X86_LZCNT (1<<4) /* SSE4a LZCNT insn */
/* amd64: baseline capability is SSE2, with cmpxchg8b but not
cmpxchg16b. */
-#define VEX_HWCAPS_AMD64_SSE3 (1<<4) /* SSE3 support */
-#define VEX_HWCAPS_AMD64_CX16 (1<<5) /* cmpxchg16b support */
+#define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */
+#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */
+#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */
/* ppc32: baseline capability is integer only */
-#define VEX_HWCAPS_PPC32_F (1<<6) /* basic (non-optional) FP */
-#define VEX_HWCAPS_PPC32_V (1<<7) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC32_FX (1<<8) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC32_GX (1<<9) /* Graphics extns
- (fres,frsqrte,fsel,stfiwx) */
+#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */
+#define VEX_HWCAPS_PPC32_V (1<<9) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC32_FX (1<<10) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC32_GX (1<<11) /* Graphics extns
+ (fres,frsqrte,fsel,stfiwx) */
/* ppc64: baseline capability is integer and basic FP insns */
-#define VEX_HWCAPS_PPC64_V (1<<10) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC64_FX (1<<11) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC64_GX (1<<12) /* Graphics extns
- (fres,frsqrte,fsel,stfiwx) */
+#define VEX_HWCAPS_PPC64_V (1<<12) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC64_FX (1<<13) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC64_GX (1<<14) /* Graphics extns
+ (fres,frsqrte,fsel,stfiwx) */
/* arm: baseline capability is ARMv4 */
/* No extra capabilities */
|
|
From: <sv...@va...> - 2010-07-29 15:20:03
|
Author: bart
Date: 2010-07-29 16:19:50 +0100 (Thu, 29 Jul 2010)
New Revision: 11240
Log:
Made gmp, mpfr and mpc prefixes configurable.
Modified:
trunk/drd/scripts/download-and-build-gcc
Modified: trunk/drd/scripts/download-and-build-gcc
===================================================================
--- trunk/drd/scripts/download-and-build-gcc 2010-07-29 09:34:46 UTC (rev 11239)
+++ trunk/drd/scripts/download-and-build-gcc 2010-07-29 15:19:50 UTC (rev 11240)
@@ -14,20 +14,26 @@
BUILD=${SRC}-build
TAR=gcc-${GCC_VERSION}.tar.bz2
PREFIX=$HOME/gcc-${GCC_VERSION}
+GMP_PREFIX=/usr
+#GMP_PREFIX=$HOME/gmp-5.0.1
+MPFR_PREFIX=/usr
+#MPFR_PREFIX=$HOME/mpfr-2.4.2
+MPC_PREFIX=/usr
+#MPC_PREFIX=$HOME/mpc-0.8.1
export LC_ALL=C
export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))"
-if [ ! -e /usr/include/gmp.h ]; then
+if [ ! -e $GMP_PREFIX/include/gmp.h ]; then
echo "Please install the gmp library development package first."
exit 1
fi
-if [ ! -e /usr/include/mpfr.h ]; then
+if [ ! -e $MPFR_PREFIX/include/mpfr.h ]; then
echo "Please install the mpfr library development package first."
exit 1
fi
-if [ ! -e /usr/include/mpc.h ]; then
+if [ ! -e $MPC_PREFIX/include/mpc.h ]; then
echo "Please install the mpc library development package first."
exit 1
fi
@@ -59,6 +65,9 @@
--enable-languages=c,c++ \
--enable-threads=posix \
--enable-tls \
- --prefix=$PREFIX
+ --prefix=$PREFIX \
+ --with-gmp=$GMP_PREFIX \
+ --with-mpfr=$MPFR_PREFIX \
+ --with-mpc=$MPC_PREFIX
time { make -s && make -s install; }
|
|
From: <sv...@va...> - 2010-07-29 11:34:46
|
Author: sewardj
Date: 2010-07-29 12:34:38 +0100 (Thu, 29 Jul 2010)
New Revision: 1994
Log:
Support the amd SSE4.something LZCNT instruction. Fixes #212335
and its various clones, at least #227551, #241290 and #240639.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_x86_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-07-29 07:19:30 UTC (rev 1993)
+++ trunk/priv/guest_amd64_toIR.c 2010-07-29 11:34:38 UTC (rev 1994)
@@ -4436,6 +4436,40 @@
}
+/* Generate an IR sequence to do a count-leading-zeroes operation on
+ the supplied IRTemp, and return a new IRTemp holding the result.
+ 'ty' may be Ity_I16, Ity_I32 or Ity_I64 only. In the case where
+ the argument is zero, return the number of bits in the word (the
+ natural semantics). */
+static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+{
+ vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16);
+
+ IRTemp src64 = newTemp(Ity_I64);
+ assign(src64, widenUto64( mkexpr(src) ));
+
+ IRTemp src64x = newTemp(Ity_I64);
+ assign(src64x,
+ binop(Iop_Shl64, mkexpr(src64),
+ mkU8(64 - 8 * sizeofIRType(ty))));
+
+ // Clz64 has undefined semantics when its input is zero, so
+ // special-case around that.
+ IRTemp res64 = newTemp(Ity_I64);
+ assign(res64,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ64, mkexpr(src64x), mkU64(0))),
+ unop(Iop_Clz64, mkexpr(src64x)),
+ mkU64(8 * sizeofIRType(ty))
+ ));
+
+ IRTemp res = newTemp(ty);
+ assign(res, narrowTo(ty, mkexpr(res64)));
+ return res;
+}
+
+
/*------------------------------------------------------------*/
/*--- ---*/
/*--- x87 FLOATING POINT INSTRUCTIONS ---*/
@@ -15065,6 +15099,67 @@
goto decode_success;
}
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, but
+ fortunately occupying opcode space which AFAICS is not occupied
+ by anything else, even in Intel land. NB: 0F BD is BSR, but
+ that's decoded below here, and we reject it if there's an F3
+ prefix. Hence there is no possibility of confusion with this
+ one. */
+ if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
+ && insn[0] == 0x0F && insn[1] == 0xBD) {
+ vassert(sz == 2 || sz == 4 || sz == 8);
+ /*IRType*/ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ modrm = insn[2];
+ if (epartIsReg(modrm)) {
+ assign(src, getIRegE(sz, pfx, modrm));
+ delta += 2+1;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+ nameIRegG(sz, pfx, modrm));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0);
+ assign(src, loadLE(ty, mkexpr(addr)));
+ delta += 2+alen;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ nameIRegG(sz, pfx, modrm));
+ }
+
+ IRTemp res = gen_LZCNT(ty, src);
+ putIRegG(sz, pfx, modrm, mkexpr(res));
+
+ // Update flags. This is pretty lame .. perhaps can do better
+ // if this turns out to be performance critical.
+ // O S A P are cleared. Z is set if RESULT == 0.
+ // C is set if SRC is zero.
+ IRTemp src64 = newTemp(Ity_I64);
+ IRTemp res64 = newTemp(Ity_I64);
+ assign(src64, widenUto64(mkexpr(src)));
+ assign(res64, widenUto64(mkexpr(res)));
+
+ IRTemp oszacp = newTemp(Ity_I64);
+ assign(
+ oszacp,
+ binop(Iop_Or64,
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_Z)),
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_C))
+ )
+ );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+ goto decode_success;
+ }
+
+
/* ---------------------------------------------------- */
/* --- end of the SSE4 decoder --- */
/* ---------------------------------------------------- */
@@ -17707,7 +17802,73 @@
}
+/*------------------------------------------------------------*/
+/*--- Unused stuff ---*/
+/*------------------------------------------------------------*/
+// A potentially more Memcheck-friendly version of gen_LZCNT, if
+// this should ever be needed.
+//
+//static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+//{
+// /* Scheme is simple: propagate the most significant 1-bit into all
+// lower positions in the word. This gives a word of the form
+// 0---01---1. Now invert it, giving a word of the form
+// 1---10---0, then do a population-count idiom (to count the 1s,
+// which is the number of leading zeroes, or the word size if the
+// original word was 0.
+// */
+// Int i;
+// IRTemp t[7];
+// for (i = 0; i < 7; i++) {
+// t[i] = newTemp(ty);
+// }
+// if (ty == Ity_I64) {
+// assign(t[0], binop(Iop_Or64, mkexpr(src),
+// binop(Iop_Shr64, mkexpr(src), mkU8(1))));
+// assign(t[1], binop(Iop_Or64, mkexpr(t[0]),
+// binop(Iop_Shr64, mkexpr(t[0]), mkU8(2))));
+// assign(t[2], binop(Iop_Or64, mkexpr(t[1]),
+// binop(Iop_Shr64, mkexpr(t[1]), mkU8(4))));
+// assign(t[3], binop(Iop_Or64, mkexpr(t[2]),
+// binop(Iop_Shr64, mkexpr(t[2]), mkU8(8))));
+// assign(t[4], binop(Iop_Or64, mkexpr(t[3]),
+// binop(Iop_Shr64, mkexpr(t[3]), mkU8(16))));
+// assign(t[5], binop(Iop_Or64, mkexpr(t[4]),
+// binop(Iop_Shr64, mkexpr(t[4]), mkU8(32))));
+// assign(t[6], unop(Iop_Not64, mkexpr(t[5])));
+// return gen_POPCOUNT(ty, t[6]);
+// }
+// if (ty == Ity_I32) {
+// assign(t[0], binop(Iop_Or32, mkexpr(src),
+// binop(Iop_Shr32, mkexpr(src), mkU8(1))));
+// assign(t[1], binop(Iop_Or32, mkexpr(t[0]),
+// binop(Iop_Shr32, mkexpr(t[0]), mkU8(2))));
+// assign(t[2], binop(Iop_Or32, mkexpr(t[1]),
+// binop(Iop_Shr32, mkexpr(t[1]), mkU8(4))));
+// assign(t[3], binop(Iop_Or32, mkexpr(t[2]),
+// binop(Iop_Shr32, mkexpr(t[2]), mkU8(8))));
+// assign(t[4], binop(Iop_Or32, mkexpr(t[3]),
+// binop(Iop_Shr32, mkexpr(t[3]), mkU8(16))));
+// assign(t[5], unop(Iop_Not32, mkexpr(t[4])));
+// return gen_POPCOUNT(ty, t[5]);
+// }
+// if (ty == Ity_I16) {
+// assign(t[0], binop(Iop_Or16, mkexpr(src),
+// binop(Iop_Shr16, mkexpr(src), mkU8(1))));
+// assign(t[1], binop(Iop_Or16, mkexpr(t[0]),
+// binop(Iop_Shr16, mkexpr(t[0]), mkU8(2))));
+// assign(t[2], binop(Iop_Or16, mkexpr(t[1]),
+// binop(Iop_Shr16, mkexpr(t[1]), mkU8(4))));
+// assign(t[3], binop(Iop_Or16, mkexpr(t[2]),
+// binop(Iop_Shr16, mkexpr(t[2]), mkU8(8))));
+// assign(t[4], unop(Iop_Not16, mkexpr(t[3])));
+// return gen_POPCOUNT(ty, t[4]);
+// }
+// vassert(0);
+//}
+
+
/*--------------------------------------------------------------------*/
/*--- end guest_amd64_toIR.c ---*/
/*--------------------------------------------------------------------*/
Modified: trunk/priv/guest_x86_toIR.c
===================================================================
--- trunk/priv/guest_x86_toIR.c 2010-07-29 07:19:30 UTC (rev 1993)
+++ trunk/priv/guest_x86_toIR.c 2010-07-29 11:34:38 UTC (rev 1994)
@@ -3362,6 +3362,40 @@
}
+/* Generate an IR sequence to do a count-leading-zeroes operation on
+ the supplied IRTemp, and return a new IRTemp holding the result.
+ 'ty' may be Ity_I16 or Ity_I32 only. In the case where the
+ argument is zero, return the number of bits in the word (the
+ natural semantics). */
+static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+{
+ vassert(ty == Ity_I32 || ty == Ity_I16);
+
+ IRTemp src32 = newTemp(Ity_I32);
+ assign(src32, widenUto32( mkexpr(src) ));
+
+ IRTemp src32x = newTemp(Ity_I32);
+ assign(src32x,
+ binop(Iop_Shl32, mkexpr(src32),
+ mkU8(32 - 8 * sizeofIRType(ty))));
+
+ // Clz32 has undefined semantics when its input is zero, so
+ // special-case around that.
+ IRTemp res32 = newTemp(Ity_I32);
+ assign(res32,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ32, mkexpr(src32x), mkU32(0))),
+ unop(Iop_Clz32, mkexpr(src32x)),
+ mkU32(8 * sizeofIRType(ty))
+ ));
+
+ IRTemp res = newTemp(ty);
+ assign(res, narrowTo(ty, mkexpr(res32)));
+ return res;
+}
+
+
/*------------------------------------------------------------*/
/*--- ---*/
/*--- x87 FLOATING POINT INSTRUCTIONS ---*/
@@ -12579,6 +12613,66 @@
goto decode_success;
}
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, but
+ fortunately occupying opcode space which AFAICS is not occupied
+ by anything else, even in Intel land. NB: 0F BD is BSR, but
+ that's decoded below here, and it won't match there's an F3
+ prefix. Hence there is no possibility of confusion with this
+ one. */
+ if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD) {
+ vassert(sz == 2 || sz == 4);
+ /*IRType*/ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ modrm = insn[3];
+ if (epartIsReg(modrm)) {
+ assign(src, getIReg(sz, eregOfRM(modrm)));
+ delta += 3+1;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz),
+ nameIReg(sz, eregOfRM(modrm)),
+ nameIReg(sz, gregOfRM(modrm)));
+ } else {
+ addr = disAMode( &alen, sorb, delta+3, dis_buf );
+ assign(src, loadLE(ty, mkexpr(addr)));
+ delta += 3+alen;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ nameIReg(sz, gregOfRM(modrm)));
+ }
+
+ IRTemp res = gen_LZCNT(ty, src);
+ putIReg(sz, gregOfRM(modrm), mkexpr(res));
+
+ // Update flags. This is pretty lame .. perhaps can do better
+ // if this turns out to be performance critical.
+ // O S A P are cleared. Z is set if RESULT == 0.
+ // C is set if SRC is zero.
+ IRTemp src32 = newTemp(Ity_I32);
+ IRTemp res32 = newTemp(Ity_I32);
+ assign(src32, widenUto32(mkexpr(src)));
+ assign(res32, widenUto32(mkexpr(res)));
+
+ IRTemp oszacp = newTemp(Ity_I32);
+ assign(
+ oszacp,
+ binop(Iop_Or32,
+ binop(Iop_Shl32,
+ unop(Iop_1Uto32,
+ binop(Iop_CmpEQ32, mkexpr(res32), mkU32(0))),
+ mkU8(X86G_CC_SHIFT_Z)),
+ binop(Iop_Shl32,
+ unop(Iop_1Uto32,
+ binop(Iop_CmpEQ32, mkexpr(src32), mkU32(0))),
+ mkU8(X86G_CC_SHIFT_C))
+ )
+ );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+ goto decode_success;
+ }
+
/* ---------------------------------------------------- */
/* --- end of the SSE4 decoder --- */
/* ---------------------------------------------------- */
|
|
From: Bart V. A. <bva...@ac...> - 2010-07-29 09:37:10
|
That was unintended, so I have reverted r11238. Would changing the declaration type from void to Addr be safe ? As far as I know gcc 4.5.0 does not allow to suppress the warning "taking address of expression of type void". Bart. On Thu, Jul 29, 2010 at 10:09 AM, Julian Seward <js...@ac...> wrote: > > This might (or might not) break ppc64-linux, since on that > platform, &function does not return the entry point of the > function's code, but instead the address of the descriptor. > Hence the change from "&label" to "&function" may change the > meaning of the resulting address. > > J > > On Thursday, July 29, 2010, sv...@va... wrote: > > Author: bart > > Date: 2010-07-29 08:53:57 +0100 (Thu, 29 Jul 2010) > > New Revision: 11238 > > > > Log: > > Avoid that gcc 4.5.x reports the warning "taking address of expression of > > type void". > > > > > > Modified: > > trunk/coregrind/pub_core_dispatch.h > > trunk/coregrind/pub_core_trampoline.h > > > > > > Modified: trunk/coregrind/pub_core_dispatch.h > > =================================================================== > > --- trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:52:37 UTC > (rev > 11237) > > +++ trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:53:57 UTC > (rev > 11238) > > @@ -68,8 +68,8 @@ > > following somewhat bogus decls. At least on x86 and amd64. ppc32 > > and ppc64 use straightforward bl-blr to get from dispatcher to > > translation and back and so do not need these labels. */ > > -extern void VG_(run_innerloop__dispatch_unprofiled); > > -extern void VG_(run_innerloop__dispatch_profiled); > > +extern void VG_(run_innerloop__dispatch_unprofiled)( void ); > > +extern void VG_(run_innerloop__dispatch_profiled)( void ); > > #endif > > > > > > @@ -86,7 +86,7 @@ > > /* We need to a label inside VG_(run_a_noredir_translation), so that > > Vex can add branches to them from generated code. Hence the > > following somewhat bogus decl. */ > > -extern void VG_(run_a_noredir_translation__return_point); > > +extern void VG_(run_a_noredir_translation__return_point)( void ); > > #endif > > > > > > > > Modified: trunk/coregrind/pub_core_trampoline.h > > =================================================================== > > --- trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:52:37 UTC > (rev > > 11237) +++ trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:53:57 > UTC > > (rev 11238) @@ -53,32 +53,32 @@ > > readable, at least. Otherwise Memcheck complains we're jumping to > > invalid addresses. */ > > > > -extern void VG_(trampoline_stuff_start); > > -extern void VG_(trampoline_stuff_end); > > +extern void VG_(trampoline_stuff_start)( void ); > > +extern void VG_(trampoline_stuff_end)( void ); > > > > #if defined(VGP_x86_linux) > > -extern void VG_(x86_linux_SUBST_FOR_sigreturn); > > -extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn); > > +extern void VG_(x86_linux_SUBST_FOR_sigreturn)( void ); > > +extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn)( void ); > > extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int ); > > #endif > > > > #if defined(VGP_amd64_linux) > > -extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn); > > -extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday); > > -extern void VG_(amd64_linux_REDIR_FOR_vtime); > > +extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn)( void ); > > +extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday)( void ); > > +extern void VG_(amd64_linux_REDIR_FOR_vtime)( void ); > > extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* ); > > #endif > > > > #if defined(VGP_ppc32_linux) > > -extern void VG_(ppc32_linux_SUBST_FOR_sigreturn); > > -extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn); > > +extern void VG_(ppc32_linux_SUBST_FOR_sigreturn)( void ); > > +extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn)( void ); > > extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* ); > > extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* ); > > extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int ); > > #endif > > > > #if defined(VGP_ppc64_linux) > > -extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn); > > +extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn)( void ); > > extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* ); > > extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int ); > > /* A label (sans dot) marking the ultra-magical return stub via which > > @@ -88,7 +88,7 @@ > > restore the thread's LR and R2 registers from a small stack in the > > ppc64 guest state structure, and then branch to LR. Convoluted? > > Confusing? You betcha. Could I think of anything simpler? No. */ > > -extern void VG_(ppctoc_magic_redirect_return_stub); > > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > > #endif > > > > #if defined(VGP_arm_linux) > > @@ -105,22 +105,22 @@ > > then it cleans up the register state to be more what it really > > should be at client startup, and finally it jumps to the client's > > real entry point. */ > > -extern void VG_(ppc32_aix5_do_preloads_then_start_client); > > +extern void VG_(ppc32_aix5_do_preloads_then_start_client)( void ); > > > > /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ > > -extern void VG_(ppctoc_magic_redirect_return_stub); > > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > > #endif > > > > #if defined(VGP_ppc64_aix5) > > /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ > > -extern void VG_(ppctoc_magic_redirect_return_stub); > > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > > > > /* See comment for ppc32_aix5 equivalent above. */ > > -extern void VG_(ppc64_aix5_do_preloads_then_start_client); > > +extern void VG_(ppc64_aix5_do_preloads_then_start_client)( void ); > > #endif > > > > #if defined(VGP_x86_darwin) > > -extern void VG_(x86_darwin_SUBST_FOR_sigreturn); > > +extern void VG_(x86_darwin_SUBST_FOR_sigreturn)( void ); > > extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* ); > > extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* ); > > extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * ); > > @@ -130,7 +130,7 @@ > > #endif > > > > #if defined(VGP_amd64_darwin) > > -extern void VG_(amd64_darwin_SUBST_FOR_sigreturn); > > +extern void VG_(amd64_darwin_SUBST_FOR_sigreturn)( void ); > > extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* ); > > extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* ); > > extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * ); > > > > > > > --------------------------------------------------------------------------- > > --- The Palm PDK Hot Apps Program offers developers who use the > > Plug-In Development Kit to bring their C/C++ apps to Palm for a share > > of $1 Million in cash or HP Products. Visit us here for more details: > > http://p.sf.net/sfu/dev2dev-palm > > _______________________________________________ > > Valgrind-developers mailing list > > Val...@li... > > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > > > > ------------------------------------------------------------------------------ > The Palm PDK Hot Apps Program offers developers who use the > Plug-In Development Kit to bring their C/C++ apps to Palm for a share > of $1 Million in cash or HP Products. Visit us here for more details: > http://p.sf.net/sfu/dev2dev-palm > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |
|
From: <sv...@va...> - 2010-07-29 09:34:55
|
Author: bart
Date: 2010-07-29 10:34:46 +0100 (Thu, 29 Jul 2010)
New Revision: 11239
Log:
Reverted r11238.
Modified:
trunk/coregrind/pub_core_dispatch.h
trunk/coregrind/pub_core_trampoline.h
Modified: trunk/coregrind/pub_core_dispatch.h
===================================================================
--- trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:53:57 UTC (rev 11238)
+++ trunk/coregrind/pub_core_dispatch.h 2010-07-29 09:34:46 UTC (rev 11239)
@@ -68,8 +68,8 @@
following somewhat bogus decls. At least on x86 and amd64. ppc32
and ppc64 use straightforward bl-blr to get from dispatcher to
translation and back and so do not need these labels. */
-extern void VG_(run_innerloop__dispatch_unprofiled)( void );
-extern void VG_(run_innerloop__dispatch_profiled)( void );
+extern void VG_(run_innerloop__dispatch_unprofiled);
+extern void VG_(run_innerloop__dispatch_profiled);
#endif
@@ -86,7 +86,7 @@
/* We need to a label inside VG_(run_a_noredir_translation), so that
Vex can add branches to them from generated code. Hence the
following somewhat bogus decl. */
-extern void VG_(run_a_noredir_translation__return_point)( void );
+extern void VG_(run_a_noredir_translation__return_point);
#endif
Modified: trunk/coregrind/pub_core_trampoline.h
===================================================================
--- trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:53:57 UTC (rev 11238)
+++ trunk/coregrind/pub_core_trampoline.h 2010-07-29 09:34:46 UTC (rev 11239)
@@ -53,32 +53,32 @@
readable, at least. Otherwise Memcheck complains we're jumping to
invalid addresses. */
-extern void VG_(trampoline_stuff_start)( void );
-extern void VG_(trampoline_stuff_end)( void );
+extern void VG_(trampoline_stuff_start);
+extern void VG_(trampoline_stuff_end);
#if defined(VGP_x86_linux)
-extern void VG_(x86_linux_SUBST_FOR_sigreturn)( void );
-extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn)( void );
+extern void VG_(x86_linux_SUBST_FOR_sigreturn);
+extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn);
extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int );
#endif
#if defined(VGP_amd64_linux)
-extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn)( void );
-extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday)( void );
-extern void VG_(amd64_linux_REDIR_FOR_vtime)( void );
+extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
+extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday);
+extern void VG_(amd64_linux_REDIR_FOR_vtime);
extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
#endif
#if defined(VGP_ppc32_linux)
-extern void VG_(ppc32_linux_SUBST_FOR_sigreturn)( void );
-extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn)( void );
+extern void VG_(ppc32_linux_SUBST_FOR_sigreturn);
+extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);
extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* );
extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
#endif
#if defined(VGP_ppc64_linux)
-extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn)( void );
+extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
/* A label (sans dot) marking the ultra-magical return stub via which
@@ -88,7 +88,7 @@
restore the thread's LR and R2 registers from a small stack in the
ppc64 guest state structure, and then branch to LR. Convoluted?
Confusing? You betcha. Could I think of anything simpler? No. */
-extern void VG_(ppctoc_magic_redirect_return_stub)( void );
+extern void VG_(ppctoc_magic_redirect_return_stub);
#endif
#if defined(VGP_arm_linux)
@@ -105,22 +105,22 @@
then it cleans up the register state to be more what it really
should be at client startup, and finally it jumps to the client's
real entry point. */
-extern void VG_(ppc32_aix5_do_preloads_then_start_client)( void );
+extern void VG_(ppc32_aix5_do_preloads_then_start_client);
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub)( void );
+extern void VG_(ppctoc_magic_redirect_return_stub);
#endif
#if defined(VGP_ppc64_aix5)
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub)( void );
+extern void VG_(ppctoc_magic_redirect_return_stub);
/* See comment for ppc32_aix5 equivalent above. */
-extern void VG_(ppc64_aix5_do_preloads_then_start_client)( void );
+extern void VG_(ppc64_aix5_do_preloads_then_start_client);
#endif
#if defined(VGP_x86_darwin)
-extern void VG_(x86_darwin_SUBST_FOR_sigreturn)( void );
+extern void VG_(x86_darwin_SUBST_FOR_sigreturn);
extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * );
@@ -130,7 +130,7 @@
#endif
#if defined(VGP_amd64_darwin)
-extern void VG_(amd64_darwin_SUBST_FOR_sigreturn)( void );
+extern void VG_(amd64_darwin_SUBST_FOR_sigreturn);
extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * );
|
|
From: Julian S. <js...@ac...> - 2010-07-29 08:07:09
|
This might (or might not) break ppc64-linux, since on that platform, &function does not return the entry point of the function's code, but instead the address of the descriptor. Hence the change from "&label" to "&function" may change the meaning of the resulting address. J On Thursday, July 29, 2010, sv...@va... wrote: > Author: bart > Date: 2010-07-29 08:53:57 +0100 (Thu, 29 Jul 2010) > New Revision: 11238 > > Log: > Avoid that gcc 4.5.x reports the warning "taking address of expression of > type void". > > > Modified: > trunk/coregrind/pub_core_dispatch.h > trunk/coregrind/pub_core_trampoline.h > > > Modified: trunk/coregrind/pub_core_dispatch.h > =================================================================== > --- trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:52:37 UTC (rev 11237) > +++ trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:53:57 UTC (rev 11238) > @@ -68,8 +68,8 @@ > following somewhat bogus decls. At least on x86 and amd64. ppc32 > and ppc64 use straightforward bl-blr to get from dispatcher to > translation and back and so do not need these labels. */ > -extern void VG_(run_innerloop__dispatch_unprofiled); > -extern void VG_(run_innerloop__dispatch_profiled); > +extern void VG_(run_innerloop__dispatch_unprofiled)( void ); > +extern void VG_(run_innerloop__dispatch_profiled)( void ); > #endif > > > @@ -86,7 +86,7 @@ > /* We need to a label inside VG_(run_a_noredir_translation), so that > Vex can add branches to them from generated code. Hence the > following somewhat bogus decl. */ > -extern void VG_(run_a_noredir_translation__return_point); > +extern void VG_(run_a_noredir_translation__return_point)( void ); > #endif > > > > Modified: trunk/coregrind/pub_core_trampoline.h > =================================================================== > --- trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:52:37 UTC (rev > 11237) +++ trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:53:57 UTC > (rev 11238) @@ -53,32 +53,32 @@ > readable, at least. Otherwise Memcheck complains we're jumping to > invalid addresses. */ > > -extern void VG_(trampoline_stuff_start); > -extern void VG_(trampoline_stuff_end); > +extern void VG_(trampoline_stuff_start)( void ); > +extern void VG_(trampoline_stuff_end)( void ); > > #if defined(VGP_x86_linux) > -extern void VG_(x86_linux_SUBST_FOR_sigreturn); > -extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn); > +extern void VG_(x86_linux_SUBST_FOR_sigreturn)( void ); > +extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn)( void ); > extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int ); > #endif > > #if defined(VGP_amd64_linux) > -extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn); > -extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday); > -extern void VG_(amd64_linux_REDIR_FOR_vtime); > +extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn)( void ); > +extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday)( void ); > +extern void VG_(amd64_linux_REDIR_FOR_vtime)( void ); > extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* ); > #endif > > #if defined(VGP_ppc32_linux) > -extern void VG_(ppc32_linux_SUBST_FOR_sigreturn); > -extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn); > +extern void VG_(ppc32_linux_SUBST_FOR_sigreturn)( void ); > +extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn)( void ); > extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* ); > extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* ); > extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int ); > #endif > > #if defined(VGP_ppc64_linux) > -extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn); > +extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn)( void ); > extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* ); > extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int ); > /* A label (sans dot) marking the ultra-magical return stub via which > @@ -88,7 +88,7 @@ > restore the thread's LR and R2 registers from a small stack in the > ppc64 guest state structure, and then branch to LR. Convoluted? > Confusing? You betcha. Could I think of anything simpler? No. */ > -extern void VG_(ppctoc_magic_redirect_return_stub); > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > #endif > > #if defined(VGP_arm_linux) > @@ -105,22 +105,22 @@ > then it cleans up the register state to be more what it really > should be at client startup, and finally it jumps to the client's > real entry point. */ > -extern void VG_(ppc32_aix5_do_preloads_then_start_client); > +extern void VG_(ppc32_aix5_do_preloads_then_start_client)( void ); > > /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ > -extern void VG_(ppctoc_magic_redirect_return_stub); > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > #endif > > #if defined(VGP_ppc64_aix5) > /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ > -extern void VG_(ppctoc_magic_redirect_return_stub); > +extern void VG_(ppctoc_magic_redirect_return_stub)( void ); > > /* See comment for ppc32_aix5 equivalent above. */ > -extern void VG_(ppc64_aix5_do_preloads_then_start_client); > +extern void VG_(ppc64_aix5_do_preloads_then_start_client)( void ); > #endif > > #if defined(VGP_x86_darwin) > -extern void VG_(x86_darwin_SUBST_FOR_sigreturn); > +extern void VG_(x86_darwin_SUBST_FOR_sigreturn)( void ); > extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* ); > extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* ); > extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * ); > @@ -130,7 +130,7 @@ > #endif > > #if defined(VGP_amd64_darwin) > -extern void VG_(amd64_darwin_SUBST_FOR_sigreturn); > +extern void VG_(amd64_darwin_SUBST_FOR_sigreturn)( void ); > extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* ); > extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* ); > extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * ); > > > --------------------------------------------------------------------------- > --- The Palm PDK Hot Apps Program offers developers who use the > Plug-In Development Kit to bring their C/C++ apps to Palm for a share > of $1 Million in cash or HP Products. Visit us here for more details: > http://p.sf.net/sfu/dev2dev-palm > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
|
From: <sv...@va...> - 2010-07-29 07:54:05
|
Author: bart
Date: 2010-07-29 08:53:57 +0100 (Thu, 29 Jul 2010)
New Revision: 11238
Log:
Avoid that gcc 4.5.x reports the warning "taking address of expression of type void".
Modified:
trunk/coregrind/pub_core_dispatch.h
trunk/coregrind/pub_core_trampoline.h
Modified: trunk/coregrind/pub_core_dispatch.h
===================================================================
--- trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:52:37 UTC (rev 11237)
+++ trunk/coregrind/pub_core_dispatch.h 2010-07-29 07:53:57 UTC (rev 11238)
@@ -68,8 +68,8 @@
following somewhat bogus decls. At least on x86 and amd64. ppc32
and ppc64 use straightforward bl-blr to get from dispatcher to
translation and back and so do not need these labels. */
-extern void VG_(run_innerloop__dispatch_unprofiled);
-extern void VG_(run_innerloop__dispatch_profiled);
+extern void VG_(run_innerloop__dispatch_unprofiled)( void );
+extern void VG_(run_innerloop__dispatch_profiled)( void );
#endif
@@ -86,7 +86,7 @@
/* We need to a label inside VG_(run_a_noredir_translation), so that
Vex can add branches to them from generated code. Hence the
following somewhat bogus decl. */
-extern void VG_(run_a_noredir_translation__return_point);
+extern void VG_(run_a_noredir_translation__return_point)( void );
#endif
Modified: trunk/coregrind/pub_core_trampoline.h
===================================================================
--- trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:52:37 UTC (rev 11237)
+++ trunk/coregrind/pub_core_trampoline.h 2010-07-29 07:53:57 UTC (rev 11238)
@@ -53,32 +53,32 @@
readable, at least. Otherwise Memcheck complains we're jumping to
invalid addresses. */
-extern void VG_(trampoline_stuff_start);
-extern void VG_(trampoline_stuff_end);
+extern void VG_(trampoline_stuff_start)( void );
+extern void VG_(trampoline_stuff_end)( void );
#if defined(VGP_x86_linux)
-extern void VG_(x86_linux_SUBST_FOR_sigreturn);
-extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn);
+extern void VG_(x86_linux_SUBST_FOR_sigreturn)( void );
+extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn)( void );
extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int );
#endif
#if defined(VGP_amd64_linux)
-extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
-extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday);
-extern void VG_(amd64_linux_REDIR_FOR_vtime);
+extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn)( void );
+extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday)( void );
+extern void VG_(amd64_linux_REDIR_FOR_vtime)( void );
extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
#endif
#if defined(VGP_ppc32_linux)
-extern void VG_(ppc32_linux_SUBST_FOR_sigreturn);
-extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);
+extern void VG_(ppc32_linux_SUBST_FOR_sigreturn)( void );
+extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn)( void );
extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* );
extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
#endif
#if defined(VGP_ppc64_linux)
-extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
+extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn)( void );
extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
/* A label (sans dot) marking the ultra-magical return stub via which
@@ -88,7 +88,7 @@
restore the thread's LR and R2 registers from a small stack in the
ppc64 guest state structure, and then branch to LR. Convoluted?
Confusing? You betcha. Could I think of anything simpler? No. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern void VG_(ppctoc_magic_redirect_return_stub)( void );
#endif
#if defined(VGP_arm_linux)
@@ -105,22 +105,22 @@
then it cleans up the register state to be more what it really
should be at client startup, and finally it jumps to the client's
real entry point. */
-extern void VG_(ppc32_aix5_do_preloads_then_start_client);
+extern void VG_(ppc32_aix5_do_preloads_then_start_client)( void );
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern void VG_(ppctoc_magic_redirect_return_stub)( void );
#endif
#if defined(VGP_ppc64_aix5)
/* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern void VG_(ppctoc_magic_redirect_return_stub)( void );
/* See comment for ppc32_aix5 equivalent above. */
-extern void VG_(ppc64_aix5_do_preloads_then_start_client);
+extern void VG_(ppc64_aix5_do_preloads_then_start_client)( void );
#endif
#if defined(VGP_x86_darwin)
-extern void VG_(x86_darwin_SUBST_FOR_sigreturn);
+extern void VG_(x86_darwin_SUBST_FOR_sigreturn)( void );
extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * );
@@ -130,7 +130,7 @@
#endif
#if defined(VGP_amd64_darwin)
-extern void VG_(amd64_darwin_SUBST_FOR_sigreturn);
+extern void VG_(amd64_darwin_SUBST_FOR_sigreturn)( void );
extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* );
extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* );
extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * );
|
|
From: <sv...@va...> - 2010-07-29 07:52:44
|
Author: bart
Date: 2010-07-29 08:52:37 +0100 (Thu, 29 Jul 2010)
New Revision: 11237
Log:
Updated list of suppression patterns.
Modified:
trunk/glibc-2.X-drd.supp
Modified: trunk/glibc-2.X-drd.supp
===================================================================
--- trunk/glibc-2.X-drd.supp 2010-07-29 07:03:05 UTC (rev 11236)
+++ trunk/glibc-2.X-drd.supp 2010-07-29 07:52:37 UTC (rev 11237)
@@ -72,6 +72,11 @@
fun:__deallocate_stack
}
{
+ drd-libpthread-__free_stacks
+ drd:ConflictingAccess
+ fun:__free_stacks
+}
+{
drd-libpthread-__free_tcb
drd:ConflictingAccess
...
@@ -233,6 +238,11 @@
drd:ConflictingAccess
fun:_ZN10QMutexPool3getEPKv
}
+{
+ drd-libQtCore-qt_gettime_is_monotonic()
+ drd:ConflictingAccess
+ fun:_Z23qt_gettime_is_monotonicv
+}
#
# Suppression patterns for libboost.
|
|
From: <sv...@va...> - 2010-07-29 07:19:37
|
Author: sewardj
Date: 2010-07-29 08:19:30 +0100 (Thu, 29 Jul 2010)
New Revision: 1993
Log:
Handle mov[ua[pd G(xmm) -> E(xmm) case, which is something binutils
doesn't produce, presumably because it uses the E->G encoding for xmm
reg-reg moves. Fixes #238713. (Pierre Willenbrock,
pi...@pi...).
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-07-29 07:01:29 UTC (rev 1992)
+++ trunk/priv/guest_amd64_toIR.c 2010-07-29 07:19:30 UTC (rev 1993)
@@ -11036,19 +11036,24 @@
/* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
/* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F
+ if (have66noF2noF3(pfx) && insn[0] == 0x0F
&& (insn[1] == 0x29 || insn[1] == 0x11)) {
+ HChar* wot = insn[1]==0x29 ? "apd" : "upd";
modrm = getUChar(delta+2);
if (epartIsReg(modrm)) {
- /* fall through; awaiting test case */
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg( gregOfRexRM(pfx,modrm) ) );
+ DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ delta += 2+1;
} else {
addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("mov[ua]pd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- dis_buf );
+ DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
delta += 2+alen;
- goto decode_success;
}
+ goto decode_success;
}
/* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */
|
|
From: <sv...@va...> - 2010-07-29 07:03:13
|
Author: sewardj Date: 2010-07-29 08:03:05 +0100 (Thu, 29 Jul 2010) New Revision: 11236 Log: Update expected output for Ubuntu 10.04. Modified: trunk/none/tests/amd64/bug132918.stdout.exp Modified: trunk/none/tests/amd64/bug132918.stdout.exp =================================================================== --- trunk/none/tests/amd64/bug132918.stdout.exp 2010-07-29 07:02:18 UTC (rev 11235) +++ trunk/none/tests/amd64/bug132918.stdout.exp 2010-07-29 07:03:05 UTC (rev 11236) @@ -1,6 +1,6 @@ xx1 -> 0x4200 8.300000 xx2 -> 0x0000 1.440000 -xx -> 0x0000 nan +xx -> 0x0000 -nan xx -> 0x0000 0.809017 xx -> 0x0000 0.309018 xx -> 0x0000 -0.309015 |
|
From: <sv...@va...> - 2010-07-29 07:02:30
|
Author: sewardj
Date: 2010-07-29 08:02:18 +0100 (Thu, 29 Jul 2010)
New Revision: 11235
Log:
Update expected outputs following vex r1992.
Modified:
trunk/none/tests/amd64/fxtract.stdout.exp
trunk/none/tests/x86/fxtract.stdout.exp
Modified: trunk/none/tests/amd64/fxtract.stdout.exp
===================================================================
--- trunk/none/tests/amd64/fxtract.stdout.exp 2010-07-29 05:28:02 UTC (rev 11234)
+++ trunk/none/tests/amd64/fxtract.stdout.exp 2010-07-29 07:02:18 UTC (rev 11235)
@@ -40,7 +40,7 @@
2.7049662808e+02 -> 1.0566274534 8.0000000000
0.0000000000e+00 -> 0.0000000000 -inf
inf -> inf inf
- nan -> nan nan
+ -nan -> -nan -nan
7.2124891681e-308 -> 1.6207302828 -1021.0000000000
5.7982756057e-308 -> 1.3029400313 -1021.0000000000
4.3840620434e-308 -> 1.9702995595 -1022.0000000000
Modified: trunk/none/tests/x86/fxtract.stdout.exp
===================================================================
--- trunk/none/tests/x86/fxtract.stdout.exp 2010-07-29 05:28:02 UTC (rev 11234)
+++ trunk/none/tests/x86/fxtract.stdout.exp 2010-07-29 07:02:18 UTC (rev 11235)
@@ -40,7 +40,7 @@
2.7049662808e+02 -> 1.0566274534 8.0000000000
0.0000000000e+00 -> 0.0000000000 -inf
inf -> inf inf
- nan -> nan nan
+ -nan -> -nan -nan
7.2124891681e-308 -> 1.6207302828 -1021.0000000000
5.7982756057e-308 -> 1.3029400313 -1021.0000000000
4.3840620434e-308 -> 1.9702995595 -1022.0000000000
|
|
From: <sv...@va...> - 2010-07-29 07:01:36
|
Author: sewardj
Date: 2010-07-29 08:01:29 +0100 (Thu, 29 Jul 2010)
New Revision: 1992
Log:
x86/amd64 FXTRACT: mimic the Core i5 behaviour when the argument is a
negative NaN.
Modified:
trunk/priv/guest_generic_x87.c
Modified: trunk/priv/guest_generic_x87.c
===================================================================
--- trunk/priv/guest_generic_x87.c 2010-07-29 05:13:58 UTC (rev 1991)
+++ trunk/priv/guest_generic_x87.c 2010-07-29 07:01:29 UTC (rev 1992)
@@ -453,13 +453,13 @@
const ULong bit52 = 1ULL << 52;
const ULong sigMask = bit52 - 1;
- /* Mimic PIII behaviour for special cases. */
+ /* Mimic Core i5 behaviour for special cases. */
if (arg == posInf)
return getExp ? posInf : posInf;
if (arg == negInf)
return getExp ? posInf : negInf;
if ((arg & nanMask) == nanMask)
- return qNan;
+ return qNan | (arg & (1ULL << 63));
if (arg == posZero)
return getExp ? negInf : posZero;
if (arg == negZero)
|
|
From: <sv...@va...> - 2010-07-29 05:32:41
|
Author: sewardj
Date: 2010-07-29 06:24:20 +0100 (Thu, 29 Jul 2010)
New Revision: 11233
Log:
Comment-only change.
Modified:
trunk/configure.in
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2010-07-29 05:18:09 UTC (rev 11232)
+++ trunk/configure.in 2010-07-29 05:24:20 UTC (rev 11233)
@@ -584,7 +584,7 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_DARWIN)
-# Similarly, set up VGCONF_OF_IS_<os>. Exactly one of these becomes defined.
+# Similarly, set up VGCONF_OS_IS_<os>. Exactly one of these becomes defined.
# Relies on the assumption that the primary and secondary targets are
# for the same OS, so therefore only necessary to test the primary.
AM_CONDITIONAL(VGCONF_OS_IS_LINUX,
|
|
From: <sv...@va...> - 2010-07-29 05:32:41
|
Author: sewardj
Date: 2010-07-29 06:13:58 +0100 (Thu, 29 Jul 2010)
New Revision: 1991
Log:
Ignore a redundant REX.W prefix on an MMX pinsrw instruction
(Dan Gohman, dg...@gm...). Fixes #239992.
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-07-28 19:26:59 UTC (rev 1990)
+++ trunk/priv/guest_amd64_toIR.c 2010-07-29 05:13:58 UTC (rev 1991)
@@ -9951,7 +9951,8 @@
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
put it into the specified lane of mmx(G). */
- if (haveNo66noF2noF3(pfx) && sz == 4
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
&& insn[0] == 0x0F && insn[1] == 0xC4) {
/* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
mmx reg. t4 is the new lane value. t5 is the original
|
|
From: <sv...@va...> - 2010-07-29 05:28:10
|
Author: sewardj
Date: 2010-07-29 06:28:02 +0100 (Thu, 29 Jul 2010)
New Revision: 11234
Log:
When reporting an error about an attempt to re-lock an already-locked
lock, also report the stack where the lock was previously locked.
This makes it easier to diagnose deadlocks.
Modified:
trunk/helgrind/hg_errors.c
trunk/helgrind/hg_errors.h
trunk/helgrind/hg_main.c
Modified: trunk/helgrind/hg_errors.c
===================================================================
--- trunk/helgrind/hg_errors.c 2010-07-29 05:24:20 UTC (rev 11233)
+++ trunk/helgrind/hg_errors.c 2010-07-29 05:28:02 UTC (rev 11234)
@@ -222,8 +222,10 @@
ExeContext* after_ec;
} LockOrder;
struct {
- Thread* thr;
- HChar* errstr; /* persistent, in tool-arena */
+ Thread* thr;
+ HChar* errstr; /* persistent, in tool-arena */
+ HChar* auxstr; /* optional, persistent, in tool-arena */
+ ExeContext* auxctx; /* optional */
} Misc;
} XE;
}
@@ -507,7 +509,8 @@
XE_PthAPIerror, 0, NULL, &xe );
}
-void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
+void HG_(record_error_Misc_w_aux) ( Thread* thr, HChar* errstr,
+ HChar* auxstr, ExeContext* auxctx )
{
XError xe;
tl_assert( HG_(is_sane_Thread)(thr) );
@@ -516,6 +519,8 @@
xe.tag = XE_Misc;
xe.XE.Misc.thr = thr;
xe.XE.Misc.errstr = string_table_strdup(errstr);
+ xe.XE.Misc.auxstr = auxstr ? string_table_strdup(auxstr) : NULL;
+ xe.XE.Misc.auxctx = auxctx;
// FIXME: tid vs thr
tl_assert( HG_(is_sane_ThreadId)(thr->coretid) );
tl_assert( thr->coretid != VG_INVALID_THREADID );
@@ -523,6 +528,11 @@
XE_Misc, 0, NULL, &xe );
}
+void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
+{
+ HG_(record_error_Misc_w_aux)(thr, errstr, NULL, NULL);
+}
+
Bool HG_(eq_Error) ( VgRes not_used, Error* e1, Error* e2 )
{
XError *xe1, *xe2;
@@ -716,6 +726,11 @@
(Int)xe->XE.Misc.thr->errmsg_index );
emit( " </xwhat>\n" );
VG_(pp_ExeContext)( VG_(get_error_where)(err) );
+ if (xe->XE.Misc.auxstr) {
+ emit(" <auxwhat>%s</auxwhat>\n", xe->XE.Misc.auxstr);
+ if (xe->XE.Misc.auxctx)
+ VG_(pp_ExeContext)( xe->XE.Misc.auxctx );
+ }
} else {
@@ -723,6 +738,11 @@
(Int)xe->XE.Misc.thr->errmsg_index,
xe->XE.Misc.errstr );
VG_(pp_ExeContext)( VG_(get_error_where)(err) );
+ if (xe->XE.Misc.auxstr) {
+ emit(" %s\n", xe->XE.Misc.auxstr);
+ if (xe->XE.Misc.auxctx)
+ VG_(pp_ExeContext)( xe->XE.Misc.auxctx );
+ }
}
break;
Modified: trunk/helgrind/hg_errors.h
===================================================================
--- trunk/helgrind/hg_errors.h 2010-07-29 05:24:20 UTC (rev 11233)
+++ trunk/helgrind/hg_errors.h 2010-07-29 05:28:02 UTC (rev 11234)
@@ -59,8 +59,11 @@
void HG_(record_error_PthAPIerror) ( Thread*, HChar*, Word, HChar* );
void HG_(record_error_LockOrder) ( Thread*, Addr, Addr,
ExeContext*, ExeContext* );
-void HG_(record_error_Misc) ( Thread*, HChar* );
+void HG_(record_error_Misc_w_aux) ( Thread*, HChar* errstr,
+ HChar* auxstr, ExeContext* auxctx );
+void HG_(record_error_Misc) ( Thread* thr, HChar* errstr );
+
/* Statistics pertaining to error management. */
extern ULong HG_(stats__LockN_to_P_queries);
extern ULong HG_(stats__LockN_to_P_get_map_size) ( void );
Modified: trunk/helgrind/hg_main.c
===================================================================
--- trunk/helgrind/hg_main.c 2010-07-29 05:24:20 UTC (rev 11233)
+++ trunk/helgrind/hg_main.c 2010-07-29 05:28:02 UTC (rev 11234)
@@ -1980,8 +1980,14 @@
this is a real lock operation (not a speculative "tryLock"
kind of thing). Duh. Deadlock coming up; but at least
produce an error message. */
- HG_(record_error_Misc)( thr, "Attempt to re-lock a "
- "non-recursive lock I already hold" );
+ HChar* errstr = "Attempt to re-lock a "
+ "non-recursive lock I already hold";
+ HChar* auxstr = "Lock was previously acquired";
+ if (lk->acquired_at) {
+ HG_(record_error_Misc_w_aux)( thr, errstr, auxstr, lk->acquired_at );
+ } else {
+ HG_(record_error_Misc)( thr, errstr );
+ }
}
}
|
|
From: <sv...@va...> - 2010-07-29 05:27:39
|
Author: sewardj
Date: 2010-07-29 06:18:09 +0100 (Thu, 29 Jul 2010)
New Revision: 11232
Log:
Handle sys_ioperm on Linux. Fixes #237723.
Modified:
trunk/exp-ptrcheck/h_main.c
Modified: trunk/exp-ptrcheck/h_main.c
===================================================================
--- trunk/exp-ptrcheck/h_main.c 2010-07-27 09:09:55 UTC (rev 11231)
+++ trunk/exp-ptrcheck/h_main.c 2010-07-29 05:18:09 UTC (rev 11232)
@@ -2330,6 +2330,7 @@
ADD(0, __NR_getuid32);
# endif
ADD(0, __NR_getxattr);
+ ADD(0, __NR_ioperm);
ADD(0, __NR_inotify_add_watch);
ADD(0, __NR_inotify_init);
# if defined(__NR_inotify_init1)
|