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From: Nicholas N. <n.n...@gm...> - 2010-02-28 23:41:40
|
On Fri, Feb 19, 2010 at 10:01 AM, <sv...@va...> wrote: > Author: sewardj > Date: 2010-02-18 23:01:26 +0000 (Thu, 18 Feb 2010) > New Revision: 1960 > > Log: > Majorly improved implementation of self-checking for translations. > This reduces the overhead of --smc-check=all by a factor of between 2 > and 3. Nice! I added a note about this in NEWS. N |
|
From: <sv...@va...> - 2010-02-28 23:41:28
|
Author: njn Date: 2010-02-28 23:41:07 +0000 (Sun, 28 Feb 2010) New Revision: 11057 Log: some updates for NEWS Modified: trunk/NEWS Modified: trunk/NEWS =================================================================== --- trunk/NEWS 2010-02-28 09:51:00 UTC (rev 11056) +++ trunk/NEWS 2010-02-28 23:41:07 UTC (rev 11057) @@ -1,4 +1,13 @@ +Release 3.6.0 (???) +~~~~~~~~~~~~~~~~~~~ +Improvements: +- XXX: ARM support + +- --smc-check=all is much faster + + + Release 3.5.0 (19 August 2009) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3.5.0 is a feature release with many significant improvements and the |
|
From: Bart V. A. <bva...@ac...> - 2010-02-28 11:56:27
|
On Sun, Feb 28, 2010 at 12:51 PM, Konstantin Serebryany <kon...@gm...> wrote: > On Sun, Feb 28, 2010 at 2:44 PM, Bart Van Assche <bva...@ac...> wrote: >> Recently I found out that support has been added in Intel Parallel Studio >> and lock annotations. More information can be found here: >> http://software.intel.com/sites/support/padvisor/annotation_summary.htm >> http://software.intel.com/sites/support/padvisor/title.htm > > Interesting! :) > Thread Checker had something similar, but the names were different. The reason I posted this information on the valgrind-developers mailing list is that when adding new annotations we can have a look at that list in order to avoid defining macro's with the same name but different semantics. Bart. |
|
From: Konstantin S. <kon...@gm...> - 2010-02-28 11:51:43
|
Interesting! :) Thread Checker had something similar, but the names were different. --kcc On Sun, Feb 28, 2010 at 2:44 PM, Bart Van Assche <bva...@ac...> wrote: > Hello, > > Recently I found out that support has been added in Intel Parallel Studio > and lock annotations. More information can be found here: > http://software.intel.com/sites/support/padvisor/annotation_summary.htm > http://software.intel.com/sites/support/padvisor/title.htm > > Bart. > |
|
From: Bart V. A. <bva...@ac...> - 2010-02-28 11:44:37
|
Hello, Recently I found out that support has been added in Intel Parallel Studio and lock annotations. More information can be found here: http://software.intel.com/sites/support/padvisor/annotation_summary.htm http://software.intel.com/sites/support/padvisor/title.htm Bart. |
|
From: <sv...@va...> - 2010-02-28 09:51:15
|
Author: bart
Date: 2010-02-28 09:51:00 +0000 (Sun, 28 Feb 2010)
New Revision: 11056
Log:
Updated the semantics of ANNOTATE_BENIGN_RACE() as discussed on the Valgrind
developers mailing list (on February 15, 2010).
Modified:
trunk/drd/drd.h
Modified: trunk/drd/drd.h
===================================================================
--- trunk/drd/drd.h 2010-02-23 10:49:48 UTC (rev 11055)
+++ trunk/drd/drd.h 2010-02-28 09:51:00 UTC (rev 11056)
@@ -228,10 +228,11 @@
#define ANNOTATE_PCQ_GET(pcq) do { } while(0)
/**
- * Tell DRD that data races in the specified address range are expected and
- * must not be reported.
+ * Tell DRD that data races at the specified address are expected and must not
+ * be reported.
*/
-#define ANNOTATE_BENIGN_RACE(addr, descr) DRDCL_(ignore_range)(addr, 4)
+#define ANNOTATE_BENIGN_RACE(addr, descr) \
+ DRDCL_(ignore_range)(addr, sizeof(*addr))
/** Tell DRD to ignore all reads performed by the current thread. */
#define ANNOTATE_IGNORE_READS_BEGIN() DRDCL_(set_record_loads)(0)
|
|
From: <sv...@va...> - 2010-02-28 04:53:30
|
Author: sewardj
Date: 2010-02-28 04:53:07 +0000 (Sun, 28 Feb 2010)
New Revision: 1963
Log:
Handle SBB Eb,Gb.
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-02-28 04:51:02 UTC (rev 1962)
+++ trunk/priv/guest_amd64_toIR.c 2010-02-28 04:53:07 UTC (rev 1963)
@@ -14442,9 +14442,10 @@
delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
break;
-//.. //-- case 0x1A: /* SBB Eb,Gb */
-//.. //-- delta = dis_op2_E_G ( sorb, True, SBB, True, 1, delta, "sbb" );
-//.. //-- break;
+ case 0x1A: /* SBB Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ break;
case 0x1B: /* SBB Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
|
|
From: <sv...@va...> - 2010-02-28 04:52:00
|
Author: sewardj
Date: 2010-02-28 04:51:02 +0000 (Sun, 28 Feb 2010)
New Revision: 1962
Log:
Fix incorrect spec rule for LE after INCB, for end-of range cases (arg = 0x7F).
Modified:
trunk/priv/guest_amd64_helpers.c
Modified: trunk/priv/guest_amd64_helpers.c
===================================================================
--- trunk/priv/guest_amd64_helpers.c 2010-02-21 20:40:53 UTC (rev 1961)
+++ trunk/priv/guest_amd64_helpers.c 2010-02-28 04:51:02 UTC (rev 1962)
@@ -1189,11 +1189,12 @@
/*---------------- INCB ----------------*/
if (isU64(cc_op, AMD64G_CC_OP_INCB) && isU64(cond, AMD64CondLE)) {
- /* 8-bit inc, then LE --> test result <=s 0 */
- return unop(Iop_1Uto64,
- binop(Iop_CmpLE64S,
- binop(Iop_Shl64,cc_dep1,mkU8(56)),
- mkU64(0)));
+ /* 8-bit inc, then LE --> sign bit of the arg */
+ return binop(Iop_And64,
+ binop(Iop_Shr64,
+ binop(Iop_Sub64, cc_dep1, mkU64(1)),
+ mkU8(7)),
+ mkU64(1));
}
/*---------------- INCW ----------------*/
|