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From: <sv...@va...> - 2009-12-29 16:56:32
|
Author: bart
Date: 2009-12-29 16:56:18 +0000 (Tue, 29 Dec 2009)
New Revision: 10972
Log:
Removed dependency of include/pub_tool_basics.h on config.h.
Modified:
trunk/configure.in
trunk/coregrind/m_aspacemgr/aspacemgr-common.c
trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
trunk/coregrind/m_syswrap/syswrap-generic.c
trunk/helgrind/hg_intercepts.c
trunk/include/pub_tool_basics.h
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/configure.in 2009-12-29 16:56:18 UTC (rev 10972)
@@ -1378,24 +1378,6 @@
CFLAGS=$safe_CFLAGS
-# does this compiler support __builtin_expect?
-AC_MSG_CHECKING([if gcc supports __builtin_expect])
-
-AC_TRY_LINK(, [
-return __builtin_expect(1, 1) ? 1 : 0
-],
-[
-ac_have_builtin_expect=yes
-AC_MSG_RESULT([yes])
-], [
-ac_have_builtin_expect=no
-AC_MSG_RESULT([no])
-])
-if test x$ac_have_builtin_expect = xyes ; then
- AC_DEFINE(HAVE_BUILTIN_EXPECT, 1, [Define to 1 if gcc supports __builtin_expect.])
-fi
-
-
# does the ppc assembler support "mtocrf" et al?
AC_MSG_CHECKING([if ppc32/64 as supports mtocrf/mfocrf])
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-common.c
===================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-common.c 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-common.c 2009-12-29 16:56:18 UTC (rev 10972)
@@ -37,6 +37,7 @@
************************************************************* */
#include "priv_aspacemgr.h"
+#include "config.h"
/*-----------------------------------------------------------------*/
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
===================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-linux.c 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-linux.c 2009-12-29 16:56:18 UTC (rev 10972)
@@ -40,6 +40,7 @@
************************************************************* */
#include "priv_aspacemgr.h"
+#include "config.h"
/* Note: many of the exported functions implemented below are
Modified: trunk/coregrind/m_syswrap/syswrap-generic.c
===================================================================
--- trunk/coregrind/m_syswrap/syswrap-generic.c 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/coregrind/m_syswrap/syswrap-generic.c 2009-12-29 16:56:18 UTC (rev 10972)
@@ -62,7 +62,9 @@
#include "priv_types_n_macros.h"
#include "priv_syswrap-generic.h"
+#include "config.h"
+
/* Returns True iff address range is something the client can
plausibly mess with: all of it is either already belongs to the
client or is free or a reservation. */
Modified: trunk/helgrind/hg_intercepts.c
===================================================================
--- trunk/helgrind/hg_intercepts.c 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/helgrind/hg_intercepts.c 2009-12-29 16:56:18 UTC (rev 10972)
@@ -56,6 +56,7 @@
#include "pub_tool_redir.h"
#include "valgrind.h"
#include "helgrind.h"
+#include "config.h"
#define TRACE_PTH_FNS 0
#define TRACE_QT4_FNS 0
Modified: trunk/include/pub_tool_basics.h
===================================================================
--- trunk/include/pub_tool_basics.h 2009-12-29 15:08:14 UTC (rev 10971)
+++ trunk/include/pub_tool_basics.h 2009-12-29 16:56:18 UTC (rev 10972)
@@ -49,10 +49,7 @@
// For varargs types
#include <stdarg.h>
-/* For HAVE_BUILTIN_EXPECT */
-#include "config.h"
-
/* ---------------------------------------------------------------------
symbol prefixing
------------------------------------------------------------------ */
@@ -318,7 +315,7 @@
#define VG_BUGS_TO "www.valgrind.org"
/* Branch prediction hints. */
-#if HAVE_BUILTIN_EXPECT
+#if 1 /*HAVE_BUILTIN_EXPECT*/
# define LIKELY(x) __builtin_expect(!!(x), 1)
# define UNLIKELY(x) __builtin_expect((x), 0)
#else
|
|
From: Konstantin S. <kon...@gm...> - 2009-12-29 15:38:17
|
On Tue, Dec 29, 2009 at 6:19 PM, Bart Van Assche <bar...@gm...>wrote: > On Tue, Dec 29, 2009 at 11:53 AM, Konstantin Serebryany > <kon...@gm...> wrote: > > First question: > > Valgrind installation contains include files, which makes me think that > it is possible to build valgrind tools w/o having the valgrind sources. > > However, with the current version of valgrind, it does dot > work: include/valgrind/pub_tool_basics.h includes "config.h", which is not a > part of valgrind installation. > > Can that be fixed? > > The header file "config.h" is included because the configure script > figures out whether or not the selected compiler supports > __builtin_expect() (HAVE_BUILTIN_EXPECT). Since gcc supports > __builtin_expect() since at least gcc 3.0, and since we only support > gcc 3.2 and above, it's probably safe to remove the #ifdef > HAVE_BUILTIN_EXPECT and #include "config.h". > That sounds good! > > > Third question: > > Few of the valgrind public headers are not C++-able. > > Can that be fixed? > > Should be fixed through r10970 and r10971. By the way, r10970 builds > fine on Darwin and x86-64 but not on PPC. > Yep, works! Thanks! --kcc > > Bart. > |
|
From: Bart V. A. <bar...@gm...> - 2009-12-29 15:19:48
|
On Tue, Dec 29, 2009 at 11:53 AM, Konstantin Serebryany <kon...@gm...> wrote: > First question: > Valgrind installation contains include files, which makes me think that it is possible to build valgrind tools w/o having the valgrind sources. > However, with the current version of valgrind, it does dot work: include/valgrind/pub_tool_basics.h includes "config.h", which is not a part of valgrind installation. > Can that be fixed? The header file "config.h" is included because the configure script figures out whether or not the selected compiler supports __builtin_expect() (HAVE_BUILTIN_EXPECT). Since gcc supports __builtin_expect() since at least gcc 3.0, and since we only support gcc 3.2 and above, it's probably safe to remove the #ifdef HAVE_BUILTIN_EXPECT and #include "config.h". > Third question: > Few of the valgrind public headers are not C++-able. > Can that be fixed? Should be fixed through r10970 and r10971. By the way, r10970 builds fine on Darwin and x86-64 but not on PPC. Bart. |
|
From: <sv...@va...> - 2009-12-29 15:08:31
|
Author: bart
Date: 2009-12-29 15:08:14 +0000 (Tue, 29 Dec 2009)
New Revision: 10971
Log:
Made sure that C++ compilers do not complain about the _VKI_IOC_TYPECHECK() macro.
Modified:
trunk/include/vki/vki-ppc32-linux.h
trunk/include/vki/vki-ppc64-linux.h
trunk/include/vki/vki-x86-linux.h
Modified: trunk/include/vki/vki-ppc32-linux.h
===================================================================
--- trunk/include/vki/vki-ppc32-linux.h 2009-12-29 14:11:38 UTC (rev 10970)
+++ trunk/include/vki/vki-ppc32-linux.h 2009-12-29 15:08:14 UTC (rev 10971)
@@ -516,11 +516,9 @@
((size) << _VKI_IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
-extern unsigned int __VKI_invalid_size_argument_for_IOC;
#define _VKI_IOC_TYPECHECK(t) \
- ((sizeof(t) == sizeof(t[1]) && \
- sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \
- sizeof(t) : __VKI_invalid_size_argument_for_IOC)
+ (sizeof(t) / (sizeof(t) == sizeof(t[1]) && \
+ sizeof(t) < (1 << _VKI_IOC_SIZEBITS)))
/* used to create numbers */
#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
Modified: trunk/include/vki/vki-ppc64-linux.h
===================================================================
--- trunk/include/vki/vki-ppc64-linux.h 2009-12-29 14:11:38 UTC (rev 10970)
+++ trunk/include/vki/vki-ppc64-linux.h 2009-12-29 15:08:14 UTC (rev 10971)
@@ -559,11 +559,9 @@
((size) << _VKI_IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
-extern unsigned int __invalid_size_argument_for_IOC;
#define _VKI_IOC_TYPECHECK(t) \
- ((sizeof(t) == sizeof(t[1]) && \
- sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \
- sizeof(t) : __invalid_size_argument_for_IOC)
+ (sizeof(t) / (sizeof(t) == sizeof(t[1]) && \
+ sizeof(t) < (1 << _VKI_IOC_SIZEBITS)))
/* used to create numbers */
#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
Modified: trunk/include/vki/vki-x86-linux.h
===================================================================
--- trunk/include/vki/vki-x86-linux.h 2009-12-29 14:11:38 UTC (rev 10970)
+++ trunk/include/vki/vki-x86-linux.h 2009-12-29 15:08:14 UTC (rev 10971)
@@ -480,11 +480,9 @@
((size) << _VKI_IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
-extern unsigned int __vki_invalid_size_argument_for_IOC;
#define _VKI_IOC_TYPECHECK(t) \
- ((sizeof(t) == sizeof(t[1]) && \
- sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \
- sizeof(t) : __vki_invalid_size_argument_for_IOC)
+ (sizeof(t) / (sizeof(t) == sizeof(t[1]) && \
+ sizeof(t) < (1 << _VKI_IOC_SIZEBITS)))
/* used to create numbers */
#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
|
|
From: Konstantin S. <kon...@gm...> - 2009-12-29 14:44:55
|
Thank you, Bart!
Two things are still wrong:
1.pub_tool_basics.h still includes config.h, but config.h is not a part of
valgrind installation
2. When I compile none/tests/valgrind_cpp_test.cpp with gcc4.4 on linux with
-m32 I get this:
g++ -Iinst/include/valgrind -I. -DVGA_x86=1 -DVGO_linux=1 -DVGP_x86_linux=1
-m32 none/tests/valgrind_cpp_test.cpp
In file included from inst/include/valgrind/pub_tool_vki.h:49,
from none/tests/valgrind_cpp_test.cpp:14:
inst/include/valgrind/vki/vki-linux.h:2154: error:
'__vki_invalid_size_argument_for_IOC' cannot appear in a constant-expression
inst/include/valgrind/vki/vki-linux.h:2157: error:
'__vki_invalid_size_argument_for_IOC' cannot appear in a constant-expression
You need this (or similar) patch to resolve this:
Index: include/vki/vki-x86-linux.h
===================================================================
--- include/vki/vki-x86-linux.h (revision 10969)
+++ include/vki/vki-x86-linux.h (working copy)
@@ -479,12 +479,11 @@
((nr) << _VKI_IOC_NRSHIFT) | \
((size) << _VKI_IOC_SIZESHIFT))
-/* provoke compile error for invalid uses of size argument */
-extern unsigned int __vki_invalid_size_argument_for_IOC;
+/* provoke compile error (div by zero) for invalid uses of size argument */
#define _VKI_IOC_TYPECHECK(t) \
- ((sizeof(t) == sizeof(t[1]) && \
- sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \
- sizeof(t) : __vki_invalid_size_argument_for_IOC)
+ (sizeof(t) / \
+ (sizeof(t) == sizeof(t[1]) && \
+ sizeof(t) < (1 << _VKI_IOC_SIZEBITS)))
/* used to create numbers */
#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
--kcc
On Tue, Dec 29, 2009 at 5:11 PM, <sv...@va...> wrote:
> Author: bart
> Date: 2009-12-29 14:11:38 +0000 (Tue, 29 Dec 2009)
> New Revision: 10970
>
> Log:
> Changes:
> - Made sure that C++ compilers do not complain about the header files
> include/pub_tool_libcassert.h and include/pub_tool_basics.h.
> - Added the source file none/tests/valgrind_cpp_test.cpp. This source file
> is compiled together with the regression tests in order to verify that
> Valgrind's public header files compile cleanly with a C++ compiler.
> These modifications are based on a patch provided by Konstantin Serebryany.
>
>
> Added:
> trunk/none/tests/valgrind_cpp_test.cpp
> Modified:
> trunk/include/pub_tool_basics.h
> trunk/include/pub_tool_libcassert.h
> trunk/none/tests/
> trunk/none/tests/Makefile.am
>
>
> Modified: trunk/include/pub_tool_basics.h
> ===================================================================
> --- trunk/include/pub_tool_basics.h 2009-12-21 11:29:54 UTC (rev 10969)
> +++ trunk/include/pub_tool_basics.h 2009-12-29 14:11:38 UTC (rev 10970)
> @@ -193,15 +193,18 @@
> SysRes;
> #elif defined(VGO_darwin)
> typedef
> + enum {
> + SysRes_MACH=40, // MACH, result is _wLO
> + SysRes_MDEP, // MDEP, result is _wLO
> + SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO
> + SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO
> + }
> + SysResMode;
> +typedef
> struct {
> UWord _wLO;
> UWord _wHI;
> - enum {
> - SysRes_MACH=40, // MACH, result is _wLO
> - SysRes_MDEP, // MDEP, result is _wLO
> - SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO
> - SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO
> - } _mode;
> + SysResMode _mode;
> }
> SysRes;
> #else
>
> Modified: trunk/include/pub_tool_libcassert.h
> ===================================================================
> --- trunk/include/pub_tool_libcassert.h 2009-12-21 11:29:54 UTC (rev 10969)
> +++ trunk/include/pub_tool_libcassert.h 2009-12-29 14:11:38 UTC (rev 10970)
> @@ -33,15 +33,17 @@
>
> #define tl_assert(expr) \
> ((void) ((expr) ? 0 : \
> - (VG_(assert_fail) (/*isCore?*/False, #expr, \
> - __FILE__, __LINE__, __PRETTY_FUNCTION__, \
> - ""), \
> + (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \
> + (const Char*)__FILE__, __LINE__, \
> + (const Char*)__PRETTY_FUNCTION__, \
> + (const HChar*)""), \
> 0)))
>
> #define tl_assert2(expr, format, args...) \
> ((void) ((expr) ? 0 : \
> - (VG_(assert_fail) (/*isCore?*/False, #expr, \
> - __FILE__, __LINE__, __PRETTY_FUNCTION__, \
> + (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \
> + (const Char*)__FILE__, __LINE__, \
> + (const Char*)__PRETTY_FUNCTION__, \
> format, ##args), \
> 0)))
>
>
>
> Property changes on: trunk/none/tests
> ___________________________________________________________________
> Name: svn:ignore
> - *.dSYM
> *.so
> *.stderr.diff*
> *.stderr.out
> *.stdout.diff*
> *.stdout.out
> .deps
> ansi
> args
> async-sigs
> as_mmap
> as_shm
> bitfield1
> blockfault
> bug129866
> closeall
> coolo_sigaction
> coolo_strlen
> discard
> exec-sigmask
> execve
> faultstatus
> fcntl_setown
> fdleak_cmsg
> fdleak_creat
> fdleak_dup
> fdleak_dup2
> fdleak_fcntl
> fdleak_ipv4
> fdleak_open
> fdleak_pipe
> fdleak_socketpair
> floored
> fork
> fucomip
> gxx304
> insn_basic
> insn_basic.c
> insn_cmov
> insn_cmov.c
> insn_fpu
> insn_fpu.c
> insn_mmx
> insn_mmx.c
> insn_mmxext
> insn_mmxext.c
> insn_sse
> insn_sse.c
> insn_sse2
> insn_sse2.c
> Makefile
> Makefile.in
> manythreads
> map_unaligned
> map_unmap
> mq
> mremap
> mremap2
> munmap_exe
> nestedfns
> pending
> pluto
> procfs-cmdline-exe
> pth_atfork1
> pth_blockedsig
> pth_cancel1
> pth_cancel2
> pth_cvsimple
> pth_detached
> pth_empty
> pth_exit
> pth_exit2
> pth_mutexspeed
> pth_once
> pth_rwlock
> pth_semaphore1
> pth_simple_mutex
> pth_simple_threads
> pth_specific
> pth_stackalign
> pth_yield
> rcrl
> readline1
> resolv
> res_search
> rlimit_nofile
> selfrun
> sem
> semlimit
> sha1_test
> shortpush
> shorts
> sigstackgrowth
> smc1
> stackgrowth
> susphello
> syscall-restart1
> syscall-restart2
> syslog
> system
> thread-exits
> threaded-fork
> threadederrno
> timestamp
> tls
> vgcore.*
> vgprintf
> yield
>
> + *.dSYM
> *.so
> *.stderr.diff*
> *.stderr.out
> *.stdout.diff*
> *.stdout.out
> .deps
> ansi
> args
> async-sigs
> as_mmap
> as_shm
> bitfield1
> blockfault
> bug129866
> closeall
> coolo_sigaction
> coolo_strlen
> discard
> exec-sigmask
> execve
> faultstatus
> fcntl_setown
> fdleak_cmsg
> fdleak_creat
> fdleak_dup
> fdleak_dup2
> fdleak_fcntl
> fdleak_ipv4
> fdleak_open
> fdleak_pipe
> fdleak_socketpair
> floored
> fork
> fucomip
> gxx304
> insn_basic
> insn_basic.c
> insn_cmov
> insn_cmov.c
> insn_fpu
> insn_fpu.c
> insn_mmx
> insn_mmx.c
> insn_mmxext
> insn_mmxext.c
> insn_sse
> insn_sse.c
> insn_sse2
> insn_sse2.c
> Makefile
> Makefile.in
> manythreads
> map_unaligned
> map_unmap
> mq
> mremap
> mremap2
> munmap_exe
> nestedfns
> pending
> pluto
> procfs-cmdline-exe
> pth_atfork1
> pth_blockedsig
> pth_cancel1
> pth_cancel2
> pth_cvsimple
> pth_detached
> pth_empty
> pth_exit
> pth_exit2
> pth_mutexspeed
> pth_once
> pth_rwlock
> pth_semaphore1
> pth_simple_mutex
> pth_simple_threads
> pth_specific
> pth_stackalign
> pth_yield
> rcrl
> readline1
> resolv
> res_search
> rlimit_nofile
> selfrun
> sem
> semlimit
> sha1_test
> shortpush
> shorts
> sigstackgrowth
> smc1
> stackgrowth
> susphello
> syscall-restart1
> syscall-restart2
> syslog
> system
> thread-exits
> threaded-fork
> threadederrno
> timestamp
> tls
> valgrind_cpp_test
> vgcore.*
> vgprintf
> yield
>
>
> Modified: trunk/none/tests/Makefile.am
> ===================================================================
> --- trunk/none/tests/Makefile.am 2009-12-21 11:29:54 UTC (rev 10969)
> +++ trunk/none/tests/Makefile.am 2009-12-29 14:11:38 UTC (rev 10970)
> @@ -175,6 +175,7 @@
> tls \
> tls.so \
> tls2.so \
> + valgrind_cpp_test \
> vgprintf \
> coolo_sigaction \
> gxx304
> @@ -262,6 +263,9 @@
> tls2_so_LDFLAGS = -shared
> endif
>
> +valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
> +valgrind_cpp_test_LDADD = -lstdc++
> +
> # C++ tests
> coolo_sigaction_SOURCES = coolo_sigaction.cpp
> gxx304_SOURCES = gxx304.cpp
>
> Added: trunk/none/tests/valgrind_cpp_test.cpp
> ===================================================================
> --- trunk/none/tests/valgrind_cpp_test.cpp
> (rev 0)
> +++ trunk/none/tests/valgrind_cpp_test.cpp 2009-12-29 14:11:38 UTC
> (rev 10970)
> @@ -0,0 +1,47 @@
> +// Test program to verify whether the Valgrind header files compile fine
> +// with a C++ compiler.
> +
> +
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include "pub_tool_basics.h"
> +#include "pub_tool_libcassert.h"
> +#include "pub_tool_libcbase.h"
> +#include "pub_tool_mallocfree.h"
> +#include "pub_tool_libcprint.h"
> +#include "pub_tool_libcfile.h"
> +#include "pub_tool_libcproc.h"
> +#include "pub_tool_vki.h"
> +#include "pub_tool_threadstate.h"
> +#include "pub_tool_errormgr.h"
> +#include "pub_tool_options.h"
> +#include "pub_tool_machine.h"
> +#include "pub_tool_debuginfo.h"
> +#include "pub_tool_seqmatch.h"
> +#include "pub_tool_tooliface.h"
> +#include "pub_tool_options.h"
> +
> +#if defined(VGO_darwin)
> +int CheckSys()
> +{
> + return SysRes_MACH;
> +}
> +#endif
> +
> +void CheckAssert(int x)
> +{
> + tl_assert(x);
> + tl_assert2(x, "fail");
> +}
> +
> +int main(int argc, char** argv)
> +{
> + fprintf(stderr, "Compilation succeeded.\n");
> + return 0;
> +}
> +
> +void VG_(assert_fail)(Bool isCore, const Char* expr, const Char* file,
> + Int line, const Char* fn, const HChar* format, ... )
> +{
> + abort();
> +}
>
>
>
> ------------------------------------------------------------------------------
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> Take advantage of Verizon's best-in-class app development support
> A streamlined, 14 day to market process makes app distribution fast and
> easy
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> _______________________________________________
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> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers
>
|
|
From: <sv...@va...> - 2009-12-29 14:38:04
|
Author: sewardj
Date: 2009-12-29 14:37:50 +0000 (Tue, 29 Dec 2009)
New Revision: 1946
Log:
Comment-only change: update comments w.r.t. register classes and spill
slot sizes.
Modified:
branches/ARM/priv/host_generic_reg_alloc2.c
branches/ARM/priv/host_generic_regs.h
Modified: branches/ARM/priv/host_generic_reg_alloc2.c
===================================================================
--- branches/ARM/priv/host_generic_reg_alloc2.c 2009-12-29 14:21:22 UTC (rev 1945)
+++ branches/ARM/priv/host_generic_reg_alloc2.c 2009-12-29 14:37:50 UTC (rev 1946)
@@ -832,7 +832,7 @@
}
/* The spill slots are 64 bits in size. As per the comment on
- definition of HRegClass in h_generic_regs.h, that means, to
+ definition of HRegClass in host_generic_regs.h, that means, to
spill a vreg of class Flt64 or Vec128, we'll need to find two
adjacent spill slots to use. Note, this logic needs to kept
in sync with the size info on the definition of HRegClass. */
Modified: branches/ARM/priv/host_generic_regs.h
===================================================================
--- branches/ARM/priv/host_generic_regs.h 2009-12-29 14:21:22 UTC (rev 1945)
+++ branches/ARM/priv/host_generic_regs.h 2009-12-29 14:37:50 UTC (rev 1946)
@@ -74,9 +74,9 @@
Note further that since the class field is never 1111b, no valid
register can have the value INVALID_HREG.
- There are currently 5 register classes:
+ There are currently 6 register classes:
- int32 int64 float64 simd64 simd128
+ int32 int64 float32 float64 simd64 simd128
*/
typedef UInt HReg;
@@ -87,18 +87,20 @@
available on any specific host. For example on x86, the available
classes are: Int32, Flt64, Vec128 only.
- IMPORTANT NOTE: reg_alloc2.c needs how much space is needed to spill
- each class of register. It has the following knowledge hardwired in:
+ IMPORTANT NOTE: host_generic_reg_alloc2.c needs how much space is
+ needed to spill each class of register. It allocates the following
+ amount of space:
- HRcInt32 32 bits
+ HRcInt32 64 bits
HRcInt64 64 bits
- HRcFlt32 ?? bits
- HRcFlt64 80 bits (on x86 these are spilled by fstpt/fldt)
+ HRcFlt32 64 bits
+ HRcFlt64 128 bits (on x86 these are spilled by fstpt/fldt and
+ so won't fit in a 64-bit slot)
HRcVec64 64 bits
HRcVec128 128 bits
If you add another regclass, you must remember to update
- reg_alloc2.c accordingly.
+ host_generic_reg_alloc2.c accordingly.
*/
typedef
enum {
|
|
From: <sv...@va...> - 2009-12-29 14:21:53
|
Author: sewardj
Date: 2009-12-29 14:21:22 +0000 (Tue, 29 Dec 2009)
New Revision: 1945
Log:
iselCondCode: check we're not return _NV or _AL
Modified:
branches/ARM/priv/host_arm_isel.c
Modified: branches/ARM/priv/host_arm_isel.c
===================================================================
--- branches/ARM/priv/host_arm_isel.c 2009-12-29 13:49:10 UTC (rev 1944)
+++ branches/ARM/priv/host_arm_isel.c 2009-12-29 14:21:22 UTC (rev 1945)
@@ -902,8 +902,9 @@
static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e )
{
- /* Uh, there's nothing we can sanity check here, unfortunately. */
- return iselCondCode_wrk(env,e);
+ ARMCondCode cc = iselCondCode_wrk(env,e);
+ vassert(cc != ARMcc_AL && cc != ARMcc_NV);
+ return cc;
}
static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
@@ -1014,8 +1015,6 @@
/* DO NOT CALL THIS DIRECTLY ! */
static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
-//zz MatchInfo mi;
-
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
|
|
From: <sv...@va...> - 2009-12-29 14:11:50
|
Author: bart
Date: 2009-12-29 14:11:38 +0000 (Tue, 29 Dec 2009)
New Revision: 10970
Log:
Changes:
- Made sure that C++ compilers do not complain about the header files
include/pub_tool_libcassert.h and include/pub_tool_basics.h.
- Added the source file none/tests/valgrind_cpp_test.cpp. This source file
is compiled together with the regression tests in order to verify that
Valgrind's public header files compile cleanly with a C++ compiler.
These modifications are based on a patch provided by Konstantin Serebryany.
Added:
trunk/none/tests/valgrind_cpp_test.cpp
Modified:
trunk/include/pub_tool_basics.h
trunk/include/pub_tool_libcassert.h
trunk/none/tests/
trunk/none/tests/Makefile.am
Modified: trunk/include/pub_tool_basics.h
===================================================================
--- trunk/include/pub_tool_basics.h 2009-12-21 11:29:54 UTC (rev 10969)
+++ trunk/include/pub_tool_basics.h 2009-12-29 14:11:38 UTC (rev 10970)
@@ -193,15 +193,18 @@
SysRes;
#elif defined(VGO_darwin)
typedef
+ enum {
+ SysRes_MACH=40, // MACH, result is _wLO
+ SysRes_MDEP, // MDEP, result is _wLO
+ SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO
+ SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO
+ }
+ SysResMode;
+typedef
struct {
UWord _wLO;
UWord _wHI;
- enum {
- SysRes_MACH=40, // MACH, result is _wLO
- SysRes_MDEP, // MDEP, result is _wLO
- SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO
- SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO
- } _mode;
+ SysResMode _mode;
}
SysRes;
#else
Modified: trunk/include/pub_tool_libcassert.h
===================================================================
--- trunk/include/pub_tool_libcassert.h 2009-12-21 11:29:54 UTC (rev 10969)
+++ trunk/include/pub_tool_libcassert.h 2009-12-29 14:11:38 UTC (rev 10970)
@@ -33,15 +33,17 @@
#define tl_assert(expr) \
((void) ((expr) ? 0 : \
- (VG_(assert_fail) (/*isCore?*/False, #expr, \
- __FILE__, __LINE__, __PRETTY_FUNCTION__, \
- ""), \
+ (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \
+ (const Char*)__FILE__, __LINE__, \
+ (const Char*)__PRETTY_FUNCTION__, \
+ (const HChar*)""), \
0)))
#define tl_assert2(expr, format, args...) \
((void) ((expr) ? 0 : \
- (VG_(assert_fail) (/*isCore?*/False, #expr, \
- __FILE__, __LINE__, __PRETTY_FUNCTION__, \
+ (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \
+ (const Char*)__FILE__, __LINE__, \
+ (const Char*)__PRETTY_FUNCTION__, \
format, ##args), \
0)))
Property changes on: trunk/none/tests
___________________________________________________________________
Name: svn:ignore
- *.dSYM
*.so
*.stderr.diff*
*.stderr.out
*.stdout.diff*
*.stdout.out
.deps
ansi
args
async-sigs
as_mmap
as_shm
bitfield1
blockfault
bug129866
closeall
coolo_sigaction
coolo_strlen
discard
exec-sigmask
execve
faultstatus
fcntl_setown
fdleak_cmsg
fdleak_creat
fdleak_dup
fdleak_dup2
fdleak_fcntl
fdleak_ipv4
fdleak_open
fdleak_pipe
fdleak_socketpair
floored
fork
fucomip
gxx304
insn_basic
insn_basic.c
insn_cmov
insn_cmov.c
insn_fpu
insn_fpu.c
insn_mmx
insn_mmx.c
insn_mmxext
insn_mmxext.c
insn_sse
insn_sse.c
insn_sse2
insn_sse2.c
Makefile
Makefile.in
manythreads
map_unaligned
map_unmap
mq
mremap
mremap2
munmap_exe
nestedfns
pending
pluto
procfs-cmdline-exe
pth_atfork1
pth_blockedsig
pth_cancel1
pth_cancel2
pth_cvsimple
pth_detached
pth_empty
pth_exit
pth_exit2
pth_mutexspeed
pth_once
pth_rwlock
pth_semaphore1
pth_simple_mutex
pth_simple_threads
pth_specific
pth_stackalign
pth_yield
rcrl
readline1
resolv
res_search
rlimit_nofile
selfrun
sem
semlimit
sha1_test
shortpush
shorts
sigstackgrowth
smc1
stackgrowth
susphello
syscall-restart1
syscall-restart2
syslog
system
thread-exits
threaded-fork
threadederrno
timestamp
tls
vgcore.*
vgprintf
yield
+ *.dSYM
*.so
*.stderr.diff*
*.stderr.out
*.stdout.diff*
*.stdout.out
.deps
ansi
args
async-sigs
as_mmap
as_shm
bitfield1
blockfault
bug129866
closeall
coolo_sigaction
coolo_strlen
discard
exec-sigmask
execve
faultstatus
fcntl_setown
fdleak_cmsg
fdleak_creat
fdleak_dup
fdleak_dup2
fdleak_fcntl
fdleak_ipv4
fdleak_open
fdleak_pipe
fdleak_socketpair
floored
fork
fucomip
gxx304
insn_basic
insn_basic.c
insn_cmov
insn_cmov.c
insn_fpu
insn_fpu.c
insn_mmx
insn_mmx.c
insn_mmxext
insn_mmxext.c
insn_sse
insn_sse.c
insn_sse2
insn_sse2.c
Makefile
Makefile.in
manythreads
map_unaligned
map_unmap
mq
mremap
mremap2
munmap_exe
nestedfns
pending
pluto
procfs-cmdline-exe
pth_atfork1
pth_blockedsig
pth_cancel1
pth_cancel2
pth_cvsimple
pth_detached
pth_empty
pth_exit
pth_exit2
pth_mutexspeed
pth_once
pth_rwlock
pth_semaphore1
pth_simple_mutex
pth_simple_threads
pth_specific
pth_stackalign
pth_yield
rcrl
readline1
resolv
res_search
rlimit_nofile
selfrun
sem
semlimit
sha1_test
shortpush
shorts
sigstackgrowth
smc1
stackgrowth
susphello
syscall-restart1
syscall-restart2
syslog
system
thread-exits
threaded-fork
threadederrno
timestamp
tls
valgrind_cpp_test
vgcore.*
vgprintf
yield
Modified: trunk/none/tests/Makefile.am
===================================================================
--- trunk/none/tests/Makefile.am 2009-12-21 11:29:54 UTC (rev 10969)
+++ trunk/none/tests/Makefile.am 2009-12-29 14:11:38 UTC (rev 10970)
@@ -175,6 +175,7 @@
tls \
tls.so \
tls2.so \
+ valgrind_cpp_test \
vgprintf \
coolo_sigaction \
gxx304
@@ -262,6 +263,9 @@
tls2_so_LDFLAGS = -shared
endif
+valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
+valgrind_cpp_test_LDADD = -lstdc++
+
# C++ tests
coolo_sigaction_SOURCES = coolo_sigaction.cpp
gxx304_SOURCES = gxx304.cpp
Added: trunk/none/tests/valgrind_cpp_test.cpp
===================================================================
--- trunk/none/tests/valgrind_cpp_test.cpp (rev 0)
+++ trunk/none/tests/valgrind_cpp_test.cpp 2009-12-29 14:11:38 UTC (rev 10970)
@@ -0,0 +1,47 @@
+// Test program to verify whether the Valgrind header files compile fine
+// with a C++ compiler.
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "pub_tool_basics.h"
+#include "pub_tool_libcassert.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_mallocfree.h"
+#include "pub_tool_libcprint.h"
+#include "pub_tool_libcfile.h"
+#include "pub_tool_libcproc.h"
+#include "pub_tool_vki.h"
+#include "pub_tool_threadstate.h"
+#include "pub_tool_errormgr.h"
+#include "pub_tool_options.h"
+#include "pub_tool_machine.h"
+#include "pub_tool_debuginfo.h"
+#include "pub_tool_seqmatch.h"
+#include "pub_tool_tooliface.h"
+#include "pub_tool_options.h"
+
+#if defined(VGO_darwin)
+int CheckSys()
+{
+ return SysRes_MACH;
+}
+#endif
+
+void CheckAssert(int x)
+{
+ tl_assert(x);
+ tl_assert2(x, "fail");
+}
+
+int main(int argc, char** argv)
+{
+ fprintf(stderr, "Compilation succeeded.\n");
+ return 0;
+}
+
+void VG_(assert_fail)(Bool isCore, const Char* expr, const Char* file,
+ Int line, const Char* fn, const HChar* format, ... )
+{
+ abort();
+}
|
|
From: <sv...@va...> - 2009-12-29 13:49:23
|
Author: sewardj
Date: 2009-12-29 13:49:10 +0000 (Tue, 29 Dec 2009)
New Revision: 1944
Log:
Big mechanical cleanup to insn decoding: use a macro to fish bits out
of 'insn' instead of a whole bunch of variables.
Modified:
branches/ARM/priv/guest_arm_toIR.c
Modified: branches/ARM/priv/guest_arm_toIR.c
===================================================================
--- branches/ARM/priv/guest_arm_toIR.c 2009-12-29 11:11:55 UTC (rev 1943)
+++ branches/ARM/priv/guest_arm_toIR.c 2009-12-29 13:49:10 UTC (rev 1944)
@@ -149,18 +149,6 @@
/*--- arm insn stream. ---*/
/*------------------------------------------------------------*/
-/* Do a big-endian load of a 32-bit word, regardless of the endianness
- of the underlying host. */
-static UInt getUIntBigEndianly ( UChar* p )
-{
- UInt w = 0;
- w = (w << 8) | p[0];
- w = (w << 8) | p[1];
- w = (w << 8) | p[2];
- w = (w << 8) | p[3];
- return w;
-}
-
/* Do a little-endian load of a 32-bit word, regardless of the
endianness of the underlying host. */
static UInt getUIntLittleEndianly ( UChar* p )
@@ -1545,15 +1533,18 @@
VexAbiInfo* abiinfo
)
{
+ // A macro to fish bits out of 'insn'.
+# define INSN(_bMax,_bMin) \
+ ((insn >> (_bMin)) & ((1 << ((_bMax) - (_bMin) + 1)) - 1))
+# define INSN_COND \
+ INSN(31,28)
+
DisResult dres;
UInt insn;
//Bool allow_VFP = False;
//UInt hwcaps = archinfo->hwcaps;
IRTemp condT; /* :: Ity_I32 */
- UInt insn_cond, insn_27_20, insn_24_21, insn_11_0, insn_3_0;
- UInt insn_25, insn_7, insn_4, insn_27_24, insn_21, summary;
- UInt insn_11_4, insn_19_12, insn_19_16, insn_15_12;
- UInt insn_11_8, insn_7_4, insn_22_21, insn_22_20;
+ UInt summary;
HChar dis_buf[128]; // big enough to hold LDMIA etc text
/* What insn variants are we supporting today? */
@@ -1586,25 +1577,6 @@
llPutIReg( 15, mkU32(guest_R15_curr_instr) );
}
- insn_cond = (insn >> 28) & 0xF;
- insn_27_20 = (insn >> 20) & 0xFF;
- insn_24_21 = (insn >> 21) & 0xF;
- insn_11_0 = (insn >> 0) & 0xFFF;
- insn_3_0 = (insn >> 0) & 0xF;
- insn_25 = (insn >> 25) & 1;
- insn_7 = (insn >> 7) & 1;
- insn_4 = (insn >> 4) & 1;
- insn_27_24 = (insn >> 24) & 0xF;
- insn_22_21 = (insn >> 21) & 3;
- insn_22_20 = (insn >> 20) & 7;
- insn_21 = (insn >> 21) & 1;
- insn_11_4 = (insn >> 4) & 0xFF;
- insn_19_12 = (insn >> 12) & 0xFF;
- insn_19_16 = (insn >> 16) & 0xF;
- insn_15_12 = (insn >> 12) & 0xF;
- insn_11_8 = (insn >> 8) & 0xF;
- insn_7_4 = (insn >> 4) & 0xF;
-
/* ----------------------------------------------------------- */
/* Spot "Special" instructions (see comment at top of file). */
@@ -1675,7 +1647,7 @@
whether they must generate a side exit before the instruction.
condT :: Ity_I32 and is always either zero or one. */
condT = IRTemp_INVALID;
- switch ( (ARMCondcode)insn_cond ) {
+ switch ( (ARMCondcode)INSN_COND ) {
case ARMCondNV: // Illegal instruction prior to v5 (see ARM ARM A3-5)
goto decode_failure;
case ARMCondAL: // Always executed
@@ -1685,7 +1657,7 @@
case ARMCondHI: case ARMCondLS: case ARMCondGE: case ARMCondLT:
case ARMCondGT: case ARMCondLE:
condT = newTemp(Ity_I32);
- assign( condT, mk_armg_calculate_condition( insn_cond ));
+ assign( condT, mk_armg_calculate_condition( INSN_COND ));
break;
}
@@ -1695,8 +1667,8 @@
/* ---------------- Data processing ops ------------------- */
- if (0 == (insn_27_20 & BITS8(1,1,0,0,0,0,0,0))
- && !(insn_25 == 0 && insn_7 == 1 && insn_4 == 1)) {
+ if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0))
+ && !(INSN(25,25) == 0 && INSN(7,7) == 1 && INSN(4,4) == 1)) {
IRTemp shop = IRTemp_INVALID; /* shifter operand */
IRTemp shco = IRTemp_INVALID; /* shifter carry out */
UInt rD = (insn >> 12) & 0xF; /* 15:12 */
@@ -1710,7 +1682,7 @@
IROp op = Iop_INVALID;
Bool ok;
- switch (insn_24_21) {
+ switch (INSN(24,21)) {
/* --------- ADD, SUB, AND, OR --------- */
case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */
@@ -1730,7 +1702,7 @@
rd_eq_rn_op_SO: {
Bool isRSB = False;
Bool isBIC = False;
- switch (insn_24_21) {
+ switch (INSN(24,21)) {
case BITS4(0,0,1,1):
vassert(op == Iop_Sub32); isRSB = True; break;
case BITS4(1,1,1,0):
@@ -1741,7 +1713,7 @@
rNt = newTemp(Ity_I32);
assign(rNt, getIReg(rN));
ok = mk_shifter_operand(
- insn_25, insn_11_0,
+ INSN(25,25), INSN(11,0),
&shop, bitS ? &shco : NULL, dis_buf
);
if (!ok)
@@ -1800,18 +1772,18 @@
}
}
DIP("%s%s%s r%u, r%u, %s\n",
- name, nCC(insn_cond), bitS ? "s" : "", rD, rN, dis_buf );
+ name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
goto decode_success;
}
/* --------- MOV, MVN --------- */
case BITS4(1,1,0,1): /* MOV: Rd = shifter_operand */
case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
- Bool isMVN = insn_24_21 == BITS4(1,1,1,1);
+ Bool isMVN = INSN(24,21) == BITS4(1,1,1,1);
if (rN != 0)
break; /* rN must be zero */
ok = mk_shifter_operand(
- insn_25, insn_11_0,
+ INSN(25,25), INSN(11,0),
&shop, bitS ? &shco : NULL, dis_buf
);
if (!ok)
@@ -1835,14 +1807,14 @@
}
DIP("%s%s%s r%u, %s\n",
isMVN ? "mvn" : "mov",
- nCC(insn_cond), bitS ? "s" : "", rD, dis_buf );
+ nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
goto decode_success;
}
/* --------- CMP --------- */
case BITS4(1,0,1,0): /* CMP: (void) Rn - shifter_operand */
case BITS4(1,0,1,1): { /* CMN: (void) Rn + shifter_operand */
- Bool isCMN = insn_24_21 == BITS4(1,0,1,1);
+ Bool isCMN = INSN(24,21) == BITS4(1,0,1,1);
if (rD != 0)
break; /* rD must be zero */
if (bitS == 0)
@@ -1850,7 +1822,7 @@
rNt = newTemp(Ity_I32);
assign(rNt, getIReg(rN));
ok = mk_shifter_operand(
- insn_25, insn_11_0,
+ INSN(25,25), INSN(11,0),
&shop, NULL, dis_buf
);
if (!ok)
@@ -1860,14 +1832,14 @@
rNt, shop, condT );
DIP("%s%s r%u, %s\n",
isCMN ? "cmn" : "cmp",
- nCC(insn_cond), rN, dis_buf );
+ nCC(INSN_COND), rN, dis_buf );
goto decode_success;
}
/* --------- TST --------- */
case BITS4(1,0,0,0): /* TST: (void) Rn & shifter_operand */
case BITS4(1,0,0,1): { /* TEQ: (void) Rn ^ shifter_operand */
- Bool isTEQ = insn_24_21 == BITS4(1,0,0,1);
+ Bool isTEQ = INSN(24,21) == BITS4(1,0,0,1);
if (rD != 0)
break; /* rD must be zero */
if (bitS == 0)
@@ -1875,7 +1847,7 @@
rNt = newTemp(Ity_I32);
assign(rNt, getIReg(rN));
ok = mk_shifter_operand(
- insn_25, insn_11_0,
+ INSN(25,25), INSN(11,0),
&shop, &shco, dis_buf
);
if (!ok)
@@ -1890,7 +1862,7 @@
res, shco, oldV, condT );
DIP("%s%s r%u, %s\n",
isTEQ ? "teq" : "tst",
- nCC(insn_cond), rN, dis_buf );
+ nCC(INSN_COND), rN, dis_buf );
goto decode_success;
}
@@ -1905,7 +1877,7 @@
rNt = newTemp(Ity_I32);
assign(rNt, getIReg(rN));
ok = mk_shifter_operand(
- insn_25, insn_11_0,
+ INSN(25,25), INSN(11,0),
&shop, bitS ? &shco : NULL, dis_buf
);
if (!ok)
@@ -1914,7 +1886,7 @@
assign( oldC, mk_armg_calculate_flag_c() );
res = newTemp(Ity_I32);
// compute the main result
- switch (insn_24_21) {
+ switch (INSN(24,21)) {
case BITS4(0,1,0,1): /* ADC */
assign(res,
binop(Iop_Add32,
@@ -1947,7 +1919,7 @@
/* Update the flags thunk if necessary */
if (bitS) {
vassert(shco != IRTemp_INVALID);
- switch (insn_24_21) {
+ switch (INSN(24,21)) {
case BITS4(0,1,0,1): /* ADC */
setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
rNt, shop, oldC, condT );
@@ -1965,7 +1937,7 @@
}
}
DIP("%s%s%s r%u, r%u, %s\n",
- name, nCC(insn_cond), bitS ? "s" : "", rD, rN, dis_buf );
+ name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
goto decode_success;
}
@@ -1973,7 +1945,7 @@
default:
break;
}
- } /* if (0 == (insn_27_20 & BITS8(1,1,0,0,0,0,0,0)) */
+ } /* if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) */
/* --------------------- Load/store (ubyte & word) -------- */
// LDR STR LDRB STRB
@@ -1995,27 +1967,30 @@
32 Rn +/- Rm sh2 imm5
*/
/* Quickly skip over all of this for hopefully most instructions */
- if ((insn_27_24 & BITS4(1,1,0,0)) != BITS4(0,1,0,0))
+ if ((INSN(27,24) & BITS4(1,1,0,0)) != BITS4(0,1,0,0))
goto after_load_store_ubyte_or_word;
summary = 0;
- /**/ if (insn_27_24 == BITS4(0,1,0,1) && insn_21 == 0) {
+ /**/ if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 0) {
summary = 1 | 16;
}
- else if (insn_27_24 == BITS4(0,1,1,1) && insn_21 == 0 && insn_4 == 0) {
+ else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 0
+ && INSN(4,4) == 0) {
summary = 1 | 32;
}
- else if (insn_27_24 == BITS4(0,1,0,1) && insn_21 == 1) {
+ else if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 1) {
summary = 2 | 16;
}
- else if (insn_27_24 == BITS4(0,1,1,1) && insn_21 == 1 && insn_4 == 0) {
+ else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 1
+ && INSN(4,4) == 0) {
summary = 2 | 32;
}
- else if (insn_27_24 == BITS4(0,1,0,0) && insn_21 == 0) {
+ else if (INSN(27,24) == BITS4(0,1,0,0) && INSN(21,21) == 0) {
summary = 3 | 16;
}
- else if (insn_27_24 == BITS4(0,1,1,0) && insn_21 == 0 && insn_4 == 0) {
+ else if (INSN(27,24) == BITS4(0,1,1,0) && INSN(21,21) == 0
+ && INSN(4,4) == 0) {
summary = 3 | 32;
}
else goto after_load_store_ubyte_or_word;
@@ -2147,15 +2122,15 @@
switch (summary & 0x0F) {
case 1: DIP("%sr%s%s r%u, %s\n",
bL == 0 ? "st" : "ld",
- bB == 0 ? "" : "b", nCC(insn_cond), rD, dis_buf);
+ bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
break;
case 2: DIP("%sr%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
bL == 0 ? "st" : "ld",
- bB == 0 ? "" : "b", nCC(insn_cond), rD, dis_buf);
+ bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
break;
case 3: DIP("%sr%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
bL == 0 ? "st" : "ld",
- bB == 0 ? "" : "b", nCC(insn_cond), rD, dis_buf);
+ bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
break;
default: vassert(0);
}
@@ -2203,31 +2178,31 @@
32 Rn +/- Rm
*/
/* Quickly skip over all of this for hopefully most instructions */
- if ((insn_27_24 & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
+ if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
goto after_load_store_sbyte_or_hword;
/* Check the "1SH1" thing. */
- if ((insn_7_4 & BITS4(1,0,0,1)) != BITS4(1,0,0,1))
+ if ((INSN(7,4) & BITS4(1,0,0,1)) != BITS4(1,0,0,1))
goto after_load_store_sbyte_or_hword;
summary = 0;
- /**/ if (insn_27_24 == BITS4(0,0,0,1) && insn_22_21 == BITS2(1,0)) {
+ /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,0)) {
summary = 1 | 16;
}
- else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_21 == BITS2(0,0)) {
+ else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,0)) {
summary = 1 | 32;
}
- else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_21 == BITS2(1,1)) {
+ else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,1)) {
summary = 2 | 16;
}
- else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_21 == BITS2(0,1)) {
+ else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,1)) {
summary = 2 | 32;
}
- else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_21 == BITS2(1,0)) {
+ else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(1,0)) {
summary = 3 | 16;
}
- else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_21 == BITS2(0,0)) {
+ else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(0,0)) {
summary = 3 | 32;
}
else goto after_load_store_sbyte_or_hword;
@@ -2352,13 +2327,13 @@
}
switch (summary & 0x0F) {
- case 1: DIP("%s%s r%u, %s\n", name, nCC(insn_cond), rD, dis_buf);
+ case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
break;
case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
- name, nCC(insn_cond), rD, dis_buf);
+ name, nCC(INSN_COND), rD, dis_buf);
break;
case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
- name, nCC(insn_cond), rD, dis_buf);
+ name, nCC(INSN_COND), rD, dis_buf);
break;
default: vassert(0);
}
@@ -2387,7 +2362,7 @@
// LD/STMIA LD/STMIB LD/STMDA LD/STMDB
// Remarkably complex and difficult to get right
// match 27:20 as 100XX0WL
- if (BITS8(1,0,0,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,0,0,1,0,0))) {
+ if (BITS8(1,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))) {
// A5-50 LD/STMIA cond 1000 10WL Rn RegList
// A5-51 LD/STMIB cond 1001 10WL Rn RegList
// A5-53 LD/STMDA cond 1000 00WL Rn RegList
@@ -2572,7 +2547,7 @@
//}
DIP("%sm%c%c%s r%u%s, {0x%04x}\n",
bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a',
- nCC(insn_cond),
+ nCC(INSN_COND),
rN, bW ? "!" : "", regList);
goto decode_success;
@@ -2583,7 +2558,7 @@
/* --------------------- Control flow --------------------- */
// B, BL (Branch, or Branch-and-Link, to immediate offset)
//
- if (BITS8(1,0,1,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,0,0,0,0,0))) {
+ if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) {
UInt link = (insn >> 24) & 1;
UInt uimm24 = insn & ((1<<24)-1);
Int simm24 = (Int)uimm24;
@@ -2613,20 +2588,20 @@
irsb->next = mkU32(guest_R15_curr_instr + 4);
irsb->jumpkind = jk;
dres.whatNext = Dis_StopHere;
- DIP("b%s%s 0x%x\n", link ? "l" : "", nCC(insn_cond), dst);
+ DIP("b%s%s 0x%x\n", link ? "l" : "", nCC(INSN_COND), dst);
}
goto decode_success;
}
// BX, BLX (Branch, or Branch-and-Link, to a register)
//
- if (insn_27_20 == BITS8(0,0,0,1,0,0,1,0)
- && insn_19_12 == BITS8(1,1,1,1,1,1,1,1)
- && (insn_11_4 == BITS8(1,1,1,1,0,0,1,1)
- || insn_11_4 == BITS8(1,1,1,1,0,0,0,1))) {
+ if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0)
+ && INSN(19,12) == BITS8(1,1,1,1,1,1,1,1)
+ && (INSN(11,4) == BITS8(1,1,1,1,0,0,1,1)
+ || INSN(11,4) == BITS8(1,1,1,1,0,0,0,1))) {
IRExpr* dst;
- UInt link = (insn_11_4 >> 1) & 1;
- UInt rM = insn_3_0;
+ UInt link = (INSN(11,4) >> 1) & 1;
+ UInt rM = INSN(3,0);
// we don't decode the case (link && rM == 15), as that's
// Unpredictable.
if (!(link && rM == 15)) {
@@ -2647,7 +2622,7 @@
if (condT == IRTemp_INVALID) {
DIP("b%sx r%u\n", link ? "l" : "", rM);
} else {
- DIP("b%sx%s r%u\n", link ? "l" : "", nCC(insn_cond), rM);
+ DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
}
goto decode_success;
}
@@ -2656,11 +2631,11 @@
/* --------------------- Clz --------------------- */
// CLZ
- if (insn_27_20 == BITS8(0,0,0,1,0,1,1,0)
- && insn_19_16 == BITS4(1,1,1,1)
- && insn_11_4 == BITS8(1,1,1,1,0,0,0,1)) {
- UInt rD = insn_15_12;
- UInt rM = insn_3_0;
+ if (INSN(27,20) == BITS8(0,0,0,1,0,1,1,0)
+ && INSN(19,16) == BITS4(1,1,1,1)
+ && INSN(11,4) == BITS8(1,1,1,1,0,0,0,1)) {
+ UInt rD = INSN(15,12);
+ UInt rM = INSN(3,0);
IRTemp arg = newTemp(Ity_I32);
IRTemp res = newTemp(Ity_I32);
assign(arg, getIReg(rM));
@@ -2671,19 +2646,19 @@
mkU32(32)
));
putIReg(rD, mkexpr(res), condT, Ijk_Boring);
- DIP("clz%s r%u, r%u\n", nCC(insn_cond), rD, rM);
+ DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
goto decode_success;
}
/* --------------------- Mul etc --------------------- */
// MUL
- if (BITS8(0,0,0,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,1,1,1,0))
- && insn_15_12 == BITS4(0,0,0,0)
- && insn_7_4 == BITS4(1,0,0,1)) {
+ if (BITS8(0,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
+ && INSN(15,12) == BITS4(0,0,0,0)
+ && INSN(7,4) == BITS4(1,0,0,1)) {
UInt bitS = (insn >> 20) & 1; /* 20:20 */
- UInt rD = insn_19_16;
- UInt rS = insn_11_8;
- UInt rM = insn_3_0;
+ UInt rD = INSN(19,16);
+ UInt rS = INSN(11,8);
+ UInt rM = INSN(3,0);
if (rD == 15 || rM == 15 || rS == 15) {
/* Unpredictable; don't decode; fall through */
} else {
@@ -2711,21 +2686,21 @@
setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
}
DIP("mul%c%s r%u, r%u, r%u\n",
- bitS ? 's' : ' ', nCC(insn_cond), rD, rM, rS);
+ bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
goto decode_success;
}
/* fall through */
}
// MLA, MLS
- if (BITS8(0,0,0,0,0,0,1,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,0))
- && insn_7_4 == BITS4(1,0,0,1)) {
+ if (BITS8(0,0,0,0,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+ && INSN(7,4) == BITS4(1,0,0,1)) {
UInt bitS = (insn >> 20) & 1; /* 20:20 */
UInt isMLS = (insn >> 22) & 1; /* 22:22 */
- UInt rD = insn_19_16;
- UInt rN = insn_15_12;
- UInt rS = insn_11_8;
- UInt rM = insn_3_0;
+ UInt rD = INSN(19,16);
+ UInt rN = INSN(15,12);
+ UInt rS = INSN(11,8);
+ UInt rM = INSN(3,0);
if (bitS == 1 && isMLS == 1) {
/* This isn't allowed (MLS that sets flags). don't decode;
fall through */
@@ -2763,21 +2738,21 @@
setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
}
DIP("ml%c%c%s r%u, r%u, r%u, r%u\n",
- isMLS ? 's' : 'a', bitS ? 's' : ' ', nCC(insn_cond), rD, rM, rS, rN);
+ isMLS ? 's' : 'a', bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS, rN);
goto decode_success;
}
/* fall through */
}
// SMULL, UMULL
- if (BITS8(0,0,0,0,1,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,0))
- && insn_7_4 == BITS4(1,0,0,1)) {
+ if (BITS8(0,0,0,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+ && INSN(7,4) == BITS4(1,0,0,1)) {
UInt bitS = (insn >> 20) & 1; /* 20:20 */
- UInt rDhi = insn_19_16;
- UInt rDlo = insn_15_12;
- UInt rS = insn_11_8;
- UInt rM = insn_3_0;
- UInt isS = (insn_27_20 >> 2) & 1; /* 22:22 */
+ UInt rDhi = INSN(19,16);
+ UInt rDlo = INSN(15,12);
+ UInt rS = INSN(11,8);
+ UInt rM = INSN(3,0);
+ UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */
if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
/* Unpredictable; don't decode; fall through */
} else {
@@ -2812,21 +2787,21 @@
}
DIP("%cmull%c%s r%u, r%u, r%u, r%u\n",
isS ? 's' : 'u', bitS ? 's' : ' ',
- nCC(insn_cond), rDlo, rDhi, rM, rS);
+ nCC(INSN_COND), rDlo, rDhi, rM, rS);
goto decode_success;
}
/* fall through */
}
// SMLAL, UMLAL
- if (BITS8(0,0,0,0,1,0,1,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,0))
- && insn_7_4 == BITS4(1,0,0,1)) {
+ if (BITS8(0,0,0,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+ && INSN(7,4) == BITS4(1,0,0,1)) {
UInt bitS = (insn >> 20) & 1; /* 20:20 */
- UInt rDhi = insn_19_16;
- UInt rDlo = insn_15_12;
- UInt rS = insn_11_8;
- UInt rM = insn_3_0;
- UInt isS = (insn_27_20 >> 2) & 1; /* 22:22 */
+ UInt rDhi = INSN(19,16);
+ UInt rDlo = INSN(15,12);
+ UInt rS = INSN(11,8);
+ UInt rM = INSN(3,0);
+ UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */
if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
/* Unpredictable; don't decode; fall through */
} else {
@@ -2864,7 +2839,7 @@
setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT );
}
DIP("%cmlal%c%s r%u, r%u, r%u, r%u\n",
- isS ? 's' : 'u', bitS ? 's' : ' ', nCC(insn_cond),
+ isS ? 's' : 'u', bitS ? 's' : ' ', nCC(INSN_COND),
rDlo, rDhi, rM, rS);
goto decode_success;
}
@@ -2874,12 +2849,12 @@
/* --------------------- Msr etc --------------------- */
// MSR (immediate form, flags only)
- if (BITS8(0,0,1,1,0,0,1,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && insn_15_12 == BITS4(1,1,1,1)) {
+ if (BITS8(0,0,1,1,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && INSN(15,12) == BITS4(1,1,1,1)) {
UInt bitR = (insn >> 22) & 1;
- if (bitR == 0 && insn_19_16 == BITS4(1,0,0,0)) {
- UInt imm = (insn_11_0 >> 0) & 0xFF;
- UInt rot = 2 * ((insn_11_0 >> 8) & 0xF);
+ if (bitR == 0 && INSN(19,16) == BITS4(1,0,0,0)) {
+ UInt imm = (INSN(11,0) >> 0) & 0xFF;
+ UInt rot = 2 * ((INSN(11,0) >> 8) & 0xF);
IRTemp immT = newTemp(Ity_I32);
vassert(rot <= 30);
imm = ROR32(imm, rot);
@@ -2888,30 +2863,30 @@
| ARMG_CC_MASK_V | ARMG_CC_MASK_C);
assign( immT, mkU32(imm & 0xF0000000) );
setFlags_D1(ARMG_CC_OP_COPY, immT, condT);
- DIP("msr%s cpsr_f, #0x%08x\n", nCC(insn_cond), imm);
+ DIP("msr%s cpsr_f, #0x%08x\n", nCC(INSN_COND), imm);
goto decode_success;
}
/* fall through */
}
// MRS
- if (BITS8(0,0,0,1,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && insn_19_16 == BITS4(1,1,1,1)
- && insn_11_0 == 0) {
+ if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && INSN(19,16) == BITS4(1,1,1,1)
+ && INSN(11,0) == 0) {
UInt bitR = (insn >> 22) & 1;
- UInt rD = insn_15_12;
+ UInt rD = INSN(15,12);
if (bitR == 0 && rD != 15) {
IRTemp res = newTemp(Ity_I32);
assign( res, mk_armg_calculate_flags_nzcv() );
putIReg( rD, mkexpr(res), condT, Ijk_Boring );
- DIP("mrs%s r%u, cpsr\n", nCC(insn_cond), rD);
+ DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
goto decode_success;
}
/* fall through */
}
/* --------------------- Svc --------------------- */
- if (BITS8(1,1,1,1,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,0,0,0,0))) {
+ if (BITS8(1,1,1,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))) {
UInt imm24 = (insn >> 0) & 0xFFFFFF;
if (imm24 == 0) {
/* A syscall. We can't do this conditionally, hence: */
@@ -2922,7 +2897,7 @@
irsb->next = mkU32( guest_R15_curr_instr + 4 );
irsb->jumpkind = Ijk_Sys_syscall;
dres.whatNext = Dis_StopHere;
- DIP("svc%s #0x%08x\n", nCC(insn_cond), imm24);
+ DIP("svc%s #0x%08x\n", nCC(INSN_COND), imm24);
goto decode_success;
}
/* fall through */
@@ -2931,12 +2906,12 @@
/* ------------------------ swp ------------------------ */
// SWP, SWPB
- if (BITS8(0,0,0,1,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(0,0,0,0) == insn_11_8
- && BITS4(1,0,0,1) == insn_7_4) {
- UInt rN = insn_19_16;
- UInt rD = insn_15_12;
- UInt rM = insn_3_0;
+ if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(0,0,0,0) == INSN(11,8)
+ && BITS4(1,0,0,1) == INSN(7,4)) {
+ UInt rN = INSN(19,16);
+ UInt rD = INSN(15,12);
+ UInt rM = INSN(3,0);
IRTemp tRn = newTemp(Ity_I32);
IRTemp tNew = newTemp(Ity_I32);
IRTemp tOld = IRTemp_INVALID;
@@ -2975,7 +2950,7 @@
putIReg(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
IRTemp_INVALID, Ijk_Boring);
DIP("swp%s%s r%u, r%u, [r%u]\n",
- isB ? "b" : "", nCC(insn_cond), rD, rM, rN);
+ isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
goto decode_success;
}
/* fall through */
@@ -3006,15 +2981,15 @@
2 ia-Rn (access at Rn, then Rn += 4+8n)
3 db-Rn (Rn -= 4+8n, then access at Rn)
*/
- if (BITS8(1,1,0,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,0,0,1,0,0))
- && insn_11_8 == BITS4(1,0,1,1)) {
+ if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))
+ && INSN(11,8) == BITS4(1,0,1,1)) {
UInt bP = (insn >> 24) & 1;
UInt bU = (insn >> 23) & 1;
UInt bW = (insn >> 21) & 1;
UInt bL = (insn >> 20) & 1;
UInt offset = (insn >> 0) & 0xFF;
- UInt rN = insn_19_16;
- UInt dD = insn_15_12;
+ UInt rN = INSN(19,16);
+ UInt dD = INSN(15,12);
UInt nRegs = (offset - 1) / 2;
Int i;
@@ -3093,13 +3068,13 @@
HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%smx%s r%u, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
case 2: DIP("f%smiax%s r%u!, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
case 3: DIP("f%smdbx%s r%u!, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
default: vassert(0);
}
@@ -3132,15 +3107,15 @@
2 ia-Rn (access at Rn, then Rn += 8n)
3 db-Rn (Rn -= 8n, then access at Rn)
*/
- if (BITS8(1,1,0,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,0,0,1,0,0))
- && insn_11_8 == BITS4(1,0,1,1)) {
+ if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))
+ && INSN(11,8) == BITS4(1,0,1,1)) {
UInt bP = (insn >> 24) & 1;
UInt bU = (insn >> 23) & 1;
UInt bW = (insn >> 21) & 1;
UInt bL = (insn >> 20) & 1;
UInt offset = (insn >> 0) & 0xFF;
- UInt rN = insn_19_16;
- UInt dD = insn_15_12;
+ UInt rN = INSN(19,16);
+ UInt dD = INSN(15,12);
UInt nRegs = offset / 2;
Int i;
@@ -3219,13 +3194,13 @@
HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%smd%s r%u, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
case 2: DIP("f%smiad%s r%u!, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
case 3: DIP("f%smdbd%s r%u!, {d%u-d%u}\n",
- nm, nCC(insn_cond), rN, dD, dD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
break;
default: vassert(0);
}
@@ -3237,11 +3212,11 @@
after_vfp_fldmd_fstmd:
/* ------------------- fmrx, fmxr ------------------- */
- if (BITS8(1,1,1,0,1,1,1,1) == insn_27_20
- && BITS4(1,0,1,0) == insn_11_8
+ if (BITS8(1,1,1,0,1,1,1,1) == INSN(27,20)
+ && BITS4(1,0,1,0) == INSN(11,8)
&& BITS8(0,0,0,1,0,0,0,0) == (insn & 0xFF)) {
- UInt rD = insn_15_12;
- UInt reg = insn_19_16;
+ UInt rD = INSN(15,12);
+ UInt reg = INSN(19,16);
if (reg == BITS4(0,0,0,1)) {
if (rD == 15) {
IRTemp nzcvT = newTemp(Ity_I32);
@@ -3252,26 +3227,26 @@
IRExpr_Get(OFFB_FPSCR, Ity_I32),
mkU32(0xF0000000)));
setFlags_D1(ARMG_CC_OP_COPY, nzcvT, condT);
- DIP("fmstat%s\n", nCC(insn_cond));
+ DIP("fmstat%s\n", nCC(INSN_COND));
} else {
/* Otherwise, merely transfer FPSCR to r0 .. r14. */
putIReg(rD, IRExpr_Get(OFFB_FPSCR, Ity_I32),
condT, Ijk_Boring);
- DIP("fmrx%s r%u, fpscr\n", nCC(insn_cond), rD);
+ DIP("fmrx%s r%u, fpscr\n", nCC(INSN_COND), rD);
}
goto decode_success;
}
/* fall through */
}
- if (BITS8(1,1,1,0,1,1,1,0) == insn_27_20
- && BITS4(1,0,1,0) == insn_11_8
+ if (BITS8(1,1,1,0,1,1,1,0) == INSN(27,20)
+ && BITS4(1,0,1,0) == INSN(11,8)
&& BITS8(0,0,0,1,0,0,0,0) == (insn & 0xFF)) {
- UInt rD = insn_15_12;
- UInt reg = insn_19_16;
+ UInt rD = INSN(15,12);
+ UInt reg = INSN(19,16);
if (reg == BITS4(0,0,0,1)) {
putMiscReg32(OFFB_FPSCR, getIReg(rD), condT);
- DIP("fmxr%s fpscr, r%u\n", nCC(insn_cond), rD);
+ DIP("fmxr%s fpscr, r%u\n", nCC(INSN_COND), rD);
goto decode_success;
}
/* fall through */
@@ -3280,9 +3255,9 @@
/* --------------------- vmov --------------------- */
// VMOV dM, rD, rN
if (0x0C400B10 == (insn & 0x0FF00FF0)) {
- UInt dM = insn_3_0;
- UInt rD = insn_15_12; /* lo32 */
- UInt rN = insn_19_16; /* hi32 */
+ UInt dM = INSN(3,0);
+ UInt rD = INSN(15,12); /* lo32 */
+ UInt rN = INSN(19,16); /* hi32 */
if (rD == 15 || rN == 15) {
/* fall through */
} else {
@@ -3290,7 +3265,7 @@
unop(Iop_ReinterpI64asF64,
binop(Iop_32HLto64, getIReg(rN), getIReg(rD))),
condT);
- DIP("vmov%s d%u, r%u, r%u\n", nCC(insn_cond), dM, rD, rN);
+ DIP("vmov%s d%u, r%u, r%u\n", nCC(INSN_COND), dM, rD, rN);
goto decode_success;
}
/* fall through */
@@ -3298,9 +3273,9 @@
// VMOV rD, rN, dM
if (0x0C500B10 == (insn & 0x0FF00FF0)) {
- UInt dM = insn_3_0;
- UInt rD = insn_15_12; /* lo32 */
- UInt rN = insn_19_16; /* hi32 */
+ UInt dM = INSN(3,0);
+ UInt rD = INSN(15,12); /* lo32 */
+ UInt rN = INSN(19,16); /* hi32 */
if (rD == 15 || rN == 15 || rD == rN) {
/* fall through */
} else {
@@ -3308,7 +3283,7 @@
assign(i64, unop(Iop_ReinterpF64asI64, getDReg(dM)));
putIReg(rN, unop(Iop_64HIto32, mkexpr(i64)), condT, Ijk_Boring);
putIReg(rD, unop(Iop_64to32, mkexpr(i64)), condT, Ijk_Boring);
- DIP("vmov%s r%u, r%u, d%u\n", nCC(insn_cond), rD, rN, dM);
+ DIP("vmov%s r%u, r%u, d%u\n", nCC(INSN_COND), rD, rN, dM);
goto decode_success;
}
/* fall through */
@@ -3316,10 +3291,10 @@
/* --------------------- f{ld,st}d --------------------- */
// FLDD, FSTD
- if (BITS8(1,1,0,1,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,0,1,1,0))
- && BITS4(1,0,1,1) == insn_11_8) {
- UInt dD = insn_15_12;
- UInt rN = insn_19_16;
+ if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,0))
+ && BITS4(1,0,1,1) == INSN(11,8)) {
+ UInt dD = INSN(15,12);
+ UInt rN = INSN(19,16);
UInt offset = (insn & 0xFF) << 2;
UInt bU = (insn >> 23) & 1; /* 1: +offset 0: -offset */
UInt bL = (insn >> 20) & 1; /* 1: load 0: store */
@@ -3337,18 +3312,18 @@
storeLE(mkexpr(ea), getDReg(dD));
}
DIP("f%sd%s d%u, [r%u, %c#%u]\n",
- bL ? "ld" : "st", nCC(insn_cond), dD, rN,
+ bL ? "ld" : "st", nCC(INSN_COND), dD, rN,
bU ? '+' : '-', offset);
goto decode_success;
}
/* --------------------- dp insns (D) --------------------- */
- if (BITS8(1,1,1,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,0,1,0,0))
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(0,0,0,0) == (insn_7_4 & BITS4(1,0,1,1))) {
- UInt dM = insn_3_0; /* argR */
- UInt dD = insn_15_12; /* dst/acc */
- UInt dN = insn_19_16; /* argL */
+ if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,0,0))
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(1,0,1,1))) {
+ UInt dM = INSN(3,0); /* argR */
+ UInt dD = INSN(15,12); /* dst/acc */
+ UInt dN = INSN(19,16); /* argL */
UInt bP = (insn >> 23) & 1;
UInt bQ = (insn >> 21) & 1;
UInt bR = (insn >> 20) & 1;
@@ -3362,7 +3337,7 @@
triop(Iop_MulF64, rm, getDReg(dN),
getDReg(dM))),
condT);
- DIP("fmacd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fmacd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,0,0,1): /* NMAC: d - n * m */
putDReg(dD, triop(Iop_SubF64, rm,
@@ -3370,7 +3345,7 @@
triop(Iop_MulF64, rm, getDReg(dN),
getDReg(dM))),
condT);
- DIP("fnmacd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fnmacd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,0,1,0): /* MSC: - d + n * m */
putDReg(dD, triop(Iop_AddF64, rm,
@@ -3378,7 +3353,7 @@
triop(Iop_MulF64, rm, getDReg(dN),
getDReg(dM))),
condT);
- DIP("fmscd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fmscd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,0,1,1): /* NMSC: - d - n * m */
putDReg(dD, triop(Iop_SubF64, rm,
@@ -3386,34 +3361,34 @@
triop(Iop_MulF64, rm, getDReg(dN),
getDReg(dM))),
condT);
- DIP("fnmscd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fnmscd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,1,0,0): /* MUL: n * m */
putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
condT);
- DIP("fmuld%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fmuld%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,1,0,1): /* NMUL: - n * m */
putDReg(dD, unop(Iop_NegF64,
triop(Iop_MulF64, rm, getDReg(dN),
getDReg(dM))),
condT);
- DIP("fnmuld%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fnmuld%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,1,1,0): /* ADD: n + m */
putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
condT);
- DIP("faddd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("faddd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(0,1,1,1): /* SUB: n - m */
putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
condT);
- DIP("fsubd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fsubd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
case BITS4(1,0,0,0): /* DIV: n / m */
putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
condT);
- DIP("fdivd%s d%u, d%u, d%u\n", nCC(insn_cond), dD, dN, dM);
+ DIP("fdivd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
goto decode_success;
default:
break;
@@ -3436,15 +3411,15 @@
N=0 generates Invalid Operation exn if either arg is a signalling NaN
(Not that we pay any attention to N here)
*/
- if (BITS8(1,1,1,0,1,0,1,1) == insn_27_20
- && BITS4(0,1,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,1,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+ && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
UInt bZ = (insn >> 16) & 1;
UInt bN = (insn >> 7) & 1;
- UInt dD = insn_15_12;
- UInt dM = insn_3_0;
- if (bZ && insn_3_0 != 0) {
+ UInt dD = INSN(15,12);
+ UInt dM = INSN(3,0);
+ if (bZ && INSN(3,0) != 0) {
/* does not decode; fall through */
} else {
IRTemp argL = newTemp(Ity_F64);
@@ -3483,9 +3458,9 @@
putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
if (bZ) {
- DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(insn_cond), dD);
+ DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(INSN_COND), dD);
} else {
- DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(insn_cond), dD, dM);
+ DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(INSN_COND), dD, dM);
}
goto decode_success;
}
@@ -3493,37 +3468,37 @@
}
/* --------------------- unary (D) --------------------- */
- if (BITS8(1,1,1,0,1,0,1,1) == insn_27_20
- && BITS4(0,0,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,1,1))) {
- UInt dD = insn_15_12;
- UInt dM = insn_3_0;
+ if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+ && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
+ UInt dD = INSN(15,12);
+ UInt dM = INSN(3,0);
UInt b16 = (insn >> 16) & 1;
UInt b7 = (insn >> 7) & 1;
/**/ if (b16 == 0 && b7 == 0) {
// FCPYD
putDReg(dD, getDReg(dM), condT);
- DIP("fcpyd%s d%u, d%u\n", nCC(insn_cond), dD, dM);
+ DIP("fcpyd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
goto decode_success;
}
else if (b16 == 0 && b7 == 1) {
// FABSD
putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT);
- DIP("fabsd%s d%u, d%u\n", nCC(insn_cond), dD, dM);
+ DIP("fabsd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
goto decode_success;
}
else if (b16 == 1 && b7 == 0) {
// FNEGD
putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT);
- DIP("fnegd%s d%u, d%u\n", nCC(insn_cond), dD, dM);
+ DIP("fnegd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
goto decode_success;
}
else if (b16 == 1 && b7 == 1) {
// FSQRTD
IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
- DIP("fsqrtd%s d%u, d%u\n", nCC(insn_cond), dD, dM);
+ DIP("fsqrtd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
goto decode_success;
}
else
@@ -3535,38 +3510,38 @@
/* ----------------- I <-> D conversions ----------------- */
// F{S,U}ITOD dD, fM
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,1,1,1))
- && BITS4(1,0,0,0) == (insn_19_16 & BITS4(1,1,1,1))
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,0,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,1))
+ && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
UInt bM = (insn >> 5) & 1;
- UInt fM = (insn_3_0 << 1) | bM;
- UInt dD = insn_15_12;
+ UInt fM = (INSN(3,0) << 1) | bM;
+ UInt dD = INSN(15,12);
UInt syned = (insn >> 7) & 1;
if (syned) {
// FSITOD
putDReg(dD, unop(Iop_I32StoF64,
unop(Iop_ReinterpF32asI32, getFReg(fM))),
condT);
- DIP("fsitod%s d%u, s%u\n", nCC(insn_cond), dD, fM);
+ DIP("fsitod%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
} else {
// FUITOD
putDReg(dD, unop(Iop_I32UtoF64,
unop(Iop_ReinterpF32asI32, getFReg(fM))),
condT);
- DIP("fuitod%s d%u, s%u\n", nCC(insn_cond), dD, fM);
+ DIP("fuitod%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
}
goto decode_success;
}
// FTO{S,U}ID fD, dM
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(1,1,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,1,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
UInt bD = (insn >> 22) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- UInt dM = insn_3_0;
+ UInt fD = (INSN(15,12) << 1) | bD;
+ UInt dM = INSN(3,0);
UInt bZ = (insn >> 7) & 1;
UInt syned = (insn >> 16) & 1;
IRTemp rmode = newTemp(Ity_I32);
@@ -3579,7 +3554,7 @@
getDReg(dM))),
condT);
DIP("ftosi%sd%s s%u, d%u\n", bZ ? "z" : "",
- nCC(insn_cond), fD, dM);
+ nCC(INSN_COND), fD, dM);
} else {
// FTOUID
putFReg(fD, unop(Iop_ReinterpI32asF32,
@@ -3587,7 +3562,7 @@
getDReg(dM))),
condT);
DIP("ftoui%sd%s s%u, d%u\n", bZ ? "z" : "",
- nCC(insn_cond), fD, dM);
+ nCC(INSN_COND), fD, dM);
}
goto decode_success;
}
@@ -3617,16 +3592,16 @@
2 ia-Rn (access at Rn, then Rn += 4n)
3 db-Rn (Rn -= 4n, then access at Rn)
*/
- if (BITS8(1,1,0,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,0,0,0,0,0))
- && insn_11_8 == BITS4(1,0,1,0)) {
+ if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
+ && INSN(11,8) == BITS4(1,0,1,0)) {
UInt bP = (insn >> 24) & 1;
UInt bU = (insn >> 23) & 1;
UInt bW = (insn >> 21) & 1;
UInt bL = (insn >> 20) & 1;
UInt bD = (insn >> 22) & 1;
UInt offset = (insn >> 0) & 0xFF;
- UInt rN = insn_19_16;
- UInt fD = (insn_15_12 << 1) | bD;
+ UInt rN = INSN(19,16);
+ UInt fD = (INSN(15,12) << 1) | bD;
UInt nRegs = offset;
Int i;
@@ -3705,13 +3680,13 @@
HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%sms%s r%u, {s%u-s%u}\n",
- nm, nCC(insn_cond), rN, fD, fD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
break;
case 2: DIP("f%smias%s r%u!, {s%u-s%u}\n",
- nm, nCC(insn_cond), rN, fD, fD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
break;
case 3: DIP("f%smdbs%s r%u!, {s%u-s%u}\n",
- nm, nCC(insn_cond), rN, fD, fD + nRegs - 1);
+ nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
break;
default: vassert(0);
}
@@ -3723,13 +3698,13 @@
after_vfp_fldms_fstms:
/* --------------------- fmsr, fmrs --------------------- */
- if (BITS8(1,1,1,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,1,1,1,0))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,0,0,0) == insn_3_0
- && BITS4(0,0,0,1) == (insn_7_4 & BITS4(0,1,1,1))) {
- UInt rD = insn_15_12;
+ if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,0,0,0) == INSN(3,0)
+ && BITS4(0,0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
+ UInt rD = INSN(15,12);
UInt b7 = (insn >> 7) & 1;
- UInt fN = (insn_19_16 << 1) | b7;
+ UInt fN = (INSN(19,16) << 1) | b7;
UInt b20 = (insn >> 20) & 1;
if (rD == 15) {
/* fall through */
@@ -3741,10 +3716,10 @@
if (b20) {
putIReg(rD, unop(Iop_ReinterpF32asI32, getFReg(fN)),
condT, Ijk_Boring);
- DIP("fmrs%s r%u, s%u\n", nCC(insn_cond), rD, fN);
+ DIP("fmrs%s r%u, s%u\n", nCC(INSN_COND), rD, fN);
} else {
putFReg(fN, unop(Iop_ReinterpI32asF32, getIReg(rD)), condT);
- DIP("fmsr%s s%u, r%u\n", nCC(insn_cond), fN, rD);
+ DIP("fmsr%s s%u, r%u\n", nCC(INSN_COND), fN, rD);
}
goto decode_success;
}
@@ -3753,11 +3728,11 @@
/* --------------------- f{ld,st}s --------------------- */
// FLDS, FSTS
- if (BITS8(1,1,0,1,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,0,0,1,0))
- && BITS4(1,0,1,0) == insn_11_8) {
+ if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0))
+ && BITS4(1,0,1,0) == INSN(11,8)) {
UInt bD = (insn >> 22) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- UInt rN = insn_19_16;
+ UInt fD = (INSN(15,12) << 1) | bD;
+ UInt rN = INSN(19,16);
UInt offset = (insn & 0xFF) << 2;
UInt bU = (insn >> 23) & 1; /* 1: +offset 0: -offset */
UInt bL = (insn >> 20) & 1; /* 1: load 0: store */
@@ -3775,21 +3750,21 @@
storeLE(mkexpr(ea), getFReg(fD));
}
DIP("f%ss%s s%u, [r%u, %c#%u]\n",
- bL ? "ld" : "st", nCC(insn_cond), fD, rN,
+ bL ? "ld" : "st", nCC(INSN_COND), fD, rN,
bU ? '+' : '-', offset);
goto decode_success;
}
/* --------------------- dp insns (F) --------------------- */
- if (BITS8(1,1,1,0,0,0,0,0) == (insn_27_20 & BITS8(1,1,1,1,0,0,0,0))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,0,0,0) == (insn_7_4 & BITS4(0,0,0,1))) {
+ if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) {
UInt bM = (insn >> 5) & 1;
UInt bD = (insn >> 22) & 1;
UInt bN = (insn >> 7) & 1;
- UInt fM = (insn_3_0 << 1) | bM; /* argR */
- UInt fD = (insn_15_12 << 1) | bD; /* dst/acc */
- UInt fN = (insn_19_16 << 1) | bN; /* argL */
+ UInt fM = (INSN(3,0) << 1) | bM; /* argR */
+ UInt fD = (INSN(15,12) << 1) | bD; /* dst/acc */
+ UInt fN = (INSN(19,16) << 1) | bN; /* argL */
UInt bP = (insn >> 23) & 1;
UInt bQ = (insn >> 21) & 1;
UInt bR = (insn >> 20) & 1;
@@ -3802,50 +3777,50 @@
getFReg(fD),
triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
condT);
- DIP("fmacs%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fmacs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,0,0,1): /* NMAC: d - n * m */
putFReg(fD, triop(Iop_SubF32, rm,
getFReg(fD),
triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
condT);
- DIP("fnmacs%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fnmacs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,0,1,0): /* MSC: - d + n * m */
putFReg(fD, triop(Iop_AddF32, rm,
unop(Iop_NegF32, getFReg(fD)),
triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
condT);
- DIP("fmscs%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fmscs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,0,1,1): /* NMSC: - d - n * m */
break; //ATC
case BITS4(0,1,0,0): /* MUL: n * m */
putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
condT);
- DIP("fmuls%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fmuls%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,1,0,1): /* NMUL: - n * m */
putFReg(fD, unop(Iop_NegF32,
triop(Iop_MulF32, rm, getFReg(fN),
getFReg(fM))),
condT);
- DIP("fnmuls%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fnmuls%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,1,1,0): /* ADD: n + m */
putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
condT);
- DIP("fadds%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fadds%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(0,1,1,1): /* SUB: n - m */
putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
condT);
- DIP("fsubs%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fsubs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
case BITS4(1,0,0,0): /* DIV: n / m */
putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
condT);
- DIP("fdivs%s s%u, s%u, s%u\n", nCC(insn_cond), fD, fN, fM);
+ DIP("fdivs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
goto decode_success;
default:
break;
@@ -3868,17 +3843,17 @@
N=0 generates Invalid Operation exn if either arg is a signalling NaN
(Not that we pay any attention to N here)
*/
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(0,1,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,0,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
UInt bZ = (insn >> 16) & 1;
UInt bN = (insn >> 7) & 1;
UInt bD = (insn >> 22) & 1;
UInt bM = (insn >> 5) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- UInt fM = (insn_3_0 << 1) | bM;
- if (bZ && (insn_3_0 != 0 || (insn_7_4 & 3) != 0)) {
+ UInt fD = (INSN(15,12) << 1) | bD;
+ UInt fM = (INSN(3,0) << 1) | bM;
+ if (bZ && (INSN(3,0) != 0 || (INSN(7,4) & 3) != 0)) {
/* does not decode; fall through */
} else {
IRTemp argL = newTemp(Ity_F64);
@@ -3919,10 +3894,10 @@
putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
if (bZ) {
- DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(insn_cond), fD);
+ DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(INSN_COND), fD);
} else {
DIP("fcmp%ss%s s%u, s%u\n", bN ? "e" : "",
- nCC(insn_cond), fD, fM);
+ nCC(INSN_COND), fD, fM);
}
goto decode_success;
}
@@ -3930,39 +3905,39 @@
}
/* --------------------- unary (S) --------------------- */
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(0,0,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,0,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
UInt bD = (insn >> 22) & 1;
UInt bM = (insn >> 5) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- UInt fM = (insn_3_0 << 1) | bM;
+ UInt fD = (INSN(15,12) << 1) | bD;
+ UInt fM = (INSN(3,0) << 1) | bM;
UInt b16 = (insn >> 16) & 1;
UInt b7 = (insn >> 7) & 1;
/**/ if (b16 == 0 && b7 == 0) {
// FCPYS
putFReg(fD, getFReg(fM), condT);
- DIP("fcpys%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fcpys%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
goto decode_success;
}
else if (b16 == 0 && b7 == 1) {
// FABSS
putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT);
- DIP("fabss%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fabss%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
goto decode_success;
}
else if (b16 == 1 && b7 == 0) {
// FNEGS
putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT);
- DIP("fnegs%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fnegs%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
goto decode_success;
}
else if (b16 == 1 && b7 == 1) {
// FSQRTS
IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
- DIP("fsqrts%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fsqrts%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
goto decode_success;
}
else
@@ -3979,14 +3954,14 @@
no possibility of a loss of precision, but that's obviously not
the case here. Hence this case possibly requires rounding, and
so it drags in the current rounding mode. */
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(1,0,0,0) == (insn_19_16 & BITS4(1,1,1,1))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,0,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
UInt bM = (insn >> 5) & 1;
UInt bD = (insn >> 22) & 1;
- UInt fM = (insn_3_0 << 1) | bM;
- UInt fD = (insn_15_12 << 1) | bD;
+ UInt fM = (INSN(3,0) << 1) | bM;
+ UInt fD = (INSN(15,12) << 1) | bD;
UInt syned = (insn >> 7) & 1;
IRTemp rmode = newTemp(Ity_I32);
assign(rmode, mkexpr(mk_get_IR_rounding_mode()));
@@ -3997,7 +3972,7 @@
unop(Iop_I32StoF64,
unop(Iop_ReinterpF32asI32, getFReg(fM)))),
condT);
- DIP("fsitos%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fsitos%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
} else {
// FUITOS
putFReg(fD, binop(Iop_F64toF32,
@@ -4005,20 +3980,20 @@
unop(Iop_I32UtoF64,
unop(Iop_ReinterpF32asI32, getFReg(fM)))),
condT);
- DIP("fuitos%s s%u, s%u\n", nCC(insn_cond), fD, fM);
+ DIP("fuitos%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
}
goto decode_success;
}
// FTO{S,U}IS fD, fM
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(1,1,0,0) == (insn_19_16 & BITS4(1,1,1,0))
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(0,1,0,0) == (insn_7_4 & BITS4(0,1,0,1))) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
UInt bM = (insn >> 5) & 1;
UInt bD = (insn >> 22) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- UInt fM = (insn_3_0 << 1) | bM;
+ UInt fD = (INSN(15,12) << 1) | bD;
+ UInt fM = (INSN(3,0) << 1) | bM;
UInt bZ = (insn >> 7) & 1;
UInt syned = (insn >> 16) & 1;
IRTemp rmode = newTemp(Ity_I32);
@@ -4031,7 +4006,7 @@
unop(Iop_F32toF64, getFReg(fM)))),
condT);
DIP("ftosi%ss%s s%u, d%u\n", bZ ? "z" : "",
- nCC(insn_cond), fD, fM);
+ nCC(INSN_COND), fD, fM);
goto decode_success;
} else {
// FTOUIS
@@ -4040,7 +4015,7 @@
// unop(Iop_F32toF64, getFReg(fM)))),
// condT);
//DIP("ftoui%ss%s s%u, d%u\n", bZ ? "z" : "",
- // nCC(insn_cond), fD, fM);
+ // nCC(INSN_COND), fD, fM);
//goto decode_success;
}
}
@@ -4048,31 +4023,31 @@
/* ----------------- S <-> D conversions ----------------- */
// FCVTDS
- if (BITS8(1,1,1,0,1,0,1,1) == insn_27_20
- && BITS4(0,1,1,1) == insn_19_16
- && BITS4(1,0,1,0) == insn_11_8
- && BITS4(1,1,0,0) == (insn_7_4 & BITS4(1,1,0,1))) {
- UInt dD = insn_15_12;
+ if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+ && BITS4(0,1,1,1) == INSN(19,16)
+ && BITS4(1,0,1,0) == INSN(11,8)
+ && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) {
+ UInt dD = INSN(15,12);
UInt bM = (insn >> 5) & 1;
- UInt fM = (insn_3_0 << 1) | bM;
+ UInt fM = (INSN(3,0) << 1) | bM;
putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT);
- DIP("fcvtds%s d%u, s%u\n", nCC(insn_cond), dD, fM);
+ DIP("fcvtds%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
goto decode_success;
}
// FCVTSD
- if (BITS8(1,1,1,0,1,0,1,1) == (insn_27_20 & BITS8(1,1,1,1,1,0,1,1))
- && BITS4(0,1,1,1) == insn_19_16
- && BITS4(1,0,1,1) == insn_11_8
- && BITS4(1,1,0,0) == insn_7_4) {
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(0,1,1,1) == INSN(19,16)
+ && BITS4(1,0,1,1) == INSN(11,8)
+ && BITS4(1,1,0,0) == INSN(7,4)) {
UInt bD = (insn >> 22) & 1;
- UInt fD = (insn_15_12 << 1) | bD;
- U...
[truncated message content] |
|
From: <sv...@va...> - 2009-12-29 11:12:11
|
Author: sewardj
Date: 2009-12-29 11:11:55 +0000 (Tue, 29 Dec 2009)
New Revision: 1943
Log:
Enable another LDRD/STRD amode: xxRD rD, [rN], #imm
Modified:
branches/ARM/priv/guest_arm_toIR.c
Modified: branches/ARM/priv/guest_arm_toIR.c
===================================================================
--- branches/ARM/priv/guest_arm_toIR.c 2009-12-27 23:21:08 UTC (rev 1942)
+++ branches/ARM/priv/guest_arm_toIR.c 2009-12-29 11:11:55 UTC (rev 1943)
@@ -4398,7 +4398,6 @@
}
else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_20 == BITS3(1,0,0)) {
summary = 3 | 16;
- goto decode_failure; //ATC
}
else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_20 == BITS3(0,0,0)) {
summary = 3 | 32;
|
|
From: Konstantin S. <kon...@gm...> - 2009-12-29 10:55:06
|
Hi Valgrind devs, First question: Valgrind installation contains include files, which makes me think that it is possible to build valgrind tools w/o having the valgrind sources. However, with the current version of valgrind, it does dot work: include/valgrind/pub_tool_basics.h includes "config.h", which is not a part of valgrind installation. Can that be fixed? Second question: Building valgrind tools requires passing quite unusual and system-dependent flags to gcc and ld. When building valgrind tools in the usual way, these flags are generated by automake/configure. Is there a simple way to guess these flags from the valgrind installation tree? Third question: Few of the valgrind public headers are not C++-able. Can that be fixed? Here is what I need to build my valgrind tool in C++. cxx.patch: the patch valgrind_cxx_test.cc: the test Linux: g++ -Itrunk/inst/include/valgrind -Itrunk -DVGA_x86=1 -DVGO_linux=1 -DVGP_x86_linux=1 -m32 valgrind_cxx_test.cc -c g++ -Itrunk/inst/include/valgrind -Itrunk -DVGA_amd64=1 -DVGO_linux=1 -DVGP_amd64_linux=1 -m64 valgrind_cxx_test.cc -c Mac g++ -Itrunk/inst/include/valgrind -Itrunk -DVGA_x86=1 -DVGO_darwin=1 -DVGP_x86_darwin=1 -m32 valgrind_cxx_test.cc -c If you build the test w/o the patch, you will see why the patch is required. Thanks and happy New Year! --kcc |
|
From: <sv...@va...> - 2009-12-27 23:21:26
|
Author: sewardj
Date: 2009-12-27 23:21:08 +0000 (Sun, 27 Dec 2009)
New Revision: 1942
Log:
Fix incorrect implementation of SXTAB in r1941 (zero extended when
should have sign extended) and implement UXTAH.
Modified:
branches/ARM/priv/guest_arm_toIR.c
Modified: branches/ARM/priv/guest_arm_toIR.c
===================================================================
--- branches/ARM/priv/guest_arm_toIR.c 2009-12-27 17:00:11 UTC (rev 1941)
+++ branches/ARM/priv/guest_arm_toIR.c 2009-12-27 23:21:08 UTC (rev 1942)
@@ -4548,18 +4548,45 @@
IRTemp srcL = newTemp(Ity_I32);
IRTemp srcR = newTemp(Ity_I32);
IRTemp res = newTemp(Ity_I32);
+ assign(srcR, getIReg(rM));
+ assign(srcL, getIReg(rN));
+ assign(res, binop(Iop_Add32,
+ mkexpr(srcL),
+ unop(Iop_8Sto32,
+ unop(Iop_32to8,
+ genROR32(srcR, 8 * rot)))));
+ putIReg(rD, mkexpr(res), condT, Ijk_Boring);
+ DIP("sxtab%s r%u, r%u, r%u, ror #%u\n",
+ nCC(insn_cond), rD, rN, rM, rot);
+ goto decode_success;
+ }
+ /* fall through */
+ }
+ /* ------------------- uxtah ------------- */
+ if (BITS8(0,1,1,0,1,1,1,1) == insn_27_20
+ && BITS4(0,0,0,0) == (insn_11_8 & BITS4(0,0,1,1))
+ && BITS4(0,1,1,1) == insn_7_4) {
+ UInt rN = insn_19_16;
+ UInt rD = insn_15_12;
+ UInt rM = insn_3_0;
+ UInt rot = (insn >> 10) & 3;
+ if (rN == 15/*it's UXTH*/ || rD == 15 || rM == 15) {
+ /* undecodable; fall through */
+ } else {
+ IRTemp srcL = newTemp(Ity_I32);
+ IRTemp srcR = newTemp(Ity_I32);
+ IRTemp res = newTemp(Ity_I32);
assign(srcR, getIReg(rM));
assign(srcL, getIReg(rN));
assign(res, binop(Iop_Add32,
mkexpr(srcL),
- binop(Iop_And32,
- genROR32(srcR, 8 * rot),
- mkU32(0xFF))));
-
+ unop(Iop_16Uto32,
+ unop(Iop_32to16,
+ genROR32(srcR, 8 * rot)))));
putIReg(rD, mkexpr(res), condT, Ijk_Boring);
- DIP("sxtab%s r%u, r%u, r%u, ror #%u\n",
+ DIP("uxtah%s r%u, r%u, r%u, ror #%u\n",
nCC(insn_cond), rD, rN, rM, rot);
goto decode_success;
}
|
|
From: Stefan K. <en...@ho...> - 2009-12-27 23:16:41
|
Am 27.12.2009 16:29, schrieb Bart Van Assche:
> On Sat, Dec 26, 2009 at 5:52 PM, Stefan Kost <en...@ho...
> <mailto:en...@ho...>> wrote:
>
> I am quite interested in a coverage tool that does not need
> recompilation. There
> seems to be a patched qemu somewhere, but then I found
> valgrind-vcov. I had some
> issue building the branch.
>
>
> That is because at the time a Valgrind branch is created, only Valgrind
> is branched but not VEX. If you look up the last modification date of
> the Valgrind code on the Valgrind branch and update the VEX source code
> to that date, then the build should succeed.
>
> Bart.
Thanks that helps, would be nice to put this to README_DEVELOPERS. This is what
I did:
> svn log -r PREV
------------------------------------------------------------------------
r10643 | njn | 2009-07-28 03:39:43 +0300 (Di, 28. Jul 2009) | 3 Zeilen
Merged all the changes from the trunk between r7367:10642, updated VCov for
various changes, and fixed a few other minor things.
------------------------------------------------------------------------
> cd VEX
> svn up -r{2009-07-28}
...
> cd ..
Unfortunately this does not magically fix the VCOV issues.
Stefan
|
|
From: <sv...@va...> - 2009-12-27 17:00:28
|
Author: sewardj
Date: 2009-12-27 17:00:11 +0000 (Sun, 27 Dec 2009)
New Revision: 1941
Log:
Handle v6 SXTAB insn.
Modified:
branches/ARM/priv/guest_arm_toIR.c
Modified: branches/ARM/priv/guest_arm_toIR.c
===================================================================
--- branches/ARM/priv/guest_arm_toIR.c 2009-12-27 16:20:38 UTC (rev 1940)
+++ branches/ARM/priv/guest_arm_toIR.c 2009-12-27 17:00:11 UTC (rev 1941)
@@ -4534,6 +4534,38 @@
after_load_store_doubleword:
+ /* ------------------- sxtab ------------- */
+ if (BITS8(0,1,1,0,1,0,1,0) == insn_27_20
+ && BITS4(0,0,0,0) == (insn_11_8 & BITS4(0,0,1,1))
+ && BITS4(0,1,1,1) == insn_7_4) {
+ UInt rN = insn_19_16;
+ UInt rD = insn_15_12;
+ UInt rM = insn_3_0;
+ UInt rot = (insn >> 10) & 3;
+ if (rN == 15/*it's SXTB*/ || rD == 15 || rM == 15) {
+ /* undecodable; fall through */
+ } else {
+ IRTemp srcL = newTemp(Ity_I32);
+ IRTemp srcR = newTemp(Ity_I32);
+ IRTemp res = newTemp(Ity_I32);
+
+ assign(srcR, getIReg(rM));
+ assign(srcL, getIReg(rN));
+ assign(res, binop(Iop_Add32,
+ mkexpr(srcL),
+ binop(Iop_And32,
+ genROR32(srcR, 8 * rot),
+ mkU32(0xFF))));
+
+ putIReg(rD, mkexpr(res), condT, Ijk_Boring);
+
+ DIP("sxtab%s r%u, r%u, r%u, ror #%u\n",
+ nCC(insn_cond), rD, rN, rM, rot);
+ goto decode_success;
+ }
+ /* fall through */
+ }
+
/* ----------------------------------------------------------- */
/* -- Undecodable -- */
/* ----------------------------------------------------------- */
|
|
From: <sv...@va...> - 2009-12-27 16:20:53
|
Author: sewardj
Date: 2009-12-27 16:20:38 +0000 (Sun, 27 Dec 2009)
New Revision: 1940
Log:
Add support for v6 instructions SMUL{B,T}{B,T} and LDRD/STRD. This
makes it possible to run OpenOffice. Also fixes #219131.
Modified:
branches/ARM/priv/guest_arm_toIR.c
Modified: branches/ARM/priv/guest_arm_toIR.c
===================================================================
--- branches/ARM/priv/guest_arm_toIR.c 2009-12-15 10:23:44 UTC (rev 1939)
+++ branches/ARM/priv/guest_arm_toIR.c 2009-12-27 16:20:38 UTC (rev 1940)
@@ -184,6 +184,9 @@
#define BITS2(_b1,_b0) \
(((_b1) << 1) | (_b0))
+#define BITS3(_b2,_b1,_b0) \
+ (((_b2) << 2) | ((_b1) << 1) | (_b0))
+
#define BITS4(_b3,_b2,_b1,_b0) \
(((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0))
@@ -1550,7 +1553,7 @@
UInt insn_cond, insn_27_20, insn_24_21, insn_11_0, insn_3_0;
UInt insn_25, insn_7, insn_4, insn_27_24, insn_21, summary;
UInt insn_11_4, insn_19_12, insn_19_16, insn_15_12;
- UInt insn_11_8, insn_7_4, insn_22_21;
+ UInt insn_11_8, insn_7_4, insn_22_21, insn_22_20;
HChar dis_buf[128]; // big enough to hold LDMIA etc text
/* What insn variants are we supporting today? */
@@ -1593,6 +1596,7 @@
insn_4 = (insn >> 4) & 1;
insn_27_24 = (insn >> 24) & 0xF;
insn_22_21 = (insn >> 21) & 3;
+ insn_22_20 = (insn >> 20) & 7;
insn_21 = (insn >> 21) & 1;
insn_11_4 = (insn >> 4) & 0xFF;
insn_19_12 = (insn >> 12) & 0xFF;
@@ -4311,6 +4315,225 @@
/* fall through */
}
+ /* ------------------- smul{b,t}{b,t} ------------- */
+ if (BITS8(0,0,0,1,0,1,1,0) == insn_27_20
+ && BITS4(0,0,0,0) == insn_15_12
+ && BITS4(1,0,0,0) == (insn_7_4 & BITS4(1,0,0,1))) {
+ UInt rD = insn_19_16;
+ UInt rM = insn_11_8;
+ UInt rN = insn_3_0;
+ UInt bM = (insn >> 6) & 1;
+ UInt bN = (insn >> 5) & 1;
+ if (bN == 0 && bM == 1) goto decode_failure; //ATC
+ if (bN == 1 && bM == 0) goto decode_failure; //ATC
+ if (bN == 1 && bM == 1) goto decode_failure; //ATC
+ if (rD == 15 || rN == 15 || rM == 15) {
+ /* undecodable; fall through */
+ } else {
+ IRTemp srcL = newTemp(Ity_I32);
+ IRTemp srcR = newTemp(Ity_I32);
+ IRTemp res = newTemp(Ity_I32);
+
+ /* Extract and sign extend the two 16-bit operands */
+ assign(srcL, binop(Iop_Sar32,
+ binop(Iop_Shl32, getIReg(rN),
+ mkU8(bN ? 0 : 16)),
+ mkU8(16)));
+ assign(srcR, binop(Iop_Sar32,
+ binop(Iop_Shl32, getIReg(rM),
+ mkU8(bM ? 0 : 16)),
+ mkU8(16)));
+
+ assign(res, binop(Iop_Mul32, mkexpr(srcL), mkexpr(srcR)));
+ putIReg(rD, mkexpr(res), condT, Ijk_Boring);
+
+ DIP("smul%c%c%s r%u, r%u, r%u\n",
+ bN ? 't' : 'b', bM ? 't' : 'b', nCC(insn_cond), rD, rN, rM);
+ goto decode_success;
+ }
+ /* fall through */
+ }
+
+ /* --------------------- Load/store doubleword ------------- */
+ // LDRD STRD
+ /* 31 27 23 19 15 11 7 3 # highest bit
+ 28 24 20 16 12 8 4 0
+ A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l
+ A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
+ A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l
+ A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
+ A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l
+ A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
+ */
+ /* case coding:
+ 1 at-ea (access at ea)
+ 2 at-ea-then-upd (access at ea, then Rn = ea)
+ 3 at-Rn-then-upd (access at Rn, then Rn = ea)
+ ea coding
+ 16 Rn +/- imm8
+ 32 Rn +/- Rm
+ */
+ /* Quickly skip over all of this for hopefully most instructions */
+ if ((insn_27_24 & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
+ goto after_load_store_doubleword;
+
+ /* Check the "11S1" thing. */
+ if ((insn_7_4 & BITS4(1,1,0,1)) != BITS4(1,1,0,1))
+ goto after_load_store_doubleword;
+
+ summary = 0;
+
+ /**/ if (insn_27_24 == BITS4(0,0,0,1) && insn_22_20 == BITS3(1,0,0)) {
+ summary = 1 | 16;
+ }
+ else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_20 == BITS3(0,0,0)) {
+ summary = 1 | 32;
+ }
+ else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_20 == BITS3(1,1,0)) {
+ summary = 2 | 16;
+ }
+ else if (insn_27_24 == BITS4(0,0,0,1) && insn_22_20 == BITS3(0,1,0)) {
+ summary = 2 | 32;
+ goto decode_failure; //ATC
+ }
+ else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_20 == BITS3(1,0,0)) {
+ summary = 3 | 16;
+ goto decode_failure; //ATC
+ }
+ else if (insn_27_24 == BITS4(0,0,0,0) && insn_22_20 == BITS3(0,0,0)) {
+ summary = 3 | 32;
+ goto decode_failure; //ATC
+ }
+ else goto after_load_store_doubleword;
+
+ { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
+ UInt rD = (insn >> 12) & 0xF; /* 15:12 */
+ UInt rM = (insn >> 0) & 0xF; /* 3:0 */
+ UInt bU = (insn >> 23) & 1; /* 23 U=1 offset+, U=0 offset- */
+ UInt bS = (insn >> 5) & 1; /* S=1 store, S=0 load */
+ UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
+
+ /* Require rD to be an even numbered register */
+ if ((rD & 1) != 0)
+ goto after_load_store_doubleword;
+
+ /* Require 11:8 == 0 for Rn +/- Rm cases */
+ if ((summary & 32) != 0 && (imm8 & 0xF0) != 0)
+ goto after_load_store_doubleword;
+
+ /* Skip some invalid cases, which would lead to two competing
+ updates to the same register, or which are otherwise
+ disallowed by the spec. */
+ switch (summary) {
+ case 1 | 16:
+ break;
+ case 1 | 32:
+ if (rM == 15) goto after_load_store_doubleword;
+ break;
+ case 2 | 16: case 3 | 16:
+ if (rN == 15) goto after_load_store_doubleword;
+ if (bS == 0 && (rN == rD || rN == rD+1))
+ goto after_load_store_doubleword;
+ break;
+ case 2 | 32: case 3 | 32:
+ if (rM == 15) goto after_load_store_doubleword;
+ if (rN == 15) goto after_load_store_doubleword;
+ if (rN == rM) goto after_load_store_doubleword;
+ if (bS == 0 && (rN == rD || rN == rD+1))
+ goto after_load_store_doubleword;
+ break;
+ default:
+ vassert(0);
+ }
+
+ /* Now, we can't do a conditional load or store, since that very
+ likely will generate an exception. So we have to take a side
+ exit at this point if the condition is false. */
+ if (condT != IRTemp_INVALID) {
+ mk_skip_to_next_if_cond_is_false( condT );
+ condT = IRTemp_INVALID;
+ }
+ /* Ok, now we're unconditional. Do the load or store. */
+
+ /* compute the effective address. Bind it to a tmp since we
+ may need to use it twice. */
+ IRExpr* eaE = NULL;
+ switch (summary & 0xF0) {
+ case 16:
+ eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf );
+ break;
+ case 32:
+ eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
+ break;
+ }
+ vassert(eaE);
+ IRTemp eaT = newTemp(Ity_I32);
+ assign(eaT, eaE);
+
+ /* get the old Rn value */
+ IRTemp rnT = newTemp(Ity_I32);
+ assign(rnT, getIReg(rN));
+
+ /* decide on the transfer address */
+ IRTemp taT = IRTemp_INVALID;
+ switch (summary & 0x0F) {
+ case 1: case 2: taT = eaT; break;
+ case 3: taT = rnT; break;
+ }
+ vassert(taT != IRTemp_INVALID);
+
+ /* XXX deal with alignment constraints */
+ /* XXX: but the A8 doesn't seem to trap for misaligned loads, so,
+ ignore alignment issues for the time being. */
+
+ /* doubleword store S 1
+ doubleword load S 0
+ */
+ HChar* name = NULL;
+ /* generate the transfers */
+ if (bS == 1) { // doubleword store
+ storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIReg(rD+0) );
+ storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(4)), getIReg(rD+1) );
+ name = "strd";
+ } else { // doubleword load
+ putIReg( rD+0,
+ loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(0))),
+ IRTemp_INVALID, Ijk_Boring );
+ putIReg( rD+1,
+ loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(4))),
+ IRTemp_INVALID, Ijk_Boring );
+ name = "ldrd";
+ }
+
+ /* Update Rn if necessary. */
+ switch (summary & 0x0F) {
+ case 2: case 3:
+ // should be assured by logic above:
+ if (bS == 0) {
+ vassert(rD+0 != rN); /* since we just wrote rD+0 */
+ vassert(rD+1 != rN); /* since we just wrote rD+1 */
+ }
+ putIReg( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
+ break;
+ }
+
+ switch (summary & 0x0F) {
+ case 1: DIP("%s%s r%u, %s\n", name, nCC(insn_cond), rD, dis_buf);
+ break;
+ case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
+ name, nCC(insn_cond), rD, dis_buf);
+ break;
+ case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
+ name, nCC(insn_cond), rD, dis_buf);
+ break;
+ default: vassert(0);
+ }
+
+ goto decode_success;
+ }
+
+ after_load_store_doubleword:
+
/* ----------------------------------------------------------- */
/* -- Undecodable -- */
/* ----------------------------------------------------------- */
|
|
From: Bart V. A. <bar...@gm...> - 2009-12-27 14:29:56
|
On Sat, Dec 26, 2009 at 5:52 PM, Stefan Kost <en...@ho...>wrote: > I am quite interested in a coverage tool that does not need recompilation. > There > seems to be a patched qemu somewhere, but then I found valgrind-vcov. I had > some > issue building the branch. > That is because at the time a Valgrind branch is created, only Valgrind is branched but not VEX. If you look up the last modification date of the Valgrind code on the Valgrind branch and update the VEX source code to that date, then the build should succeed. Bart. |
|
From: Stefan K. <en...@ho...> - 2009-12-26 16:53:08
|
Hi, I am quite interested in a coverage tool that does not need recompilation. There seems to be a patched qemu somewhere, but then I found valgrind-vcov. I had some issue building the branch. mv -f .deps/memcheck_x86_linux-mc_main.Tpo .deps/memcheck_x86_linux-mc_main.Po gcc -DHAVE_CONFIG_H -I. -I.. -I.. -I../include -I../VEX/pub -DVGA_x86=1 -DVGO_linux=1 -DVGP_x86_linux=1 -m32 -mpreferred-stack-boundary=2 -O2 -g -Wall -Wmissing-prototypes -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Wno-format-zero-length -fno-strict-aliasing -O2 -Wno-long-long -Wno-pointer-sign -Wdeclaration-after-statement -fno-stack-protector -MT memcheck_x86_linux-mc_translate.o -MD -MP -MF .deps/memcheck_x86_linux-mc_translate.Tpo -c -o memcheck_x86_linux-mc_translate.o `test -f 'mc_translate.c' || echo './'`mc_translate.c mc_translate.c: In function ‘vgMemCheck_instrument’: mc_translate.c:4202: error: ‘struct <anonymous>’ has no member named ‘resSC’ mc_translate.c:4204: error: ‘struct <anonymous>’ has no member named ‘resSC’ mc_translate.c:4208: error: ‘struct <anonymous>’ has no member named ‘resSC’ mc_translate.c: In function ‘schemeS’: mc_translate.c:4949: error: ‘struct <anonymous>’ has no member named ‘resSC’ mc_translate.c:4950: error: ‘struct <anonymous>’ has no member named ‘resSC’ make[4]: *** [memcheck_x86_linux-mc_translate.o] Fehler 1 make[4]: Leaving directory `/home/ensonic/projects/valgrind-vcov/memcheck' make[3]: *** [all-recursive] Fehler 1 make[3]: Leaving directory `/home/ensonic/projects/valgrind-vcov/memcheck' make[2]: *** [all] Fehler 2 make[2]: Leaving directory `/home/ensonic/projects/valgrind-vcov/memcheck' make[1]: *** [all-recursive] Fehler 1 make[1]: Leaving directory `/home/ensonic/projects/valgrind-vcov' make: *** [all] Fehler 2 After skipping memcheck, I could get the rest to build, but get issues running it. Any ideas? I would be interested to figure if it can be made useable together with lcov or is vcov abandoned? Stefan /vg-in-place --tool=exp-vcov /path/to/testapp ==26250== exp-VCov, a test coverage tool. ==26250== NOTE: This is an Experimental-Class Valgrind Tool. ==26250== Copyright (C) 2002-2008, and GNU GPL'd, by Nicholas Nethercote. ==26250== Using Valgrind-3.5.0.SVN and LibVEX; rerun with -h for copyright info ==26250== exp-VCov: vc_main.c:385 (doOneInstr): the 'impossible' happened. exp-VCov: didn't find 43 in lineCCs (/usr/src/debug//////////glibc-2.10.1/setjmp/../sysdeps/i386/setjmp.S) ==26250== at 0x38002AB0: report_and_quit (m_libcassert.c:145) ==26250== by 0x38002CEC: vgPlain_assert_fail (m_libcassert.c:217) ==26250== by 0x38000B83: doOneInstr (vc_main.c:384) ==26250== by 0x38000C8F: vc_instrument (vc_main.c:435) ==26250== by 0x38095912: LibVEX_Translate (main_main.c:495) ==26250== by 0x38018CE1: vgPlain_translate (m_translate.c:1517) ==26250== by 0x3803D991: vgPlain_scheduler (scheduler.c:844) ==26250== by 0x38069414: run_a_thread_NORETURN (syswrap-linux.c:91) sched status: running_tid=1 Thread 1: status = VgTs_Runnable ==26250== at 0x466BD80: __sigsetjmp (setjmp.S:34) ==26250== by 0x46622B8: setlocale (setlocale.c:333) ==26250== by 0x8049E3A: main (bt-cmd.c:65) |
|
From: Dmitry Z. <zh...@is...> - 2009-12-23 09:19:49
|
Hello. It seems like ARM branch can't be compiled with recent versions of GCC (stock GCC 4.4 and CodeSourcery arm-2008q3 or even earlier). A patch is attached that allows building of Valgrind. Probably the reason for the failure is in the GCC version 4.4 changelog: "On ARM EABI targets, the C++ mangling of the va_list type has been changed to conform to the current revision of the EABI". This should mean that for ARM va_list is not integer (but a structure it seems) anymore which is still true for other platforms that Valgrind supports. Valgrind sources are written in such a way that it wants va_list to be able to be casted to an integer type implicitly. This is no longer available in current GCC for ARM. Seems like CodeSourcery made this change a little bit earlier (as original GCC version 4.3.2 is able to build Valgrind without errors). Please review the patch. It only makes a cast using union. Following is the error log: In file included from m_debuglog.c:57: ../include/valgrind.h: In function 'VALGRIND_PRINTF': ../include/valgrind.h:4186: error: aggregate value used where an integer was expected ../include/valgrind.h: In function 'VALGRIND_PRINTF_BACKTRACE': ../include/valgrind.h:4201: error: aggregate value used where an integer was expected make[3]: *** [libcoregrind_arm_linux_a-m_debuglog.o] Error 1 make[3]: *** Waiting for unfinished jobs.... mv -f .deps/libcoregrind_arm_linux_a-m_debugger.Tpo .deps/libcoregrind_arm_linux_a-m_debugger.Po mv -f .deps/libcoregrind_arm_linux_a-m_commandline.Tpo .deps/libcoregrind_arm_linux_a-m_commandline.Po make[3]: Leaving directory `/home/batuzovk/valgrind/valgrind-clean/coregrind' make[2]: *** [all] Error 2 make[2]: Leaving directory `/home/batuzovk/valgrind/valgrind-clean/coregrind' make[1]: *** [all-recursive] Error 1 make[1]: Leaving directory `/home/batuzovk/valgrind/valgrind-clean' make: *** [all] Error 2 Regards, Dmitry |
|
From: Bill H. <bil...@ki...> - 2009-12-22 15:25:32
|
If you have a program that uses fork and exec and the exec fails and you
call _exit, then valgrind reports all memory used as leaks. Here is a
simple test case:
foo.c:
#include <stdlib.h>
#include <unistd.h>
int main()
{
void* v = malloc(10);
int pid = fork();
if(pid == 0)
{
#ifdef LEAK
_exit(1);
#endif
}
free(v);
return 0;
}
gcc -DLEAK foo.c
valgrind -q --leak-check=full --show-reachable=yes -v ./a.out
HEAP SUMMARY:
==22620== in use at exit: 10 bytes in 1 blocks
==22620== total heap usage: 1 allocs, 0 frees, 10 bytes allocated
==22620==
==22620== 10 bytes in 1 blocks are still reachable in loss record 1 of 1
==22620== at 0x4C221A7: malloc (vg_replace_malloc.c:195)
==22620== by 0x4005DD: main (in
/home/hoffman/MyBuilds/CMake-nighly-build/a.out)
==22620==
gcc foo.c
valgrind -q --leak-check=full --show-reachable=yes -v ./a.out
==22664== HEAP SUMMARY:
==22664== in use at exit: 0 bytes in 0 blocks
==22664== total heap usage: 1 allocs, 1 frees, 10 bytes allocated
--
Bill Hoffman
Kitware, Inc.
28 Corporate Drive
Clifton Park, NY 12065
bil...@ki...
http://www.kitware.com
518 881-4905 (Direct)
518 371-3971 x105
Fax (518) 371-4573
|
|
From: Bill H. <bil...@ki...> - 2009-12-22 14:15:44
|
Bill Hoffman wrote: > If you have a program that uses fork and exec and the exec fails and you > call _exit, then valgrind reports all memory used as leaks. Here is a > simple test case: > > RTFM.... --child-silent-after-fork=yes seems to be the option I was missing. Sorry for the noise. -Bill |
|
From: Alexander P. <gl...@go...> - 2009-12-22 09:31:41
|
Nightly build on mcgrind ( Darwin 9.7.0 i386 ) Started at 2009-12-22 09:06:00 MSK Ended at 2009-12-22 09:24:34 MSK Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 433 tests, 22 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/null_socket (stdout) memcheck/tests/origin5-bz2 (stderr) memcheck/tests/varinfo1 (stderr) memcheck/tests/varinfo2 (stderr) memcheck/tests/varinfo3 (stderr) memcheck/tests/varinfo4 (stderr) memcheck/tests/varinfo5 (stderr) memcheck/tests/varinfo6 (stderr) none/tests/async-sigs (stderr) none/tests/faultstatus (stderr) none/tests/pth_blockedsig (stderr) helgrind/tests/hg03_inherit (stderr) helgrind/tests/hg04_race (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/rwlock_race (stderr) helgrind/tests/tc01_simple_race (stderr) helgrind/tests/tc05_simple_race (stderr) helgrind/tests/tc06_two_races (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc16_byterace (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc21_pthonce (stderr) helgrind/tests/tc23_bogus_condwait (stderr) -- Alexander Potapenko Software Engineer Google Moscow |
|
From: Tom H. <to...@co...> - 2009-12-22 08:30:10
|
On 22/12/09 04:23, NODA, Kai wrote: > At this time, spe_program_load() in libspe2 returns "No such process" error. > > http://valgrind.org/docs/manual/dist.news.html says >> Release 3.4.0 (2 January 2009) > ... >> 167288 Patch file for missing system calls on Cell BE > > I believe this was done by incorporating the patch in > http://bugs.kde.org/show_bug.cgi?id=167288 > > Does the error shown above mean that the patch doesn't keep up > with changes in the Valgrind core? > If so, how can I modify it so that Memcheck works on Cell/B.E. ? That patch is only for ppc32 but it looks like you're running a 64 bit program. > Is it necessary to modify coregrind/m_syswrap/syswrap-ppc64-linux.c > as done in the rev. 8731 ? Basically, yes. Tom -- Tom Hughes (to...@co...) http://www.compton.nu/ |
|
From: Bart V. A. <bar...@gm...> - 2009-12-22 08:29:23
|
Nightly build on cellbuzz-native ( cellbuzz, ppc64, Fedora 7, native ) Started at 2009-12-22 02:00:05 EST Ended at 2009-12-22 03:28:57 EST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 449 tests, 45 stderr failures, 10 stdout failures, 0 post failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cases-full (stderr) memcheck/tests/leak-cases-summary (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/linux/timerfd-syscall (stdout) memcheck/tests/linux-syscalls-2007 (stderr) memcheck/tests/origin5-bz2 (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/varinfo1 (stderr) memcheck/tests/varinfo2 (stderr) memcheck/tests/varinfo3 (stderr) memcheck/tests/varinfo4 (stderr) memcheck/tests/varinfo5 (stderr) memcheck/tests/varinfo6 (stderr) memcheck/tests/wrap8 (stdout) memcheck/tests/wrap8 (stderr) none/tests/empty-exe (stderr) none/tests/linux/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-vmx (stdout) none/tests/ppc32/round (stdout) none/tests/ppc32/test_gx (stdout) none/tests/ppc64/jm-fp (stdout) none/tests/ppc64/jm-vmx (stdout) none/tests/ppc64/round (stdout) none/tests/shell_valid2 (stderr) none/tests/shell_valid3 (stderr) none/tests/shell_zerolength (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/tc06_two_races_xml (stderr) helgrind/tests/tc22_exit_w_lock (stderr) helgrind/tests/tc23_bogus_condwait (stderr) drd/tests/tc23_bogus_condwait (stderr) exp-ptrcheck/tests/bad_percentify (stderr) exp-ptrcheck/tests/base (stderr) exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/fp (stderr) exp-ptrcheck/tests/globalerr (stderr) exp-ptrcheck/tests/hackedbz2 (stderr) exp-ptrcheck/tests/hp_bounds (stderr) exp-ptrcheck/tests/hp_dangle (stderr) exp-ptrcheck/tests/hsg (stderr) exp-ptrcheck/tests/justify (stderr) exp-ptrcheck/tests/partial_bad (stderr) exp-ptrcheck/tests/partial_good (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) exp-ptrcheck/tests/realloc (stderr) exp-ptrcheck/tests/stackerr (stderr) exp-ptrcheck/tests/strcpy (stderr) exp-ptrcheck/tests/supp (stderr) exp-ptrcheck/tests/tricky (stderr) exp-ptrcheck/tests/unaligned (stderr) exp-ptrcheck/tests/zero (stderr) |
|
From: NODA, K. <no...@gm...> - 2009-12-22 04:24:10
|
Hi, all I tried to use Memcheck on Cell/B.E., but got the following error: > --18696-- WARNING: unhandled syscall: 279 > ==18696== at 0x80C92207A0: syscall (in /lib64/libc-2.5.so) > ==18696== by 0x80C92FAEAB: _base_spe_context_create (in /usr/lib64/libspe2.so.2.2.80) > ==18696== by 0x80C92FA23B: spe_context_create (in /usr/lib64/libspe2.so.2.2.80) > ==18696== by 0x10001477: main (in /home/k_noda/crank-nicholson/wrapper) > --18696-- You may be able to write your own handler. > --18696-- Read the file README_MISSING_SYSCALL_OR_IOCTL. > --18696-- Nevertheless we consider this a bug. Please report > --18696-- it at http://valgrind.org/support/bug_reports.html. ... > spu_create(): Function not implemented At this time, spe_program_load() in libspe2 returns "No such process" error. http://valgrind.org/docs/manual/dist.news.html says > Release 3.4.0 (2 January 2009) ... > 167288 Patch file for missing system calls on Cell BE I believe this was done by incorporating the patch in http://bugs.kde.org/show_bug.cgi?id=167288 Does the error shown above mean that the patch doesn't keep up with changes in the Valgrind core? If so, how can I modify it so that Memcheck works on Cell/B.E. ? Is it necessary to modify coregrind/m_syswrap/syswrap-ppc64-linux.c as done in the rev. 8731 ? Any advice is welcome. Thanks, Kai |
|
From: Tom H. <th...@cy...> - 2009-12-22 03:49:30
|
Nightly build on lloyd ( x86_64, Fedora 7 ) Started at 2009-12-22 03:05:06 GMT Ended at 2009-12-22 03:49:04 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 531 tests, 2 stderr failures, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) helgrind/tests/tc06_two_races_xml (stderr) |