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From: Dan K. <da...@ke...> - 2009-04-19 18:45:01
|
On Tue, Apr 14, 2009 at 7:17 AM, Dan Kegel <da...@ke...> wrote: > On Wed, Feb 18, 2009 at 2:53 PM, Bill Hoffman <bil...@ki...> wrote: >> Attached is a new version of the patch that is more robust and contains the >> requested documentation. > > This would be very handy. I have to jump through hoops > to avoid valgrinding python subprocesses at the > moment, and this option would have saved me > some time. Here's the same patch, updated slightly to apply to svn (it's been dragged through the mud a bit, but I think these are the right bits). - Dan |
|
From: Dominic A. <zer...@go...> - 2009-04-19 10:59:20
|
Hi Josef,
Yes, thank you. The second call to the cache model is indeed not
necessary as it will
always hit. Thus the performance loss should be even lower.
My extended cache-model will still need to be called though - but that
is a different story.
Performance will probably stay about the same unless your compiler/architecture
moves to a vastly different operating point ;-) Something I have
noticed recently
with different gcc-options!
-Dominic
On Sun, Apr 19, 2009 at 12:55 AM, Josef Weidendorfer
<Jos...@gm...> wrote:
> On Saturday 18 April 2009, Dominic Account wrote:
>> I hope I did not introduce new bugs here. Please, review
>> my patch.
>
> Just a minor remark: inlining the patch would have made it easier.
>
>> +void log_1I_1Dm_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
>> +{
>> + //VG_(printf)("1I_1Dm: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n"
>> + // " daddr=0x%010lx, dsize=%lu\n",
>> + // n, n->instr_addr, n->instr_len, data_addr, data_size);
>> + cachesim_I1_doref(n->instr_addr, n->instr_len,
>> + &n->parent->Ir.m1, &n->parent->Ir.m2);
>> + n->parent->Ir.a++;
>> +
>> + cachesim_D1_doref(data_addr, data_size,
>> + &n->parent->Dr.m1, &n->parent->Dr.m2);
>> + cachesim_D1_doref(data_addr, data_size,
>> + &n->parent->Dw.m1, &n->parent->Dw.m2);
>
> Given the cache model and the fact that no other thread can access the cache
> inbetween, the second call into the simulator should not be needed, as it always
> will be a L1 hit. Same for other handlers.
> It would be interesting to see the performance hit introduced by your patch.
>
> Josef
>
>> +
>> + n->parent->Dr.a++;
>> + n->parent->Dw.a++;
>> +}
>
|
|
From: Tom H. <th...@cy...> - 2009-04-19 03:04:13
|
Nightly build on lloyd ( x86_64, Fedora 7 ) started at 2009-04-19 03:05:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... done Regression test results follow == 478 tests, 0 stderr failures, 0 stdout failures, 0 post failures == |
|
From: Tom H. <th...@cy...> - 2009-04-19 02:46:55
|
Nightly build on mg ( x86_64, Fedora 9 ) started at 2009-04-19 03:10:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 484 tests, 0 stderr failures, 1 stdout failure, 0 post failures == none/tests/linux/mremap2 (stdout) |