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From: <sv...@va...> - 2009-01-26 23:26:24
|
Author: njn
Date: 2009-01-26 23:26:20 +0000 (Mon, 26 Jan 2009)
New Revision: 9082
Log:
Merge r9080 (handle non-power-of-2 cache attributes) from the trunk.
Added:
branches/DARWIN/cachegrind/tests/notpower2.stderr.exp
branches/DARWIN/cachegrind/tests/notpower2.vgtest
branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest
branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-use.vgtest
branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-wb.vgtest
branches/DARWIN/callgrind/tests/notpower2.stderr.exp
branches/DARWIN/callgrind/tests/notpower2.vgtest
Modified:
branches/DARWIN/cachegrind/cg-x86.c
branches/DARWIN/cachegrind/cg_main.c
branches/DARWIN/cachegrind/cg_sim.c
branches/DARWIN/cachegrind/docs/cg-manual.xml
branches/DARWIN/cachegrind/tests/Makefile.am
branches/DARWIN/cachegrind/tests/filter_stderr
branches/DARWIN/callgrind/sim.c
branches/DARWIN/callgrind/tests/Makefile.am
branches/DARWIN/callgrind/tests/filter_stderr
Modified: branches/DARWIN/cachegrind/cg-x86.c
===================================================================
--- branches/DARWIN/cachegrind/cg-x86.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg-x86.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -113,12 +113,7 @@
case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break;
case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;
- case 0x0e:
- /* Real D1 cache configuration is:
- D1c = (cache_t) { 24, 6, 64 }; */
- VG_(message)(Vg_DebugMsg, "warning: 24Kb D1 cache detected, treating as 16Kb");
- *D1c = (cache_t) { 16, 4, 64 };
- break;
+ case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break;
case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;
/* IA-64 info -- panic! */
@@ -149,12 +144,7 @@
case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break;
case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break;
case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break;
- case 0x48:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
- *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
- break;
+ case 0x48: *L2c = (cache_t) { 3072,12, 64 }; L2_found = True; break;
case 0x49:
if ((family == 15) && (model == 6))
/* On Xeon MP (family F, model 6), this is for L3 */
@@ -163,12 +153,7 @@
else
*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
break;
- case 0x4e:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
- *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
- break;
+ case 0x4e: *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; break;
/* These are sectored, whatever that means */
case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
Modified: branches/DARWIN/cachegrind/cg_main.c
===================================================================
--- branches/DARWIN/cachegrind/cg_main.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg_main.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -1158,21 +1158,15 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
+ "error: %s set count not a power of two; aborting.",
+ name);
VG_(exit)(1);
}
- if (-1 == VG_(log2)(cache->assoc)) {
- VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
Modified: branches/DARWIN/cachegrind/cg_sim.c
===================================================================
--- branches/DARWIN/cachegrind/cg_sim.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg_sim.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -44,7 +44,6 @@
Int line_size; /* bytes */
Int sets;
Int sets_min_1;
- Int assoc_bits;
Int line_size_bits;
Int tag_shift;
Char desc_line[128];
@@ -62,7 +61,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
@@ -111,8 +109,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
\
/* This loop is unrolled for just the first case, which is the most */\
/* common. We can't unroll any further because it would screw up */\
@@ -143,7 +140,7 @@
/* Second case: word straddles two lines. */ \
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
if (tag == set[0]) { \
goto block2; \
} \
@@ -162,7 +159,7 @@
set[0] = tag; \
is_miss = True; \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
tag2 = (a+size-1) >> L.tag_shift; \
if (tag2 == set[0]) { \
goto miss_treatment; \
Modified: branches/DARWIN/cachegrind/docs/cg-manual.xml
===================================================================
--- branches/DARWIN/cachegrind/docs/cg-manual.xml 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/docs/cg-manual.xml 2009-01-26 23:26:20 UTC (rev 9082)
@@ -142,7 +142,7 @@
</listitem>
<listitem>
- <para>Bit-selection hash function: the line(s) in the cache
+ <para>Bit-selection hash function: the set of line(s) in the cache
to which a memory block maps is chosen by the middle bits
M--(M+N-1) of the byte address, where:</para>
<itemizedlist>
@@ -150,15 +150,17 @@
<para>line size = 2^M bytes</para>
</listitem>
<listitem>
- <para>(cache size / line size) = 2^N bytes</para>
+ <para>(cache size / line size / associativity) = 2^N bytes</para>
</listitem>
</itemizedlist>
</listitem>
<listitem>
- <para>Inclusive L2 cache: the L2 cache replicates all the
- entries of the L1 cache. This is standard on Pentium chips,
- but AMD Opterons, Athlons and Durons
+ <para>Inclusive L2 cache: the L2 cache typically replicates all
+ the entries of the L1 caches, because fetching into L1 involves
+ fetching into L2 first (this does not guarantee strict inclusiveness,
+ as lines evicted from L2 still could reside in L1). This is
+ standard on Pentium chips, but AMD Opterons, Athlons and Durons
use an exclusive L2 cache that only holds
blocks evicted from L1. Ditto most modern VIA CPUs.</para>
</listitem>
@@ -176,7 +178,10 @@
(I1/D1/L2) of the cache from the command line using the
<computeroutput>--I1</computeroutput>,
<computeroutput>--D1</computeroutput> and
-<computeroutput>--L2</computeroutput> options.</para>
+<computeroutput>--L2</computeroutput> options.
+For cache parameters to be valid for simulation, the number
+of sets (with associativity being the number of cache lines in
+each set) has to be a power of two.</para>
<para>On PowerPC platforms
Cachegrind cannot automatically
@@ -227,10 +232,7 @@
<para>If you are interested in simulating a cache with different
properties, it is not particularly hard to write your own cache
simulator, or to modify the existing ones in
-<computeroutput>vg_cachesim_I1.c</computeroutput>,
-<computeroutput>vg_cachesim_D1.c</computeroutput>,
-<computeroutput>vg_cachesim_L2.c</computeroutput> and
-<computeroutput>vg_cachesim_gen.c</computeroutput>. We'd be
+<computeroutput>cg_sim.c</computeroutput>. We'd be
interested to hear from anyone who does.</para>
</sect2>
Modified: branches/DARWIN/cachegrind/tests/Makefile.am
===================================================================
--- branches/DARWIN/cachegrind/tests/Makefile.am 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/tests/Makefile.am 2009-01-26 23:26:20 UTC (rev 9082)
@@ -15,6 +15,7 @@
chdir.vgtest chdir.stderr.exp \
clreq.vgtest clreq.stderr.exp \
dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \
+ notpower2.vgtest notpower2.stderr.exp \
wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp
check_PROGRAMS = \
Modified: branches/DARWIN/cachegrind/tests/filter_stderr
===================================================================
--- branches/DARWIN/cachegrind/tests/filter_stderr 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/tests/filter_stderr 2009-01-26 23:26:20 UTC (rev 9082)
@@ -17,5 +17,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Copied: branches/DARWIN/cachegrind/tests/notpower2.stderr.exp (from rev 9080, trunk/cachegrind/tests/notpower2.stderr.exp)
===================================================================
--- branches/DARWIN/cachegrind/tests/notpower2.stderr.exp (rev 0)
+++ branches/DARWIN/cachegrind/tests/notpower2.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,17 @@
+
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/cachegrind/tests/notpower2.vgtest (from rev 9080, trunk/cachegrind/tests/notpower2.vgtest)
===================================================================
--- branches/DARWIN/cachegrind/tests/notpower2.vgtest (rev 0)
+++ branches/DARWIN/cachegrind/tests/notpower2.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm cachegrind.out.*
Modified: branches/DARWIN/callgrind/sim.c
===================================================================
--- branches/DARWIN/callgrind/sim.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/sim.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -74,7 +74,6 @@
Bool sectored; /* prefetch nearside cacheline on read */
int sets;
int sets_min_1;
- int assoc_bits;
int line_size_bits;
int tag_shift;
UWord tag_mask;
@@ -195,7 +194,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
c->tag_mask = ~((1<<c->tag_shift)-1);
@@ -259,8 +257,7 @@
int i, j;
UWord *set;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -359,8 +356,7 @@
int i, j;
UWord *set, tmp_tag;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -407,7 +403,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = (a+size-1) >> c->tag_shift;
+ UWord tag2 = (a+size-1) & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
@@ -676,7 +672,7 @@
/* We use lower tag bits as offset pointers to cache use info.
* I.e. some cache parameters don't work.
*/
- if (c->tag_shift < c->assoc_bits) {
+ if ( (1<<c->tag_shift) < c->assoc) {
VG_(message)(Vg_DebugMsg,
"error: Use associativity < %d for cache use statistics!",
(1<<c->tag_shift) );
@@ -690,7 +686,7 @@
static __inline__
void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
{
- int idx = (high_idx << c->assoc_bits) | low_idx;
+ int idx = (high_idx * c->assoc) + low_idx;
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
@@ -709,8 +705,7 @@
UWord *set, tmp_tag;
UInt use_mask;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
use_mask =
c->line_start_mask[a & c->line_size_mask] &
c->line_end_mask[(a+size-1) & c->line_size_mask];
@@ -745,7 +740,7 @@
}
set[0] = tag | tmp_tag;
- cacheuse_L2_miss(c, (set_no << c->assoc_bits) | tmp_tag,
+ cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
use_mask, a & ~c->line_size_mask);
return Miss;
@@ -756,7 +751,7 @@
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a >> c->tag_shift;
+ UWord tag = a & c->tag_mask;
/* Access entirely within line. */
if (set1 == set2)
@@ -765,7 +760,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a >> c->tag_shift;
+ UWord tag2 = a & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cacheuse_isMiss(c, set1, tag);
@@ -800,8 +795,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask] & \
L.line_end_mask[(a+size-1) & L.line_size_mask]; \
\
@@ -809,7 +803,7 @@
/* common. We can't unroll any further because it would screw up */\
/* if we have a direct-mapped (1-way) cache. */\
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -826,7 +820,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -842,7 +836,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
return update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
\
@@ -850,10 +844,10 @@
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask]; \
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -868,7 +862,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -882,15 +876,15 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
miss1 = update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
tag2 = (a+size-1) & L.tag_mask; \
if (tag2 == (set[0] & L.tag_mask)) { \
- idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -905,7 +899,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -919,7 +913,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag2 | tmp_tag; \
- idx = (set2 << L.assoc_bits) | tmp_tag; \
+ idx = (set2 * L.assoc) + tmp_tag; \
miss2 = update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
@@ -984,7 +978,7 @@
CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
{
UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
- UWord* set = &(L2.tags[setNo << L2.assoc_bits]);
+ UWord* set = &(L2.tags[setNo * L2.assoc]);
UWord tag = memline & L2.tag_mask;
int i, j, idx;
@@ -993,7 +987,7 @@
CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
- idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1008,7 +1002,7 @@
set[j] = set[j - 1];
}
set[0] = tmp_tag;
- idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1024,7 +1018,7 @@
set[j] = set[j - 1];
}
set[0] = tag | tmp_tag;
- idx = (setNo << L2.assoc_bits) | tmp_tag;
+ idx = (setNo * L2.assoc) + tmp_tag;
l1_loaded->dep_use = &(L2.use[idx]);
update_L2_use(idx, memline);
@@ -1380,23 +1374,16 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
- VG_(exit)(1);
+ "error: %s set count not a power of two; aborting.",
+ name);
}
- if (-1 == VG_(log2)(cache->assoc)) {
+ if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
- if (-1 == VG_(log2)(cache->line_size)) {
- VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
name, cache->line_size);
VG_(exit)(1);
Modified: branches/DARWIN/callgrind/tests/Makefile.am
===================================================================
--- branches/DARWIN/callgrind/tests/Makefile.am 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/tests/Makefile.am 2009-01-26 23:26:20 UTC (rev 9082)
@@ -11,6 +11,10 @@
simwork1.vgtest simwork1.stdout.exp simwork1.stderr.exp \
simwork2.vgtest simwork2.stdout.exp simwork2.stderr.exp \
simwork3.vgtest simwork3.stdout.exp simwork3.stderr.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ notpower2-wb.vgtest notpower2-wb.stderr.exp \
+ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
+ notpower2-use.vgtest notpower2-use.stderr.exp \
threads.vgtest threads.stderr.exp
check_PROGRAMS = clreq simwork threads
Modified: branches/DARWIN/callgrind/tests/filter_stderr
===================================================================
--- branches/DARWIN/callgrind/tests/filter_stderr 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/tests/filter_stderr 2009-01-26 23:26:20 UTC (rev 9082)
@@ -23,5 +23,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Copied: branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-hwpref.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-hwpref.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-hwpref=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-use.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-use.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-use.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-use.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-use.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --cacheuse=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-wb.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-wb.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-wb.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-wb.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-wb.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-wb=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2.vgtest (from rev 9080, trunk/callgrind/tests/notpower2.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm callgrind.out.*
|
|
From: <sv...@va...> - 2009-01-26 23:21:24
|
Author: weidendo
Date: 2009-01-26 23:21:18 +0000 (Mon, 26 Jan 2009)
New Revision: 9081
Log:
Callgrind: Remove ifdef'ed-out, non-working code.
Rechecking the diff of r9080 on the mailing list, I thought
I forgot to replace "|" with "+" in one spot. But that was part
of not-used code, so it actually does not matter.
So better get rid of this code part at all (no need to backport ;-).
Modified:
trunk/callgrind/sim.c
Modified: trunk/callgrind/sim.c
===================================================================
--- trunk/callgrind/sim.c 2009-01-26 22:56:14 UTC (rev 9080)
+++ trunk/callgrind/sim.c 2009-01-26 23:21:18 UTC (rev 9081)
@@ -680,102 +680,7 @@
}
}
-/* FIXME: A little tricky */
-#if 0
-static __inline__
-void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
-{
- int idx = (high_idx * c->assoc) + low_idx;
-
- c->use[idx].count ++;
- c->use[idx].mask |= use_mask;
-
- CLG_DEBUG(6," Hit [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",
- idx, c->loaded[idx].memline, c->loaded[idx].iaddr,
- use_mask, c->use[idx].mask, c->use[idx].count);
-}
-
-/* only used for I1, D1 */
-
-static __inline__
-CacheResult cacheuse_setref(cache_t2* c, UInt set_no, UWord tag)
-{
- int i, j, idx;
- UWord *set, tmp_tag;
- UInt use_mask;
-
- set = &(c->tags[set_no * c->assoc]);
- use_mask =
- c->line_start_mask[a & c->line_size_mask] &
- c->line_end_mask[(a+size-1) & c->line_size_mask];
-
- /* This loop is unrolled for just the first case, which is the most */
- /* common. We can't unroll any further because it would screw up */
- /* if we have a direct-mapped (1-way) cache. */
- if (tag == (set[0] & c->tag_mask)) {
- cacheuse_update(c, set_no, set[0] & ~c->tag_mask, use_mask);
- return L1_Hit;
- }
-
- /* If the tag is one other than the MRU, move it into the MRU spot */
- /* and shuffle the rest down. */
- for (i = 1; i < c->assoc; i++) {
- if (tag == (set[i] & c->tag_mask)) {
- tmp_tag = set[i];
- for (j = i; j > 0; j--) {
- set[j] = set[j - 1];
- }
- set[0] = tmp_tag;
-
- cacheuse_update(c, set_no, tmp_tag & ~c->tag_mask, use_mask);
- return L1_Hit;
- }
- }
-
- /* A miss; install this tag as MRU, shuffle rest down. */
- tmp_tag = set[L.assoc - 1] & ~c->tag_mask;
- for (j = c->assoc - 1; j > 0; j--) {
- set[j] = set[j - 1];
- }
- set[0] = tag | tmp_tag;
-
- cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
- use_mask, a & ~c->line_size_mask);
-
- return Miss;
-}
-
-
-static CacheResult cacheuse_ref(cache_t2* c, Addr a, UChar size)
-{
- UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
- UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a & c->tag_mask;
-
- /* Access entirely within line. */
- if (set1 == set2)
- return cacheuse_setref(c, set1, tag);
-
- /* Access straddles two lines. */
- /* Nb: this is a fast way of doing ((set1+1) % c->sets) */
- else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a & c->tag_mask;
-
- /* the call updates cache structures as side effect */
- CacheResult res1 = cacheuse_isMiss(c, set1, tag);
- CacheResult res2 = cacheuse_isMiss(c, set2, tag2);
- return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
-
- } else {
- VG_(printf)("addr: %x size: %u sets: %d %d", a, size, set1, set2);
- VG_(tool_panic)("item straddles more than two cache sets");
- }
- return Hit;
-}
-#endif
-
-
/* for I1/D1 caches */
#define CACHEUSE(L) \
\
|
|
From: <sv...@va...> - 2009-01-26 23:07:46
|
Author: njn
Date: 2009-01-26 21:51:35 +0000 (Mon, 26 Jan 2009)
New Revision: 9079
Log:
Comment out various m_mach pieces that aren't used.
Modified:
branches/DARWIN/coregrind/Makefile.am
branches/DARWIN/coregrind/m_mach/mach_basics.c
branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S
Modified: branches/DARWIN/coregrind/Makefile.am
===================================================================
--- branches/DARWIN/coregrind/Makefile.am 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
@@ -70,22 +70,39 @@
endif
# Mach RPC interface definitions
+# DDD: these ones aren't used...
+# clock.defs \
+# clock_priv.defs \
+# clock_reply.defs \
+# exc.defs \
+# host_priv.defs \
+# host_security.defs \
+# ledger.defs \
+# lock_set.defs \
+# mach_host.defs \
+# mach_port.defs \
+# notify.defs \
+# processor.defs \
+# processor_set.defs \
+#
+# mach_vm:
+# - mach_vm_protect is used in debugstub-darwin.c.
+# - mach_vm_region_recurse is used in aspacemgr-linux.c
+#
+# task:
+# - thread_create_running is used in debugstub-darwin.c
+# - semaphore_create is used in sema.c, syswrap-darwin.c
+# - semaphore_destroy is used in sema.c, syswrap-darwin.c
+#
+# thread_act:
+# - thread_get_state is used in scheduler.c
+# - thread_abort is used in debugstub-darwin.c
+#
+# vm_map:
+# - vm_deallocate is used in syswrap-darwin.c
if VGCONF_OS_IS_DARWIN
mach_defs = \
- clock.defs \
- clock_priv.defs \
- clock_reply.defs \
- exc.defs \
- host_priv.defs \
- host_security.defs \
- ledger.defs \
- lock_set.defs \
- mach_host.defs \
- mach_port.defs \
mach_vm.defs \
- notify.defs \
- processor.defs \
- processor_set.defs \
task.defs \
thread_act.defs \
vm_map.defs
@@ -307,6 +324,21 @@
# Note that the *User.c files are generated using 'mig' from $mach_defs
# above.
+ # DDD: these ones aren't generated (see above)...
+ # m_mach/clockUser.c \
+ # m_mach/clock_privUser.c \
+ # m_mach/clock_replyUser.c \
+ # m_mach/excUser.c \
+ # m_mach/host_privUser.c \
+ # m_mach/host_securityUser.c \
+ # m_mach/ledgerUser.c \
+ # m_mach/lock_setUser.c \
+ # m_mach/mach_hostUser.c \
+ # m_mach/mach_portUser.c \
+ # m_mach/notifyUser.c \
+ # m_mach/processorUser.c \
+ # m_mach/processor_setUser.c \
+ #
COREGRIND_DARWIN_SOURCE = \
m_aspacemgr/aspacemgr-linux.c \
m_debuginfo/readdwarf.c \
@@ -314,23 +346,10 @@
m_debuginfo/readstabs.c \
m_debuginfo/readmacho.c \
m_debugstub/debugstub-darwin.c \
- m_mach/clockUser.c \
- m_mach/clock_privUser.c \
- m_mach/clock_replyUser.c \
- m_mach/excUser.c \
- m_mach/host_privUser.c \
- m_mach/host_securityUser.c \
- m_mach/ledgerUser.c \
- m_mach/lock_setUser.c \
- m_mach/mach_hostUser.c \
- m_mach/mach_portUser.c \
m_mach/mach_vmUser.c \
- m_mach/notifyUser.c \
- m_mach/processorUser.c \
- m_mach/processor_setUser.c \
m_mach/taskUser.c \
- m_mach/thread_actUser.c \
- m_mach/vm_mapUser.c \
+ m_mach/thread_actUser.c \
+ m_mach/vm_mapUser.c \
m_mach/mach_basics.c \
m_mach/mach_msg.c \
m_initimg/initimg-darwin.c \
Modified: branches/DARWIN/coregrind/m_mach/mach_basics.c
===================================================================
--- branches/DARWIN/coregrind/m_mach/mach_basics.c 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/m_mach/mach_basics.c 2009-01-26 21:51:35 UTC (rev 9079)
@@ -37,7 +37,7 @@
#include <mach/machine/ndr_def.h>
/* From mach_traps-<arch>-darwin.S */
-extern mach_port_name_t host_self_trap(void);
+//extern mach_port_name_t host_self_trap(void);
extern mach_port_name_t thread_self_trap(void);
extern mach_port_t mach_reply_port(void);
@@ -46,10 +46,11 @@
mach_port_name_t mach_task_self_ = 0;
-mach_port_name_t mach_host_self(void)
-{
- return host_self_trap();
-}
+// DDD: doesn't get used...
+//mach_port_name_t mach_host_self(void)
+//{
+// return host_self_trap();
+//}
mach_port_name_t mach_thread_self(void)
Modified: branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S
===================================================================
--- branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S 2009-01-26 21:51:35 UTC (rev 9079)
@@ -39,15 +39,16 @@
syscall
ret
- // mach_port_name_t host_self_trap(void)
- .text
- .align 4
- .globl _host_self_trap
-_host_self_trap:
- movq $__NR_host_self_trap, %rax
- movq %rcx, %r10
- syscall
- ret
+// DDD: doesn't get used...
+// // mach_port_name_t host_self_trap(void)
+// .text
+// .align 4
+// .globl _host_self_trap
+//_host_self_trap:
+// movq $__NR_host_self_trap, %rax
+// movq %rcx, %r10
+// syscall
+// ret
// mach_port_name_t thread_self_trap(void)
.text
|
|
From: <sv...@va...> - 2009-01-26 22:56:20
|
Author: weidendo
Date: 2009-01-26 22:56:14 +0000 (Mon, 26 Jan 2009)
New Revision: 9080
Log:
Cachegrind/Callgrind: allow for cache sizes other than only powers of two
The number of sets, ie. number of cache lines divided by associativity,
and the cache line size still have to be powers of two.
This change is needed for default cache parameters used on some Intel
Core 2 and Atom processors.
Includes cachegrind manual update and explicit tests with 24KB D1/3MB L2
Reverts addition of 6MB warning to {cachegrind,callgrind}/tests/filter_stderr
Backporting to VALGRIND_3_4_BRANCH needs r8912
Added:
trunk/cachegrind/tests/notpower2.stderr.exp
trunk/cachegrind/tests/notpower2.vgtest
trunk/callgrind/tests/notpower2-hwpref.stderr.exp
trunk/callgrind/tests/notpower2-hwpref.vgtest
trunk/callgrind/tests/notpower2-use.stderr.exp
trunk/callgrind/tests/notpower2-use.vgtest
trunk/callgrind/tests/notpower2-wb.stderr.exp
trunk/callgrind/tests/notpower2-wb.vgtest
trunk/callgrind/tests/notpower2.stderr.exp
trunk/callgrind/tests/notpower2.vgtest
Modified:
trunk/cachegrind/cg-x86.c
trunk/cachegrind/cg_main.c
trunk/cachegrind/cg_sim.c
trunk/cachegrind/docs/cg-manual.xml
trunk/cachegrind/tests/Makefile.am
trunk/cachegrind/tests/filter_stderr
trunk/callgrind/sim.c
trunk/callgrind/tests/Makefile.am
trunk/callgrind/tests/filter_stderr
Modified: trunk/cachegrind/cg-x86.c
===================================================================
--- trunk/cachegrind/cg-x86.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg-x86.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -113,12 +113,7 @@
case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break;
case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;
- case 0x0e:
- /* Real D1 cache configuration is:
- D1c = (cache_t) { 24, 6, 64 }; */
- VG_(message)(Vg_DebugMsg, "warning: 24Kb D1 cache detected, treating as 16Kb");
- *D1c = (cache_t) { 16, 4, 64 };
- break;
+ case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break;
case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;
/* IA-64 info -- panic! */
@@ -149,12 +144,7 @@
case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break;
case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break;
case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break;
- case 0x48:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
- *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
- break;
+ case 0x48: *L2c = (cache_t) { 3072,12, 64 }; L2_found = True; break;
case 0x49:
if ((family == 15) && (model == 6))
/* On Xeon MP (family F, model 6), this is for L3 */
@@ -163,12 +153,7 @@
else
*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
break;
- case 0x4e:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
- *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
- break;
+ case 0x4e: *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; break;
/* These are sectored, whatever that means */
case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
Modified: trunk/cachegrind/cg_main.c
===================================================================
--- trunk/cachegrind/cg_main.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg_main.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -1158,21 +1158,15 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
+ "error: %s set count not a power of two; aborting.",
+ name);
VG_(exit)(1);
}
- if (-1 == VG_(log2)(cache->assoc)) {
- VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
Modified: trunk/cachegrind/cg_sim.c
===================================================================
--- trunk/cachegrind/cg_sim.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg_sim.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -44,7 +44,6 @@
Int line_size; /* bytes */
Int sets;
Int sets_min_1;
- Int assoc_bits;
Int line_size_bits;
Int tag_shift;
Char desc_line[128];
@@ -62,7 +61,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
@@ -111,8 +109,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
\
/* This loop is unrolled for just the first case, which is the most */\
/* common. We can't unroll any further because it would screw up */\
@@ -143,7 +140,7 @@
/* Second case: word straddles two lines. */ \
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
if (tag == set[0]) { \
goto block2; \
} \
@@ -162,7 +159,7 @@
set[0] = tag; \
is_miss = True; \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
tag2 = (a+size-1) >> L.tag_shift; \
if (tag2 == set[0]) { \
goto miss_treatment; \
Modified: trunk/cachegrind/docs/cg-manual.xml
===================================================================
--- trunk/cachegrind/docs/cg-manual.xml 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/docs/cg-manual.xml 2009-01-26 22:56:14 UTC (rev 9080)
@@ -142,7 +142,7 @@
</listitem>
<listitem>
- <para>Bit-selection hash function: the line(s) in the cache
+ <para>Bit-selection hash function: the set of line(s) in the cache
to which a memory block maps is chosen by the middle bits
M--(M+N-1) of the byte address, where:</para>
<itemizedlist>
@@ -150,15 +150,17 @@
<para>line size = 2^M bytes</para>
</listitem>
<listitem>
- <para>(cache size / line size) = 2^N bytes</para>
+ <para>(cache size / line size / associativity) = 2^N bytes</para>
</listitem>
</itemizedlist>
</listitem>
<listitem>
- <para>Inclusive L2 cache: the L2 cache replicates all the
- entries of the L1 cache. This is standard on Pentium chips,
- but AMD Opterons, Athlons and Durons
+ <para>Inclusive L2 cache: the L2 cache typically replicates all
+ the entries of the L1 caches, because fetching into L1 involves
+ fetching into L2 first (this does not guarantee strict inclusiveness,
+ as lines evicted from L2 still could reside in L1). This is
+ standard on Pentium chips, but AMD Opterons, Athlons and Durons
use an exclusive L2 cache that only holds
blocks evicted from L1. Ditto most modern VIA CPUs.</para>
</listitem>
@@ -176,7 +178,10 @@
(I1/D1/L2) of the cache from the command line using the
<computeroutput>--I1</computeroutput>,
<computeroutput>--D1</computeroutput> and
-<computeroutput>--L2</computeroutput> options.</para>
+<computeroutput>--L2</computeroutput> options.
+For cache parameters to be valid for simulation, the number
+of sets (with associativity being the number of cache lines in
+each set) has to be a power of two.</para>
<para>On PowerPC platforms
Cachegrind cannot automatically
@@ -227,10 +232,7 @@
<para>If you are interested in simulating a cache with different
properties, it is not particularly hard to write your own cache
simulator, or to modify the existing ones in
-<computeroutput>vg_cachesim_I1.c</computeroutput>,
-<computeroutput>vg_cachesim_D1.c</computeroutput>,
-<computeroutput>vg_cachesim_L2.c</computeroutput> and
-<computeroutput>vg_cachesim_gen.c</computeroutput>. We'd be
+<computeroutput>cg_sim.c</computeroutput>. We'd be
interested to hear from anyone who does.</para>
</sect2>
Modified: trunk/cachegrind/tests/Makefile.am
===================================================================
--- trunk/cachegrind/tests/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/tests/Makefile.am 2009-01-26 22:56:14 UTC (rev 9080)
@@ -15,6 +15,7 @@
chdir.vgtest chdir.stderr.exp \
clreq.vgtest clreq.stderr.exp \
dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \
+ notpower2.vgtest notpower2.stderr.exp \
wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp
check_PROGRAMS = \
Modified: trunk/cachegrind/tests/filter_stderr
===================================================================
--- trunk/cachegrind/tests/filter_stderr 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/tests/filter_stderr 2009-01-26 22:56:14 UTC (rev 9080)
@@ -17,5 +17,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Added: trunk/cachegrind/tests/notpower2.stderr.exp
===================================================================
--- trunk/cachegrind/tests/notpower2.stderr.exp (rev 0)
+++ trunk/cachegrind/tests/notpower2.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,17 @@
+
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/cachegrind/tests/notpower2.vgtest
===================================================================
--- trunk/cachegrind/tests/notpower2.vgtest (rev 0)
+++ trunk/cachegrind/tests/notpower2.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm cachegrind.out.*
Modified: trunk/callgrind/sim.c
===================================================================
--- trunk/callgrind/sim.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/sim.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -74,7 +74,6 @@
Bool sectored; /* prefetch nearside cacheline on read */
int sets;
int sets_min_1;
- int assoc_bits;
int line_size_bits;
int tag_shift;
UWord tag_mask;
@@ -195,7 +194,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
c->tag_mask = ~((1<<c->tag_shift)-1);
@@ -259,8 +257,7 @@
int i, j;
UWord *set;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -359,8 +356,7 @@
int i, j;
UWord *set, tmp_tag;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -407,7 +403,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = (a+size-1) >> c->tag_shift;
+ UWord tag2 = (a+size-1) & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
@@ -676,7 +672,7 @@
/* We use lower tag bits as offset pointers to cache use info.
* I.e. some cache parameters don't work.
*/
- if (c->tag_shift < c->assoc_bits) {
+ if ( (1<<c->tag_shift) < c->assoc) {
VG_(message)(Vg_DebugMsg,
"error: Use associativity < %d for cache use statistics!",
(1<<c->tag_shift) );
@@ -690,7 +686,7 @@
static __inline__
void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
{
- int idx = (high_idx << c->assoc_bits) | low_idx;
+ int idx = (high_idx * c->assoc) + low_idx;
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
@@ -709,8 +705,7 @@
UWord *set, tmp_tag;
UInt use_mask;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
use_mask =
c->line_start_mask[a & c->line_size_mask] &
c->line_end_mask[(a+size-1) & c->line_size_mask];
@@ -745,7 +740,7 @@
}
set[0] = tag | tmp_tag;
- cacheuse_L2_miss(c, (set_no << c->assoc_bits) | tmp_tag,
+ cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
use_mask, a & ~c->line_size_mask);
return Miss;
@@ -756,7 +751,7 @@
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a >> c->tag_shift;
+ UWord tag = a & c->tag_mask;
/* Access entirely within line. */
if (set1 == set2)
@@ -765,7 +760,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a >> c->tag_shift;
+ UWord tag2 = a & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cacheuse_isMiss(c, set1, tag);
@@ -800,8 +795,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask] & \
L.line_end_mask[(a+size-1) & L.line_size_mask]; \
\
@@ -809,7 +803,7 @@
/* common. We can't unroll any further because it would screw up */\
/* if we have a direct-mapped (1-way) cache. */\
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -826,7 +820,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -842,7 +836,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
return update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
\
@@ -850,10 +844,10 @@
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask]; \
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -868,7 +862,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -882,15 +876,15 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
miss1 = update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
tag2 = (a+size-1) & L.tag_mask; \
if (tag2 == (set[0] & L.tag_mask)) { \
- idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -905,7 +899,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -919,7 +913,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag2 | tmp_tag; \
- idx = (set2 << L.assoc_bits) | tmp_tag; \
+ idx = (set2 * L.assoc) + tmp_tag; \
miss2 = update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
@@ -984,7 +978,7 @@
CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
{
UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
- UWord* set = &(L2.tags[setNo << L2.assoc_bits]);
+ UWord* set = &(L2.tags[setNo * L2.assoc]);
UWord tag = memline & L2.tag_mask;
int i, j, idx;
@@ -993,7 +987,7 @@
CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
- idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1008,7 +1002,7 @@
set[j] = set[j - 1];
}
set[0] = tmp_tag;
- idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1024,7 +1018,7 @@
set[j] = set[j - 1];
}
set[0] = tag | tmp_tag;
- idx = (setNo << L2.assoc_bits) | tmp_tag;
+ idx = (setNo * L2.assoc) + tmp_tag;
l1_loaded->dep_use = &(L2.use[idx]);
update_L2_use(idx, memline);
@@ -1380,23 +1374,16 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
- VG_(exit)(1);
+ "error: %s set count not a power of two; aborting.",
+ name);
}
- if (-1 == VG_(log2)(cache->assoc)) {
+ if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
- if (-1 == VG_(log2)(cache->line_size)) {
- VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
name, cache->line_size);
VG_(exit)(1);
Modified: trunk/callgrind/tests/Makefile.am
===================================================================
--- trunk/callgrind/tests/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/tests/Makefile.am 2009-01-26 22:56:14 UTC (rev 9080)
@@ -11,6 +11,10 @@
simwork1.vgtest simwork1.stdout.exp simwork1.stderr.exp \
simwork2.vgtest simwork2.stdout.exp simwork2.stderr.exp \
simwork3.vgtest simwork3.stdout.exp simwork3.stderr.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ notpower2-wb.vgtest notpower2-wb.stderr.exp \
+ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
+ notpower2-use.vgtest notpower2-use.stderr.exp \
threads.vgtest threads.stderr.exp
check_PROGRAMS = clreq simwork threads
Modified: trunk/callgrind/tests/filter_stderr
===================================================================
--- trunk/callgrind/tests/filter_stderr 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/tests/filter_stderr 2009-01-26 22:56:14 UTC (rev 9080)
@@ -23,5 +23,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Added: trunk/callgrind/tests/notpower2-hwpref.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-hwpref.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-hwpref.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-hwpref.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-hwpref.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-hwpref.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-hwpref=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2-use.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-use.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-use.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-use.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-use.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-use.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --cacheuse=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2-wb.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-wb.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-wb.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-wb.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-wb.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-wb.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-wb=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm callgrind.out.*
|
|
From: Nicholas N. <n.n...@gm...> - 2009-01-26 22:43:29
|
On Tue, Jan 27, 2009 at 2:45 AM, Konstantin Serebryany <kon...@gm...> wrote: > > Did you ever think that two data race detectors (Helgrind and Drd) is > too much for the Valgrind project? > In fact, I think that two is too few. :) > > Please welcome ThreadSanitizer, yet another data race detector based > on Valgrind. > http://code.google.com/p/data-race-test/wiki/ThreadSanitizer > > I'd appreciate your feedback, How similar is it to Helgrind -- could it conceivably be folded into Helgrind? Nick |
|
From: <sv...@va...> - 2009-01-26 16:01:23
|
Author: sewardj
Date: 2009-01-26 16:01:19 +0000 (Mon, 26 Jan 2009)
New Revision: 9078
Log:
merge r8945:
Do not only intercept SIGILL during detection of the supported
instruction set on ppc but also SIGFPE.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c 2009-01-26 15:45:59 UTC (rev 9077)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c 2009-01-26 16:01:19 UTC (rev 9078)
@@ -35,7 +35,8 @@
#include "pub_core_libcbase.h"
#include "pub_core_machine.h"
#include "pub_core_cpuid.h"
-#include "pub_core_libcsignal.h" // for ppc32 messing with SIGILL
+#include "pub_core_libcsignal.h" // for ppc32 messing with SIGILL and SIGFPE
+#include "pub_core_debuglog.h"
#define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
@@ -333,8 +334,8 @@
#if defined(VGA_ppc32) || defined(VGA_ppc64)
#include <setjmp.h> // For jmp_buf
-static jmp_buf env_sigill;
-static void handler_sigill ( Int x ) { __builtin_longjmp(env_sigill,1); }
+static jmp_buf env_unsup_insn;
+static void handler_unsup_insn ( Int x ) { __builtin_longjmp(env_unsup_insn,1); }
#endif
Bool VG_(machine_get_hwcaps)( void )
@@ -393,38 +394,55 @@
return True;
#elif defined(VGA_ppc32)
- { /* ppc32 doesn't seem to have a sane way to find out what insn
- sets the CPU supports. So we have to arse around with
- SIGILLs. Yuck. */
+ {
+ /* Find out which subset of the ppc32 instruction set is supported by
+ verifying whether various ppc32 instructions generate a SIGILL
+ or a SIGFPE. An alternative approach is to check the AT_HWCAP and
+ AT_PLATFORM entries in the ELF auxiliary table -- see also
+ the_iifii.client_auxv in m_main.c.
+ */
vki_sigset_t saved_set, tmp_set;
- struct vki_sigaction saved_act, tmp_act;
+ struct vki_sigaction saved_sigill_act, tmp_sigill_act;
+ struct vki_sigaction saved_sigfpe_act, tmp_sigfpe_act;
volatile Bool have_F, have_V, have_FX, have_GX;
Int r;
VG_(sigemptyset)(&tmp_set);
VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+ VG_(sigaddset)(&tmp_set, VKI_SIGFPE);
r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
vg_assert(r == 0);
- r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_act);
+ r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act);
vg_assert(r == 0);
- tmp_act = saved_act;
+ tmp_sigill_act = saved_sigill_act;
+ r = VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act);
+ vg_assert(r == 0);
+ tmp_sigfpe_act = saved_sigfpe_act;
+
/* NODEFER: signal handler does not return (from the kernel's point of
view), hence if it is to successfully catch a signal more than once,
we need the NODEFER flag. */
- tmp_act.sa_flags &= ~VKI_SA_RESETHAND;
- tmp_act.sa_flags &= ~VKI_SA_SIGINFO;
- tmp_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigill_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.ksa_handler = handler_unsup_insn;
+ r = VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+ vg_assert(r == 0);
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigfpe_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
+ r = VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+ vg_assert(r == 0);
+
/* standard FP insns */
have_F = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_F = False;
} else {
__asm__ __volatile__(".long 0xFC000090"); /*fmr 0,0 */
@@ -432,10 +450,7 @@
/* Altivec insns */
have_V = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_V = False;
} else {
/* Unfortunately some older assemblers don't speak Altivec (or
@@ -448,10 +463,7 @@
/* General-Purpose optional (fsqrt, fsqrts) */
have_FX = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_FX = False;
} else {
__asm__ __volatile__(".long 0xFC00002C"); /*fsqrt 0,0 */
@@ -459,23 +471,20 @@
/* Graphics optional (stfiwx, fres, frsqrte, fsel) */
have_GX = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_GX = False;
} else {
__asm__ __volatile__(".long 0xFC000034"); /* frsqrte 0,0 */
}
- r = VG_(sigaction)(VKI_SIGILL, &saved_act, NULL);
+ r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
vg_assert(r == 0);
+ r = VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
+ vg_assert(r == 0);
r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
vg_assert(r == 0);
- /*
- VG_(printf)("F %d V %d FX %d GX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX);
- */
/* Make FP a prerequisite for VMX (bogusly so), and for FX and GX. */
if (have_V && !have_F)
have_V = False;
@@ -501,32 +510,45 @@
}
#elif defined(VGA_ppc64)
- { /* Same idiocy as for ppc32 - arse around with SIGILLs. */
+ {
+ /* Same instruction set detection algorithm as for ppc32. */
vki_sigset_t saved_set, tmp_set;
- struct vki_sigaction saved_act, tmp_act;
+ struct vki_sigaction saved_sigill_act, tmp_sigill_act;
+ struct vki_sigaction saved_sigfpe_act, tmp_sigfpe_act;
volatile Bool have_F, have_V, have_FX, have_GX;
VG_(sigemptyset)(&tmp_set);
VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+ VG_(sigaddset)(&tmp_set, VKI_SIGFPE);
VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
- VG_(sigaction)(VKI_SIGILL, NULL, &saved_act);
- tmp_act = saved_act;
+ VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act);
+ tmp_sigill_act = saved_sigill_act;
+ VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act);
+ tmp_sigfpe_act = saved_sigfpe_act;
+
+
/* NODEFER: signal handler does not return (from the kernel's point of
view), hence if it is to successfully catch a signal more than once,
we need the NODEFER flag. */
- tmp_act.sa_flags &= ~VKI_SA_RESETHAND;
- tmp_act.sa_flags &= ~VKI_SA_SIGINFO;
- tmp_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigill_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.ksa_handler = handler_unsup_insn;
+ VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigfpe_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
+ VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+
/* standard FP insns */
have_F = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_F = False;
} else {
__asm__ __volatile__("fmr 0,0");
@@ -534,9 +556,7 @@
/* Altivec insns */
have_V = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_V = False;
} else {
__asm__ __volatile__(".long 0x10000484"); /*vor 0,0,0*/
@@ -544,9 +564,7 @@
/* General-Purpose optional (fsqrt, fsqrts) */
have_FX = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_FX = False;
} else {
__asm__ __volatile__(".long 0xFC00002C"); /*fsqrt 0,0*/
@@ -554,21 +572,17 @@
/* Graphics optional (stfiwx, fres, frsqrte, fsel) */
have_GX = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_GX = False;
} else {
__asm__ __volatile__(".long 0xFC000034"); /*frsqrte 0,0*/
}
- VG_(sigaction)(VKI_SIGILL, &saved_act, NULL);
+ VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
+ VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
- /*
- if (0)
- VG_(printf)("F %d V %d FX %d GX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX);
- */
/* on ppc64, if we don't even have FP, just give up. */
if (!have_F)
return False;
|
|
From: <sv...@va...> - 2009-01-26 15:54:09
|
Author: sewardj
Date: 2009-01-26 15:54:03 +0000 (Mon, 26 Jan 2009)
New Revision: 1883
Log:
merge r1882: Handle redundant REX.W on PUNPCKHgg. #173751.
Modified:
branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c 2009-01-24 10:34:19 UTC (rev 1882)
+++ branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c 2009-01-26 15:54:03 UTC (rev 1883)
@@ -6594,7 +6594,8 @@
case 0x68:
case 0x69:
case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
- if (sz != 4)
+ if (sz != 4
+ && /*ignore redundant REX.W*/!(sz==8 && haveNo66noF2noF3(pfx)))
goto mmx_decode_failure;
delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "punpckh", True );
break;
|
|
From: Konstantin S. <kon...@gm...> - 2009-01-26 15:46:02
|
Hello Valgrind developers, Did you ever think that two data race detectors (Helgrind and Drd) is too much for the Valgrind project? In fact, I think that two is too few. :) Please welcome ThreadSanitizer, yet another data race detector based on Valgrind. http://code.google.com/p/data-race-test/wiki/ThreadSanitizer I'd appreciate your feedback, Thanks, --kcc |
|
From: <sv...@va...> - 2009-01-26 15:13:47
|
Author: sewardj
Date: 2009-01-26 15:13:44 +0000 (Mon, 26 Jan 2009)
New Revision: 9076
Log:
merge r9063 Helgrind: Initialise laog and laog__exposition (properly).
Modified:
branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c
Modified: branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c 2009-01-26 15:08:46 UTC (rev 9075)
+++ branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c 2009-01-26 15:13:44 UTC (rev 9076)
@@ -2849,6 +2849,21 @@
/* end EXPOSITION ONLY */
+__attribute__((noinline))
+static void laog__init ( void )
+{
+ tl_assert(!laog);
+ tl_assert(!laog_exposition);
+
+ laog = VG_(newFM)( HG_(zalloc), "hg.laog__init.1",
+ HG_(free), NULL/*unboxedcmp*/ );
+
+ laog_exposition = VG_(newFM)( HG_(zalloc), "hg.laog__init.2", HG_(free),
+ cmp_LAOGLinkExposition );
+ tl_assert(laog);
+ tl_assert(laog_exposition);
+}
+
static void laog__show ( Char* who ) {
Word i, ws_size;
UWord* ws_words;
@@ -3015,8 +3030,8 @@
UWord* ws_words;
Lock* me;
LAOGLinks* links;
- if ( !laog )
- return; /* nothing much we can do */
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
VG_(initIterFM)( laog );
me = NULL;
links = NULL;
@@ -3128,12 +3143,8 @@
if (HG_(elemWS)( univ_lsets, thr->locksetA, (Word)lk ))
return;
- if (!laog)
- laog = VG_(newFM)( HG_(zalloc), "hg.lptal.1",
- HG_(free), NULL/*unboxedcmp*/ );
- if (!laog_exposition)
- laog_exposition = VG_(newFM)( HG_(zalloc), "hg.lptal.2", HG_(free),
- cmp_LAOGLinkExposition );
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
/* First, the check. Complain if there is any path in laog from lk
to any of the locks already held by thr, since if any such path
@@ -3206,6 +3217,9 @@
Word preds_size, succs_size, i, j;
UWord *preds_words, *succs_words;
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
+
preds = laog__preds( lk );
succs = laog__succs( lk );
@@ -3237,11 +3251,8 @@
// Word i, ws_size;
// UWord* ws_words;
//
-// if (!laog)
-// laog = VG_(newFM)( HG_(zalloc), "hg.lhld.1", HG_(free), NULL/*unboxedcmp*/ );
-// if (!laog_exposition)
-// laog_exposition = VG_(newFM)( HG_(zalloc), "hg.lhld.2", HG_(free),
-// cmp_LAOGLinkExposition );
+// if (UNLIKELY(!laog || !laog_exposition))
+// laog__init();
//
// HG_(getPayloadWS)( &ws_words, &ws_size, univ_lsets, locksToDelete );
// for (i = 0; i < ws_size; i++)
|
|
From: <sv...@va...> - 2009-01-26 15:08:50
|
Author: sewardj
Date: 2009-01-26 15:08:46 +0000 (Mon, 26 Jan 2009)
New Revision: 9075
Log:
merge m9058:
Handle a couple of artefacts produced by icc11:
DW_TAG_reference_type that doesn't have a size, and DW_FORM_ref_addr
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:05:25 UTC (rev 9074)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:08:46 UTC (rev 9075)
@@ -418,6 +418,9 @@
/* Where is .debug_line? */
UChar* debug_line_img;
UWord debug_line_sz;
+ /* Where is .debug_info? */
+ UChar* debug_info_img;
+ UWord debug_info_sz;
/* --- Needed so we can add stuff to the string table. --- */
struct _DebugInfo* di;
/* --- a cache for set_abbv_Cursor --- */
@@ -901,7 +904,8 @@
/* address size. If this isn't equal to the host word size, just
give up. This makes it safe to assume elsewhere that
- DW_FORM_addr can be treated as a host word. */
+ DW_FORM_addr and DW_FORM_ref_addr can be treated as a host
+ word. */
address_size = get_UChar( c );
if (address_size != sizeof(void*))
cc->barf( "parse_CU_Header: invalid address_size" );
@@ -1083,12 +1087,43 @@
*ctsSzB = sizeof(UWord);
TRACE_D3("0x%lx", (UWord)*cts);
break;
+
+ case DW_FORM_ref_addr:
+ /* We make the same word-size assumption as DW_FORM_addr. */
+ /* What does this really mean? From D3 Sec 7.5.4,
+ description of "reference", it would appear to reference
+ some other DIE, by specifying the offset from the
+ beginning of a .debug_info section. The D3 spec mentions
+ that this might be in some other shared object and
+ executable. But I don't see how the name of the other
+ object/exe is specified.
+
+ At least for the DW_FORM_ref_addrs created by icc11, the
+ references seem to be within the same object/executable.
+ So for the moment we merely range-check, to see that they
+ actually do specify a plausible offset within this
+ object's .debug_info, and return the value unchanged.
+ */
+ *cts = (ULong)(UWord)get_UWord(c);
+ *ctsSzB = sizeof(UWord);
+ TRACE_D3("0x%lx", (UWord)*cts);
+ if (0) VG_(printf)("DW_FORM_ref_addr 0x%lx\n", (UWord)*cts);
+ if (/* the following 2 are surely impossible, but ... */
+ cc->debug_info_img == NULL || cc->debug_info_sz == 0
+ || *cts >= (ULong)cc->debug_info_sz) {
+ /* Hmm. Offset is nonsensical for this object's .debug_info
+ section. Be safe and reject it. */
+ cc->barf("get_Form_contents: DW_FORM_ref_addr points "
+ "outside .debug_info");
+ }
+ break;
+
case DW_FORM_strp: {
/* this is an offset into .debug_str */
UChar* str;
UWord uw = (UWord)get_Dwarfish_UWord( c, cc->is_dw64 );
if (cc->debug_str_img == NULL || uw >= cc->debug_str_sz)
- cc->barf("read_and_show_Form: DW_FORM_strp "
+ cc->barf("get_Form_contents: DW_FORM_strp "
"points outside .debug_str");
/* FIXME: check the entire string lies inside debug_str,
not just the first byte of it. */
@@ -1149,8 +1184,9 @@
break;
}
default:
- VG_(printf)("get_Form_contents: unhandled %d (%s)\n",
- form, ML_(pp_DW_FORM)(form));
+ VG_(printf)(
+ "get_Form_contents: unhandled %d (%s) at <%lx>\n",
+ form, ML_(pp_DW_FORM)(form), get_position_of_Cursor(c));
c->barf("get_Form_contents: unhandled DW_FORM");
}
}
@@ -2184,14 +2220,13 @@
typeE.Te.TyPorR.typeR = D3_FAKEVOID_CUOFF;
typeE.Te.TyPorR.isPtr = dtag == DW_TAG_pointer_type
|| dtag == DW_TAG_ptr_to_member_type;
- /* Pointer types don't *have* to specify their size, in which
- case we assume it's a machine word. But if they do specify
- it, it must be a machine word :-) This probably assumes that
- the word size of the Dwarf3 we're reading is the same size as
- that on the machine. gcc appears to give a size whereas icc9
- doesn't. */
- if (typeE.Te.TyPorR.isPtr)
- typeE.Te.TyPorR.szB = sizeof(Word);
+ /* These three type kinds don't *have* to specify their size, in
+ which case we assume it's a machine word. But if they do
+ specify it, it must be a machine word :-) This probably
+ assumes that the word size of the Dwarf3 we're reading is the
+ same size as that on the machine. gcc appears to give a size
+ whereas icc9 doesn't. */
+ typeE.Te.TyPorR.szB = sizeof(UWord);
while (True) {
DW_AT attr = (DW_AT) get_ULEB128( c_abbv );
DW_FORM form = (DW_FORM)get_ULEB128( c_abbv );
@@ -2206,7 +2241,7 @@
}
}
/* Do we have something that looks sane? */
- if (typeE.Te.TyPorR.szB != sizeof(Word))
+ if (typeE.Te.TyPorR.szB != sizeof(UWord))
goto bad_DIE;
else
goto acquire_Type;
@@ -3437,6 +3472,8 @@
cc.debug_loc_sz = debug_loc_sz;
cc.debug_line_img = debug_line_img;
cc.debug_line_sz = debug_line_sz;
+ cc.debug_info_img = debug_info_img;
+ cc.debug_info_sz = debug_info_sz;
cc.cu_start_offset = cu_start_offset;
cc.di = di;
/* The CU's svma can be deduced by looking at the AT_low_pc
|
|
From: <sv...@va...> - 2009-01-26 15:05:31
|
Author: sewardj
Date: 2009-01-26 15:05:25 +0000 (Mon, 26 Jan 2009)
New Revision: 9074
Log:
merge r9057:
Handle a couple of artefacts generated by gcc-4.4:
DW_OP_reg{0..31} and DW_OP_const1s.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 15:02:20 UTC (rev 9073)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 15:05:25 UTC (rev 9074)
@@ -2555,6 +2555,16 @@
VG_(printf)("DW_OP_breg%d: %ld", reg, sw);
break;
+ case DW_OP_reg0 ... DW_OP_reg31:
+ /* push: reg */
+ reg = (Int)opcode - (Int)DW_OP_reg0;
+ vg_assert(reg >= 0 && reg <= 31);
+ ix = ML_(CfiExpr_DwReg)( dst, reg );
+ PUSH(ix);
+ if (ddump_frames)
+ VG_(printf)("DW_OP_reg%d", reg);
+ break;
+
case DW_OP_plus_uconst:
uw = read_leb128U( &expr );
PUSH( ML_(CfiExpr_Const)( dst, uw ) );
@@ -2574,6 +2584,15 @@
VG_(printf)("DW_OP_const4s: %ld", sw);
break;
+ case DW_OP_const1s:
+ /* push: 8-bit signed immediate */
+ sw = read_le_s_encoded_literal( expr, 1 );
+ expr += 1;
+ PUSH( ML_(CfiExpr_Const)( dst, (UWord)sw ) );
+ if (ddump_frames)
+ VG_(printf)("DW_OP_const1s: %ld", sw);
+ break;
+
case DW_OP_minus:
op = Cop_Sub; opname = "minus"; goto binop;
case DW_OP_plus:
|
|
From: <sv...@va...> - 2009-01-26 15:02:23
|
Author: sewardj
Date: 2009-01-26 15:02:20 +0000 (Mon, 26 Jan 2009)
New Revision: 9073
Log:
merge r9055: Accept 'enum' type DIEs that do not have any names
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:00:15 UTC (rev 9072)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:02:20 UTC (rev 9073)
@@ -2236,9 +2236,14 @@
typeE.Te.TyEnum.szB = cts;
}
}
+
+ if (!typeE.Te.TyEnum.name)
+ typeE.Te.TyEnum.name
+ = ML_(dinfo_strdup)( "di.readdwarf3.pTD.enum_type.3",
+ "<anon_enum_type>" );
+
/* Do we have something that looks sane? */
- if (typeE.Te.TyEnum.szB == 0 /* we must know the size */
- /* But the name can be present, or not */)
+ if (typeE.Te.TyEnum.szB == 0 /* we must know the size */)
goto bad_DIE;
/* On't stack! */
typestack_push( cc, parser, td3, &typeE, level );
|
|
From: <sv...@va...> - 2009-01-26 15:00:28
|
Author: sewardj
Date: 2009-01-26 15:00:15 +0000 (Mon, 26 Jan 2009)
New Revision: 9072
Log:
merge r9051:
VG_(apply_StackTrace): following r8818, we should regard an entry
of -1 as denoting the logical end of the stack.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_stacktrace.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_stacktrace.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_stacktrace.c 2009-01-26 14:57:27 UTC (rev 9071)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_stacktrace.c 2009-01-26 15:00:15 UTC (rev 9072)
@@ -561,7 +561,13 @@
action(i, ip);
i++;
- } while (i < n_ips && ips[i] != 0 && !main_done);
+ // re 'while' condition: stop if we hit a zero value (the traditional
+ // end-of-stack marker) or a ~0 value. The latter because r8818
+ // (in this file) changes the meaning of entries [1] and above in a
+ // stack trace, by subtracting 1 from them. Hence stacks that used
+ // to end with a zero value now end in -1 and so we must detect
+ // that too.
+ } while (i < n_ips && ips[i] != 0 && ips[i] != ~(Addr)0 && !main_done);
#undef MYBUF_LEN
}
|
|
From: <sv...@va...> - 2009-01-26 14:57:38
|
Author: sewardj
Date: 2009-01-26 14:57:27 +0000 (Mon, 26 Jan 2009)
New Revision: 9071
Log:
merge r9050 ML_(evaluate_trivial_GX): handle the case
(DW_OP_addr: DW_OP_plus_uconst: ULEB < 128)
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c 2009-01-26 14:53:38 UTC (rev 9070)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c 2009-01-26 14:57:27 UTC (rev 9071)
@@ -736,7 +736,10 @@
* any of the subexpressions do not produce a manifest constant
* there's more than one subexpression, all of which successfully
evaluate to a constant, but they don't all produce the same constant.
- */
+ JRS 23Jan09: the special-casing in this function is a nasty kludge.
+ Really it ought to be pulled out and turned into a general
+ constant- expression evaluator.
+*/
GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di )
{
GXResult res;
@@ -747,7 +750,7 @@
MaybeULong *mul, *mul2;
HChar* badness = NULL;
- UChar* p = &gx->payload[0];
+ UChar* p = &gx->payload[0]; /* must remain unsigned */
XArray* results = VG_(newXA)( ML_(dinfo_zalloc), "di.d3basics.etG.1",
ML_(dinfo_free),
sizeof(MaybeULong) );
@@ -778,18 +781,41 @@
/* Peer at this particular subexpression, to see if it's
obviously a constant. */
if (nbytes == 1 + sizeof(Addr) && *p == DW_OP_addr) {
+ /* DW_OP_addr a */
Addr a = *(Addr*)(p+1);
if (bias_address(&a, di)) {
thisResult.b = True;
thisResult.ul = (ULong)a;
+ } else {
+ if (!badness)
+ badness = "trivial GExpr denotes constant address "
+ "in unknown section (1)";
}
- else if (!badness) {
- badness = "trivial GExpr denotes constant address in unknown section";
+ }
+ else
+ if (nbytes == 1 + sizeof(Addr) + 1 + 1
+ /* 11 byte block: 3 c0 b6 2b 0 0 0 0 0 23 4
+ (DW_OP_addr: 2bb6c0; DW_OP_plus_uconst: 4)
+ This is really a nasty kludge - only matches if the
+ trailing ULEB denotes a number in the range 0 .. 127
+ inclusive. */
+ && p[0] == DW_OP_addr
+ && p[1 + sizeof(Addr)] == DW_OP_plus_uconst
+ && p[1 + sizeof(Addr) + 1] < 0x80 /*1-byte ULEB*/) {
+ Addr a = *(Addr*)&p[1];
+ if (bias_address(&a, di)) {
+ thisResult.b = True;
+ thisResult.ul = (ULong)a + (ULong)p[1 + sizeof(Addr) + 1];
+ } else {
+ if (!badness)
+ badness = "trivial GExpr denotes constant address "
+ "in unknown section (2)";
}
}
- else if (nbytes == 2 + sizeof(Addr)
- && *p == DW_OP_addr
- && *(p + 1 + sizeof(Addr)) == DW_OP_GNU_push_tls_address) {
+ else
+ if (nbytes == 2 + sizeof(Addr)
+ && *p == DW_OP_addr
+ && *(p + 1 + sizeof(Addr)) == DW_OP_GNU_push_tls_address) {
if (!badness)
badness = "trivial GExpr is DW_OP_addr plus trailing junk";
}
|
|
From: <sv...@va...> - 2009-01-26 14:53:41
|
Author: sewardj
Date: 2009-01-26 14:53:38 +0000 (Mon, 26 Jan 2009)
New Revision: 9070
Log:
merge r9049:
Handle the case where a Compilation Unit (CU) (or, really, the CU
and its associated DIEs) occupies less space than stated in the
CU's header.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 14:48:43 UTC (rev 9069)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 14:53:38 UTC (rev 9070)
@@ -387,7 +387,12 @@
Bool is_dw64;
/* Which DWARF version ? (2 or 3) */
UShort version;
- /* Length of this Compilation Unit, excluding its Header */
+ /* Length of this Compilation Unit, as stated in the
+ .unit_length :: InitialLength field of the CU Header.
+ However, this size (as specified by the D3 spec) does not
+ include the size of the .unit_length field itself, which is
+ either 4 or 12 bytes (32-bit or 64-bit Dwarf3). That value
+ can be obtained through the expression ".is_dw64 ? 12 : 4". */
ULong unit_length;
/* Offset of start of this unit in .debug_info */
UWord cu_start_offset;
@@ -3368,12 +3373,30 @@
while (True) {
UWord cu_start_offset, cu_offset_now;
CUConst cc;
+ /* It may be that the stated size of this CU is larger than the
+ amount of stuff actually in it. icc9 seems to generate CUs
+ thusly. We use these variables to figure out if this is
+ indeed the case, and if so how many bytes we need to skip to
+ get to the start of the next CU. Not skipping those bytes
+ causes us to misidentify the start of the next CU, and it all
+ goes badly wrong after that (not surprisingly). */
+ UWord cu_size_including_IniLen, cu_amount_used;
/* It seems icc9 finishes the DIE info before debug_info_sz
bytes have been used up. So be flexible, and declare the
sequence complete if there is not enough remaining bytes to
hold even the smallest conceivable CU header. (11 bytes I
reckon). */
+ /* JRS 23Jan09: I suspect this is no longer necessary now that
+ the code below contains a 'while (cu_amount_used <
+ cu_size_including_IniLen ...' style loop, which skips over
+ any leftover bytes at the end of a CU in the case where the
+ CU's stated size is larger than its actual size (as
+ determined by reading all its DIEs). However, for prudence,
+ I'll leave the following test in place. I can't see that a
+ CU header can be smaller than 11 bytes, so I don't think
+ there's any harm possible through the test -- it just adds
+ robustness. */
Word avail = get_remaining_length_Cursor( &info );
if (avail < 11) {
if (avail > 0)
@@ -3447,10 +3470,36 @@
&info, td3, &cc, 0 );
cu_offset_now = get_position_of_Cursor( &info );
+
+ if (0) VG_(printf)("Travelled: %lu size %llu\n",
+ cu_offset_now - cc.cu_start_offset,
+ cc.unit_length + (cc.is_dw64 ? 12 : 4));
+
+ /* How big the CU claims it is .. */
+ cu_size_including_IniLen = cc.unit_length + (cc.is_dw64 ? 12 : 4);
+ /* .. vs how big we have found it to be */
+ cu_amount_used = cu_offset_now - cc.cu_start_offset;
+
if (1) TRACE_D3("offset now %ld, d-i-size %ld\n",
cu_offset_now, debug_info_sz);
if (cu_offset_now > debug_info_sz)
barf("toplevel DIEs beyond end of CU");
+
+ /* If the CU is bigger than it claims to be, we've got a serious
+ problem. */
+ if (cu_amount_used > cu_size_including_IniLen)
+ barf("CU's actual size appears to be larger than it claims it is");
+
+ /* If the CU is smaller than it claims to be, we need to skip some
+ bytes. Loop updates cu_offset_new and cu_amount_used. */
+ while (cu_amount_used < cu_size_including_IniLen
+ && get_remaining_length_Cursor( &info ) > 0) {
+ if (0) VG_(printf)("SKIP\n");
+ (void)get_UChar( &info );
+ cu_offset_now = get_position_of_Cursor( &info );
+ cu_amount_used = cu_offset_now - cc.cu_start_offset;
+ }
+
if (cu_offset_now == debug_info_sz)
break;
|
|
From: <sv...@va...> - 2009-01-26 14:48:49
|
Author: sewardj
Date: 2009-01-26 14:48:43 +0000 (Mon, 26 Jan 2009)
New Revision: 9069
Log:
merge r9028: Helgrind: Suppress any error at all that occurs in libpthread
Modified:
branches/VALGRIND_3_4_BRANCH/glibc-2.34567-NPTL-helgrind.supp
Modified: branches/VALGRIND_3_4_BRANCH/glibc-2.34567-NPTL-helgrind.supp
===================================================================
--- branches/VALGRIND_3_4_BRANCH/glibc-2.34567-NPTL-helgrind.supp 2009-01-26 14:42:36 UTC (rev 9068)
+++ branches/VALGRIND_3_4_BRANCH/glibc-2.34567-NPTL-helgrind.supp 2009-01-26 14:48:43 UTC (rev 9069)
@@ -1,4 +1,7 @@
+# FIXME 22 Jan 09: helgrind-glibc2X-005 overlaps with a lot of
+# other stuff. They should be removed.
+
##----------------------------------------------------------------------##
# Suppressions for the Helgrind tool when using
# a glibc-2.{3,4,5,6,7,8,9} system
@@ -41,7 +44,6 @@
helgrind-glibc2X-005
Helgrind:Race
obj:/lib*/libpthread-2.*so*
- obj:/lib*/libpthread-2.*so*
}
# helgrind-glibc2X-006 was merged into helgrind-glibc2X-005
|
|
From: <sv...@va...> - 2009-01-26 14:42:41
|
Author: sewardj
Date: 2009-01-26 14:42:36 +0000 (Mon, 26 Jan 2009)
New Revision: 9068
Log:
merge r9029 Minor tidyings: (in debuginfo reader)
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c 2009-01-26 13:02:16 UTC (rev 9067)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c 2009-01-26 14:42:36 UTC (rev 9068)
@@ -1036,7 +1036,17 @@
(di->bss_present
&& di->bss_size > 0
&& di->bss_avma <= ptr
- && ptr < di->bss_avma + di->bss_size);
+ && ptr < di->bss_avma + di->bss_size)
+ ||
+ (di->sbss_present
+ && di->sbss_size > 0
+ && di->sbss_avma <= ptr
+ && ptr < di->sbss_avma + di->sbss_size)
+ ||
+ (di->rodata_present
+ && di->rodata_size > 0
+ && di->rodata_avma <= ptr
+ && ptr < di->rodata_avma + di->rodata_size);
}
if (!inRange) continue;
@@ -1064,6 +1074,7 @@
DebugInfo* di;
for (di = debugInfo_list; di != NULL; di = di->next) {
if (di->text_present
+ && di->text_size > 0
&& di->text_avma <= ptr
&& ptr < di->text_avma + di->text_size) {
lno = ML_(search_one_loctab) ( di, ptr );
@@ -1250,6 +1261,7 @@
expect this to produce a result. */
for (di = debugInfo_list; di != NULL; di = di->next) {
if (di->text_present
+ && di->text_size > 0
&& di->text_avma <= a
&& a < di->text_avma + di->text_size) {
VG_(strncpy_safely)(buf, di->filename, nbuf);
@@ -1288,6 +1300,7 @@
DebugInfo* di;
for (di = debugInfo_list; di != NULL; di = di->next) {
if (di->text_present
+ && di->text_size > 0
&& di->text_avma <= a
&& a < di->text_avma + di->text_size) {
return di;
@@ -2939,6 +2952,7 @@
case Vg_SectGOT: return "GOT";
case Vg_SectPLT: return "PLT";
case Vg_SectOPD: return "OPD";
+ case Vg_SectGOTPLT: return "GOTPLT";
default: vg_assert(0);
}
}
@@ -2989,6 +3003,12 @@
res = Vg_SectBSS;
break;
}
+ if (di->sbss_present
+ && di->sbss_size > 0
+ && a >= di->sbss_avma && a < di->sbss_avma + di->sbss_size) {
+ res = Vg_SectBSS;
+ break;
+ }
if (di->plt_present
&& di->plt_size > 0
&& a >= di->plt_avma && a < di->plt_avma + di->plt_size) {
|
|
From: Tom H. <to...@co...> - 2009-01-26 14:28:59
|
Julian Seward wrote: > I'm doing some merging of stuff into 3_4_BRANCH. Before I commit > every merge I like to do svn diff -rHEAD to see what I'm about > to commit. In a trunk tree that works as expected. However, in a > 3_4_BRANCH tree I get a load of other output too, which I don't > understand. > > The unexpected output is shown below. Is it significant? > What does it mean? And how can I get rid of it? The svn:mergeinfo property is used by recent versions of subversion to track what merges have been done - it means that if you merge a branch a second time it knows which edits have already been merged and doesn't need to do them again. It may well be entirely normal for it to be deleted sometimes during a merge - I don't really have enough experience with it to know. Or it might be some side effect of some of us using clients which support it and some of us not doing so. Tom -- Tom Hughes (to...@co...) http://www.compton.nu/ |
|
From: Julian S. <js...@ac...> - 2009-01-26 14:03:57
|
I'm doing some merging of stuff into 3_4_BRANCH. Before I commit every merge I like to do svn diff -rHEAD to see what I'm about to commit. In a trunk tree that works as expected. However, in a 3_4_BRANCH tree I get a load of other output too, which I don't understand. The unexpected output is shown below. Is it significant? What does it mean? And how can I get rid of it? J sewardj@phoenix:~/Vg34BRANCH/branch34$ svn diff -rHEAD Property changes on: coregrind/m_wordfm.c ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: . ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: glibc-2.X.supp.in ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: exp-ptrcheck/h_intercepts.c ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: memcheck/tests/malloc_free_fill.stderr.exp ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: include/pub_tool_wordfm.h ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/boost_thread.stderr.exp ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/pth_cond_race3.vgtest ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/boost_thread.cpp ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/tc09_bad_unlock.stderr.exp-glibc2.8 ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/circular_buffer.stderr.exp-with-atomic-builtins ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/pth_cond_race3.stderr.exp ___________________________________________________________________ Deleted: svn:mergeinfo Property changes on: drd/tests/boost_thread.vgtest ___________________________________________________________________ Deleted: svn:mergeinfo |
|
From: <sv...@va...> - 2009-01-26 13:02:25
|
Author: sewardj
Date: 2009-01-26 13:02:16 +0000 (Mon, 26 Jan 2009)
New Revision: 9067
Log:
Merge from the trunk, a bunch of changes to fix ELF segment mapping
and bias computation problems:
9020 Improve detection of where ELF sections have been mapped
9021 Don't assume that all global variables are in the data section
9022 Removed unused round_Addr_upwards function.
9024 Handle the rodata and sbss sections
9025 Accept zero size text segments.
9026 Don't worry about an unmapped, zero sized, bss segment.
9053 Fix aix5 build breakage following r9021.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_d3basics.h
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_storage.h
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readelf.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readxcoff.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/storage.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/tytypes.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/d3basics.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -35,6 +35,7 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_debuginfo.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
#include "pub_core_options.h"
@@ -45,6 +46,7 @@
#include "priv_misc.h"
#include "priv_d3basics.h" /* self */
+#include "priv_storage.h"
HChar* ML_(pp_DW_children) ( DW_children hashch )
{
@@ -372,7 +374,6 @@
return (Long)val;
}
-
/* FIXME: duplicates logic in readdwarf.c: copy_convert_CfiExpr_tree
and {FP,SP}_REG decls */
static Bool get_Dwarf_Reg( /*OUT*/Addr* a, Word regno, RegSummary* regs )
@@ -400,12 +401,52 @@
return False;
}
+/* Convert a stated address to an actual address */
+static Bool bias_address( Addr* a, const DebugInfo* di )
+{
+ if (di->text_present
+ && di->text_size > 0
+ && *a >= di->text_svma && *a < di->text_svma + di->text_size) {
+ *a += di->text_bias;
+ }
+ else if (di->data_present
+ && di->data_size > 0
+ && *a >= di->data_svma && *a < di->data_svma + di->data_size) {
+ *a += di->data_bias;
+ }
+ else if (di->sdata_present
+ && di->sdata_size > 0
+ && *a >= di->sdata_svma && *a < di->sdata_svma + di->sdata_size) {
+ *a += di->sdata_bias;
+ }
+ else if (di->rodata_present
+ && di->rodata_size > 0
+ && *a >= di->rodata_svma && *a < di->rodata_svma + di->rodata_size) {
+ *a += di->rodata_bias;
+ }
+ else if (di->bss_present
+ && di->bss_size > 0
+ && *a >= di->bss_svma && *a < di->bss_svma + di->bss_size) {
+ *a += di->bss_bias;
+ }
+ else if (di->sbss_present
+ && di->sbss_size > 0
+ && *a >= di->sbss_svma && *a < di->sbss_svma + di->sbss_size) {
+ *a += di->sbss_bias;
+ }
+ else {
+ return False;
+ }
+ return True;
+}
+
+
/* Evaluate a standard DWARF3 expression. See detailed description in
priv_d3basics.h. */
GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB,
GExpr* fbGX, RegSummary* regs,
- Addr data_bias,
+ const DebugInfo* di,
Bool push_initial_zero )
{
# define N_EXPR_STACK 20
@@ -508,14 +549,21 @@
horrible prelinking-induced complications as described
in "Comment_Regarding_DWARF3_Text_Biasing" in
readdwarf3.c? Currently I don't know. */
- PUSH( *(Addr*)expr + data_bias );
- expr += sizeof(Addr);
+ a1 = *(Addr*)expr;
+ if (bias_address(&a1, di)) {
+ PUSH( a1 );
+ expr += sizeof(Addr);
+ }
+ else {
+ FAIL("evaluate_Dwarf3_Expr: DW_OP_addr with address "
+ "in unknown section");
+ }
break;
case DW_OP_fbreg:
if (!fbGX)
FAIL("evaluate_Dwarf3_Expr: DW_OP_fbreg with "
"no expr for fbreg present");
- fbval = ML_(evaluate_GX)(fbGX, NULL, regs, data_bias);
+ fbval = ML_(evaluate_GX)(fbGX, NULL, regs, di);
/* Convert fbval into something we can use. If we got a
Value, no problem. However, as per D3 spec sec 3.3.5
(Low Level Information) sec 2, we could also get a
@@ -621,7 +669,7 @@
/* Evaluate a so-called Guarded (DWARF3) expression. See detailed
description in priv_d3basics.h. */
GXResult ML_(evaluate_GX)( GExpr* gx, GExpr* fbGX,
- RegSummary* regs, Addr data_bias )
+ RegSummary* regs, const DebugInfo* di )
{
GXResult res;
Addr aMin, aMax;
@@ -655,7 +703,7 @@
/* Assert this is the first guard. */
vg_assert(nGuards == 1);
res = ML_(evaluate_Dwarf3_Expr)(
- p, (UWord)nbytes, fbGX, regs, data_bias,
+ p, (UWord)nbytes, fbGX, regs, di,
False/*push_initial_zero*/ );
/* Now check there are no more guards. */
p += (UWord)nbytes;
@@ -665,7 +713,7 @@
if (aMin <= regs->ip && regs->ip <= aMax) {
/* found a matching range. Evaluate the expression. */
return ML_(evaluate_Dwarf3_Expr)(
- p, (UWord)nbytes, fbGX, regs, data_bias,
+ p, (UWord)nbytes, fbGX, regs, di,
False/*push_initial_zero*/ );
}
}
@@ -689,7 +737,7 @@
* there's more than one subexpression, all of which successfully
evaluate to a constant, but they don't all produce the same constant.
*/
-GXResult ML_(evaluate_trivial_GX)( GExpr* gx, Addr data_bias )
+GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di )
{
GXResult res;
Addr aMin, aMax;
@@ -730,8 +778,14 @@
/* Peer at this particular subexpression, to see if it's
obviously a constant. */
if (nbytes == 1 + sizeof(Addr) && *p == DW_OP_addr) {
- thisResult.b = True;
- thisResult.ul = (ULong)(*(Addr*)(p+1)) + (ULong)data_bias;
+ Addr a = *(Addr*)(p+1);
+ if (bias_address(&a, di)) {
+ thisResult.b = True;
+ thisResult.ul = (ULong)a;
+ }
+ else if (!badness) {
+ badness = "trivial GExpr denotes constant address in unknown section";
+ }
}
else if (nbytes == 2 + sizeof(Addr)
&& *p == DW_OP_addr
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/debuginfo.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -1928,7 +1928,7 @@
DiVariable* var,
RegSummary* regs,
Addr data_addr,
- Addr data_bias )
+ const DebugInfo* di )
{
MaybeULong mul;
SizeT var_szB;
@@ -1965,7 +1965,7 @@
return False;
}
- res = ML_(evaluate_GX)( var->gexpr, var->fbGX, regs, data_bias );
+ res = ML_(evaluate_GX)( var->gexpr, var->fbGX, regs, di );
if (show) {
VG_(printf)("VVVV: -> ");
@@ -2243,7 +2243,7 @@
var->name,arange->aMin,arange->aMax,ip);
if (data_address_is_in_var( &offset, di->admin_tyents,
var, ®s,
- data_addr, di->data_bias )) {
+ data_addr, di )) {
OffT residual_offset = 0;
XArray* described = ML_(describe_type)( &residual_offset,
di->admin_tyents,
@@ -2342,7 +2342,7 @@
fail. */
if (data_address_is_in_var( &offset, di->admin_tyents, var,
NULL/* RegSummary* */,
- data_addr, di->data_bias )) {
+ data_addr, di )) {
OffT residual_offset = 0;
XArray* described = ML_(describe_type)( &residual_offset,
di->admin_tyents,
@@ -2467,7 +2467,7 @@
static
void analyse_deps ( /*MOD*/XArray* /* of FrameBlock */ blocks,
XArray* /* TyEnt */ tyents,
- Addr ip, Addr data_bias, DiVariable* var,
+ Addr ip, const DebugInfo* di, DiVariable* var,
Bool arrays_only )
{
GXResult res_sp_6k, res_sp_7k, res_fp_6k, res_fp_7k;
@@ -2512,22 +2512,22 @@
regs.fp = 0;
regs.ip = ip;
regs.sp = 6 * 1024;
- res_sp_6k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res_sp_6k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
regs.fp = 0;
regs.ip = ip;
regs.sp = 7 * 1024;
- res_sp_7k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res_sp_7k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
regs.fp = 6 * 1024;
regs.ip = ip;
regs.sp = 0;
- res_fp_6k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res_fp_6k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
regs.fp = 7 * 1024;
regs.ip = ip;
regs.sp = 0;
- res_fp_7k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res_fp_7k = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
vg_assert(res_sp_6k.kind == res_sp_7k.kind);
vg_assert(res_sp_6k.kind == res_fp_6k.kind);
@@ -2549,7 +2549,7 @@
if (sp_delta == 1024 && fp_delta == 0) {
regs.sp = regs.fp = 0;
regs.ip = ip;
- res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
tl_assert(res.kind == GXR_Value);
if (debug)
VG_(printf)(" %5ld .. %5ld (sp) %s\n",
@@ -2568,7 +2568,7 @@
if (sp_delta == 0 && fp_delta == 1024) {
regs.sp = regs.fp = 0;
regs.ip = ip;
- res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, data_bias );
+ res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di );
tl_assert(res.kind == GXR_Value);
if (debug)
VG_(printf)(" %5ld .. %5ld (FP) %s\n",
@@ -2698,7 +2698,7 @@
VG_(printf)("QQQQ: var:name=%s %#lx-%#lx %#lx\n",
var->name,arange->aMin,arange->aMax,ip);
analyse_deps( res, di->admin_tyents, ip,
- di->data_bias, var, arrays_only );
+ di, var, arrays_only );
}
}
@@ -2781,7 +2781,7 @@
it. */
if (0) { VG_(printf)("EVAL: "); ML_(pp_GX)(var->gexpr);
VG_(printf)("\n"); }
- res = ML_(evaluate_trivial_GX)( var->gexpr, di->data_bias );
+ res = ML_(evaluate_trivial_GX)( var->gexpr, di );
/* Not a constant address => not interesting */
if (res.kind != GXR_Value) {
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_d3basics.h
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_d3basics.h 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_d3basics.h 2009-01-26 13:02:16 UTC (rev 9067)
@@ -621,7 +621,7 @@
NULL but the frame base is still needed, then evaluation of gx as a
whole will fail. */
GXResult ML_(evaluate_GX)( GExpr* gx, GExpr* fbGX,
- RegSummary* regs, Addr data_bias );
+ RegSummary* regs, const DebugInfo* di );
/* This is a subsidiary of ML_(evaluate_GX), which just evaluates a
single standard DWARF3 expression. Conventions w.r.t regs and fbGX
@@ -632,7 +632,7 @@
recursive. */
GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB,
GExpr* fbGX, RegSummary* regs,
- Addr data_bias,
+ const DebugInfo* di,
Bool push_initial_zero );
/* Evaluate a very simple Guarded (DWARF3) expression. The expression
@@ -642,7 +642,7 @@
location is denoted, a frame base expression is required, or the
expression is not manifestly a constant. The range of addresses
covered by the guard is also ignored. */
-GXResult ML_(evaluate_trivial_GX)( GExpr* gx, Addr data_bias );
+GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di );
#endif /* ndef __PRIV_D3BASICS_H */
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_storage.h
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_storage.h 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/priv_storage.h 2009-01-26 13:02:16 UTC (rev 9067)
@@ -366,12 +366,24 @@
Addr sdata_avma;
SizeT sdata_size;
OffT sdata_bias;
+ /* .rodata */
+ Bool rodata_present;
+ Addr rodata_svma;
+ Addr rodata_avma;
+ SizeT rodata_size;
+ OffT rodata_bias;
/* .bss */
Bool bss_present;
Addr bss_svma;
Addr bss_avma;
SizeT bss_size;
OffT bss_bias;
+ /* .sbss */
+ Bool sbss_present;
+ Addr sbss_svma;
+ Addr sbss_avma;
+ SizeT sbss_size;
+ OffT sbss_bias;
/* .plt */
Bool plt_present;
Addr plt_avma;
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -34,6 +34,7 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_debuginfo.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -133,6 +133,7 @@
groupies always show up at the top of performance profiles. */
#include "pub_core_basics.h"
+#include "pub_core_debuginfo.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readelf.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readelf.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readelf.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -36,6 +36,7 @@
#include "pub_core_basics.h"
#include "pub_core_vki.h"
+#include "pub_core_debuginfo.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcprint.h"
#include "pub_core_libcassert.h"
@@ -219,7 +220,7 @@
)
{
Bool plausible, is_in_opd;
- Bool in_text, in_data, in_sdata, in_bss;
+ Bool in_text, in_data, in_sdata, in_rodata, in_bss, in_sbss;
/* Set defaults */
*sym_name_out = sym_name;
@@ -276,12 +277,26 @@
*is_text_out = False;
*sym_avma_out += di->sdata_bias;
} else
+ if (di->rodata_present
+ && di->rodata_size > 0
+ && sym_svma >= di->rodata_svma
+ && sym_svma < di->rodata_svma + di->rodata_size) {
+ *is_text_out = False;
+ *sym_avma_out += di->rodata_bias;
+ } else
if (di->bss_present
&& di->bss_size > 0
&& sym_svma >= di->bss_svma
&& sym_svma < di->bss_svma + di->bss_size) {
*is_text_out = False;
*sym_avma_out += di->bss_bias;
+ } else
+ if (di->sbss_present
+ && di->sbss_size > 0
+ && sym_svma >= di->sbss_svma
+ && sym_svma < di->sbss_svma + di->sbss_size) {
+ *is_text_out = False;
+ *sym_avma_out += di->sbss_bias;
} else {
/* Assume it's in .text. Is this a good idea? */
*is_text_out = True;
@@ -450,13 +465,25 @@
&& !(*sym_avma_out + *sym_size_out <= di->sdata_avma
|| *sym_avma_out >= di->sdata_avma + di->sdata_size);
+ in_rodata
+ = di->rodata_present
+ && di->rodata_size > 0
+ && !(*sym_avma_out + *sym_size_out <= di->rodata_avma
+ || *sym_avma_out >= di->rodata_avma + di->rodata_size);
+
in_bss
= di->bss_present
&& di->bss_size > 0
&& !(*sym_avma_out + *sym_size_out <= di->bss_avma
|| *sym_avma_out >= di->bss_avma + di->bss_size);
+ in_sbss
+ = di->sbss_present
+ && di->sbss_size > 0
+ && !(*sym_avma_out + *sym_size_out <= di->sbss_avma
+ || *sym_avma_out >= di->sbss_avma + di->sbss_size);
+
if (*is_text_out) {
/* This used to reject any symbol falling outside the text
segment ("if (!in_text) ..."). Now it is relaxed slightly,
@@ -479,9 +506,9 @@
return False;
}
} else {
- if (!(in_data || in_sdata || in_bss)) {
+ if (!(in_data || in_sdata || in_rodata || in_bss || in_sbss)) {
TRACE_SYMTAB(
- "ignore -- %#lx .. %#lx outside .data / .sdata / .bss svma ranges\n",
+ "ignore -- %#lx .. %#lx outside .data / .sdata / .rodata / .bss / .sbss svma ranges\n",
*sym_avma_out, *sym_avma_out + *sym_size_out);
return False;
}
@@ -955,16 +982,7 @@
return (void*)( ((UChar*)base) + idx * scale );
}
-static Addr round_Addr_upwards ( Addr a, UInt align )
-{
- if (align > 0) {
- vg_assert(-1 != VG_(log2)(align));
- a = VG_ROUNDUP(a, align);
- }
- return a;
-}
-
/* Find the file offset corresponding to SVMA by using the program
headers. This is taken from binutils-2.17/binutils/readelf.c
offset_from_vma(). */
@@ -1027,15 +1045,13 @@
UWord shdr_ent_szB = 0;
UChar* shdr_strtab_img = NULL;
- /* To do with figuring out where .sbss is relative to .bss. A
- kludge at the best of times. */
- SizeT sbss_size;
- Addr sbss_svma;
- UInt bss_align;
- UInt sbss_align;
- UInt data_align;
- SizeT bss_totsize;
- Addr gen_bss_lowest_svma;
+ /* SVMAs covered by rx and rw segments and corresponding bias. */
+ Addr rx_svma_base = 0;
+ Addr rx_svma_limit = 0;
+ OffT rx_bias = 0;
+ Addr rw_svma_base = 0;
+ Addr rw_svma_limit = 0;
+ OffT rw_bias = 0;
vg_assert(di);
vg_assert(di->have_rx_map == True);
@@ -1203,6 +1219,22 @@
goto out;
}
prev_svma = phdr->p_vaddr;
+ if (rx_svma_limit == 0
+ && phdr->p_offset >= di->rx_map_foff
+ && phdr->p_offset < di->rx_map_foff + di->rx_map_size
+ && phdr->p_offset + phdr->p_filesz <= di->rx_map_foff + di->rx_map_size) {
+ rx_svma_base = phdr->p_vaddr;
+ rx_svma_limit = phdr->p_vaddr + phdr->p_memsz;
+ rx_bias = di->rx_map_avma - di->rx_map_foff + phdr->p_offset - phdr->p_vaddr;
+ }
+ else if (rw_svma_limit == 0
+ && phdr->p_offset >= di->rw_map_foff
+ && phdr->p_offset < di->rw_map_foff + di->rw_map_size
+ && phdr->p_offset + phdr->p_filesz <= di->rw_map_foff + di->rw_map_size) {
+ rw_svma_base = phdr->p_vaddr;
+ rw_svma_limit = phdr->p_vaddr + phdr->p_memsz;
+ rw_bias = di->rw_map_avma - di->rw_map_foff + phdr->p_offset - phdr->p_vaddr;
+ }
}
/* Try to get the soname. If there isn't one, use "NONE".
@@ -1254,15 +1286,9 @@
di->soname = "NONE";
}
- /*SizeT*/ sbss_size = 0;
- /*Addr */ sbss_svma = 0;
- /*UInt */ bss_align = 0;
- /*UInt */ sbss_align = 0;
+ vg_assert(rx_svma_limit != 0);
+ vg_assert(rw_svma_limit != 0);
- /* UInt */ data_align = 0;
- /* SizeT */ bss_totsize = 0;
- /* Addr */ gen_bss_lowest_svma = ~((Addr)0);
-
/* Now read the section table. */
TRACE_SYMTAB("\n");
TRACE_SYMTAB("------ Examining the section headers "
@@ -1270,9 +1296,13 @@
TRACE_SYMTAB("rx: at %#lx are mapped foffsets %ld .. %ld\n",
di->rx_map_avma,
di->rx_map_foff, di->rx_map_foff + di->rx_map_size - 1 );
+ TRACE_SYMTAB("rx: contains svmas %#lx .. %#lx with bias %#lx\n",
+ rx_svma_base, rx_svma_limit - 1, rx_bias );
TRACE_SYMTAB("rw: at %#lx are mapped foffsets %ld .. %ld\n",
di->rw_map_avma,
di->rw_map_foff, di->rw_map_foff + di->rw_map_size - 1 );
+ TRACE_SYMTAB("rw: contains svmas %#lx .. %#lx with bias %#lx\n",
+ rw_svma_base, rw_svma_limit - 1, rw_bias );
for (i = 0; i < shdr_nent; i++) {
ElfXX_Shdr* shdr = INDEX_BIS( shdr_img, i, shdr_ent_szB );
@@ -1282,10 +1312,8 @@
UWord size = shdr->sh_size;
UInt alyn = shdr->sh_addralign;
Bool bits = !(shdr->sh_type == SHT_NOBITS);
- Bool inrx = foff >= di->rx_map_foff
- && foff < di->rx_map_foff + di->rx_map_size;
- Bool inrw = foff >= di->rw_map_foff
- && foff < di->rw_map_foff + di->rw_map_size;
+ Bool inrx = svma >= rx_svma_base && svma < rx_svma_limit;
+ Bool inrw = svma >= rw_svma_base && svma < rw_svma_limit;
TRACE_SYMTAB(" [sec %2ld] %s %s al%2u foff %6ld .. %6ld "
" svma %p name \"%s\"\n",
@@ -1313,17 +1341,17 @@
goto out; \
} while (0)
- /* Find avma-s for: .text .data .sdata .bss .plt .got .opd
+ /* Find avma-s for: .text .data .sdata .rodata .bss .sbss .plt .got .opd
and .eh_frame */
- /* Accept .text where mapped as rx (code) */
+ /* Accept .text where mapped as rx (code), even if zero-sized */
if (0 == VG_(strcmp)(name, ".text")) {
- if (inrx && size > 0 && !di->text_present) {
+ if (inrx && size >= 0 && !di->text_present) {
di->text_present = True;
di->text_svma = svma;
- di->text_avma = di->rx_map_avma + foff - di->rx_map_foff;
+ di->text_avma = svma + rx_bias;
di->text_size = size;
- di->text_bias = di->text_avma - svma;
+ di->text_bias = rx_bias;
TRACE_SYMTAB("acquiring .text svma = %#lx .. %#lx\n",
di->text_svma,
di->text_svma + di->text_size - 1);
@@ -1339,13 +1367,11 @@
/* Accept .data where mapped as rw (data), even if zero-sized */
if (0 == VG_(strcmp)(name, ".data")) {
if (inrw && size >= 0 && !di->data_present) {
- if (alyn > data_align)
- data_align = alyn;
di->data_present = True;
di->data_svma = svma;
- di->data_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->data_avma = svma + rw_bias;
di->data_size = size;
- di->data_bias = di->data_avma - svma;
+ di->data_bias = rw_bias;
TRACE_SYMTAB("acquiring .data svma = %#lx .. %#lx\n",
di->data_svma,
di->data_svma + di->data_size - 1);
@@ -1361,13 +1387,11 @@
/* Accept .sdata where mapped as rw (data) */
if (0 == VG_(strcmp)(name, ".sdata")) {
if (inrw && size > 0 && !di->sdata_present) {
- if (alyn > data_align)
- data_align = alyn;
di->sdata_present = True;
di->sdata_svma = svma;
- di->sdata_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->sdata_avma = svma + rw_bias;
di->sdata_size = size;
- di->sdata_bias = di->sdata_avma - svma;
+ di->sdata_bias = rw_bias;
TRACE_SYMTAB("acquiring .sdata svma = %#lx .. %#lx\n",
di->sdata_svma,
di->sdata_svma + di->sdata_size - 1);
@@ -1380,20 +1404,34 @@
}
}
+ /* Accept .rodata where mapped as rx (data), even if zero-sized */
+ if (0 == VG_(strcmp)(name, ".rodata")) {
+ if (inrx && size >= 0 && !di->rodata_present) {
+ di->rodata_present = True;
+ di->rodata_svma = svma;
+ di->rodata_avma = svma + rx_bias;
+ di->rodata_size = size;
+ di->rodata_bias = rx_bias;
+ TRACE_SYMTAB("acquiring .rodata svma = %#lx .. %#lx\n",
+ di->rodata_svma,
+ di->rodata_svma + di->rodata_size - 1);
+ TRACE_SYMTAB("acquiring .rodata avma = %#lx .. %#lx\n",
+ di->rodata_avma,
+ di->rodata_avma + di->rodata_size - 1);
+ TRACE_SYMTAB("acquiring .rodata bias = %#lx\n", di->rodata_bias);
+ } else {
+ BAD(".rodata");
+ }
+ }
+
/* Accept .bss where mapped as rw (data), even if zero-sized */
if (0 == VG_(strcmp)(name, ".bss")) {
if (inrw && size >= 0 && !di->bss_present) {
- bss_totsize += round_Addr_upwards(size, alyn);
- if (svma < gen_bss_lowest_svma)
- gen_bss_lowest_svma = svma;
- TRACE_SYMTAB("increasing total bss-like size to %ld\n",
- bss_totsize);
di->bss_present = True;
di->bss_svma = svma;
- di->bss_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->bss_avma = svma + rw_bias;
di->bss_size = size;
- di->bss_bias = di->bss_avma - svma;
- bss_align = alyn;
+ di->bss_bias = rw_bias;
TRACE_SYMTAB("acquiring .bss svma = %#lx .. %#lx\n",
di->bss_svma,
di->bss_svma + di->bss_size - 1);
@@ -1413,7 +1451,6 @@
di->bss_avma = 0;
di->bss_size = 0;
di->bss_bias = 0;
- bss_align = 0;
if (!VG_(clo_xml)) {
VG_(message)(Vg_UserMsg, "Warning: the following file's .bss is "
"mapped r-x only - ignoring .bss syms");
@@ -1423,14 +1460,13 @@
}
} else
- if ((!inrw) && (!inrx) && size > 0 && !di->bss_present) {
+ if ((!inrw) && (!inrx) && size >= 0 && !di->bss_present) {
/* File contains a .bss, but it didn't get mapped. Ignore. */
di->bss_present = False;
di->bss_svma = 0;
di->bss_avma = 0;
di->bss_size = 0;
di->bss_bias = 0;
- bss_align = 0;
} else {
BAD(".bss");
}
@@ -1438,38 +1474,29 @@
/* Accept .sbss where mapped as rw (data) */
if (0 == VG_(strcmp)(name, ".sbss")) {
- if (inrw && size > 0 && sbss_size == 0) {
- bss_totsize += round_Addr_upwards(size, alyn);
- if (svma < gen_bss_lowest_svma)
- gen_bss_lowest_svma = svma;
- TRACE_SYMTAB("increasing total bss-like size to %ld\n",
- bss_totsize);
- sbss_size = size;
- sbss_svma = svma;
- sbss_align = alyn;
+ if (inrw && size > 0 && !di->sbss_present) {
+ di->sbss_present = True;
+ di->sbss_svma = svma;
+ di->sbss_avma = svma + rw_bias;
+ di->sbss_size = size;
+ di->sbss_bias = rw_bias;
+ TRACE_SYMTAB("acquiring .sbss svma = %#lx .. %#lx\n",
+ di->sbss_svma,
+ di->sbss_svma + di->sbss_size - 1);
+ TRACE_SYMTAB("acquiring .sbss avma = %#lx .. %#lx\n",
+ di->sbss_avma,
+ di->sbss_avma + di->sbss_size - 1);
+ TRACE_SYMTAB("acquiring .sbss bias = %#lx\n", di->sbss_bias);
} else {
BAD(".sbss");
}
}
- /* Accept .dynbss where mapped as rw (data) */
- if (0 == VG_(strcmp)(name, ".dynbss")) {
- if (inrw && size > 0 /* && sbss_size == 0*/) {
- bss_totsize += round_Addr_upwards(size, alyn);
- if (svma < gen_bss_lowest_svma)
- gen_bss_lowest_svma = svma;
- TRACE_SYMTAB("increasing total bss-like size to %ld\n",
- bss_totsize);
- } else {
- BAD(".dynbss");
- }
- }
-
/* Accept .got where mapped as rw (data) */
if (0 == VG_(strcmp)(name, ".got")) {
if (inrw && size > 0 && !di->got_present) {
di->got_present = True;
- di->got_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->got_avma = svma + rw_bias;
di->got_size = size;
TRACE_SYMTAB("acquiring .got avma = %#lx\n", di->got_avma);
} else {
@@ -1481,7 +1508,7 @@
if (0 == VG_(strcmp)(name, ".got.plt")) {
if (inrw && size > 0 && !di->gotplt_present) {
di->gotplt_present = True;
- di->gotplt_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->gotplt_avma = svma + rw_bias;
di->gotplt_size = size;
TRACE_SYMTAB("acquiring .got.plt avma = %#lx\n", di->gotplt_avma);
} else if (size != 0) {
@@ -1495,7 +1522,7 @@
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrx && size > 0 && !di->plt_present) {
di->plt_present = True;
- di->plt_avma = di->rx_map_avma + foff - di->rx_map_foff;
+ di->plt_avma = svma + rx_bias;
di->plt_size = size;
TRACE_SYMTAB("acquiring .plt avma = %#lx\n", di->plt_avma);
} else {
@@ -1507,7 +1534,7 @@
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrw && size > 0 && !di->plt_present) {
di->plt_present = True;
- di->plt_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->plt_avma = svma + rw_bias;
di->plt_size = size;
TRACE_SYMTAB("acquiring .plt avma = %#lx\n", di->plt_avma);
} else {
@@ -1519,7 +1546,7 @@
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrw && size > 0 && !di->plt_present) {
di->plt_present = True;
- di->plt_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->plt_avma = svma + rw_bias;
di->plt_size = size;
TRACE_SYMTAB("acquiring .plt avma = %#lx\n", di->plt_avma);
} else
@@ -1542,7 +1569,7 @@
if (0 == VG_(strcmp)(name, ".opd")) {
if (inrw && size > 0 && !di->opd_present) {
di->opd_present = True;
- di->opd_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->opd_avma = svma + rw_bias;
di->opd_size = size;
TRACE_SYMTAB("acquiring .opd avma = %#lx\n", di->opd_avma);
} else {
@@ -1556,13 +1583,13 @@
if (0 == VG_(strcmp)(name, ".eh_frame")) {
if (inrx && size > 0 && !di->ehframe_present) {
di->ehframe_present = True;
- di->ehframe_avma = di->rx_map_avma + foff - di->rx_map_foff;
+ di->ehframe_avma = svma + rx_bias;
di->ehframe_size = size;
TRACE_SYMTAB("acquiring .eh_frame avma = %#lx\n", di->ehframe_avma);
} else
if (inrw && size > 0 && !di->ehframe_present) {
di->ehframe_present = True;
- di->ehframe_avma = di->rw_map_avma + foff - di->rw_map_foff;
+ di->ehframe_avma = svma + rw_bias;
di->ehframe_size = size;
TRACE_SYMTAB("acquiring .eh_frame avma = %#lx\n", di->ehframe_avma);
} else {
@@ -1574,24 +1601,6 @@
}
- /* Kludge: ignore all previous computations for .bss avma range,
- and simply assume that .bss immediately follows .data/.sdata.*/
- if (1) {
- SizeT data_al = round_Addr_upwards(di->data_avma, data_align)
- - di->data_avma;
- TRACE_SYMTAB("data_al = %ld\n", data_al);
- bss_totsize += data_al;
- di->bss_svma = gen_bss_lowest_svma;
- di->bss_size = bss_totsize;
- di->bss_avma = di->data_avma + (di->bss_svma - di->data_svma);
- di->bss_bias = di->data_bias;
- TRACE_SYMTAB("kludged .bss svma = %#lx .. %#lx\n",
- di->bss_svma, di->bss_svma + di->bss_size - 1);
- TRACE_SYMTAB("kludged .bss avma = %#lx .. %#lx\n",
- di->bss_avma, di->bss_avma + di->bss_size - 1);
- TRACE_SYMTAB("kludged .bss bias = %#lx\n", di->bss_bias);
- }
-
if (0) VG_(printf)("YYYY text_: avma %#lx size %ld bias %#lx\n",
di->text_avma, di->text_size, di->text_bias);
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readxcoff.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readxcoff.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readxcoff.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -58,6 +58,7 @@
#include "pub_core_xarray.h"
#include "priv_misc.h"
#include "priv_tytypes.h"
+#include "pub_tool_debuginfo.h"
#include "priv_d3basics.h"
#include "priv_storage.h"
#include "priv_readxcoff.h" /* self */
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/storage.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/storage.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/storage.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -39,6 +39,7 @@
#include "pub_core_basics.h"
#include "pub_core_options.h" /* VG_(clo_verbosity) */
+#include "pub_core_debuginfo.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcprint.h"
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/tytypes.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/tytypes.c 2009-01-26 12:41:31 UTC (rev 9066)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/tytypes.c 2009-01-26 13:02:16 UTC (rev 9067)
@@ -34,6 +34,7 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_debuginfo.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcprint.h"
|
|
From: <sv...@va...> - 2009-01-26 13:01:21
|
Author: sewardj
Date: 2009-01-26 12:24:36 +0000 (Mon, 26 Jan 2009)
New Revision: 9065
Log:
merge r8930 (Add signalfd4 support.)
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/priv_syswrap-linux.h
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-amd64-linux.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-linux.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc32-linux.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc64-linux.c
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/priv_syswrap-linux.h
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/priv_syswrap-linux.h 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/priv_syswrap-linux.h 2009-01-26 12:24:36 UTC (rev 9065)
@@ -133,6 +133,7 @@
DECL_TEMPLATE(linux, sys_timerfd_settime);
DECL_TEMPLATE(linux, sys_signalfd);
+DECL_TEMPLATE(linux, sys_signalfd4);
DECL_TEMPLATE(linux, sys_capget);
DECL_TEMPLATE(linux, sys_capset);
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-amd64-linux.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-amd64-linux.c 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-amd64-linux.c 2009-01-26 12:24:36 UTC (rev 9065)
@@ -1361,7 +1361,7 @@
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 286
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 287
// (__NR_paccept, sys_ni_syscall) // 288
- // (__NR_signalfd4, sys_ni_syscall) // 289
+ LINXY(__NR_signalfd4, sys_signalfd4), // 289
LINX_(__NR_eventfd2, sys_eventfd2), // 290
// (__NR_epoll_create1, sys_ni_syscall) // 291
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-linux.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-linux.c 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-linux.c 2009-01-26 12:24:36 UTC (rev 9065)
@@ -2431,7 +2431,7 @@
PRE(sys_signalfd)
{
- PRINT("sys_signalfd ( %d, %#lx, %llu )", (Int)ARG1, ARG2, (ULong) ARG3);
+ PRINT("sys_signalfd ( %d, %#lx, %llu )", (Int)ARG1,ARG2,(ULong)ARG3);
PRE_REG_READ3(long, "sys_signalfd",
int, fd, vki_sigset_t *, sigmask, vki_size_t, sigsetsize);
PRE_MEM_READ( "signalfd(sigmask)", ARG2, sizeof(vki_sigset_t) );
@@ -2449,7 +2449,27 @@
}
}
+PRE(sys_signalfd4)
+{
+ PRINT("sys_signalfd4 ( %d, %#lx, %llu, %ld )", (Int)ARG1,ARG2,(ULong)ARG3,ARG4);
+ PRE_REG_READ4(long, "sys_signalfd4",
+ int, fd, vki_sigset_t *, sigmask, vki_size_t, sigsetsize, int, flags);
+ PRE_MEM_READ( "signalfd(sigmask)", ARG2, sizeof(vki_sigset_t) );
+ if ((int)ARG1 != -1 && !ML_(fd_allowed)(ARG1, "signalfd", tid, False))
+ SET_STATUS_Failure( VKI_EBADF );
+}
+POST(sys_signalfd4)
+{
+ if (!ML_(fd_allowed)(RES, "signalfd4", tid, True)) {
+ VG_(close)(RES);
+ SET_STATUS_Failure( VKI_EMFILE );
+ } else {
+ if (VG_(clo_track_fds))
+ ML_(record_fd_open_nameless) (tid, RES);
+ }
+}
+
/* ---------------------------------------------------------------------
rt_sig* wrappers
------------------------------------------------------------------ */
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc32-linux.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc32-linux.c 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc32-linux.c 2009-01-26 12:24:36 UTC (rev 9065)
@@ -1859,7 +1859,7 @@
// LINXY(__NR_subpage_prot, sys_ni_syscall), // 310
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 312
- // (__NR_signalfd4, sys_ni_syscall) // 313
+ LINXY(__NR_signalfd4, sys_signalfd4), // 313
LINX_(__NR_eventfd2, sys_eventfd2), // 314
// (__NR_epoll_create1, sys_ni_syscall) // 315
// (__NR_dup3, sys_ni_syscall) // 316
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc64-linux.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc64-linux.c 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-ppc64-linux.c 2009-01-26 12:24:36 UTC (rev 9065)
@@ -1499,7 +1499,7 @@
// LINXY(__NR_subpage_prot, sys_ni_syscall), // 310
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 312
- // (__NR_signalfd4, sys_ni_syscall) // 313
+ LINXY(__NR_signalfd4, sys_signalfd4), // 313
LINX_(__NR_eventfd2, sys_eventfd2), // 314
// (__NR_epoll_create1, sys_ni_syscall) // 315
// (__NR_dup3, sys_ni_syscall) // 316
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c 2009-01-26 12:18:35 UTC (rev 9064)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c 2009-01-26 12:24:36 UTC (rev 9065)
@@ -2234,7 +2234,7 @@
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326
- // (__NR_signalfd4, sys_ni_syscall) // 327
+ LINXY(__NR_signalfd4, sys_signalfd4), // 327
LINX_(__NR_eventfd2, sys_eventfd2), // 328
// (__NR_epoll_create1, sys_ni_syscall) // 329
|
|
From: <sv...@va...> - 2009-01-26 12:56:19
|
Author: sewardj
Date: 2009-01-26 12:18:35 +0000 (Mon, 26 Jan 2009)
New Revision: 9064
Log:
merge r8917 (Handle __NR_socketpair in Ptrcheck.)
Modified:
branches/VALGRIND_3_4_BRANCH/exp-ptrcheck/h_main.c
Modified: branches/VALGRIND_3_4_BRANCH/exp-ptrcheck/h_main.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/exp-ptrcheck/h_main.c 2009-01-26 10:45:16 UTC (rev 9063)
+++ branches/VALGRIND_3_4_BRANCH/exp-ptrcheck/h_main.c 2009-01-26 12:18:35 UTC (rev 9064)
@@ -2332,6 +2332,9 @@
# if defined(__NR_socketcall)
ADD(0, __NR_socketcall); /* the nasty x86-linux socket multiplexor */
# endif
+# if defined(__NR_socketpair)
+ ADD(0, __NR_socketpair);
+# endif
# if defined(__NR_statfs64)
ADD(0, __NR_statfs64);
# endif
Property changes on: branches/VALGRIND_3_4_BRANCH/exp-ptrcheck/h_main.c
___________________________________________________________________
Name: svn:mergeinfo
-
|
|
From: Ali J. <a.j...@gm...> - 2009-01-26 12:55:17
|
Hi,
It is working....
Ali
> -----Original Message-----
> From: Julian Seward [mailto:js...@ac...]
> Sent: Montag, 26. Januar 2009 11:46
> To: val...@li...
> Cc: Ali Jannesari
> Subject: Re: [Valgrind-developers] Bug in Helgrind
>
>
> Fixed (r9063); can you test?
>
> Thanks for the bug report and test cases.
>
> J
>
> On Sunday 25 January 2009, Ali Jannesari wrote:
> > Sorry, we used a very old revision of unittest. The bug can be
> reproduced
> > until revision 382.
> > Since revision 383, every printf is synchronized via mutex and
> helgrind's
> > loag gets initialized in every case.
> >
> > The following simple program also triggers the described behaviour:
> >
> > #include <pthread.h>
> >
> > pthread_mutex_t mutex;
> >
> > int main(int argc, char* argv[])
> > {
> > pthread_mutex_init(&mutex, NULL);
> > pthread_mutex_destroy(&mutex);
> > return 0;
> > }
> >
> >
> > Ali
> >
> > > -----Original Message-----
> > > From: Julian Seward [mailto:js...@ac...]
> > > Sent: Samstag, 24. Januar 2009 21:30
> > > To: val...@li...
> > > Cc: Ali Jannesari
> > > Subject: Re: [Valgrind-developers] Bug in Helgrind
> > >
> > > > test00: negative
> > > > GLOB=0
> > > > --22433-- VALGRIND INTERNAL ERROR: Valgrind received a signal 11
> > >
> > > (SIGSEGV)
> > >
> > > > - exiting
> > > > --22433-- si_code=1; Faulting address: 0x10; sp: 0x62e67e88
> > > >
> > > > Test 0's destructor is trying to delete a mutex, but the whole
> > >
> > > program
> > >
> > > > never used mutexes.
> > > > So, Helgrind's loag is not initialized and trying to delete the
> mutex
> > > > faults.
> > >
> > > I understand what you're saying, but I can't reproduce this
> failure:
> > >
> > > sewardj@zazenhausen:~/DaRaT/unittest$
> > > valgrind-3.4.0 --tool=helgrind ./racecheck_unittest 0
> > > ==24354== Helgrind, a thread error detector.
> > > ==24354== Copyright (C) 2007-2008, and GNU GPL'd, by OpenWorks LLP
> et
> > > al.
> > > ==24354== Using LibVEX rev 1878, a library for dynamic binary
> > > translation.
> > > ==24354== Copyright (C) 2004-2008, and GNU GPL'd, by OpenWorks LLP.
> > > ==24354== Using valgrind-3.4.0, a dynamic binary instrumentation
> > > framework.
> > > ==24354== Copyright (C) 2000-2008, and GNU GPL'd, by Julian Seward
> et
> > > al.
> > > ==24354== For more details, rerun with: -v
> > > ==24354==
> > > test00: negative
> > > GLOB=0
> > > ==24354==
> > > ==24354== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0
> from
> > > 0)
> > >
> > > Do I need to build racecheck_unittest in some special way? I
> simply
> > > checked out the sources and did 'make' in the unittest directory;
> > > maybe there is some other config option needed? I believe there
> are
> > > some magic configuration options for racecheck_unittest, but I
> don't
> > > know what they are.
> > >
> > > J
> >
> > ---------------------------------------------------------------------
> ------
> >--- This SF.net email is sponsored by:
> > SourcForge Community
> > SourceForge wants to tell your story.
> > http://p.sf.net/sfu/sf-spreadtheword
> > _______________________________________________
> > Valgrind-developers mailing list
> > Val...@li...
> > https://lists.sourceforge.net/lists/listinfo/valgrind-developers
|
|
From: <sv...@va...> - 2009-01-26 12:51:21
|
Author: sewardj
Date: 2009-01-26 12:41:31 +0000 (Mon, 26 Jan 2009)
New Revision: 9066
Log:
merge:
r8957 The SG_GET_VERSION_NUM ioctl writes to memory rather than
reading it.
r8958 The SG_GET_TIMEOUT ioctl doesn't write to memory - it returns the
timeout via it's return value.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-generic.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-generic.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-generic.c 2009-01-26 12:24:36 UTC (rev 9065)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_syswrap/syswrap-generic.c 2009-01-26 12:41:31 UTC (rev 9066)
@@ -3351,10 +3351,9 @@
PRE_MEM_WRITE( "ioctl(SG_GET_RESERVED_SIZE)", ARG3, sizeof(int) );
break;
case VKI_SG_GET_TIMEOUT:
- PRE_MEM_WRITE( "ioctl(SG_GET_TIMEOUT)", ARG3, sizeof(int) );
break;
case VKI_SG_GET_VERSION_NUM:
- PRE_MEM_READ( "ioctl(SG_GET_VERSION_NUM)", ARG3, sizeof(int) );
+ PRE_MEM_WRITE( "ioctl(SG_GET_VERSION_NUM)", ARG3, sizeof(int) );
break;
case VKI_SG_EMULATED_HOST: /* 0x2203 */
PRE_MEM_WRITE( "ioctl(SG_EMULATED_HOST)", ARG3, sizeof(int) );
@@ -4431,9 +4430,9 @@
POST_MEM_WRITE(ARG3, sizeof(int));
break;
case VKI_SG_GET_TIMEOUT:
- POST_MEM_WRITE(ARG3, sizeof(int));
break;
case VKI_SG_GET_VERSION_NUM:
+ POST_MEM_WRITE(ARG3, sizeof(int));
break;
case VKI_SG_EMULATED_HOST:
POST_MEM_WRITE(ARG3, sizeof(int));
|
|
From: Julian S. <js...@ac...> - 2009-01-26 10:46:29
|
Fixed (r9063); can you test?
Thanks for the bug report and test cases.
J
On Sunday 25 January 2009, Ali Jannesari wrote:
> Sorry, we used a very old revision of unittest. The bug can be reproduced
> until revision 382.
> Since revision 383, every printf is synchronized via mutex and helgrind's
> loag gets initialized in every case.
>
> The following simple program also triggers the described behaviour:
>
> #include <pthread.h>
>
> pthread_mutex_t mutex;
>
> int main(int argc, char* argv[])
> {
> pthread_mutex_init(&mutex, NULL);
> pthread_mutex_destroy(&mutex);
> return 0;
> }
>
>
> Ali
>
> > -----Original Message-----
> > From: Julian Seward [mailto:js...@ac...]
> > Sent: Samstag, 24. Januar 2009 21:30
> > To: val...@li...
> > Cc: Ali Jannesari
> > Subject: Re: [Valgrind-developers] Bug in Helgrind
> >
> > > test00: negative
> > > GLOB=0
> > > --22433-- VALGRIND INTERNAL ERROR: Valgrind received a signal 11
> >
> > (SIGSEGV)
> >
> > > - exiting
> > > --22433-- si_code=1; Faulting address: 0x10; sp: 0x62e67e88
> > >
> > > Test 0's destructor is trying to delete a mutex, but the whole
> >
> > program
> >
> > > never used mutexes.
> > > So, Helgrind's loag is not initialized and trying to delete the mutex
> > > faults.
> >
> > I understand what you're saying, but I can't reproduce this failure:
> >
> > sewardj@zazenhausen:~/DaRaT/unittest$
> > valgrind-3.4.0 --tool=helgrind ./racecheck_unittest 0
> > ==24354== Helgrind, a thread error detector.
> > ==24354== Copyright (C) 2007-2008, and GNU GPL'd, by OpenWorks LLP et
> > al.
> > ==24354== Using LibVEX rev 1878, a library for dynamic binary
> > translation.
> > ==24354== Copyright (C) 2004-2008, and GNU GPL'd, by OpenWorks LLP.
> > ==24354== Using valgrind-3.4.0, a dynamic binary instrumentation
> > framework.
> > ==24354== Copyright (C) 2000-2008, and GNU GPL'd, by Julian Seward et
> > al.
> > ==24354== For more details, rerun with: -v
> > ==24354==
> > test00: negative
> > GLOB=0
> > ==24354==
> > ==24354== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from
> > 0)
> >
> > Do I need to build racecheck_unittest in some special way? I simply
> > checked out the sources and did 'make' in the unittest directory;
> > maybe there is some other config option needed? I believe there are
> > some magic configuration options for racecheck_unittest, but I don't
> > know what they are.
> >
> > J
>
> ---------------------------------------------------------------------------
>--- This SF.net email is sponsored by:
> SourcForge Community
> SourceForge wants to tell your story.
> http://p.sf.net/sfu/sf-spreadtheword
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers
|