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|
From: Tom H. <th...@cy...> - 2009-01-28 03:47:29
|
Nightly build on vauxhall ( x86_64, Fedora 10 ) started at 2009-01-28 03:20:04 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 486 tests, 2 stderr failures, 0 stdout failures, 0 post failures == helgrind/tests/hg05_race2 (stderr) memcheck/tests/x86-linux/scalar (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 486 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Jan 28 03:33:44 2009 --- new.short Wed Jan 28 03:47:22 2009 *************** *** 8,10 **** ! == 486 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) --- 8,11 ---- ! == 486 tests, 2 stderr failures, 0 stdout failures, 0 post failures == ! helgrind/tests/hg05_race2 (stderr) memcheck/tests/x86-linux/scalar (stderr) |
|
From: Tom H. <th...@cy...> - 2009-01-28 03:44:19
|
Nightly build on lloyd ( x86_64, Fedora 7 ) started at 2009-01-28 03:05:07 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 477 tests, 6 stderr failures, 0 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) helgrind/tests/tc20_verifywrap (stderr) memcheck/tests/x86-linux/scalar (stderr) |
|
From: Tom H. <th...@cy...> - 2009-01-28 03:32:07
|
Nightly build on mg ( x86_64, Fedora 9 ) started at 2009-01-28 03:10:04 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 483 tests, 6 stderr failures, 2 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) helgrind/tests/hg05_race2 (stderr) memcheck/tests/linux/timerfd-syscall (stdout) memcheck/tests/x86-linux/scalar (stderr) none/tests/mremap2 (stdout) |
|
From: Julian S. <js...@ac...> - 2009-01-28 00:53:04
|
> Note to valgrind experts: this is _not_ about the Conditional thing in
> zlib, but about an uninitialized byte _in the middle_ of the zlib output
> buffer.
I understand. But -- whilst we're on the subject of the Conditional thing:
I thought I'd suppressed all those zlib FAQ#36 complaints, but apparently
not. Could you try the following and see if it helps?
Index: xfree-4.supp
===================================================================
--- xfree-4.supp (revision 9082)
+++ xfree-4.supp (working copy)
@@ -315,6 +315,7 @@
zlib-1.2.x trickyness (1a): See http://www.zlib.net/zlib_faq.html#faq36
Memcheck:Cond
obj:/*lib*/libz.so.1.2.*
+ ...
obj:/*lib*/libz.so.1.2.*
fun:deflate
}
@@ -329,6 +330,7 @@
zlib-1.2.x trickyness (2a): See http://www.zlib.net/zlib_faq.html#faq36
Memcheck:Value8
obj:/*lib*/libz.so.1.2.*
+ ...
obj:/*lib*/libz.so.1.2.*
fun:deflate
}
@@ -343,6 +345,7 @@
zlib-1.2.x trickyness (3a): See http://www.zlib.net/zlib_faq.html#faq36
Memcheck:Value4
obj:/*lib*/libz.so.1.2.*
+ ...
obj:/*lib*/libz.so.1.2.*
fun:deflate
}
Now to your real question. I believe this is either a bug in Valgrind
or some strangeness with libc. I don't think it has anything to do
with zlib.
One way to make sense of it is to force Memcheck to check the definedness
of the output buffer as soon as you're done with zlib. This is easier to
make sense of than trying to infer what's going on by interpreting complaints
about badness deep in the innards of libc. Thusly:
--- zlib_bad.c-ORIG 2009-01-28 01:25:46.000000000 +0100
+++ zlib_bad.c 2009-01-28 01:41:13.000000000 +0100
@@ -2,6 +2,7 @@
#include <stdlib.h>
#include <string.h>
#include <zlib.h>
+#include <memcheck.h>
int main(int argc, char **argv)
{
@@ -64,12 +65,17 @@
if (deflateEnd(&stream) != Z_OK)
return 1;
+ int nAvail = size - stream.avail_out;
+ printf("nAvail = %d\n", nAvail);
+ VALGRIND_CHECK_MEM_IS_DEFINED(compressed, nAvail);
+#if 0
out = fopen("/dev/null", "w");
fwrite(compressed + 51, 51, 1, out);
fwrite(compressed + 51, 1, 1, stderr);
fflush(out);
fclose(out);
+#endif
free(compressed);
return 0;
}
Program as modified w/ patch runs Memcheck-clean for me. Whereas if
you change the check to
VALGRIND_CHECK_MEM_IS_DEFINED(compressed, nAvail+1);
then I get
nAvail = 58
==3891== Uninitialised byte(s) found during client check request
==3891== at 0x40092D: main (zlib_bad.c:70)
==3891== Address 0x53da882 is 58 bytes inside a block of size 193 alloc'd
==3891== at 0x4C2594E: malloc (vg_replace_malloc.c:207)
==3891== by 0x400859: main (zlib_bad.c:46)
as expected.
That said, I don't have any concrete offerings as to what the problem
really is, or even whether there is a problem. I do know that zlib's
handwritten assembly inner loops tend to cause Memcheck's definedness
tracking to have problems. If you want to chase this further, I suggest you
build zlib from source, with -g -O0, and make sure you use the generic
C versions of deflate et al. Then you might be in with a fighting chance
of getting to the bottom of this.
Please lmk what the outcome is, so I know if it's a bug in Memcheck.
A final comment - you should make friends with --track-origins=yes.
It doesn't help much here, but in general it makes finding the sources
of uninitialised values a whole lot easier.
J
|
|
From: Johannes S. <Joh...@gm...> - 2009-01-27 23:33:16
|
Hi,
unfortunately unsubscribed users cannot send to your list, so I am
forwarding this after subscribing.
Short story: we have problems with zlib. No, not those problems.
Apparently, there are uninitialized bytes _in the middle_ of the buffer
filled by deflate().
Maybe someone can shed some light into the issue?
Thanks,
Dscho
---------- Forwarded message ----------
Date: Tue, 27 Jan 2009 22:52:39 +0100 (CET)
From: Johannes Schindelin <Joh...@gm...>
To: Linus Torvalds <tor...@li...>
Cc: zl...@gz..., val...@li...,
Mark Brown <br...@si...>, Jeff King <pe...@pe...>,
Junio C Hamano <gi...@po...>, Git Mailing List <gi...@vg...>
Subject: Re: Valgrind updates
Hi,
[Cc'ed the valgrind-users list, maybe the valgrind Gods can see that our
case is pretty strange, and tell us what we do wrong.]
Note to valgrind experts: this is _not_ about the Conditional thing in
zlib, but about an uninitialized byte _in the middle_ of the zlib output
buffer.
On Tue, 27 Jan 2009, Linus Torvalds wrote:
> Hmm. The zlib faq has a note about zlib doing a conditional on
> uninitialized memory that doesn't matter, and that is what the
> suppression should be about (to avoid a warning about "Conditional jump
> or move depends on uninitialised value").
>
> But that one is documented to not matter for the actual output (zlib
> FAQ#36).
>
> It's possible that zlib really does leave padding bytes around that
> literally don't matter, and that don't get initialized. That really
> would be bad, because it means that the output of git wouldn't be
> repeatable. But I doubt this is the case - original git used to actually
> do the SHA1 over the _compressed_ data, which was admittedly a totally
> and utterly broken design (and we fixed it), but it did work. Maybe it
> worked by luck, but I somehow doubt it.
>
> Some googling did find this:
>
> http://mailman.few.vu.nl/pipermail/sysprog/2008-October/000298.html
>
> which looks very similar: an uninitialized byte in the middle of a
> deflate() packet.
>
> Anyway, I'm just going to Cc 'zl...@gz...', since this definitely is
> _not_ the same issue as in the FAQ, and we're not the only ones seeing it.
>
> [...]
>
> Dscho wrote:
>
> > Yet, the buffer in question is 195 bytes, stream.total_count (which
> > totally agrees with size - stream.avail_out) says it is 58 bytes, and
> > valgrind says that the byte with offset 51 is uninitialized.
>
> The thing to note here is that what we are passing in to "write_buffer()"
> is _exactly_ what zlib deflated for us:
>
> - 'compressed' is the allocation, and is what we used to initialize
> 'stream.next_out' with (at the top of the code sequence above)
>
> - 'size' is gotten from 'stream.total_out' at the end of the compression.
>
> Oh Gods of zlib, please hear our plea for clarification..
To help ye Gods, I put together this almost minimal C program:
-- snip --
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <zlib.h>
int main(int argc, char **argv)
{
const char hdr[] = {
0x74, 0x72, 0x65, 0x65, 0x20, 0x31, 0x36, 0x35,
0x00,
};
int hdrlen = sizeof(hdr);
const char buf[] = {
0x31, 0x30, 0x30, 0x36, 0x34, 0x34, 0x20, 0x66,
0x69, 0x6c, 0x65, 0x31, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x31, 0x30, 0x30, 0x36, 0x34, 0x34, 0x20,
0x66, 0x69, 0x6c, 0x65, 0x32, 0x00, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x31, 0x30, 0x30, 0x36, 0x34, 0x34,
0x20, 0x66, 0x69, 0x6c, 0x65, 0x33, 0x00, 0x30,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x31, 0x30, 0x30, 0x36, 0x34,
0x34, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x34, 0x00,
0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x31, 0x30, 0x30, 0x36,
0x34, 0x34, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x35,
0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
};
int len = sizeof(buf);
z_stream stream;
unsigned char *compressed;
int size, ret, i;
FILE *out;
memset(&stream, 0, sizeof(stream));
deflateInit(&stream, Z_BEST_SPEED);
size = 8 + deflateBound(&stream, len+hdrlen);
compressed = malloc(size);
if (!compressed)
return 1;
stream.next_out = compressed;
stream.avail_out = size;
stream.next_in = (unsigned char *)hdr;
stream.avail_in = hdrlen;
while ((ret = deflate(&stream, 0)) == Z_OK)
/* nothing */;
/* deflate() returns Z_BUF_ERROR at this point */
stream.next_in = (unsigned char *)buf;
stream.avail_in = len;
ret = deflate(&stream, Z_FINISH);
if (ret != Z_STREAM_END)
return 1;
if (deflateEnd(&stream) != Z_OK)
return 1;
out = fopen("/dev/null", "w");
fwrite(compressed + 51, 51, 1, out);
fwrite(compressed + 51, 1, 1, stderr);
fflush(out);
fclose(out);
free(compressed);
return 0;
}
-- snap --
... which produces this output...
-- snip --
==6348== Memcheck, a memory error detector.
==6348== Copyright (C) 2002-2008, and GNU GPL'd, by Julian Seward et al.
==6348== Using LibVEX rev exported, a library for dynamic binary translation.
==6348== Copyright (C) 2004-2008, and GNU GPL'd, by OpenWorks LLP.
==6348== Using valgrind-3.5.0.SVN, a dynamic binary instrumentation framework.
==6348== Copyright (C) 2000-2008, and GNU GPL'd, by Julian Seward et al.
==6348== For more details, rerun with: -v
==6348==
==6348== Use of uninitialised value of size 8
==6348== at 0x4E2FC5B: (within /usr/lib/libz.so.1.2.3.3)
==6348== by 0x4E317B6: (within /usr/lib/libz.so.1.2.3.3)
==6348== by 0x4E2DF9C: (within /usr/lib/libz.so.1.2.3.3)
==6348== by 0x4E2E654: deflate (in /usr/lib/libz.so.1.2.3.3)
==6348== by 0x400957: main (valgrind-testcase.c:60)
==6348==
==6348== Syscall param write(buf) points to uninitialised byte(s)
==6348== at 0x5103D50: write (in /lib/libc-2.6.1.so)
==6348== by 0x50A9AE2: _IO_file_write (in /lib/libc-2.6.1.so)
==6348== by 0x50A9748: (within /lib/libc-2.6.1.so)
==6348== by 0x50A9A4B: _IO_file_xsputn (in /lib/libc-2.6.1.so)
==6348== by 0x509FDBA: fwrite (in /lib/libc-2.6.1.so)
==6348== by 0x4009D7: main (valgrind-testcase.c:69)
==6348== Address 0x53da87b is 51 bytes inside a block of size 195 alloc'd
==6348== at 0x4C222CB: malloc (in /usr/local/lib/valgrind/amd64-linux/vgpreload_memcheck.so)
==6348== by 0x4008D7: main (valgrind-testcase.c:45)
,==6348==
==6348== Syscall param write(buf) points to uninitialised byte(s)
==6348== at 0x5103D50: write (in /lib/libc-2.6.1.so)
==6348== by 0x50A9AE2: _IO_file_write (in /lib/libc-2.6.1.so)
==6348== by 0x50A9748: (within /lib/libc-2.6.1.so)
==6348== by 0x50A9A83: _IO_do_write (in /lib/libc-2.6.1.so)
==6348== by 0x50AA048: _IO_file_sync (in /lib/libc-2.6.1.so)
==6348== by 0x509EDB9: fflush (in /lib/libc-2.6.1.so)
==6348== by 0x4009E0: main (valgrind-testcase.c:70)
==6348== Address 0x4020000 is not stack'd, malloc'd or (recently) free'd
==6348==
==6348== ERROR SUMMARY: 3 errors from 3 contexts (suppressed: 15 from 4)
==6348== malloc/free: in use at exit: 0 bytes in 0 blocks.
==6348== malloc/free: 7 allocs, 7 frees, 268,835 bytes allocated.
==6348== For counts of detected errors, rerun with: -v
==6348== Use --track-origins=yes to see where uninitialised values come from
==6348== All heap blocks were freed -- no leaks are possible.
-- snap --
Note that the error only occurs when fwrite()ing to stderr, not
any other file.
This is with valgrind compiled from a git-svn mirror updated today, i.e.
valgrind-3.5.0.SVN.
Ciao,
Dscho
--
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From: Konstantin S. <kon...@gm...> - 2009-01-27 14:04:36
|
On Tue, Jan 27, 2009 at 5:25 AM, Nicholas Nethercote <n.n...@gm...> wrote: > On Sat, Jan 24, 2009 at 7:54 AM, Rodrigo Dominguez <ro...@ho...> wrote: >> I realize it's a bit early to ask but is Valgrind planning to participate in >> this year's Google Summer of Code? A few students in my group spent last >> summer hacking some of the code and I think participating in the SoC would >> be a nice next step. I'm _really_ interested in that! I have some ideas >> myself and I am also open to suggestions. > > We've never participated. We have a suggested projects page > (http://www.valgrind.org/help/projects.html) with projects of varying > quality. It could be a good fit... Nick, Julian, The page mentioned by Nick looks partially outdated. At least few items (--track-origins=yes, C++ demangler) are already implemented. It would be nice to update the page with fresh ideas before SoC. --kcc (@google.com) > > Nick > > ------------------------------------------------------------------------------ > This SF.net email is sponsored by: > SourcForge Community > SourceForge wants to tell your story. > http://p.sf.net/sfu/sf-spreadtheword > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |
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From: Bart V. A. <bar...@gm...> - 2009-01-27 11:08:05
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Hello, Regarding the nightly PPC build: this nightly build will work again as soon as the system this build is run on is operational again. The following message appears currently when logging in on the cellbuzz cluster: *** Submitting jobs to the cell nodes is currently not working, due to our PBS Pro license expiring. We are working with Altair to get it renewed. Thank you for your patience. *** Bart. ---------- Forwarded message ---------- From: Bart Van Assche <bar...@gm...> Date: Fri, Jan 23, 2009 at 5:48 PM Subject: [Valgrind-developers] 2009-01-23 02:00:01 EST nightly build (georgia-tech-cellbuzz-native, cellbuzz, ppc64, Fedora 7, native) To: val...@li... Nightly build on georgia-tech-cellbuzz-native ( cellbuzz, ppc64, Fedora 7, native ) started at 2009-01-23 02:00:01 EST Results differ from 24 hours ago Checking out valgrind source tree ... failed Last 20 lines of verbose log follow echo Checking out valgrind source tree ... svn co svn://svn.valgrind.org/valgrind/trunk -r {2009-01-23T02:00:01} valgrind Job ID = 20666.cell-user cat: cmd-output.txt: No such file or directory ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... failed Last 20 lines of verbose log follow echo Checking out valgrind source tree ... svn co svn://svn.valgrind.org/valgrind/trunk -r {2009-01-22T02:00:01} valgrind Job ID = 20661.cell-user cat: cmd-output.txt: No such file or directory ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Fri Jan 23 11:47:58 2009 --- new.short Fri Jan 23 11:48:08 2009 *************** *** 5,8 **** ! Checking out valgrind source tree ... svn co svn://svn.valgrind.org/valgrind/trunk -r {2009-01-22T02:00:01} valgrind ! Job ID = 20661.cell-user cat: cmd-output.txt: No such file or directory --- 5,8 ---- ! Checking out valgrind source tree ... svn co svn://svn.valgrind.org/valgrind/trunk -r {2009-01-23T02:00:01} valgrind ! Job ID = 20666.cell-user cat: cmd-output.txt: No such file or directory |
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From: Ashley P. <as...@pi...> - 2009-01-27 09:46:36
|
On Mon, 2009-01-26 at 14:28 +0000, Tom Hughes wrote: > Julian Seward wrote: > > > I'm doing some merging of stuff into 3_4_BRANCH. Before I commit > > every merge I like to do svn diff -rHEAD to see what I'm about > > to commit. In a trunk tree that works as expected. However, in a > > 3_4_BRANCH tree I get a load of other output too, which I don't > > understand. > > > > The unexpected output is shown below. Is it significant? > > What does it mean? And how can I get rid of it? > > The svn:mergeinfo property is used by recent versions of subversion to > track what merges have been done - it means that if you merge a branch a > second time it knows which edits have already been merged and doesn't > need to do them again. > > It may well be entirely normal for it to be deleted sometimes during a > merge - I don't really have enough experience with it to know. I read this to mean that the 3_4_BRANCH has had something merged to it but the HEAD has not, in which case it could be safely ignored. Ashley, |
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From: Konstantin S. <kon...@gm...> - 2009-01-27 05:13:36
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On Tue, Jan 27, 2009 at 12:46 AM, Nicholas Nethercote <n.n...@gm...> wrote: > On Tue, Jan 27, 2009 at 2:45 AM, Konstantin Serebryany > <kon...@gm...> wrote: >> >> Did you ever think that two data race detectors (Helgrind and Drd) is >> too much for the Valgrind project? >> In fact, I think that two is too few. :) >> >> Please welcome ThreadSanitizer, yet another data race detector based >> on Valgrind. >> http://code.google.com/p/data-race-test/wiki/ThreadSanitizer >> >> I'd appreciate your feedback, > > How similar is it to Helgrind http://code.google.com/p/data-race-test/wiki/ThreadSanitizerVsOthers > -- could it conceivably be folded into Helgrind? Yes, and I will be glad if it does! --kcc > > Nick > |
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From: Nicholas N. <n.n...@gm...> - 2009-01-27 04:26:26
|
On Tue, Jan 20, 2009 at 6:33 AM, Greg Parker <gp...@ap...> wrote: > > I think Xcode is able to build dwarf-in-executable, but I don't know what > options or programs it uses to do that. I tried using Xcode. It has three options for debug info: stabs, DWARF, DWARF + dSYM. The DWARF seems to be exactly the same as DWARF + dSYM except that it doesn't create the .dSYM directory -- ie. it doesn't put the debug info in the executable, just the object files, which isn't much help. Frustrating. Nick |
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From: Tom H. <th...@cy...> - 2009-01-27 03:47:45
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Nightly build on vauxhall ( x86_64, Fedora 10 ) started at 2009-01-27 03:20:05 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 486 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 481 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 27 03:33:54 2009 --- new.short Tue Jan 27 03:47:34 2009 *************** *** 8,10 **** ! == 481 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) --- 8,10 ---- ! == 486 tests, 1 stderr failure, 0 stdout failures, 0 post failures == memcheck/tests/x86-linux/scalar (stderr) |
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From: Tom H. <th...@cy...> - 2009-01-27 03:44:20
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Nightly build on lloyd ( x86_64, Fedora 7 ) started at 2009-01-27 03:05:07 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 477 tests, 6 stderr failures, 0 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) helgrind/tests/tc20_verifywrap (stderr) memcheck/tests/x86-linux/scalar (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 472 tests, 6 stderr failures, 0 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) helgrind/tests/tc20_verifywrap (stderr) memcheck/tests/x86-linux/scalar (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 27 03:24:47 2009 --- new.short Tue Jan 27 03:44:11 2009 *************** *** 8,10 **** ! == 472 tests, 6 stderr failures, 0 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) --- 8,10 ---- ! == 477 tests, 6 stderr failures, 0 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) |
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From: Tom H. <th...@cy...> - 2009-01-27 03:32:09
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Nightly build on mg ( x86_64, Fedora 9 ) started at 2009-01-27 03:10:07 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 483 tests, 5 stderr failures, 2 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) memcheck/tests/linux/timerfd-syscall (stdout) memcheck/tests/x86-linux/scalar (stderr) none/tests/mremap2 (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 478 tests, 5 stderr failures, 2 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) exp-ptrcheck/tests/preen_invars (stderr) exp-ptrcheck/tests/pth_create (stderr) exp-ptrcheck/tests/pth_specific (stderr) memcheck/tests/linux/timerfd-syscall (stdout) memcheck/tests/x86-linux/scalar (stderr) none/tests/mremap2 (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 27 03:21:04 2009 --- new.short Tue Jan 27 03:32:01 2009 *************** *** 8,10 **** ! == 478 tests, 5 stderr failures, 2 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) --- 8,10 ---- ! == 483 tests, 5 stderr failures, 2 stdout failures, 0 post failures == exp-ptrcheck/tests/ccc (stderr) |
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From: Nicholas N. <n.n...@gm...> - 2009-01-27 02:59:06
|
On Sat, Jan 24, 2009 at 7:54 AM, Rodrigo Dominguez <ro...@ho...> wrote: > I realize it's a bit early to ask but is Valgrind planning to participate in > this year's Google Summer of Code? A few students in my group spent last > summer hacking some of the code and I think participating in the SoC would > be a nice next step. I'm _really_ interested in that! I have some ideas > myself and I am also open to suggestions. We've never participated. We have a suggested projects page (http://www.valgrind.org/help/projects.html) with projects of varying quality. It could be a good fit... Nick |
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From: <sv...@va...> - 2009-01-26 23:26:24
|
Author: njn
Date: 2009-01-26 23:26:20 +0000 (Mon, 26 Jan 2009)
New Revision: 9082
Log:
Merge r9080 (handle non-power-of-2 cache attributes) from the trunk.
Added:
branches/DARWIN/cachegrind/tests/notpower2.stderr.exp
branches/DARWIN/cachegrind/tests/notpower2.vgtest
branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest
branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-use.vgtest
branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp
branches/DARWIN/callgrind/tests/notpower2-wb.vgtest
branches/DARWIN/callgrind/tests/notpower2.stderr.exp
branches/DARWIN/callgrind/tests/notpower2.vgtest
Modified:
branches/DARWIN/cachegrind/cg-x86.c
branches/DARWIN/cachegrind/cg_main.c
branches/DARWIN/cachegrind/cg_sim.c
branches/DARWIN/cachegrind/docs/cg-manual.xml
branches/DARWIN/cachegrind/tests/Makefile.am
branches/DARWIN/cachegrind/tests/filter_stderr
branches/DARWIN/callgrind/sim.c
branches/DARWIN/callgrind/tests/Makefile.am
branches/DARWIN/callgrind/tests/filter_stderr
Modified: branches/DARWIN/cachegrind/cg-x86.c
===================================================================
--- branches/DARWIN/cachegrind/cg-x86.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg-x86.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -113,12 +113,7 @@
case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break;
case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;
- case 0x0e:
- /* Real D1 cache configuration is:
- D1c = (cache_t) { 24, 6, 64 }; */
- VG_(message)(Vg_DebugMsg, "warning: 24Kb D1 cache detected, treating as 16Kb");
- *D1c = (cache_t) { 16, 4, 64 };
- break;
+ case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break;
case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;
/* IA-64 info -- panic! */
@@ -149,12 +144,7 @@
case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break;
case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break;
case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break;
- case 0x48:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
- *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
- break;
+ case 0x48: *L2c = (cache_t) { 3072,12, 64 }; L2_found = True; break;
case 0x49:
if ((family == 15) && (model == 6))
/* On Xeon MP (family F, model 6), this is for L3 */
@@ -163,12 +153,7 @@
else
*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
break;
- case 0x4e:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
- *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
- break;
+ case 0x4e: *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; break;
/* These are sectored, whatever that means */
case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
Modified: branches/DARWIN/cachegrind/cg_main.c
===================================================================
--- branches/DARWIN/cachegrind/cg_main.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg_main.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -1158,21 +1158,15 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
+ "error: %s set count not a power of two; aborting.",
+ name);
VG_(exit)(1);
}
- if (-1 == VG_(log2)(cache->assoc)) {
- VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
Modified: branches/DARWIN/cachegrind/cg_sim.c
===================================================================
--- branches/DARWIN/cachegrind/cg_sim.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/cg_sim.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -44,7 +44,6 @@
Int line_size; /* bytes */
Int sets;
Int sets_min_1;
- Int assoc_bits;
Int line_size_bits;
Int tag_shift;
Char desc_line[128];
@@ -62,7 +61,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
@@ -111,8 +109,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
\
/* This loop is unrolled for just the first case, which is the most */\
/* common. We can't unroll any further because it would screw up */\
@@ -143,7 +140,7 @@
/* Second case: word straddles two lines. */ \
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
if (tag == set[0]) { \
goto block2; \
} \
@@ -162,7 +159,7 @@
set[0] = tag; \
is_miss = True; \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
tag2 = (a+size-1) >> L.tag_shift; \
if (tag2 == set[0]) { \
goto miss_treatment; \
Modified: branches/DARWIN/cachegrind/docs/cg-manual.xml
===================================================================
--- branches/DARWIN/cachegrind/docs/cg-manual.xml 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/docs/cg-manual.xml 2009-01-26 23:26:20 UTC (rev 9082)
@@ -142,7 +142,7 @@
</listitem>
<listitem>
- <para>Bit-selection hash function: the line(s) in the cache
+ <para>Bit-selection hash function: the set of line(s) in the cache
to which a memory block maps is chosen by the middle bits
M--(M+N-1) of the byte address, where:</para>
<itemizedlist>
@@ -150,15 +150,17 @@
<para>line size = 2^M bytes</para>
</listitem>
<listitem>
- <para>(cache size / line size) = 2^N bytes</para>
+ <para>(cache size / line size / associativity) = 2^N bytes</para>
</listitem>
</itemizedlist>
</listitem>
<listitem>
- <para>Inclusive L2 cache: the L2 cache replicates all the
- entries of the L1 cache. This is standard on Pentium chips,
- but AMD Opterons, Athlons and Durons
+ <para>Inclusive L2 cache: the L2 cache typically replicates all
+ the entries of the L1 caches, because fetching into L1 involves
+ fetching into L2 first (this does not guarantee strict inclusiveness,
+ as lines evicted from L2 still could reside in L1). This is
+ standard on Pentium chips, but AMD Opterons, Athlons and Durons
use an exclusive L2 cache that only holds
blocks evicted from L1. Ditto most modern VIA CPUs.</para>
</listitem>
@@ -176,7 +178,10 @@
(I1/D1/L2) of the cache from the command line using the
<computeroutput>--I1</computeroutput>,
<computeroutput>--D1</computeroutput> and
-<computeroutput>--L2</computeroutput> options.</para>
+<computeroutput>--L2</computeroutput> options.
+For cache parameters to be valid for simulation, the number
+of sets (with associativity being the number of cache lines in
+each set) has to be a power of two.</para>
<para>On PowerPC platforms
Cachegrind cannot automatically
@@ -227,10 +232,7 @@
<para>If you are interested in simulating a cache with different
properties, it is not particularly hard to write your own cache
simulator, or to modify the existing ones in
-<computeroutput>vg_cachesim_I1.c</computeroutput>,
-<computeroutput>vg_cachesim_D1.c</computeroutput>,
-<computeroutput>vg_cachesim_L2.c</computeroutput> and
-<computeroutput>vg_cachesim_gen.c</computeroutput>. We'd be
+<computeroutput>cg_sim.c</computeroutput>. We'd be
interested to hear from anyone who does.</para>
</sect2>
Modified: branches/DARWIN/cachegrind/tests/Makefile.am
===================================================================
--- branches/DARWIN/cachegrind/tests/Makefile.am 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/tests/Makefile.am 2009-01-26 23:26:20 UTC (rev 9082)
@@ -15,6 +15,7 @@
chdir.vgtest chdir.stderr.exp \
clreq.vgtest clreq.stderr.exp \
dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \
+ notpower2.vgtest notpower2.stderr.exp \
wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp
check_PROGRAMS = \
Modified: branches/DARWIN/cachegrind/tests/filter_stderr
===================================================================
--- branches/DARWIN/cachegrind/tests/filter_stderr 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/cachegrind/tests/filter_stderr 2009-01-26 23:26:20 UTC (rev 9082)
@@ -17,5 +17,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Copied: branches/DARWIN/cachegrind/tests/notpower2.stderr.exp (from rev 9080, trunk/cachegrind/tests/notpower2.stderr.exp)
===================================================================
--- branches/DARWIN/cachegrind/tests/notpower2.stderr.exp (rev 0)
+++ branches/DARWIN/cachegrind/tests/notpower2.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,17 @@
+
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/cachegrind/tests/notpower2.vgtest (from rev 9080, trunk/cachegrind/tests/notpower2.vgtest)
===================================================================
--- branches/DARWIN/cachegrind/tests/notpower2.vgtest (rev 0)
+++ branches/DARWIN/cachegrind/tests/notpower2.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm cachegrind.out.*
Modified: branches/DARWIN/callgrind/sim.c
===================================================================
--- branches/DARWIN/callgrind/sim.c 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/sim.c 2009-01-26 23:26:20 UTC (rev 9082)
@@ -74,7 +74,6 @@
Bool sectored; /* prefetch nearside cacheline on read */
int sets;
int sets_min_1;
- int assoc_bits;
int line_size_bits;
int tag_shift;
UWord tag_mask;
@@ -195,7 +194,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
c->tag_mask = ~((1<<c->tag_shift)-1);
@@ -259,8 +257,7 @@
int i, j;
UWord *set;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -359,8 +356,7 @@
int i, j;
UWord *set, tmp_tag;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -407,7 +403,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = (a+size-1) >> c->tag_shift;
+ UWord tag2 = (a+size-1) & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
@@ -676,7 +672,7 @@
/* We use lower tag bits as offset pointers to cache use info.
* I.e. some cache parameters don't work.
*/
- if (c->tag_shift < c->assoc_bits) {
+ if ( (1<<c->tag_shift) < c->assoc) {
VG_(message)(Vg_DebugMsg,
"error: Use associativity < %d for cache use statistics!",
(1<<c->tag_shift) );
@@ -690,7 +686,7 @@
static __inline__
void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
{
- int idx = (high_idx << c->assoc_bits) | low_idx;
+ int idx = (high_idx * c->assoc) + low_idx;
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
@@ -709,8 +705,7 @@
UWord *set, tmp_tag;
UInt use_mask;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
use_mask =
c->line_start_mask[a & c->line_size_mask] &
c->line_end_mask[(a+size-1) & c->line_size_mask];
@@ -745,7 +740,7 @@
}
set[0] = tag | tmp_tag;
- cacheuse_L2_miss(c, (set_no << c->assoc_bits) | tmp_tag,
+ cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
use_mask, a & ~c->line_size_mask);
return Miss;
@@ -756,7 +751,7 @@
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a >> c->tag_shift;
+ UWord tag = a & c->tag_mask;
/* Access entirely within line. */
if (set1 == set2)
@@ -765,7 +760,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a >> c->tag_shift;
+ UWord tag2 = a & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cacheuse_isMiss(c, set1, tag);
@@ -800,8 +795,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask] & \
L.line_end_mask[(a+size-1) & L.line_size_mask]; \
\
@@ -809,7 +803,7 @@
/* common. We can't unroll any further because it would screw up */\
/* if we have a direct-mapped (1-way) cache. */\
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -826,7 +820,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -842,7 +836,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
return update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
\
@@ -850,10 +844,10 @@
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask]; \
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -868,7 +862,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -882,15 +876,15 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
miss1 = update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
tag2 = (a+size-1) & L.tag_mask; \
if (tag2 == (set[0] & L.tag_mask)) { \
- idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -905,7 +899,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -919,7 +913,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag2 | tmp_tag; \
- idx = (set2 << L.assoc_bits) | tmp_tag; \
+ idx = (set2 * L.assoc) + tmp_tag; \
miss2 = update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
@@ -984,7 +978,7 @@
CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
{
UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
- UWord* set = &(L2.tags[setNo << L2.assoc_bits]);
+ UWord* set = &(L2.tags[setNo * L2.assoc]);
UWord tag = memline & L2.tag_mask;
int i, j, idx;
@@ -993,7 +987,7 @@
CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
- idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1008,7 +1002,7 @@
set[j] = set[j - 1];
}
set[0] = tmp_tag;
- idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1024,7 +1018,7 @@
set[j] = set[j - 1];
}
set[0] = tag | tmp_tag;
- idx = (setNo << L2.assoc_bits) | tmp_tag;
+ idx = (setNo * L2.assoc) + tmp_tag;
l1_loaded->dep_use = &(L2.use[idx]);
update_L2_use(idx, memline);
@@ -1380,23 +1374,16 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
- VG_(exit)(1);
+ "error: %s set count not a power of two; aborting.",
+ name);
}
- if (-1 == VG_(log2)(cache->assoc)) {
+ if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
- if (-1 == VG_(log2)(cache->line_size)) {
- VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
name, cache->line_size);
VG_(exit)(1);
Modified: branches/DARWIN/callgrind/tests/Makefile.am
===================================================================
--- branches/DARWIN/callgrind/tests/Makefile.am 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/tests/Makefile.am 2009-01-26 23:26:20 UTC (rev 9082)
@@ -11,6 +11,10 @@
simwork1.vgtest simwork1.stdout.exp simwork1.stderr.exp \
simwork2.vgtest simwork2.stdout.exp simwork2.stderr.exp \
simwork3.vgtest simwork3.stdout.exp simwork3.stderr.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ notpower2-wb.vgtest notpower2-wb.stderr.exp \
+ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
+ notpower2-use.vgtest notpower2-use.stderr.exp \
threads.vgtest threads.stderr.exp
check_PROGRAMS = clreq simwork threads
Modified: branches/DARWIN/callgrind/tests/filter_stderr
===================================================================
--- branches/DARWIN/callgrind/tests/filter_stderr 2009-01-26 23:21:18 UTC (rev 9081)
+++ branches/DARWIN/callgrind/tests/filter_stderr 2009-01-26 23:26:20 UTC (rev 9082)
@@ -23,5 +23,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Copied: branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-hwpref.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-hwpref.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-hwpref.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-hwpref.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-hwpref=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-use.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-use.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-use.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-use.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-use.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-use.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --cacheuse=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2-wb.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-wb.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2-wb.vgtest (from rev 9080, trunk/callgrind/tests/notpower2-wb.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2-wb.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2-wb.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-wb=yes
+cleanup: rm callgrind.out.*
Copied: branches/DARWIN/callgrind/tests/notpower2.stderr.exp (from rev 9080, trunk/callgrind/tests/notpower2.stderr.exp)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2.stderr.exp (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2.stderr.exp 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Copied: branches/DARWIN/callgrind/tests/notpower2.vgtest (from rev 9080, trunk/callgrind/tests/notpower2.vgtest)
===================================================================
--- branches/DARWIN/callgrind/tests/notpower2.vgtest (rev 0)
+++ branches/DARWIN/callgrind/tests/notpower2.vgtest 2009-01-26 23:26:20 UTC (rev 9082)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm callgrind.out.*
|
|
From: <sv...@va...> - 2009-01-26 23:21:24
|
Author: weidendo
Date: 2009-01-26 23:21:18 +0000 (Mon, 26 Jan 2009)
New Revision: 9081
Log:
Callgrind: Remove ifdef'ed-out, non-working code.
Rechecking the diff of r9080 on the mailing list, I thought
I forgot to replace "|" with "+" in one spot. But that was part
of not-used code, so it actually does not matter.
So better get rid of this code part at all (no need to backport ;-).
Modified:
trunk/callgrind/sim.c
Modified: trunk/callgrind/sim.c
===================================================================
--- trunk/callgrind/sim.c 2009-01-26 22:56:14 UTC (rev 9080)
+++ trunk/callgrind/sim.c 2009-01-26 23:21:18 UTC (rev 9081)
@@ -680,102 +680,7 @@
}
}
-/* FIXME: A little tricky */
-#if 0
-static __inline__
-void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
-{
- int idx = (high_idx * c->assoc) + low_idx;
-
- c->use[idx].count ++;
- c->use[idx].mask |= use_mask;
-
- CLG_DEBUG(6," Hit [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",
- idx, c->loaded[idx].memline, c->loaded[idx].iaddr,
- use_mask, c->use[idx].mask, c->use[idx].count);
-}
-
-/* only used for I1, D1 */
-
-static __inline__
-CacheResult cacheuse_setref(cache_t2* c, UInt set_no, UWord tag)
-{
- int i, j, idx;
- UWord *set, tmp_tag;
- UInt use_mask;
-
- set = &(c->tags[set_no * c->assoc]);
- use_mask =
- c->line_start_mask[a & c->line_size_mask] &
- c->line_end_mask[(a+size-1) & c->line_size_mask];
-
- /* This loop is unrolled for just the first case, which is the most */
- /* common. We can't unroll any further because it would screw up */
- /* if we have a direct-mapped (1-way) cache. */
- if (tag == (set[0] & c->tag_mask)) {
- cacheuse_update(c, set_no, set[0] & ~c->tag_mask, use_mask);
- return L1_Hit;
- }
-
- /* If the tag is one other than the MRU, move it into the MRU spot */
- /* and shuffle the rest down. */
- for (i = 1; i < c->assoc; i++) {
- if (tag == (set[i] & c->tag_mask)) {
- tmp_tag = set[i];
- for (j = i; j > 0; j--) {
- set[j] = set[j - 1];
- }
- set[0] = tmp_tag;
-
- cacheuse_update(c, set_no, tmp_tag & ~c->tag_mask, use_mask);
- return L1_Hit;
- }
- }
-
- /* A miss; install this tag as MRU, shuffle rest down. */
- tmp_tag = set[L.assoc - 1] & ~c->tag_mask;
- for (j = c->assoc - 1; j > 0; j--) {
- set[j] = set[j - 1];
- }
- set[0] = tag | tmp_tag;
-
- cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
- use_mask, a & ~c->line_size_mask);
-
- return Miss;
-}
-
-
-static CacheResult cacheuse_ref(cache_t2* c, Addr a, UChar size)
-{
- UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
- UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a & c->tag_mask;
-
- /* Access entirely within line. */
- if (set1 == set2)
- return cacheuse_setref(c, set1, tag);
-
- /* Access straddles two lines. */
- /* Nb: this is a fast way of doing ((set1+1) % c->sets) */
- else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a & c->tag_mask;
-
- /* the call updates cache structures as side effect */
- CacheResult res1 = cacheuse_isMiss(c, set1, tag);
- CacheResult res2 = cacheuse_isMiss(c, set2, tag2);
- return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
-
- } else {
- VG_(printf)("addr: %x size: %u sets: %d %d", a, size, set1, set2);
- VG_(tool_panic)("item straddles more than two cache sets");
- }
- return Hit;
-}
-#endif
-
-
/* for I1/D1 caches */
#define CACHEUSE(L) \
\
|
|
From: <sv...@va...> - 2009-01-26 23:07:46
|
Author: njn
Date: 2009-01-26 21:51:35 +0000 (Mon, 26 Jan 2009)
New Revision: 9079
Log:
Comment out various m_mach pieces that aren't used.
Modified:
branches/DARWIN/coregrind/Makefile.am
branches/DARWIN/coregrind/m_mach/mach_basics.c
branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S
Modified: branches/DARWIN/coregrind/Makefile.am
===================================================================
--- branches/DARWIN/coregrind/Makefile.am 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
@@ -70,22 +70,39 @@
endif
# Mach RPC interface definitions
+# DDD: these ones aren't used...
+# clock.defs \
+# clock_priv.defs \
+# clock_reply.defs \
+# exc.defs \
+# host_priv.defs \
+# host_security.defs \
+# ledger.defs \
+# lock_set.defs \
+# mach_host.defs \
+# mach_port.defs \
+# notify.defs \
+# processor.defs \
+# processor_set.defs \
+#
+# mach_vm:
+# - mach_vm_protect is used in debugstub-darwin.c.
+# - mach_vm_region_recurse is used in aspacemgr-linux.c
+#
+# task:
+# - thread_create_running is used in debugstub-darwin.c
+# - semaphore_create is used in sema.c, syswrap-darwin.c
+# - semaphore_destroy is used in sema.c, syswrap-darwin.c
+#
+# thread_act:
+# - thread_get_state is used in scheduler.c
+# - thread_abort is used in debugstub-darwin.c
+#
+# vm_map:
+# - vm_deallocate is used in syswrap-darwin.c
if VGCONF_OS_IS_DARWIN
mach_defs = \
- clock.defs \
- clock_priv.defs \
- clock_reply.defs \
- exc.defs \
- host_priv.defs \
- host_security.defs \
- ledger.defs \
- lock_set.defs \
- mach_host.defs \
- mach_port.defs \
mach_vm.defs \
- notify.defs \
- processor.defs \
- processor_set.defs \
task.defs \
thread_act.defs \
vm_map.defs
@@ -307,6 +324,21 @@
# Note that the *User.c files are generated using 'mig' from $mach_defs
# above.
+ # DDD: these ones aren't generated (see above)...
+ # m_mach/clockUser.c \
+ # m_mach/clock_privUser.c \
+ # m_mach/clock_replyUser.c \
+ # m_mach/excUser.c \
+ # m_mach/host_privUser.c \
+ # m_mach/host_securityUser.c \
+ # m_mach/ledgerUser.c \
+ # m_mach/lock_setUser.c \
+ # m_mach/mach_hostUser.c \
+ # m_mach/mach_portUser.c \
+ # m_mach/notifyUser.c \
+ # m_mach/processorUser.c \
+ # m_mach/processor_setUser.c \
+ #
COREGRIND_DARWIN_SOURCE = \
m_aspacemgr/aspacemgr-linux.c \
m_debuginfo/readdwarf.c \
@@ -314,23 +346,10 @@
m_debuginfo/readstabs.c \
m_debuginfo/readmacho.c \
m_debugstub/debugstub-darwin.c \
- m_mach/clockUser.c \
- m_mach/clock_privUser.c \
- m_mach/clock_replyUser.c \
- m_mach/excUser.c \
- m_mach/host_privUser.c \
- m_mach/host_securityUser.c \
- m_mach/ledgerUser.c \
- m_mach/lock_setUser.c \
- m_mach/mach_hostUser.c \
- m_mach/mach_portUser.c \
m_mach/mach_vmUser.c \
- m_mach/notifyUser.c \
- m_mach/processorUser.c \
- m_mach/processor_setUser.c \
m_mach/taskUser.c \
- m_mach/thread_actUser.c \
- m_mach/vm_mapUser.c \
+ m_mach/thread_actUser.c \
+ m_mach/vm_mapUser.c \
m_mach/mach_basics.c \
m_mach/mach_msg.c \
m_initimg/initimg-darwin.c \
Modified: branches/DARWIN/coregrind/m_mach/mach_basics.c
===================================================================
--- branches/DARWIN/coregrind/m_mach/mach_basics.c 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/m_mach/mach_basics.c 2009-01-26 21:51:35 UTC (rev 9079)
@@ -37,7 +37,7 @@
#include <mach/machine/ndr_def.h>
/* From mach_traps-<arch>-darwin.S */
-extern mach_port_name_t host_self_trap(void);
+//extern mach_port_name_t host_self_trap(void);
extern mach_port_name_t thread_self_trap(void);
extern mach_port_t mach_reply_port(void);
@@ -46,10 +46,11 @@
mach_port_name_t mach_task_self_ = 0;
-mach_port_name_t mach_host_self(void)
-{
- return host_self_trap();
-}
+// DDD: doesn't get used...
+//mach_port_name_t mach_host_self(void)
+//{
+// return host_self_trap();
+//}
mach_port_name_t mach_thread_self(void)
Modified: branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S
===================================================================
--- branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S 2009-01-26 16:01:19 UTC (rev 9078)
+++ branches/DARWIN/coregrind/m_mach/mach_traps-amd64-darwin.S 2009-01-26 21:51:35 UTC (rev 9079)
@@ -39,15 +39,16 @@
syscall
ret
- // mach_port_name_t host_self_trap(void)
- .text
- .align 4
- .globl _host_self_trap
-_host_self_trap:
- movq $__NR_host_self_trap, %rax
- movq %rcx, %r10
- syscall
- ret
+// DDD: doesn't get used...
+// // mach_port_name_t host_self_trap(void)
+// .text
+// .align 4
+// .globl _host_self_trap
+//_host_self_trap:
+// movq $__NR_host_self_trap, %rax
+// movq %rcx, %r10
+// syscall
+// ret
// mach_port_name_t thread_self_trap(void)
.text
|
|
From: <sv...@va...> - 2009-01-26 22:56:20
|
Author: weidendo
Date: 2009-01-26 22:56:14 +0000 (Mon, 26 Jan 2009)
New Revision: 9080
Log:
Cachegrind/Callgrind: allow for cache sizes other than only powers of two
The number of sets, ie. number of cache lines divided by associativity,
and the cache line size still have to be powers of two.
This change is needed for default cache parameters used on some Intel
Core 2 and Atom processors.
Includes cachegrind manual update and explicit tests with 24KB D1/3MB L2
Reverts addition of 6MB warning to {cachegrind,callgrind}/tests/filter_stderr
Backporting to VALGRIND_3_4_BRANCH needs r8912
Added:
trunk/cachegrind/tests/notpower2.stderr.exp
trunk/cachegrind/tests/notpower2.vgtest
trunk/callgrind/tests/notpower2-hwpref.stderr.exp
trunk/callgrind/tests/notpower2-hwpref.vgtest
trunk/callgrind/tests/notpower2-use.stderr.exp
trunk/callgrind/tests/notpower2-use.vgtest
trunk/callgrind/tests/notpower2-wb.stderr.exp
trunk/callgrind/tests/notpower2-wb.vgtest
trunk/callgrind/tests/notpower2.stderr.exp
trunk/callgrind/tests/notpower2.vgtest
Modified:
trunk/cachegrind/cg-x86.c
trunk/cachegrind/cg_main.c
trunk/cachegrind/cg_sim.c
trunk/cachegrind/docs/cg-manual.xml
trunk/cachegrind/tests/Makefile.am
trunk/cachegrind/tests/filter_stderr
trunk/callgrind/sim.c
trunk/callgrind/tests/Makefile.am
trunk/callgrind/tests/filter_stderr
Modified: trunk/cachegrind/cg-x86.c
===================================================================
--- trunk/cachegrind/cg-x86.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg-x86.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -113,12 +113,7 @@
case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break;
case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;
- case 0x0e:
- /* Real D1 cache configuration is:
- D1c = (cache_t) { 24, 6, 64 }; */
- VG_(message)(Vg_DebugMsg, "warning: 24Kb D1 cache detected, treating as 16Kb");
- *D1c = (cache_t) { 16, 4, 64 };
- break;
+ case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break;
case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;
/* IA-64 info -- panic! */
@@ -149,12 +144,7 @@
case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break;
case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break;
case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break;
- case 0x48:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
- *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
- break;
+ case 0x48: *L2c = (cache_t) { 3072,12, 64 }; L2_found = True; break;
case 0x49:
if ((family == 15) && (model == 6))
/* On Xeon MP (family F, model 6), this is for L3 */
@@ -163,12 +153,7 @@
else
*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
break;
- case 0x4e:
- /* Real L2 cache configuration is:
- *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
- VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
- *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
- break;
+ case 0x4e: *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; break;
/* These are sectored, whatever that means */
case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
Modified: trunk/cachegrind/cg_main.c
===================================================================
--- trunk/cachegrind/cg_main.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg_main.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -1158,21 +1158,15 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
+ "error: %s set count not a power of two; aborting.",
+ name);
VG_(exit)(1);
}
- if (-1 == VG_(log2)(cache->assoc)) {
- VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
Modified: trunk/cachegrind/cg_sim.c
===================================================================
--- trunk/cachegrind/cg_sim.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/cg_sim.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -44,7 +44,6 @@
Int line_size; /* bytes */
Int sets;
Int sets_min_1;
- Int assoc_bits;
Int line_size_bits;
Int tag_shift;
Char desc_line[128];
@@ -62,7 +61,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
@@ -111,8 +109,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
\
/* This loop is unrolled for just the first case, which is the most */\
/* common. We can't unroll any further because it would screw up */\
@@ -143,7 +140,7 @@
/* Second case: word straddles two lines. */ \
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
if (tag == set[0]) { \
goto block2; \
} \
@@ -162,7 +159,7 @@
set[0] = tag; \
is_miss = True; \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
tag2 = (a+size-1) >> L.tag_shift; \
if (tag2 == set[0]) { \
goto miss_treatment; \
Modified: trunk/cachegrind/docs/cg-manual.xml
===================================================================
--- trunk/cachegrind/docs/cg-manual.xml 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/docs/cg-manual.xml 2009-01-26 22:56:14 UTC (rev 9080)
@@ -142,7 +142,7 @@
</listitem>
<listitem>
- <para>Bit-selection hash function: the line(s) in the cache
+ <para>Bit-selection hash function: the set of line(s) in the cache
to which a memory block maps is chosen by the middle bits
M--(M+N-1) of the byte address, where:</para>
<itemizedlist>
@@ -150,15 +150,17 @@
<para>line size = 2^M bytes</para>
</listitem>
<listitem>
- <para>(cache size / line size) = 2^N bytes</para>
+ <para>(cache size / line size / associativity) = 2^N bytes</para>
</listitem>
</itemizedlist>
</listitem>
<listitem>
- <para>Inclusive L2 cache: the L2 cache replicates all the
- entries of the L1 cache. This is standard on Pentium chips,
- but AMD Opterons, Athlons and Durons
+ <para>Inclusive L2 cache: the L2 cache typically replicates all
+ the entries of the L1 caches, because fetching into L1 involves
+ fetching into L2 first (this does not guarantee strict inclusiveness,
+ as lines evicted from L2 still could reside in L1). This is
+ standard on Pentium chips, but AMD Opterons, Athlons and Durons
use an exclusive L2 cache that only holds
blocks evicted from L1. Ditto most modern VIA CPUs.</para>
</listitem>
@@ -176,7 +178,10 @@
(I1/D1/L2) of the cache from the command line using the
<computeroutput>--I1</computeroutput>,
<computeroutput>--D1</computeroutput> and
-<computeroutput>--L2</computeroutput> options.</para>
+<computeroutput>--L2</computeroutput> options.
+For cache parameters to be valid for simulation, the number
+of sets (with associativity being the number of cache lines in
+each set) has to be a power of two.</para>
<para>On PowerPC platforms
Cachegrind cannot automatically
@@ -227,10 +232,7 @@
<para>If you are interested in simulating a cache with different
properties, it is not particularly hard to write your own cache
simulator, or to modify the existing ones in
-<computeroutput>vg_cachesim_I1.c</computeroutput>,
-<computeroutput>vg_cachesim_D1.c</computeroutput>,
-<computeroutput>vg_cachesim_L2.c</computeroutput> and
-<computeroutput>vg_cachesim_gen.c</computeroutput>. We'd be
+<computeroutput>cg_sim.c</computeroutput>. We'd be
interested to hear from anyone who does.</para>
</sect2>
Modified: trunk/cachegrind/tests/Makefile.am
===================================================================
--- trunk/cachegrind/tests/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/tests/Makefile.am 2009-01-26 22:56:14 UTC (rev 9080)
@@ -15,6 +15,7 @@
chdir.vgtest chdir.stderr.exp \
clreq.vgtest clreq.stderr.exp \
dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \
+ notpower2.vgtest notpower2.stderr.exp \
wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp
check_PROGRAMS = \
Modified: trunk/cachegrind/tests/filter_stderr
===================================================================
--- trunk/cachegrind/tests/filter_stderr 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/cachegrind/tests/filter_stderr 2009-01-26 22:56:14 UTC (rev 9080)
@@ -17,5 +17,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Added: trunk/cachegrind/tests/notpower2.stderr.exp
===================================================================
--- trunk/cachegrind/tests/notpower2.stderr.exp (rev 0)
+++ trunk/cachegrind/tests/notpower2.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,17 @@
+
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/cachegrind/tests/notpower2.vgtest
===================================================================
--- trunk/cachegrind/tests/notpower2.vgtest (rev 0)
+++ trunk/cachegrind/tests/notpower2.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm cachegrind.out.*
Modified: trunk/callgrind/sim.c
===================================================================
--- trunk/callgrind/sim.c 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/sim.c 2009-01-26 22:56:14 UTC (rev 9080)
@@ -74,7 +74,6 @@
Bool sectored; /* prefetch nearside cacheline on read */
int sets;
int sets_min_1;
- int assoc_bits;
int line_size_bits;
int tag_shift;
UWord tag_mask;
@@ -195,7 +194,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
c->tag_mask = ~((1<<c->tag_shift)-1);
@@ -259,8 +257,7 @@
int i, j;
UWord *set;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -359,8 +356,7 @@
int i, j;
UWord *set, tmp_tag;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -407,7 +403,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = (a+size-1) >> c->tag_shift;
+ UWord tag2 = (a+size-1) & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
@@ -676,7 +672,7 @@
/* We use lower tag bits as offset pointers to cache use info.
* I.e. some cache parameters don't work.
*/
- if (c->tag_shift < c->assoc_bits) {
+ if ( (1<<c->tag_shift) < c->assoc) {
VG_(message)(Vg_DebugMsg,
"error: Use associativity < %d for cache use statistics!",
(1<<c->tag_shift) );
@@ -690,7 +686,7 @@
static __inline__
void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
{
- int idx = (high_idx << c->assoc_bits) | low_idx;
+ int idx = (high_idx * c->assoc) + low_idx;
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
@@ -709,8 +705,7 @@
UWord *set, tmp_tag;
UInt use_mask;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
use_mask =
c->line_start_mask[a & c->line_size_mask] &
c->line_end_mask[(a+size-1) & c->line_size_mask];
@@ -745,7 +740,7 @@
}
set[0] = tag | tmp_tag;
- cacheuse_L2_miss(c, (set_no << c->assoc_bits) | tmp_tag,
+ cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
use_mask, a & ~c->line_size_mask);
return Miss;
@@ -756,7 +751,7 @@
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a >> c->tag_shift;
+ UWord tag = a & c->tag_mask;
/* Access entirely within line. */
if (set1 == set2)
@@ -765,7 +760,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a >> c->tag_shift;
+ UWord tag2 = a & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cacheuse_isMiss(c, set1, tag);
@@ -800,8 +795,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask] & \
L.line_end_mask[(a+size-1) & L.line_size_mask]; \
\
@@ -809,7 +803,7 @@
/* common. We can't unroll any further because it would screw up */\
/* if we have a direct-mapped (1-way) cache. */\
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -826,7 +820,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -842,7 +836,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
return update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
\
@@ -850,10 +844,10 @@
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask]; \
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -868,7 +862,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -882,15 +876,15 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
miss1 = update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
tag2 = (a+size-1) & L.tag_mask; \
if (tag2 == (set[0] & L.tag_mask)) { \
- idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -905,7 +899,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -919,7 +913,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag2 | tmp_tag; \
- idx = (set2 << L.assoc_bits) | tmp_tag; \
+ idx = (set2 * L.assoc) + tmp_tag; \
miss2 = update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
@@ -984,7 +978,7 @@
CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
{
UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
- UWord* set = &(L2.tags[setNo << L2.assoc_bits]);
+ UWord* set = &(L2.tags[setNo * L2.assoc]);
UWord tag = memline & L2.tag_mask;
int i, j, idx;
@@ -993,7 +987,7 @@
CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
- idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1008,7 +1002,7 @@
set[j] = set[j - 1];
}
set[0] = tmp_tag;
- idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1024,7 +1018,7 @@
set[j] = set[j - 1];
}
set[0] = tag | tmp_tag;
- idx = (setNo << L2.assoc_bits) | tmp_tag;
+ idx = (setNo * L2.assoc) + tmp_tag;
l1_loaded->dep_use = &(L2.use[idx]);
update_L2_use(idx, memline);
@@ -1380,23 +1374,16 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
- VG_(exit)(1);
+ "error: %s set count not a power of two; aborting.",
+ name);
}
- if (-1 == VG_(log2)(cache->assoc)) {
+ if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
- if (-1 == VG_(log2)(cache->line_size)) {
- VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
name, cache->line_size);
VG_(exit)(1);
Modified: trunk/callgrind/tests/Makefile.am
===================================================================
--- trunk/callgrind/tests/Makefile.am 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/tests/Makefile.am 2009-01-26 22:56:14 UTC (rev 9080)
@@ -11,6 +11,10 @@
simwork1.vgtest simwork1.stdout.exp simwork1.stderr.exp \
simwork2.vgtest simwork2.stdout.exp simwork2.stderr.exp \
simwork3.vgtest simwork3.stdout.exp simwork3.stderr.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ notpower2-wb.vgtest notpower2-wb.stderr.exp \
+ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
+ notpower2-use.vgtest notpower2-use.stderr.exp \
threads.vgtest threads.stderr.exp
check_PROGRAMS = clreq simwork threads
Modified: trunk/callgrind/tests/filter_stderr
===================================================================
--- trunk/callgrind/tests/filter_stderr 2009-01-26 21:51:35 UTC (rev 9079)
+++ trunk/callgrind/tests/filter_stderr 2009-01-26 22:56:14 UTC (rev 9080)
@@ -23,5 +23,4 @@
sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
sed "/warning: L3 cache detected but ignored/d" |
-sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
Added: trunk/callgrind/tests/notpower2-hwpref.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-hwpref.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-hwpref.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-hwpref.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-hwpref.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-hwpref.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-hwpref=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2-use.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-use.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-use.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-use.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-use.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-use.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --cacheuse=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2-wb.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2-wb.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2-wb.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2-wb.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2-wb.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2-wb.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-wb=yes
+cleanup: rm callgrind.out.*
Added: trunk/callgrind/tests/notpower2.stderr.exp
===================================================================
--- trunk/callgrind/tests/notpower2.stderr.exp (rev 0)
+++ trunk/callgrind/tests/notpower2.stderr.exp 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,20 @@
+
+
+Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I refs:
+I1 misses:
+L2i misses:
+I1 miss rate:
+L2i miss rate:
+
+D refs:
+D1 misses:
+L2d misses:
+D1 miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
Added: trunk/callgrind/tests/notpower2.vgtest
===================================================================
--- trunk/callgrind/tests/notpower2.vgtest (rev 0)
+++ trunk/callgrind/tests/notpower2.vgtest 2009-01-26 22:56:14 UTC (rev 9080)
@@ -0,0 +1,3 @@
+prog: ../../tests/true
+vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64
+cleanup: rm callgrind.out.*
|
|
From: Nicholas N. <n.n...@gm...> - 2009-01-26 22:43:29
|
On Tue, Jan 27, 2009 at 2:45 AM, Konstantin Serebryany <kon...@gm...> wrote: > > Did you ever think that two data race detectors (Helgrind and Drd) is > too much for the Valgrind project? > In fact, I think that two is too few. :) > > Please welcome ThreadSanitizer, yet another data race detector based > on Valgrind. > http://code.google.com/p/data-race-test/wiki/ThreadSanitizer > > I'd appreciate your feedback, How similar is it to Helgrind -- could it conceivably be folded into Helgrind? Nick |
|
From: <sv...@va...> - 2009-01-26 16:01:23
|
Author: sewardj
Date: 2009-01-26 16:01:19 +0000 (Mon, 26 Jan 2009)
New Revision: 9078
Log:
merge r8945:
Do not only intercept SIGILL during detection of the supported
instruction set on ppc but also SIGFPE.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c 2009-01-26 15:45:59 UTC (rev 9077)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_machine.c 2009-01-26 16:01:19 UTC (rev 9078)
@@ -35,7 +35,8 @@
#include "pub_core_libcbase.h"
#include "pub_core_machine.h"
#include "pub_core_cpuid.h"
-#include "pub_core_libcsignal.h" // for ppc32 messing with SIGILL
+#include "pub_core_libcsignal.h" // for ppc32 messing with SIGILL and SIGFPE
+#include "pub_core_debuglog.h"
#define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
@@ -333,8 +334,8 @@
#if defined(VGA_ppc32) || defined(VGA_ppc64)
#include <setjmp.h> // For jmp_buf
-static jmp_buf env_sigill;
-static void handler_sigill ( Int x ) { __builtin_longjmp(env_sigill,1); }
+static jmp_buf env_unsup_insn;
+static void handler_unsup_insn ( Int x ) { __builtin_longjmp(env_unsup_insn,1); }
#endif
Bool VG_(machine_get_hwcaps)( void )
@@ -393,38 +394,55 @@
return True;
#elif defined(VGA_ppc32)
- { /* ppc32 doesn't seem to have a sane way to find out what insn
- sets the CPU supports. So we have to arse around with
- SIGILLs. Yuck. */
+ {
+ /* Find out which subset of the ppc32 instruction set is supported by
+ verifying whether various ppc32 instructions generate a SIGILL
+ or a SIGFPE. An alternative approach is to check the AT_HWCAP and
+ AT_PLATFORM entries in the ELF auxiliary table -- see also
+ the_iifii.client_auxv in m_main.c.
+ */
vki_sigset_t saved_set, tmp_set;
- struct vki_sigaction saved_act, tmp_act;
+ struct vki_sigaction saved_sigill_act, tmp_sigill_act;
+ struct vki_sigaction saved_sigfpe_act, tmp_sigfpe_act;
volatile Bool have_F, have_V, have_FX, have_GX;
Int r;
VG_(sigemptyset)(&tmp_set);
VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+ VG_(sigaddset)(&tmp_set, VKI_SIGFPE);
r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
vg_assert(r == 0);
- r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_act);
+ r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act);
vg_assert(r == 0);
- tmp_act = saved_act;
+ tmp_sigill_act = saved_sigill_act;
+ r = VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act);
+ vg_assert(r == 0);
+ tmp_sigfpe_act = saved_sigfpe_act;
+
/* NODEFER: signal handler does not return (from the kernel's point of
view), hence if it is to successfully catch a signal more than once,
we need the NODEFER flag. */
- tmp_act.sa_flags &= ~VKI_SA_RESETHAND;
- tmp_act.sa_flags &= ~VKI_SA_SIGINFO;
- tmp_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigill_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.ksa_handler = handler_unsup_insn;
+ r = VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+ vg_assert(r == 0);
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigfpe_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
+ r = VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+ vg_assert(r == 0);
+
/* standard FP insns */
have_F = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_F = False;
} else {
__asm__ __volatile__(".long 0xFC000090"); /*fmr 0,0 */
@@ -432,10 +450,7 @@
/* Altivec insns */
have_V = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_V = False;
} else {
/* Unfortunately some older assemblers don't speak Altivec (or
@@ -448,10 +463,7 @@
/* General-Purpose optional (fsqrt, fsqrts) */
have_FX = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_FX = False;
} else {
__asm__ __volatile__(".long 0xFC00002C"); /*fsqrt 0,0 */
@@ -459,23 +471,20 @@
/* Graphics optional (stfiwx, fres, frsqrte, fsel) */
have_GX = True;
- tmp_act.ksa_handler = handler_sigill;
- r = VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- vg_assert(r == 0);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_GX = False;
} else {
__asm__ __volatile__(".long 0xFC000034"); /* frsqrte 0,0 */
}
- r = VG_(sigaction)(VKI_SIGILL, &saved_act, NULL);
+ r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
vg_assert(r == 0);
+ r = VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
+ vg_assert(r == 0);
r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
vg_assert(r == 0);
- /*
- VG_(printf)("F %d V %d FX %d GX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX);
- */
/* Make FP a prerequisite for VMX (bogusly so), and for FX and GX. */
if (have_V && !have_F)
have_V = False;
@@ -501,32 +510,45 @@
}
#elif defined(VGA_ppc64)
- { /* Same idiocy as for ppc32 - arse around with SIGILLs. */
+ {
+ /* Same instruction set detection algorithm as for ppc32. */
vki_sigset_t saved_set, tmp_set;
- struct vki_sigaction saved_act, tmp_act;
+ struct vki_sigaction saved_sigill_act, tmp_sigill_act;
+ struct vki_sigaction saved_sigfpe_act, tmp_sigfpe_act;
volatile Bool have_F, have_V, have_FX, have_GX;
VG_(sigemptyset)(&tmp_set);
VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+ VG_(sigaddset)(&tmp_set, VKI_SIGFPE);
VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
- VG_(sigaction)(VKI_SIGILL, NULL, &saved_act);
- tmp_act = saved_act;
+ VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act);
+ tmp_sigill_act = saved_sigill_act;
+ VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act);
+ tmp_sigfpe_act = saved_sigfpe_act;
+
+
/* NODEFER: signal handler does not return (from the kernel's point of
view), hence if it is to successfully catch a signal more than once,
we need the NODEFER flag. */
- tmp_act.sa_flags &= ~VKI_SA_RESETHAND;
- tmp_act.sa_flags &= ~VKI_SA_SIGINFO;
- tmp_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigill_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigill_act.ksa_handler = handler_unsup_insn;
+ VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND;
+ tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO;
+ tmp_sigfpe_act.sa_flags |= VKI_SA_NODEFER;
+ tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
+ VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+
/* standard FP insns */
have_F = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_F = False;
} else {
__asm__ __volatile__("fmr 0,0");
@@ -534,9 +556,7 @@
/* Altivec insns */
have_V = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_V = False;
} else {
__asm__ __volatile__(".long 0x10000484"); /*vor 0,0,0*/
@@ -544,9 +564,7 @@
/* General-Purpose optional (fsqrt, fsqrts) */
have_FX = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_FX = False;
} else {
__asm__ __volatile__(".long 0xFC00002C"); /*fsqrt 0,0*/
@@ -554,21 +572,17 @@
/* Graphics optional (stfiwx, fres, frsqrte, fsel) */
have_GX = True;
- tmp_act.ksa_handler = handler_sigill;
- VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
- if (__builtin_setjmp(env_sigill)) {
+ if (__builtin_setjmp(env_unsup_insn)) {
have_GX = False;
} else {
__asm__ __volatile__(".long 0xFC000034"); /*frsqrte 0,0*/
}
- VG_(sigaction)(VKI_SIGILL, &saved_act, NULL);
+ VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
+ VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
- /*
- if (0)
- VG_(printf)("F %d V %d FX %d GX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX);
- */
/* on ppc64, if we don't even have FP, just give up. */
if (!have_F)
return False;
|
|
From: <sv...@va...> - 2009-01-26 15:54:09
|
Author: sewardj
Date: 2009-01-26 15:54:03 +0000 (Mon, 26 Jan 2009)
New Revision: 1883
Log:
merge r1882: Handle redundant REX.W on PUNPCKHgg. #173751.
Modified:
branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c 2009-01-24 10:34:19 UTC (rev 1882)
+++ branches/VEX_3_4_BRANCH/priv/guest-amd64/toIR.c 2009-01-26 15:54:03 UTC (rev 1883)
@@ -6594,7 +6594,8 @@
case 0x68:
case 0x69:
case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
- if (sz != 4)
+ if (sz != 4
+ && /*ignore redundant REX.W*/!(sz==8 && haveNo66noF2noF3(pfx)))
goto mmx_decode_failure;
delta = dis_MMXop_regmem_to_reg ( vbi, pfx, delta, opc, "punpckh", True );
break;
|
|
From: Konstantin S. <kon...@gm...> - 2009-01-26 15:46:02
|
Hello Valgrind developers, Did you ever think that two data race detectors (Helgrind and Drd) is too much for the Valgrind project? In fact, I think that two is too few. :) Please welcome ThreadSanitizer, yet another data race detector based on Valgrind. http://code.google.com/p/data-race-test/wiki/ThreadSanitizer I'd appreciate your feedback, Thanks, --kcc |
|
From: <sv...@va...> - 2009-01-26 15:13:47
|
Author: sewardj
Date: 2009-01-26 15:13:44 +0000 (Mon, 26 Jan 2009)
New Revision: 9076
Log:
merge r9063 Helgrind: Initialise laog and laog__exposition (properly).
Modified:
branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c
Modified: branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c 2009-01-26 15:08:46 UTC (rev 9075)
+++ branches/VALGRIND_3_4_BRANCH/helgrind/hg_main.c 2009-01-26 15:13:44 UTC (rev 9076)
@@ -2849,6 +2849,21 @@
/* end EXPOSITION ONLY */
+__attribute__((noinline))
+static void laog__init ( void )
+{
+ tl_assert(!laog);
+ tl_assert(!laog_exposition);
+
+ laog = VG_(newFM)( HG_(zalloc), "hg.laog__init.1",
+ HG_(free), NULL/*unboxedcmp*/ );
+
+ laog_exposition = VG_(newFM)( HG_(zalloc), "hg.laog__init.2", HG_(free),
+ cmp_LAOGLinkExposition );
+ tl_assert(laog);
+ tl_assert(laog_exposition);
+}
+
static void laog__show ( Char* who ) {
Word i, ws_size;
UWord* ws_words;
@@ -3015,8 +3030,8 @@
UWord* ws_words;
Lock* me;
LAOGLinks* links;
- if ( !laog )
- return; /* nothing much we can do */
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
VG_(initIterFM)( laog );
me = NULL;
links = NULL;
@@ -3128,12 +3143,8 @@
if (HG_(elemWS)( univ_lsets, thr->locksetA, (Word)lk ))
return;
- if (!laog)
- laog = VG_(newFM)( HG_(zalloc), "hg.lptal.1",
- HG_(free), NULL/*unboxedcmp*/ );
- if (!laog_exposition)
- laog_exposition = VG_(newFM)( HG_(zalloc), "hg.lptal.2", HG_(free),
- cmp_LAOGLinkExposition );
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
/* First, the check. Complain if there is any path in laog from lk
to any of the locks already held by thr, since if any such path
@@ -3206,6 +3217,9 @@
Word preds_size, succs_size, i, j;
UWord *preds_words, *succs_words;
+ if (UNLIKELY(!laog || !laog_exposition))
+ laog__init();
+
preds = laog__preds( lk );
succs = laog__succs( lk );
@@ -3237,11 +3251,8 @@
// Word i, ws_size;
// UWord* ws_words;
//
-// if (!laog)
-// laog = VG_(newFM)( HG_(zalloc), "hg.lhld.1", HG_(free), NULL/*unboxedcmp*/ );
-// if (!laog_exposition)
-// laog_exposition = VG_(newFM)( HG_(zalloc), "hg.lhld.2", HG_(free),
-// cmp_LAOGLinkExposition );
+// if (UNLIKELY(!laog || !laog_exposition))
+// laog__init();
//
// HG_(getPayloadWS)( &ws_words, &ws_size, univ_lsets, locksToDelete );
// for (i = 0; i < ws_size; i++)
|
|
From: <sv...@va...> - 2009-01-26 15:08:50
|
Author: sewardj
Date: 2009-01-26 15:08:46 +0000 (Mon, 26 Jan 2009)
New Revision: 9075
Log:
merge m9058:
Handle a couple of artefacts produced by icc11:
DW_TAG_reference_type that doesn't have a size, and DW_FORM_ref_addr
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:05:25 UTC (rev 9074)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf3.c 2009-01-26 15:08:46 UTC (rev 9075)
@@ -418,6 +418,9 @@
/* Where is .debug_line? */
UChar* debug_line_img;
UWord debug_line_sz;
+ /* Where is .debug_info? */
+ UChar* debug_info_img;
+ UWord debug_info_sz;
/* --- Needed so we can add stuff to the string table. --- */
struct _DebugInfo* di;
/* --- a cache for set_abbv_Cursor --- */
@@ -901,7 +904,8 @@
/* address size. If this isn't equal to the host word size, just
give up. This makes it safe to assume elsewhere that
- DW_FORM_addr can be treated as a host word. */
+ DW_FORM_addr and DW_FORM_ref_addr can be treated as a host
+ word. */
address_size = get_UChar( c );
if (address_size != sizeof(void*))
cc->barf( "parse_CU_Header: invalid address_size" );
@@ -1083,12 +1087,43 @@
*ctsSzB = sizeof(UWord);
TRACE_D3("0x%lx", (UWord)*cts);
break;
+
+ case DW_FORM_ref_addr:
+ /* We make the same word-size assumption as DW_FORM_addr. */
+ /* What does this really mean? From D3 Sec 7.5.4,
+ description of "reference", it would appear to reference
+ some other DIE, by specifying the offset from the
+ beginning of a .debug_info section. The D3 spec mentions
+ that this might be in some other shared object and
+ executable. But I don't see how the name of the other
+ object/exe is specified.
+
+ At least for the DW_FORM_ref_addrs created by icc11, the
+ references seem to be within the same object/executable.
+ So for the moment we merely range-check, to see that they
+ actually do specify a plausible offset within this
+ object's .debug_info, and return the value unchanged.
+ */
+ *cts = (ULong)(UWord)get_UWord(c);
+ *ctsSzB = sizeof(UWord);
+ TRACE_D3("0x%lx", (UWord)*cts);
+ if (0) VG_(printf)("DW_FORM_ref_addr 0x%lx\n", (UWord)*cts);
+ if (/* the following 2 are surely impossible, but ... */
+ cc->debug_info_img == NULL || cc->debug_info_sz == 0
+ || *cts >= (ULong)cc->debug_info_sz) {
+ /* Hmm. Offset is nonsensical for this object's .debug_info
+ section. Be safe and reject it. */
+ cc->barf("get_Form_contents: DW_FORM_ref_addr points "
+ "outside .debug_info");
+ }
+ break;
+
case DW_FORM_strp: {
/* this is an offset into .debug_str */
UChar* str;
UWord uw = (UWord)get_Dwarfish_UWord( c, cc->is_dw64 );
if (cc->debug_str_img == NULL || uw >= cc->debug_str_sz)
- cc->barf("read_and_show_Form: DW_FORM_strp "
+ cc->barf("get_Form_contents: DW_FORM_strp "
"points outside .debug_str");
/* FIXME: check the entire string lies inside debug_str,
not just the first byte of it. */
@@ -1149,8 +1184,9 @@
break;
}
default:
- VG_(printf)("get_Form_contents: unhandled %d (%s)\n",
- form, ML_(pp_DW_FORM)(form));
+ VG_(printf)(
+ "get_Form_contents: unhandled %d (%s) at <%lx>\n",
+ form, ML_(pp_DW_FORM)(form), get_position_of_Cursor(c));
c->barf("get_Form_contents: unhandled DW_FORM");
}
}
@@ -2184,14 +2220,13 @@
typeE.Te.TyPorR.typeR = D3_FAKEVOID_CUOFF;
typeE.Te.TyPorR.isPtr = dtag == DW_TAG_pointer_type
|| dtag == DW_TAG_ptr_to_member_type;
- /* Pointer types don't *have* to specify their size, in which
- case we assume it's a machine word. But if they do specify
- it, it must be a machine word :-) This probably assumes that
- the word size of the Dwarf3 we're reading is the same size as
- that on the machine. gcc appears to give a size whereas icc9
- doesn't. */
- if (typeE.Te.TyPorR.isPtr)
- typeE.Te.TyPorR.szB = sizeof(Word);
+ /* These three type kinds don't *have* to specify their size, in
+ which case we assume it's a machine word. But if they do
+ specify it, it must be a machine word :-) This probably
+ assumes that the word size of the Dwarf3 we're reading is the
+ same size as that on the machine. gcc appears to give a size
+ whereas icc9 doesn't. */
+ typeE.Te.TyPorR.szB = sizeof(UWord);
while (True) {
DW_AT attr = (DW_AT) get_ULEB128( c_abbv );
DW_FORM form = (DW_FORM)get_ULEB128( c_abbv );
@@ -2206,7 +2241,7 @@
}
}
/* Do we have something that looks sane? */
- if (typeE.Te.TyPorR.szB != sizeof(Word))
+ if (typeE.Te.TyPorR.szB != sizeof(UWord))
goto bad_DIE;
else
goto acquire_Type;
@@ -3437,6 +3472,8 @@
cc.debug_loc_sz = debug_loc_sz;
cc.debug_line_img = debug_line_img;
cc.debug_line_sz = debug_line_sz;
+ cc.debug_info_img = debug_info_img;
+ cc.debug_info_sz = debug_info_sz;
cc.cu_start_offset = cu_start_offset;
cc.di = di;
/* The CU's svma can be deduced by looking at the AT_low_pc
|
|
From: <sv...@va...> - 2009-01-26 15:05:31
|
Author: sewardj
Date: 2009-01-26 15:05:25 +0000 (Mon, 26 Jan 2009)
New Revision: 9074
Log:
merge r9057:
Handle a couple of artefacts generated by gcc-4.4:
DW_OP_reg{0..31} and DW_OP_const1s.
Modified:
branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
Modified: branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c
===================================================================
--- branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 15:02:20 UTC (rev 9073)
+++ branches/VALGRIND_3_4_BRANCH/coregrind/m_debuginfo/readdwarf.c 2009-01-26 15:05:25 UTC (rev 9074)
@@ -2555,6 +2555,16 @@
VG_(printf)("DW_OP_breg%d: %ld", reg, sw);
break;
+ case DW_OP_reg0 ... DW_OP_reg31:
+ /* push: reg */
+ reg = (Int)opcode - (Int)DW_OP_reg0;
+ vg_assert(reg >= 0 && reg <= 31);
+ ix = ML_(CfiExpr_DwReg)( dst, reg );
+ PUSH(ix);
+ if (ddump_frames)
+ VG_(printf)("DW_OP_reg%d", reg);
+ break;
+
case DW_OP_plus_uconst:
uw = read_leb128U( &expr );
PUSH( ML_(CfiExpr_Const)( dst, uw ) );
@@ -2574,6 +2584,15 @@
VG_(printf)("DW_OP_const4s: %ld", sw);
break;
+ case DW_OP_const1s:
+ /* push: 8-bit signed immediate */
+ sw = read_le_s_encoded_literal( expr, 1 );
+ expr += 1;
+ PUSH( ML_(CfiExpr_Const)( dst, (UWord)sw ) );
+ if (ddump_frames)
+ VG_(printf)("DW_OP_const1s: %ld", sw);
+ break;
+
case DW_OP_minus:
op = Cop_Sub; opname = "minus"; goto binop;
case DW_OP_plus:
|