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From: Philippe W. <phi...@sk...> - 2008-02-09 18:25:56
|
From: "Bart Van Assche" <bar...@gm...> Sent: Saturday, February 09, 2008 1:03 PM > <phi...@sk...> wrote: >> The idea is to implement in the valgrind core the "target" side of the >> gdb >> remote debugging protocol > > If you do this it is probably wise to try to find solid documentation > of the gdb remote debugging protocol. I have used gdb remote debugging > extensively while developing software for embedded devices, and I > remember that at that time there were quite some bugs in the protocol > implementation (both client side and server side). For the moment, the unknown factors for me are more related to valgrind core (cfr questions in the original mail). The gdb documentation looks reasonably clear at first sight, but of course it does not mean that it is correct and/or that the implementation of the protocol is correct. At what time did you work with this remote protocol ? Thanks Philippe |
|
From: Bart V. A. <bar...@gm...> - 2008-02-09 16:17:17
|
On Feb 9, 2008 3:46 PM, Julian Seward <js...@ac...> wrote: > > > I'm afraid something is wrong with one of the last commits. When I run > > the regression tests, on some systems all regression tests run fine > > and on other systems all regression tests hang. > > I did do a complete rebuild and regression test run before committing. > The usual cause of strangeness after changes in VEX is because the > dependencies are partially broken and so some stuff that should be > recompiled, isn't. If you make distclean and rebuild from the start, > does that help? After I noticed the hang, I removed the entire Valgrind directory and ran the commands mentioned above. That was not only a clean build, I also fetched the sourcecode again from the repository. Bart. |
|
From: <sv...@va...> - 2008-02-09 14:51:47
|
Author: sewardj Date: 2008-02-09 14:51:41 +0000 (Sat, 09 Feb 2008) New Revision: 7388 Log: Make exp-drd regression tests succeed when glibc-debuginfo is installed. (Bart Van Assche) Modified: trunk/exp-drd/tests/filter_stderr Modified: trunk/exp-drd/tests/filter_stderr =================================================================== --- trunk/exp-drd/tests/filter_stderr 2008-02-09 12:07:40 UTC (rev 7387) +++ trunk/exp-drd/tests/filter_stderr 2008-02-09 14:51:41 UTC (rev 7388) @@ -12,6 +12,7 @@ -e "/^exp-drd, a data race detector\.$/d" \ -e "/^NOTE: This is an Experimental-Class Valgrind Tool.$/d" \ -e "/^Copyright (C) 2006-200., and GNU GPL'd, by Bart Van Assche.$/d" \ +-e "s/\(pthread_create.c:[0-9]*\)/in libpthread-?.?.so/" \ -e "s/in [^ ]*libpthread-[0-9]*\.[0-9]*\.so/in libpthread-?.?.so/" \ -e "s/in [^ ]*libpthread-[0-9]*\.[0-9]*\.[0-9]*\.so/in libpthread-?.?.so/" \ -e "s/ (\([a-zA-Z_]*\.c\):[0-9]*)/ (\1:?)/" \ |
|
From: Julian S. <js...@ac...> - 2008-02-09 14:48:46
|
> I'm afraid something is wrong with one of the last commits. When I run > the regression tests, on some systems all regression tests run fine > and on other systems all regression tests hang. I did do a complete rebuild and regression test run before committing. The usual cause of strangeness after changes in VEX is because the dependencies are partially broken and so some stuff that should be recompiled, isn't. If you make distclean and rebuild from the start, does that help? J |
|
From: Bart V. A. <bar...@gm...> - 2008-02-09 13:17:10
|
Hello Julian, I'm afraid something is wrong with one of the last commits. When I run the regression tests, on some systems all regression tests run fine and on other systems all regression tests hang. I can reproduce this issue by running the commands below on an openSUSE 10.3 x86_64 system: $ svn co svn://svn.valgrind.org/valgrind/trunk valgrind \ && cd valgrind \ && ./autogen.sh \ && ./configure \ && make -s \ && make -s check \ && ./vg-in-place --tool=none none/tests/selfrun Output with -v enabled: $ ./vg-in-place -v --tool=none none/tests/selfrun ==29390== Nulgrind, a binary JIT-compiler. ==29390== Copyright (C) 2002-2007, and GNU GPL'd, by Nicholas Nethercote. ==29390== Using LibVEX rev 1809, a library for dynamic binary translation. ==29390== Copyright (C) 2004-2007, and GNU GPL'd, by OpenWorks LLP. ==29390== Using valgrind-3.4.0.SVN, a dynamic binary instrumentation framework. ==29390== Copyright (C) 2000-2007, and GNU GPL'd, by Julian Seward et al. ==29390== --29390-- Command line --29390-- none/tests/selfrun --29390-- Startup, with flags: --29390-- -v --29390-- --tool=none --29390-- Contents of /proc/version: --29390-- Linux version 2.6.22.16-0.2-default (geeko@buildhost) (gcc version 4.2.1 (SUSE Linux)) #1 SMP 2008/02/01 19:36:55 UTC --29390-- Arch and hwcaps: AMD64, amd64-sse2 --29390-- Page sizes: currently 4096, max supported 4096 --29390-- Valgrind library directory: ./.in_place --29390-- Reading syms from /home/bart/software/valgrind/none/tests/selfrun (0x400000) --29390-- Reading syms from /lib64/ld-2.6.1.so (0x4000000) --29390-- object doesn't have a symbol table --29390-- Reading syms from /home/bart/software/valgrind/none/none-amd64-linux (0x38000000) --29390-- object doesn't have a dynamic symbol table --29390-- Reading syms from /home/bart/software/valgrind/coregrind/vgpreload_core-amd64-linux.so (0x4A1D000) --29390-- Reading syms from /lib64/libc-2.6.1.so (0x4C1F000) --29390-- object doesn't have a symbol table (hangs) Bart. |
|
From: <sv...@va...> - 2008-02-09 12:07:39
|
Author: sewardj
Date: 2008-02-09 12:07:40 +0000 (Sat, 09 Feb 2008)
New Revision: 7387
Log:
Only build the SSSE3 tests on machines whose assemblers know about
these instructions.
Modified:
trunk/configure.in
trunk/none/tests/amd64/Makefile.am
trunk/none/tests/x86/Makefile.am
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2008-02-09 05:10:45 UTC (rev 7386)
+++ trunk/configure.in 2008-02-09 12:07:40 UTC (rev 7387)
@@ -832,6 +832,28 @@
AM_CONDITIONAL(BUILD_SSE3_TESTS, test x$ac_have_as_sse3 = xyes)
+# Ditto for SSSE3 instructions (note extra S)
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_SSSE3_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if x86/amd64 assembler speaks SSSE3])
+
+AC_TRY_COMPILE(, [
+ do { long long int x;
+ __asm__ __volatile__(
+ "pabsb (%0),%%xmm7" : : "r"(&x) : "xmm7" ); }
+ while (0)
+],
+[
+ac_have_as_ssse3=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_ssse3=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_SSSE3_TESTS, test x$ac_have_as_ssse3 = xyes)
+
+
# Check for TLS support in the compiler and linker
AC_CACHE_CHECK([for TLS support], vg_cv_tls,
[AC_ARG_ENABLE(tls, [ --enable-tls platform supports TLS],
Modified: trunk/none/tests/amd64/Makefile.am
===================================================================
--- trunk/none/tests/amd64/Makefile.am 2008-02-09 05:10:45 UTC (rev 7386)
+++ trunk/none/tests/amd64/Makefile.am 2008-02-09 12:07:40 UTC (rev 7387)
@@ -7,6 +7,9 @@
if BUILD_SSE3_TESTS
INSN_TESTS += insn_sse3 insn_ssse3
endif
+if BUILD_SSSE3_TESTS
+ INSN_TESTS += insn_ssse3 ssse3_misaligned
+endif
# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
# to avoid packaging screwups if 'make dist' is run on a machine
@@ -48,7 +51,7 @@
faultstatus fcmovnu fxtract $(INSN_TESTS) looper jrcxz \
rcl-amd64 \
redundantRexW \
- smc1 shrld ssse3_misaligned \
+ smc1 shrld \
nibz_bennee_mmap \
slahf-amd64
Modified: trunk/none/tests/x86/Makefile.am
===================================================================
--- trunk/none/tests/x86/Makefile.am 2008-02-09 05:10:45 UTC (rev 7386)
+++ trunk/none/tests/x86/Makefile.am 2008-02-09 12:07:40 UTC (rev 7387)
@@ -5,8 +5,11 @@
INSN_TESTS = insn_basic insn_fpu insn_cmov insn_mmx insn_mmxext \
insn_sse insn_sse2
if BUILD_SSE3_TESTS
- INSN_TESTS += insn_sse3 insn_ssse3
+ INSN_TESTS += insn_sse3
endif
+if BUILD_SSSE3_TESTS
+ INSN_TESTS += insn_ssse3 ssse3_misaligned
+endif
# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
# to avoid packaging screwups if 'make dist' is run on a machine
@@ -61,7 +64,7 @@
getseg incdec_alt $(INSN_TESTS) \
jcxz \
lahf looper movx int pushpopseg sbbmisc \
- seg_override sigcontext smc1 ssse3_misaligned yield
+ seg_override sigcontext smc1 yield
AM_CFLAGS = $(WERROR) -Winline -Wall -Wshadow \
@FLAG_M32@ -g -I$(top_srcdir)/include \
|
|
From: Bart V. A. <bar...@gm...> - 2008-02-09 12:05:19
|
On Feb 9, 2008 10:24 AM, Philippe Waroquiers <phi...@sk...> wrote: > The idea is to implement in the valgrind core the "target" side of the gdb > remote debugging protocol If you do this it is probably wise to try to find solid documentation of the gdb remote debugging protocol. I have used gdb remote debugging extensively while developing software for embedded devices, and I remember that at that time there were quite some bugs in the protocol implementation (both client side and server side). Bart. |
|
From: Julian S. <js...@ac...> - 2008-02-09 11:35:16
|
On Friday 08 February 2008 16:17, sv...@va... wrote: > Author: tom > Date: 2008-02-08 15:17:07 +0000 (Fri, 08 Feb 2008) > New Revision: 7383 > > Log: > Make the clone system call wrappers call VG_(register_stack) to record > the new thread's stack, then make the stack unwinder use that information > to make a better guess at the stack bounds. Seems like a good plan, perhaps a long-overdue thing to do. Some comments: * Would it perhaps be prudent to deregister the stack at thread exit? Otherwise, the linked list of stacks grows without bound (afaics -- VG_(deregister_stack) is only ever called as a result of a client request at the moment). Which clearly isn't too good for eg none/tests/manythreads.c. * In VG_(get_StackTrace), the call to VG_(stack_limits) potentially gets a new value for stack_highest_word, and that could (?) be higher than the previous value, VG_(threads)[tid].client_stack_highest_word (I don't see how, but still ..) Maybe more conservative to use the min of the values from VG_(threads)[tid].client_stack_highest_word and VG_(stack_limits)? * This might give a bit of a performance hit in unwind- intensive programs as the stacks list now has to be searched for each snapshot. I guess we could mostly ameliorate this by the usual trick of incrementally rearranging the list to diffuse frequently-requested entries towards the front. J |
|
From: Philippe W. <phi...@sk...> - 2008-02-09 09:24:32
|
Hello,
When an error is detected by valgrind, --db-attach allows the user to look at the client being run.
As far as I understand, the started gdb can only be used to look at the client memory. I think
this has a.o. the following limitations:
* the usual gdb commands (break, continue, next, step) cannot be used
* changing the client memory has no effect (I understood by quickly reading
the code of m_debugger.c that gdb is started on a forked copy, but not on the "real" client)
These limitations are somewhat annoying.
E.g. when a program does not work under valgrind, be able to really debug the client would be useful.
Also, some other features e.g. add breakpoints and (when break encountered) be able to call some
valgrind services on the fly (such as search leaks, verify memory definedness, ...) would be nice.
I wonder if the idea that follows would not allow to obtain a "reasonably debuggable" valgrind client,
at a reasonable implementation cost.
The idea is to implement in the valgrind core the "target" side of the gdb remote debugging protocol
This remote debugging protocol (documented in the gdb user manual) has a simple basis:
the mandatory subset of the "packets (i.e. commands)" is:
get/set registers
read/write <length> bytes at <address>
c/s (continue/step)
The protocol defines a lot of other optional commands, the one that looks interesting to start with
to allow a "reasonably debuggable" client are:
set/clear breakpoints;
execute at the remote monitor <free command>
(there are many others, such as tracepoints/info about threads, etc) For a complete info,
look in the gdb user manual in the annex describing the protocol.
gdb can send these packets either on a serial line or over tcp. To hook in valgrind,
tcp should be used (I do not see how to connect a serial line to valgrind :).
If valgrind core supports this protocol, then it looks to me that we would obtain
a "normally" debuggable client program.
An option --gdb-server=<host:portnr> would indicate to valgrind that it has to listen
on this port nr for a gdb to connect. (the listen could be done before starting up, or
if -db-attach is given, only when an error is encountered)
With the above 8 commands implemented + have a few free commands
such as "search_for_leaks", debugging a program "under valgrind" with the normal
gdb features would become feasible.
The protocol itself looks easy to implement (and there is code available in gdb to start from)
but it is not clear to me if hooking this at valgrind side would be easy.
Here are a few unclear points/issues:
* I guess that reading (and sending back) the client registers is straightforward
but what are the implications of setting the client registers ?
* Probably read/write the client memory has less implications:
reading should be straightforward
writing memory would only imply to change the shadow bits
* implement various "monitor" commands (such as search for leaks) would I guess also
be relatively easy
* it is unclear to me how to implement a break. Maybe a new VEX IR "break" instruction would be needed ?
Then when the set breakpoint packet is received, the translation for the address of the break would have
to be discarded, and replaced by this special instruction. Then when this VEX IR break instruction is
encountered, the gdbserver code would be executed. A continue would then just continue the execution
* how to implement "step" is also not clear.
* implementing the "continue at address": is the valgrind core supporting to "force a jump to a specific address" ?
* it would be nice to be able to "interrupt" the running valgrind program when gdb sends a control-c
character on the remote connection to interrupt.
Probably this can be implemented by having the valgrind core "polling or reading" from time to
time on the socket connection.
* any other thing to look at ? or any difficulty overlooked ?
Any feedback about the idea (e.g. interesting as a new valgrind feature ? feasibility ? difficulty ? ...) welcome.
(sorry if my poor knowledge of valgrind implementation resulted in a naive and unfeasible suggestion)
(if the feedback indicates that it is relatively easy, I might even be tempted to implement
it during the free time which is left after my wife, my children and my work have taken their
parts :)
Philippe Waroquiers
|
|
From: <sv...@va...> - 2008-02-09 05:11:15
|
Author: njn Date: 2008-02-09 05:10:45 +0000 (Sat, 09 Feb 2008) New Revision: 7386 Log: start 3.4.0 release notes Modified: trunk/NEWS Modified: trunk/NEWS =================================================================== --- trunk/NEWS 2008-02-09 01:55:52 UTC (rev 7385) +++ trunk/NEWS 2008-02-09 05:10:45 UTC (rev 7386) @@ -1,4 +1,10 @@ +Release 3.4.0 (???) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Changes include: +- SSE3 insns now supported. Changed CPUID output to be Core-2, so now it + claims to be a Core 2 E6600. + Release 3.3.0 (7 December 2007) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3.3.0 is a feature release with many significant improvements and the |
|
From: Tom H. <th...@cy...> - 2008-02-09 04:07:37
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2008-02-09 03:15:12 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo gcc -Winline -Wall -Wshadow -m32 -g -I../../../include -mmmx -msse -Wno-long-long -o smc1 smc1.o if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -m32 -g -I../../../include -mmmx -msse -Wno-long-long -MT ssse3_misaligned.o -MD -MP -MF ".deps/ssse3_misaligned.Tpo" \ -c -o ssse3_misaligned.o `test -f 'ssse3_misaligned.c' || echo './'`ssse3_misaligned.c; \ then mv -f ".deps/ssse3_misaligned.Tpo" ".deps/ssse3_misaligned.Po"; \ else rm -f ".deps/ssse3_misaligned.Tpo"; exit 1; \ fi /tmp/ccx9sCc2.s: Assembler messages: /tmp/ccx9sCc2.s:90: Error: no such instruction: `pabsb (%eax),%xmm7' make[5]: *** [ssse3_misaligned.o] Error 1 rm insn_mmx.c insn_sse2.c insn_fpu.c insn_mmxext.c insn_sse.c insn_cmov.c insn_basic.c make[5]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind' make: *** [check] Error 2 ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 339 tests, 84 stderr failures, 1 stdout failure, 29 post failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-pool-0 (stderr) memcheck/tests/leak-pool-1 (stderr) memcheck/tests/leak-pool-2 (stderr) memcheck/tests/leak-pool-3 (stderr) memcheck/tests/leak-pool-4 (stderr) memcheck/tests/leak-pool-5 (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/long_namespace_xml (stderr) memcheck/tests/lsframe1 (stderr) memcheck/tests/lsframe2 (stderr) memcheck/tests/malloc_free_fill (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/noisy_child (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/x86/bug152022 (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/xor-undef-x86 (stderr) memcheck/tests/xml1 (stderr) massif/tests/alloc-fns-A (post) massif/tests/alloc-fns-B (post) massif/tests/basic (post) massif/tests/basic2 (post) massif/tests/big-alloc (post) massif/tests/culling1 (stderr) massif/tests/culling2 (stderr) massif/tests/custom_alloc (post) massif/tests/deep-A (post) massif/tests/deep-B (stderr) massif/tests/deep-B (post) massif/tests/deep-C (stderr) massif/tests/deep-C (post) massif/tests/deep-D (post) massif/tests/ignoring (post) massif/tests/insig (post) massif/tests/long-names (post) massif/tests/long-time (post) massif/tests/new-cpp (post) massif/tests/null (post) massif/tests/one (post) massif/tests/overloaded-new (post) massif/tests/peak (post) massif/tests/peak2 (stderr) massif/tests/peak2 (post) massif/tests/realloc (stderr) massif/tests/realloc (post) massif/tests/thresholds_0_0 (post) massif/tests/thresholds_0_10 (post) massif/tests/thresholds_10_0 (post) massif/tests/thresholds_10_10 (post) massif/tests/thresholds_5_0 (post) massif/tests/thresholds_5_10 (post) massif/tests/zero1 (post) massif/tests/zero2 (post) none/tests/blockfault (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/hg01_all_ok (stderr) helgrind/tests/hg02_deadlock (stderr) helgrind/tests/hg03_inherit (stderr) helgrind/tests/hg04_race (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/hg06_readshared (stderr) helgrind/tests/tc01_simple_race (stderr) helgrind/tests/tc02_simple_tls (stderr) helgrind/tests/tc03_re_excl (stderr) helgrind/tests/tc04_free_lock (stderr) helgrind/tests/tc05_simple_race (stderr) helgrind/tests/tc06_two_races (stderr) helgrind/tests/tc07_hbl1 (stderr) helgrind/tests/tc08_hbl2 (stderr) helgrind/tests/tc09_bad_unlock (stderr) helgrind/tests/tc10_rec_lock (stderr) helgrind/tests/tc11_XCHG (stderr) helgrind/tests/tc12_rwl_trivial (stderr) helgrind/tests/tc13_laog1 (stderr) helgrind/tests/tc14_laog_dinphils (stderr) helgrind/tests/tc16_byterace (stderr) helgrind/tests/tc17_sembar (stderr) helgrind/tests/tc18_semabuse (stderr) helgrind/tests/tc19_shadowmem (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc21_pthonce (stderr) helgrind/tests/tc22_exit_w_lock (stderr) helgrind/tests/tc23_bogus_condwait (stderr) helgrind/tests/tc24_nonzero_sem (stderr) exp-drd/tests/fp_race (stderr) exp-drd/tests/fp_race2 (stderr) exp-drd/tests/matinv (stderr) exp-drd/tests/pth_barrier (stderr) exp-drd/tests/pth_broadcast (stderr) exp-drd/tests/pth_cond_race (stderr) exp-drd/tests/pth_cond_race2 (stderr) exp-drd/tests/pth_create_chain (stderr) exp-drd/tests/pth_detached (stderr) exp-drd/tests/pth_detached2 (stderr) exp-drd/tests/sem_as_mutex (stderr) exp-drd/tests/sem_as_mutex2 (stderr) exp-drd/tests/sigalrm (stderr) exp-drd/tests/tc17_sembar (stderr) exp-drd/tests/tc18_semabuse (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat Feb 9 03:50:57 2008 --- new.short Sat Feb 9 04:07:41 2008 *************** *** 6,124 **** ! Regression test results follow ! ! == 339 tests, 84 stderr failures, 1 stdout failure, 29 post failures == ! memcheck/tests/addressable (stderr) ! memcheck/tests/badjump (stderr) ! memcheck/tests/describe-block (stderr) ! memcheck/tests/erringfds (stderr) ! memcheck/tests/leak-0 (stderr) ! memcheck/tests/leak-cycle (stderr) ! memcheck/tests/leak-pool-0 (stderr) ! memcheck/tests/leak-pool-1 (stderr) ! memcheck/tests/leak-pool-2 (stderr) ! memcheck/tests/leak-pool-3 (stderr) ! memcheck/tests/leak-pool-4 (stderr) ! memcheck/tests/leak-pool-5 (stderr) ! memcheck/tests/leak-regroot (stderr) ! memcheck/tests/leak-tree (stderr) ! memcheck/tests/long_namespace_xml (stderr) ! memcheck/tests/lsframe1 (stderr) ! memcheck/tests/lsframe2 (stderr) ! memcheck/tests/malloc_free_fill (stderr) ! memcheck/tests/match-overrun (stderr) ! memcheck/tests/noisy_child (stderr) ! memcheck/tests/partial_load_dflt (stderr) ! memcheck/tests/partial_load_ok (stderr) ! memcheck/tests/partiallydefinedeq (stderr) ! memcheck/tests/pointer-trace (stderr) ! memcheck/tests/sigkill (stderr) ! memcheck/tests/stack_changes (stderr) ! memcheck/tests/supp_unknown (stderr) ! memcheck/tests/x86/bug152022 (stderr) ! memcheck/tests/x86/scalar (stderr) ! memcheck/tests/x86/scalar_supp (stderr) ! memcheck/tests/x86/xor-undef-x86 (stderr) ! memcheck/tests/xml1 (stderr) ! massif/tests/alloc-fns-A (post) ! massif/tests/alloc-fns-B (post) ! massif/tests/basic (post) ! massif/tests/basic2 (post) ! massif/tests/big-alloc (post) ! massif/tests/culling1 (stderr) ! massif/tests/culling2 (stderr) ! massif/tests/custom_alloc (post) ! massif/tests/deep-A (post) ! massif/tests/deep-B (stderr) ! massif/tests/deep-B (post) ! massif/tests/deep-C (stderr) ! massif/tests/deep-C (post) ! massif/tests/deep-D (post) ! massif/tests/ignoring (post) ! massif/tests/insig (post) ! massif/tests/long-names (post) ! massif/tests/long-time (post) ! massif/tests/new-cpp (post) ! massif/tests/null (post) ! massif/tests/one (post) ! massif/tests/overloaded-new (post) ! massif/tests/peak (post) ! massif/tests/peak2 (stderr) ! massif/tests/peak2 (post) ! massif/tests/realloc (stderr) ! massif/tests/realloc (post) ! massif/tests/thresholds_0_0 (post) ! massif/tests/thresholds_0_10 (post) ! massif/tests/thresholds_10_0 (post) ! massif/tests/thresholds_10_10 (post) ! massif/tests/thresholds_5_0 (post) ! massif/tests/thresholds_5_10 (post) ! massif/tests/zero1 (post) ! massif/tests/zero2 (post) ! none/tests/blockfault (stderr) ! none/tests/mremap (stderr) ! none/tests/mremap2 (stdout) ! helgrind/tests/hg01_all_ok (stderr) ! helgrind/tests/hg02_deadlock (stderr) ! helgrind/tests/hg03_inherit (stderr) ! helgrind/tests/hg04_race (stderr) ! helgrind/tests/hg05_race2 (stderr) ! helgrind/tests/hg06_readshared (stderr) ! helgrind/tests/tc01_simple_race (stderr) ! helgrind/tests/tc02_simple_tls (stderr) ! helgrind/tests/tc03_re_excl (stderr) ! helgrind/tests/tc04_free_lock (stderr) ! helgrind/tests/tc05_simple_race (stderr) ! helgrind/tests/tc06_two_races (stderr) ! helgrind/tests/tc07_hbl1 (stderr) ! helgrind/tests/tc08_hbl2 (stderr) ! helgrind/tests/tc09_bad_unlock (stderr) ! helgrind/tests/tc10_rec_lock (stderr) ! helgrind/tests/tc11_XCHG (stderr) ! helgrind/tests/tc12_rwl_trivial (stderr) ! helgrind/tests/tc13_laog1 (stderr) ! helgrind/tests/tc14_laog_dinphils (stderr) ! helgrind/tests/tc16_byterace (stderr) ! helgrind/tests/tc17_sembar (stderr) ! helgrind/tests/tc18_semabuse (stderr) ! helgrind/tests/tc19_shadowmem (stderr) ! helgrind/tests/tc20_verifywrap (stderr) ! helgrind/tests/tc21_pthonce (stderr) ! helgrind/tests/tc22_exit_w_lock (stderr) ! helgrind/tests/tc23_bogus_condwait (stderr) ! helgrind/tests/tc24_nonzero_sem (stderr) ! exp-drd/tests/fp_race (stderr) ! exp-drd/tests/fp_race2 (stderr) ! exp-drd/tests/matinv (stderr) ! exp-drd/tests/pth_barrier (stderr) ! exp-drd/tests/pth_broadcast (stderr) ! exp-drd/tests/pth_cond_race (stderr) ! exp-drd/tests/pth_cond_race2 (stderr) ! exp-drd/tests/pth_create_chain (stderr) ! exp-drd/tests/pth_detached (stderr) ! exp-drd/tests/pth_detached2 (stderr) ! exp-drd/tests/sem_as_mutex (stderr) ! exp-drd/tests/sem_as_mutex2 (stderr) ! exp-drd/tests/sigalrm (stderr) ! exp-drd/tests/tc17_sembar (stderr) ! exp-drd/tests/tc18_semabuse (stderr) ! --- 6,27 ---- ! Last 20 lines of verbose log follow echo ! gcc -Winline -Wall -Wshadow -m32 -g -I../../../include -mmmx -msse -Wno-long-long -o smc1 smc1.o ! if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -m32 -g -I../../../include -mmmx -msse -Wno-long-long -MT ssse3_misaligned.o -MD -MP -MF ".deps/ssse3_misaligned.Tpo" \ ! -c -o ssse3_misaligned.o `test -f 'ssse3_misaligned.c' || echo './'`ssse3_misaligned.c; \ ! then mv -f ".deps/ssse3_misaligned.Tpo" ".deps/ssse3_misaligned.Po"; \ ! else rm -f ".deps/ssse3_misaligned.Tpo"; exit 1; \ ! fi ! /tmp/ccx9sCc2.s: Assembler messages: ! /tmp/ccx9sCc2.s:90: Error: no such instruction: `pabsb (%eax),%xmm7' ! make[5]: *** [ssse3_misaligned.o] Error 1 ! rm insn_mmx.c insn_sse2.c insn_fpu.c insn_mmxext.c insn_sse.c insn_cmov.c insn_basic.c ! make[5]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' ! make[4]: *** [check-am] Error 2 ! make[4]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' ! make[3]: *** [check-recursive] Error 1 ! make[3]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests' ! make[2]: *** [check-recursive] Error 1 ! make[2]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none' ! make[1]: *** [check-recursive] Error 1 ! make[1]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind' ! make: *** [check] Error 2 |
|
From: Tom H. <th...@cy...> - 2008-02-09 03:50:43
|
Nightly build on aston ( x86_64, Fedora Core 5 ) started at 2008-02-09 03:20:06 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 379 tests, 15 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/malloc_free_fill (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/blockfault (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc22_exit_w_lock (stderr) exp-drd/tests/pth_cond_race (stderr) exp-drd/tests/sem_as_mutex2 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 375 tests, 15 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/malloc_free_fill (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/blockfault (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc22_exit_w_lock (stderr) exp-drd/tests/pth_cond_race (stderr) exp-drd/tests/sem_as_mutex2 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat Feb 9 03:33:17 2008 --- new.short Sat Feb 9 03:50:45 2008 *************** *** 8,10 **** ! == 375 tests, 15 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/addressable (stderr) --- 8,10 ---- ! == 379 tests, 15 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/addressable (stderr) |
|
From: Tom H. <th...@cy...> - 2008-02-09 03:45:08
|
Nightly build on trojan ( x86_64, Fedora Core 6 ) started at 2008-02-09 03:25:24 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 377 tests, 7 stderr failures, 5 stdout failures, 0 post failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/vcpu_fnfns (stdout) memcheck/tests/x86/bug133694 (stdout) memcheck/tests/x86/bug133694 (stderr) memcheck/tests/x86/scalar (stderr) none/tests/cmdline1 (stdout) none/tests/cmdline2 (stdout) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc22_exit_w_lock (stderr) exp-drd/tests/sem_as_mutex2 (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 373 tests, 7 stderr failures, 5 stdout failures, 0 post failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/vcpu_fnfns (stdout) memcheck/tests/x86/bug133694 (stdout) memcheck/tests/x86/bug133694 (stderr) memcheck/tests/x86/scalar (stderr) none/tests/cmdline1 (stdout) none/tests/cmdline2 (stdout) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc22_exit_w_lock (stderr) exp-drd/tests/sem_as_mutex2 (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat Feb 9 03:36:35 2008 --- new.short Sat Feb 9 03:45:11 2008 *************** *** 8,10 **** ! == 373 tests, 7 stderr failures, 5 stdout failures, 0 post failures == memcheck/tests/pointer-trace (stderr) --- 8,10 ---- ! == 377 tests, 7 stderr failures, 5 stdout failures, 0 post failures == memcheck/tests/pointer-trace (stderr) |
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From: Tom H. <th...@cy...> - 2008-02-09 03:10:41
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2008-02-09 03:00:05 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo /tmp/cc61ejPq.s:21520: Error: no such instruction: `phaddd %mm6,%mm7' /tmp/cc61ejPq.s:21623: Error: no such instruction: `phaddd -32(%ebp),%mm7' /tmp/cc61ejPq.s:21749: Error: no such instruction: `phaddd %xmm4,%xmm5' /tmp/cc61ejPq.s:21890: Error: no such instruction: `phaddd -40(%ebp),%xmm5' /tmp/cc61ejPq.s:22003: Error: no such instruction: `phaddsw %mm6,%mm7' /tmp/cc61ejPq.s:22114: Error: no such instruction: `phaddsw -32(%ebp),%mm7' /tmp/cc61ejPq.s:22240: Error: no such instruction: `phaddsw %xmm4,%xmm5' /tmp/cc61ejPq.s:22397: Error: no such instruction: `phaddsw -40(%ebp),%xmm5' make[5]: *** [insn_ssse3.o] Error 1 rm insn_sse3.c insn_sse.c insn_mmx.c insn_mmxext.c insn_fpu.c insn_sse2.c insn_basic.c insn_cmov.c make[5]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind' make: *** [check] Error 2 ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 375 tests, 30 stderr failures, 1 stdout failure, 0 post failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/malloc_free_fill (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/blockfault (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) helgrind/tests/hg01_all_ok (stderr) helgrind/tests/hg02_deadlock (stderr) helgrind/tests/hg03_inherit (stderr) helgrind/tests/hg04_race (stderr) helgrind/tests/hg05_race2 (stderr) helgrind/tests/tc01_simple_race (stderr) helgrind/tests/tc05_simple_race (stderr) helgrind/tests/tc06_two_races (stderr) helgrind/tests/tc09_bad_unlock (stderr) helgrind/tests/tc14_laog_dinphils (stderr) helgrind/tests/tc16_byterace (stderr) helgrind/tests/tc17_sembar (stderr) helgrind/tests/tc19_shadowmem (stderr) helgrind/tests/tc20_verifywrap (stderr) helgrind/tests/tc21_pthonce (stderr) helgrind/tests/tc22_exit_w_lock (stderr) helgrind/tests/tc23_bogus_condwait (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat Feb 9 03:07:35 2008 --- new.short Sat Feb 9 03:10:45 2008 *************** *** 6,41 **** ! Regression test results follow ! ! == 375 tests, 30 stderr failures, 1 stdout failure, 0 post failures == ! memcheck/tests/addressable (stderr) ! memcheck/tests/badjump (stderr) ! memcheck/tests/describe-block (stderr) ! memcheck/tests/malloc_free_fill (stderr) ! memcheck/tests/match-overrun (stderr) ! memcheck/tests/pointer-trace (stderr) ! memcheck/tests/stack_switch (stderr) ! memcheck/tests/supp_unknown (stderr) ! memcheck/tests/x86/scalar (stderr) ! memcheck/tests/x86/scalar_supp (stderr) ! none/tests/blockfault (stderr) ! none/tests/fdleak_fcntl (stderr) ! none/tests/mremap (stderr) ! none/tests/mremap2 (stdout) ! helgrind/tests/hg01_all_ok (stderr) ! helgrind/tests/hg02_deadlock (stderr) ! helgrind/tests/hg03_inherit (stderr) ! helgrind/tests/hg04_race (stderr) ! helgrind/tests/hg05_race2 (stderr) ! helgrind/tests/tc01_simple_race (stderr) ! helgrind/tests/tc05_simple_race (stderr) ! helgrind/tests/tc06_two_races (stderr) ! helgrind/tests/tc09_bad_unlock (stderr) ! helgrind/tests/tc14_laog_dinphils (stderr) ! helgrind/tests/tc16_byterace (stderr) ! helgrind/tests/tc17_sembar (stderr) ! helgrind/tests/tc19_shadowmem (stderr) ! helgrind/tests/tc20_verifywrap (stderr) ! helgrind/tests/tc21_pthonce (stderr) ! helgrind/tests/tc22_exit_w_lock (stderr) ! helgrind/tests/tc23_bogus_condwait (stderr) ! --- 6,27 ---- ! Last 20 lines of verbose log follow echo ! /tmp/cc61ejPq.s:21520: Error: no such instruction: `phaddd %mm6,%mm7' ! /tmp/cc61ejPq.s:21623: Error: no such instruction: `phaddd -32(%ebp),%mm7' ! /tmp/cc61ejPq.s:21749: Error: no such instruction: `phaddd %xmm4,%xmm5' ! /tmp/cc61ejPq.s:21890: Error: no such instruction: `phaddd -40(%ebp),%xmm5' ! /tmp/cc61ejPq.s:22003: Error: no such instruction: `phaddsw %mm6,%mm7' ! /tmp/cc61ejPq.s:22114: Error: no such instruction: `phaddsw -32(%ebp),%mm7' ! /tmp/cc61ejPq.s:22240: Error: no such instruction: `phaddsw %xmm4,%xmm5' ! /tmp/cc61ejPq.s:22397: Error: no such instruction: `phaddsw -40(%ebp),%xmm5' ! make[5]: *** [insn_ssse3.o] Error 1 ! rm insn_sse3.c insn_sse.c insn_mmx.c insn_mmxext.c insn_fpu.c insn_sse2.c insn_basic.c insn_cmov.c ! make[5]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' ! make[4]: *** [check-am] Error 2 ! make[4]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests/x86' ! make[3]: *** [check-recursive] Error 1 ! make[3]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none/tests' ! make[2]: *** [check-recursive] Error 1 ! make[2]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind/none' ! make[1]: *** [check-recursive] Error 1 ! make[1]: Leaving directory `/tmp/vgtest/2008-02-09/valgrind' ! make: *** [check] Error 2 |
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From: <sv...@va...> - 2008-02-09 01:55:47
|
Author: sewardj
Date: 2008-02-09 01:55:52 +0000 (Sat, 09 Feb 2008)
New Revision: 7385
Log:
Add SSSE3 tests.
Added:
trunk/none/tests/amd64/insn_ssse3.def
trunk/none/tests/amd64/insn_ssse3.stderr.exp
trunk/none/tests/amd64/insn_ssse3.stdout.exp
trunk/none/tests/amd64/insn_ssse3.vgtest
trunk/none/tests/amd64/ssse3_misaligned.c
trunk/none/tests/amd64/ssse3_misaligned.stderr.exp
trunk/none/tests/amd64/ssse3_misaligned.stdout.exp
trunk/none/tests/amd64/ssse3_misaligned.vgtest
trunk/none/tests/x86/insn_ssse3.def
trunk/none/tests/x86/insn_ssse3.stderr.exp
trunk/none/tests/x86/insn_ssse3.stdout.exp
trunk/none/tests/x86/insn_ssse3.vgtest
trunk/none/tests/x86/ssse3_misaligned.c
trunk/none/tests/x86/ssse3_misaligned.stderr.exp
trunk/none/tests/x86/ssse3_misaligned.stdout.exp
trunk/none/tests/x86/ssse3_misaligned.vgtest
Modified:
trunk/none/tests/amd64/Makefile.am
trunk/none/tests/x86/Makefile.am
Modified: trunk/none/tests/amd64/Makefile.am
===================================================================
--- trunk/none/tests/amd64/Makefile.am 2008-02-09 01:49:32 UTC (rev 7384)
+++ trunk/none/tests/amd64/Makefile.am 2008-02-09 01:55:52 UTC (rev 7385)
@@ -5,7 +5,7 @@
INSN_TESTS = insn_basic insn_mmx insn_sse insn_sse2 insn_fpu
if BUILD_SSE3_TESTS
- INSN_TESTS += insn_sse3
+ INSN_TESTS += insn_sse3 insn_ssse3
endif
# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
@@ -26,6 +26,7 @@
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
looper.stderr.exp looper.stdout.exp looper.vgtest \
nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
@@ -35,6 +36,8 @@
redundantRexW.stderr.exp \
smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
shrld.stderr.exp shrld.stdout.exp shrld.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest \
slahf-amd64.stderr.exp slahf-amd64.stdout.exp \
slahf-amd64.vgtest
@@ -45,7 +48,7 @@
faultstatus fcmovnu fxtract $(INSN_TESTS) looper jrcxz \
rcl-amd64 \
redundantRexW \
- smc1 shrld \
+ smc1 shrld ssse3_misaligned \
nibz_bennee_mmap \
slahf-amd64
@@ -65,6 +68,8 @@
insn_sse2_LDADD = -lm
insn_sse3_SOURCES = insn_sse3.def
insn_sse3_LDADD = -lm
+insn_ssse3_SOURCES = insn_ssse3.def
+insn_ssse3_LDADD = -lm
insn_fpu_SOURCES = insn_fpu.def
insn_fpu_LDADD = -lm
fxtract_LDADD = -lm
Added: trunk/none/tests/amd64/insn_ssse3.def
===================================================================
--- trunk/none/tests/amd64/insn_ssse3.def (rev 0)
+++ trunk/none/tests/amd64/insn_ssse3.def 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,251 @@
+psignb mm.ub[0,10,0,245,0,1,255,254] mm.ub[0,40,80,120,160,200,240,24] => 1.sb[0,40,0,-120,0,-56,16,-24]
+psignb m64.ub[0,10,0,245,0,1,255,254] mm.ub[0,41,79,119,161,199,241,23] => 1.sb[0,41,0,-119,0,-57,15,-23]
+#
+psignb xmm.ub[0,10,0,245,0,1,255,254,1,255,254,0,10,0,245,0] xmm.ub[0,40,80,120,160,200,240,24,3,2,1,0,255,254,253,252] => 1.sb[0,40,0,-120,0,-56,16,-24,3,-2,-1,0,-1,0,3,0]
+psignb m128.ub[0,10,0,245,0,1,255,254,10,0,245,0,1,254,0] xmm.ub[0,41,79,119,161,199,241,23,0,31,69,109,151,189,231,13] => 1.sb[0,41,0,-119,0,-57,15,-23,0,0,-69,0,-105,67,0]
+#
+#
+#
+psignw mm.sw[0,10,0,-11] mm.sw[999,987,986,985] => 1.sw[0,987,0,-985]
+psignw m64.sw[0,1000,0,-1111] mm.sw[909,907,906,905] => 1.sw[0,907,0,-905]
+#
+psignw xmm.sw[0,10,0,-11,1,0,-1,0] xmm.sw[999,987,986,985,888,887,886,885] => 1.sw[0,987,0,-985,888,0,-886,0]
+psignw m128.sw[0,1000,0,-1111,11,0,-11,0] xmm.sw[909,907,906,905,809,808,807,806] => 1.sw[0,907,0,-905,809,0,-807]
+#
+#
+#
+psignd mm.sd[0,10000] mm.sd[-5555,-6666] => 1.sd[0,-6666]
+psignd m64.sd[-11111,0] mm.sd[-7777,-8888] => 1.sd[7777,0]
+#
+psignd xmm.sd[0,10000,-10000,0] xmm.sd[-5555,-6666,-7777,-8888] => 1.sd[0,-6666,7777,0]
+psignd m128.sd[-11111,0,0,1111] xmm.sd[-9999,-10101,-11111,-22222] => 1.sd[9999,0,0,-22222]
+#
+#
+#
+pabsb mm.ub[0,10,0,245,0,1,255,254] mm.ub[0,40,80,120,160,200,240,24] => 1.sb[0,10,0,11,0,1,1,2]
+pabsb m64.ub[0,10,0,245,0,1,255,254] mm.ub[0,41,79,119,161,199,241,23] => 1.sb[0,10,0,11,0,1,1,2]
+#
+pabsb xmm.ub[0,10,0,245,0,1,255,254,1,255,254,0,10,0,245,0] xmm.ub[0,40,80,120,160,200,240,24,3,2,1,0,255,254,253,252] => 1.sb[0,10,0,11,0,1,1,2,1,1,2,0,10,0,11,0]
+pabsb m128.ub[0,10,0,245,0,1,255,254,10,0,245,0,1,254,0] xmm.ub[0,41,79,119,161,199,241,23,0,31,69,109,151,189,231,13] => 1.sb[0,10,0,11,0,1,1,2,10,0,11,0,1,2,0]
+#
+#
+#
+pabsw mm.sw[0,10,0,-11] mm.sw[999,987,986,985] => 1.sw[0,10,0,11]
+pabsw m64.sw[0,1000,0,-1111] mm.sw[909,907,906,905] => 1.sw[0,1000,0,1111]
+#
+pabsw xmm.sw[0,10,0,-11,1,0,-1,0] xmm.sw[999,987,986,985,888,887,886,885] => 1.sw[0,10,0,11,1,0,1,0]
+pabsw m128.sw[0,1000,0,-1111,11,0,-11,0] xmm.sw[909,907,906,905,809,808,807,806] => 1.sw[0,1000,0,1111,11,0,11]
+#
+#
+#
+pabsd mm.sd[0,10000] mm.sd[-5555,-6666] => 1.sd[0,10000]
+pabsd m64.sd[-11111,0] mm.sd[-7777,-8888] => 1.sd[11111,0]
+#
+pabsd xmm.sd[0,14000,-10700,0] xmm.sd[-5555,-6666,-7777,-8888] => 1.sd[0,14000,10700,0]
+pabsd m128.sd[-11111,0,0,1111] xmm.sd[-9999,-10101,-11111,-22222] => 1.sd[11111,0,0,1111]
+#
+#
+#
+palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
+palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
+palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
+palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
+palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
+palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
+palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
+palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
+palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
+palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
+palignr imm8[10] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655443322]
+palignr imm8[11] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433]
+palignr imm8[12] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544]
+palignr imm8[13] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655]
+palignr imm8[14] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766]
+palignr imm8[15] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77]
+palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+#
+palignr imm8[0] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
+palignr imm8[1] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
+palignr imm8[2] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
+palignr imm8[3] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
+palignr imm8[4] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
+palignr imm8[5] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
+palignr imm8[6] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
+palignr imm8[7] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
+palignr imm8[8] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
+palignr imm8[9] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
+palignr imm8[10] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655443322]
+palignr imm8[11] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433]
+palignr imm8[12] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544]
+palignr imm8[13] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655]
+palignr imm8[14] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766]
+palignr imm8[15] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77]
+palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[53] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[91] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[137] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[193] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[241] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[255] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+#
+palignr imm8[0] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[5940417471140883427,2114202203853458723]
+palignr imm8[1] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2545220547074121835,440604166586370189]
+palignr imm8[2] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[10170063027109847264,6991307731704737800]
+palignr imm8[3] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[616187561003071328,2477267993116521456]
+palignr imm8[4] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17296229551762872887,11899179844356220851]
+palignr imm8[5] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12965872729475674266,11215408247145846567]
+palignr imm8[6] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2860894107828703856,16905287193340550487]
+palignr imm8[7] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6280186048908436306,930727406554121757]
+palignr imm8[8] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2114202203853458723,7713798215990141190]
+palignr imm8[9] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[440604166586370189,2840378191760400993]
+palignr imm8[10] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6991307731704737800,17304917796414268706]
+palignr imm8[11] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2477267993116521456,9579199748148730789]
+palignr imm8[12] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11899179844356220851,3640298450912602779]
+palignr imm8[13] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11215408247145846567,2103890142923787498]
+palignr imm8[14] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[16905287193340550487,6061056220056742668]
+palignr imm8[15] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[930727406554121757,15371943530938247019]
+palignr imm8[16] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[7713798215990141190,3446753574200340519]
+palignr imm8[17] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2840378191760400993,13463881149220080]
+palignr imm8[18] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17304917796414268706,52593285739140]
+palignr imm8[19] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[9579199748148730789,205442522418]
+palignr imm8[20] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3640298450912602779,802509853]
+palignr imm8[21] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2103890142923787498,3134804]
+palignr imm8[22] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6061056220056742668,12245]
+palignr imm8[23] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[15371943530938247019,47]
+palignr imm8[24] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3446753574200340519,0]
+palignr imm8[25] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[13463881149220080,0]
+palignr imm8[26] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[52593285739140,0]
+palignr imm8[27] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[205442522418,0]
+palignr imm8[28] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[802509853,0]
+palignr imm8[29] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3134804,0]
+palignr imm8[30] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12245,0]
+palignr imm8[31] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[47,0]
+palignr imm8[32] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[33] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[53] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[91] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[137] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[193] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[241] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[255] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+#
+palignr imm8[0] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[5940417471140883427,2114202203853458723]
+palignr imm8[1] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2545220547074121835,440604166586370189]
+palignr imm8[2] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[10170063027109847264,6991307731704737800]
+palignr imm8[3] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[616187561003071328,2477267993116521456]
+palignr imm8[4] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17296229551762872887,11899179844356220851]
+palignr imm8[5] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12965872729475674266,11215408247145846567]
+palignr imm8[6] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2860894107828703856,16905287193340550487]
+palignr imm8[7] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6280186048908436306,930727406554121757]
+palignr imm8[8] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2114202203853458723,7713798215990141190]
+palignr imm8[9] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[440604166586370189,2840378191760400993]
+palignr imm8[10] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6991307731704737800,17304917796414268706]
+palignr imm8[11] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2477267993116521456,9579199748148730789]
+palignr imm8[12] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11899179844356220851,3640298450912602779]
+palignr imm8[13] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11215408247145846567,2103890142923787498]
+palignr imm8[14] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[16905287193340550487,6061056220056742668]
+palignr imm8[15] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[930727406554121757,15371943530938247019]
+palignr imm8[16] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[7713798215990141190,3446753574200340519]
+palignr imm8[17] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2840378191760400993,13463881149220080]
+palignr imm8[18] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17304917796414268706,52593285739140]
+palignr imm8[19] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[9579199748148730789,205442522418]
+palignr imm8[20] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3640298450912602779,802509853]
+palignr imm8[21] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2103890142923787498,3134804]
+palignr imm8[22] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6061056220056742668,12245]
+palignr imm8[23] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[15371943530938247019,47]
+palignr imm8[24] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3446753574200340519,0]
+palignr imm8[25] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[13463881149220080,0]
+palignr imm8[26] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[52593285739140,0]
+palignr imm8[27] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[205442522418,0]
+palignr imm8[28] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[802509853,0]
+palignr imm8[29] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3134804,0]
+palignr imm8[30] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12245,0]
+palignr imm8[31] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[47,0]
+palignr imm8[32] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[33] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[53] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[91] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[137] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[193] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[241] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[255] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+#
+#
+#
+pshufb mm.ub[14,6,4,3,1,0,255,128] mm.ub[50,51,52,53,54,55,56,57] => 1.ub[56,56,54,53,51,50,0,0]
+pshufb m64.ub[14,6,4,3,1,0,255,128] mm.ub[50,51,52,53,54,55,56,57] => 1.ub[56,56,54,53,51,50,0,0]
+#
+pshufb xmm.ub[63,31,15,14,8,7,1,0,255,128,127,126,123,231,213,103] xmm.ub[60,61,62,63,64,65,66,67,70,71,72,73,74,75,76,77] => 1.ub[77,77,77,76,70,67,61,60,0,0,77,76,73,0,0,67]
+pshufb m128.ub[63,31,15,14,8,7,1,0,255,128,127,126,123,231,213,103] xmm.ub[60,61,62,63,64,65,66,67,70,71,72,73,74,75,76,77] => 1.ub[77,77,77,76,70,67,61,60,0,0,77,76,73,0,0,67]
+#
+#
+#
+pmulhrsw mm.ub[14,26,34,173,181,200,255,128] mm.ub[50,151,52,153,54,155,56,157] => 1.uw[60075,17037,11146,25091]
+pmulhrsw m64.ub[14,26,34,173,181,200,255,128] mm.ub[50,151,52,153,54,155,56,157] => 1.uw[60075,17037,11146,25091]
+#
+pmulhrsw xmm.ub[14,26,34,173,181,200,255,128,24,36,44,183,191,210,9,138] xmm.ub[50,151,52,153,54,155,56,157,60,161,62,163,64,165,66,167] => 1.uw[60075,17037,11146,25091,58695,13511,8214,20937]
+pmulhrsw m128.ub[14,26,34,173,181,200,255,128,24,36,44,183,191,210,9,138] xmm.ub[50,151,52,153,54,155,56,157,60,161,62,163,64,165,66,167] => 1.uw[60075,17037,11146,25091,58695,13511,8214,20937]
+#
+#
+#
+pmaddubsw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[32767,-32768,-12730,27484]
+pmaddubsw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[32767,-32768,-12730,27484]
+#
+pmaddubsw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[32767,-32768,-12730,27484,32767,-32768,-13049,27259]
+pmaddubsw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[32767,-32768,-12730,27484,32767,-32768,-13049,27259]
+#
+#
+#
+phsubw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[-512,-25602,27903,23478]
+phsubw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[-512,-25602,27903,23478]
+#
+phsubw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[-512,-25602,-3328,-30672,27903,23478,27391,23989]
+phsubw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[-512,-25602,-3328,-30672,27903,23478,27391,23989]
+#
+#
+#
+phsubd mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1698235191,1082151370]
+phsubd m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1698235191,1082151370]
+#
+phsubd xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1698235191,-1528492107,1082151370,1115705291]
+phsubd m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1698235191,-1528492107,1082151370,1115705291]
+#
+#
+#
+phsubsw mm.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[-32768,-4418,32767,2457]
+phsubsw m64.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[-32768,-4418,32767,2457]
+#
+phsubsw xmm.sw[20000,-21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,18121,134,4552,235,6356,123,75] => 1.sw[-32768,-4418,-6121,48,32767,2457,23,5554]
+phsubsw m128.sw[20000,-21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,18121,134,4552,235,6356,123,75] => 1.sw[-32768,-4418,-6121,48,32767,2457,23,5554]
+#
+#
+#
+phaddw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[12798,-26002,-14337,13748]
+phaddw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[12798,-26002,-14337,13748]
+#
+phaddw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[12798,-26002,15102,-31132,-14337,13748,-14337,13747]
+phaddw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[12798,-26002,15102,-31132,-14337,13748,-14337,13747]
+#
+#
+#
+phaddd mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1724370123,444588852]
+phaddd m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1724370123,444588852]
+#
+phaddd xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1724370123,-1558569399,444588852,444588851]
+phaddd m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1724370123,-1558569399,444588852,444588851]
+#
+#
+#
+phaddsw mm.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[1121,4686,-1000,33]
+phaddsw m64.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[1121,4686,-1000,33]
+#
+phaddsw xmm.sw[20000,21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,-18121,134,4552,235,6356,123,75] => 1.sw[-32768,4686,6591,198,32767,33,91,6022]
+phaddsw m128.sw[20000,21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,-18121,134,4552,235,6356,123,75] => 1.sw[-32768,4686,6591,198,32767,33,91,6022]
Added: trunk/none/tests/amd64/insn_ssse3.stderr.exp
===================================================================
Added: trunk/none/tests/amd64/insn_ssse3.stdout.exp
===================================================================
--- trunk/none/tests/amd64/insn_ssse3.stdout.exp (rev 0)
+++ trunk/none/tests/amd64/insn_ssse3.stdout.exp 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,188 @@
+psignb_1 ... ok
+psignb_2 ... ok
+psignb_3 ... ok
+psignb_4 ... ok
+psignw_1 ... ok
+psignw_2 ... ok
+psignw_3 ... ok
+psignw_4 ... ok
+psignd_1 ... ok
+psignd_2 ... ok
+psignd_3 ... ok
+psignd_4 ... ok
+pabsb_1 ... ok
+pabsb_2 ... ok
+pabsb_3 ... ok
+pabsb_4 ... ok
+pabsw_1 ... ok
+pabsw_2 ... ok
+pabsw_3 ... ok
+pabsw_4 ... ok
+pabsd_1 ... ok
+pabsd_2 ... ok
+pabsd_3 ... ok
+pabsd_4 ... ok
+palignr_1 ... ok
+palignr_2 ... ok
+palignr_3 ... ok
+palignr_4 ... ok
+palignr_5 ... ok
+palignr_6 ... ok
+palignr_7 ... ok
+palignr_8 ... ok
+palignr_9 ... ok
+palignr_10 ... ok
+palignr_11 ... ok
+palignr_12 ... ok
+palignr_13 ... ok
+palignr_14 ... ok
+palignr_15 ... ok
+palignr_16 ... ok
+palignr_17 ... ok
+palignr_18 ... ok
+palignr_19 ... ok
+palignr_20 ... ok
+palignr_21 ... ok
+palignr_22 ... ok
+palignr_23 ... ok
+palignr_24 ... ok
+palignr_25 ... ok
+palignr_26 ... ok
+palignr_27 ... ok
+palignr_28 ... ok
+palignr_29 ... ok
+palignr_30 ... ok
+palignr_31 ... ok
+palignr_32 ... ok
+palignr_33 ... ok
+palignr_34 ... ok
+palignr_35 ... ok
+palignr_36 ... ok
+palignr_37 ... ok
+palignr_38 ... ok
+palignr_39 ... ok
+palignr_40 ... ok
+palignr_41 ... ok
+palignr_42 ... ok
+palignr_43 ... ok
+palignr_44 ... ok
+palignr_45 ... ok
+palignr_46 ... ok
+palignr_47 ... ok
+palignr_48 ... ok
+palignr_49 ... ok
+palignr_50 ... ok
+palignr_51 ... ok
+palignr_52 ... ok
+palignr_53 ... ok
+palignr_54 ... ok
+palignr_55 ... ok
+palignr_56 ... ok
+palignr_57 ... ok
+palignr_58 ... ok
+palignr_59 ... ok
+palignr_60 ... ok
+palignr_61 ... ok
+palignr_62 ... ok
+palignr_63 ... ok
+palignr_64 ... ok
+palignr_65 ... ok
+palignr_66 ... ok
+palignr_67 ... ok
+palignr_68 ... ok
+palignr_69 ... ok
+palignr_70 ... ok
+palignr_71 ... ok
+palignr_72 ... ok
+palignr_73 ... ok
+palignr_74 ... ok
+palignr_75 ... ok
+palignr_76 ... ok
+palignr_77 ... ok
+palignr_78 ... ok
+palignr_79 ... ok
+palignr_80 ... ok
+palignr_81 ... ok
+palignr_82 ... ok
+palignr_83 ... ok
+palignr_84 ... ok
+palignr_85 ... ok
+palignr_86 ... ok
+palignr_87 ... ok
+palignr_88 ... ok
+palignr_89 ... ok
+palignr_90 ... ok
+palignr_91 ... ok
+palignr_92 ... ok
+palignr_93 ... ok
+palignr_94 ... ok
+palignr_95 ... ok
+palignr_96 ... ok
+palignr_97 ... ok
+palignr_98 ... ok
+palignr_99 ... ok
+palignr_100 ... ok
+palignr_101 ... ok
+palignr_102 ... ok
+palignr_103 ... ok
+palignr_104 ... ok
+palignr_105 ... ok
+palignr_106 ... ok
+palignr_107 ... ok
+palignr_108 ... ok
+palignr_109 ... ok
+palignr_110 ... ok
+palignr_111 ... ok
+palignr_112 ... ok
+palignr_113 ... ok
+palignr_114 ... ok
+palignr_115 ... ok
+palignr_116 ... ok
+palignr_117 ... ok
+palignr_118 ... ok
+palignr_119 ... ok
+palignr_120 ... ok
+palignr_121 ... ok
+palignr_122 ... ok
+palignr_123 ... ok
+palignr_124 ... ok
+palignr_125 ... ok
+palignr_126 ... ok
+palignr_127 ... ok
+palignr_128 ... ok
+pshufb_1 ... ok
+pshufb_2 ... ok
+pshufb_3 ... ok
+pshufb_4 ... ok
+pmulhrsw_1 ... ok
+pmulhrsw_2 ... ok
+pmulhrsw_3 ... ok
+pmulhrsw_4 ... ok
+pmaddubsw_1 ... ok
+pmaddubsw_2 ... ok
+pmaddubsw_3 ... ok
+pmaddubsw_4 ... ok
+phsubw_1 ... ok
+phsubw_2 ... ok
+phsubw_3 ... ok
+phsubw_4 ... ok
+phsubd_1 ... ok
+phsubd_2 ... ok
+phsubd_3 ... ok
+phsubd_4 ... ok
+phsubsw_1 ... ok
+phsubsw_2 ... ok
+phsubsw_3 ... ok
+phsubsw_4 ... ok
+phaddw_1 ... ok
+phaddw_2 ... ok
+phaddw_3 ... ok
+phaddw_4 ... ok
+phaddd_1 ... ok
+phaddd_2 ... ok
+phaddd_3 ... ok
+phaddd_4 ... ok
+phaddsw_1 ... ok
+phaddsw_2 ... ok
+phaddsw_3 ... ok
+phaddsw_4 ... ok
Added: trunk/none/tests/amd64/insn_ssse3.vgtest
===================================================================
--- trunk/none/tests/amd64/insn_ssse3.vgtest (rev 0)
+++ trunk/none/tests/amd64/insn_ssse3.vgtest 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,3 @@
+prog: ../../../none/tests/amd64/insn_ssse3
+prereq: ../../../tests/cputest amd64-sse3
+vgopts: -q
Added: trunk/none/tests/amd64/ssse3_misaligned.c
===================================================================
--- trunk/none/tests/amd64/ssse3_misaligned.c (rev 0)
+++ trunk/none/tests/amd64/ssse3_misaligned.c 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,38 @@
+
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <signal.h>
+
+void maybe_fault ( int delta )
+{
+ char* x = memalign(16/*alignment*/,32/*size*/);
+ assert(x);
+ assert(0 == ((16-1) & (unsigned long)x));
+ memset(x, 0, 32);
+ __asm__ __volatile__(
+ "pabsb (%0),%%xmm7"
+ : /*out*/ : /*in*/ "r"(x+delta) : /*trash*/"xmm7" );
+ free(x);
+}
+
+void handler ( int signo )
+{
+ assert(signo == SIGSEGV);
+ fprintf(stderr, "three\n");
+ exit(0);
+}
+
+int main ( void )
+{
+ signal(SIGSEGV, handler);
+ fprintf(stderr, "you should see: \"one\\ntwo\\nthree\\n\"\n");
+ fprintf(stderr, "one\n");
+ maybe_fault(0);
+ fprintf(stderr, "two\n");
+ maybe_fault(5);
+ fprintf(stderr, "test failed! you shouldn't see this\n");
+ return 0;
+}
Added: trunk/none/tests/amd64/ssse3_misaligned.stderr.exp
===================================================================
--- trunk/none/tests/amd64/ssse3_misaligned.stderr.exp (rev 0)
+++ trunk/none/tests/amd64/ssse3_misaligned.stderr.exp 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,4 @@
+you should see: "one\ntwo\nthree\n"
+one
+two
+three
Added: trunk/none/tests/amd64/ssse3_misaligned.stdout.exp
===================================================================
Added: trunk/none/tests/amd64/ssse3_misaligned.vgtest
===================================================================
--- trunk/none/tests/amd64/ssse3_misaligned.vgtest (rev 0)
+++ trunk/none/tests/amd64/ssse3_misaligned.vgtest 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,3 @@
+prog: ssse3_misaligned
+prereq: ../../../tests/cputest amd64-sse3
+vgopts: -q
Modified: trunk/none/tests/x86/Makefile.am
===================================================================
--- trunk/none/tests/x86/Makefile.am 2008-02-09 01:49:32 UTC (rev 7384)
+++ trunk/none/tests/x86/Makefile.am 2008-02-09 01:55:52 UTC (rev 7385)
@@ -5,7 +5,7 @@
INSN_TESTS = insn_basic insn_fpu insn_cmov insn_mmx insn_mmxext \
insn_sse insn_sse2
if BUILD_SSE3_TESTS
- INSN_TESTS += insn_sse3
+ INSN_TESTS += insn_sse3 insn_ssse3
endif
# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
@@ -35,6 +35,7 @@
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
looper.stderr.exp looper.stdout.exp looper.vgtest \
@@ -44,6 +45,8 @@
seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest \
smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest \
yield.stderr.exp yield.stdout.exp yield.disabled
check_PROGRAMS = \
@@ -58,7 +61,7 @@
getseg incdec_alt $(INSN_TESTS) \
jcxz \
lahf looper movx int pushpopseg sbbmisc \
- seg_override sigcontext smc1 yield
+ seg_override sigcontext smc1 ssse3_misaligned yield
AM_CFLAGS = $(WERROR) -Winline -Wall -Wshadow \
@FLAG_M32@ -g -I$(top_srcdir)/include \
Added: trunk/none/tests/x86/insn_ssse3.def
===================================================================
--- trunk/none/tests/x86/insn_ssse3.def (rev 0)
+++ trunk/none/tests/x86/insn_ssse3.def 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,251 @@
+psignb mm.ub[0,10,0,245,0,1,255,254] mm.ub[0,40,80,120,160,200,240,24] => 1.sb[0,40,0,-120,0,-56,16,-24]
+psignb m64.ub[0,10,0,245,0,1,255,254] mm.ub[0,41,79,119,161,199,241,23] => 1.sb[0,41,0,-119,0,-57,15,-23]
+#
+psignb xmm.ub[0,10,0,245,0,1,255,254,1,255,254,0,10,0,245,0] xmm.ub[0,40,80,120,160,200,240,24,3,2,1,0,255,254,253,252] => 1.sb[0,40,0,-120,0,-56,16,-24,3,-2,-1,0,-1,0,3,0]
+psignb m128.ub[0,10,0,245,0,1,255,254,10,0,245,0,1,254,0] xmm.ub[0,41,79,119,161,199,241,23,0,31,69,109,151,189,231,13] => 1.sb[0,41,0,-119,0,-57,15,-23,0,0,-69,0,-105,67,0]
+#
+#
+#
+psignw mm.sw[0,10,0,-11] mm.sw[999,987,986,985] => 1.sw[0,987,0,-985]
+psignw m64.sw[0,1000,0,-1111] mm.sw[909,907,906,905] => 1.sw[0,907,0,-905]
+#
+psignw xmm.sw[0,10,0,-11,1,0,-1,0] xmm.sw[999,987,986,985,888,887,886,885] => 1.sw[0,987,0,-985,888,0,-886,0]
+psignw m128.sw[0,1000,0,-1111,11,0,-11,0] xmm.sw[909,907,906,905,809,808,807,806] => 1.sw[0,907,0,-905,809,0,-807]
+#
+#
+#
+psignd mm.sd[0,10000] mm.sd[-5555,-6666] => 1.sd[0,-6666]
+psignd m64.sd[-11111,0] mm.sd[-7777,-8888] => 1.sd[7777,0]
+#
+psignd xmm.sd[0,10000,-10000,0] xmm.sd[-5555,-6666,-7777,-8888] => 1.sd[0,-6666,7777,0]
+psignd m128.sd[-11111,0,0,1111] xmm.sd[-9999,-10101,-11111,-22222] => 1.sd[9999,0,0,-22222]
+#
+#
+#
+pabsb mm.ub[0,10,0,245,0,1,255,254] mm.ub[0,40,80,120,160,200,240,24] => 1.sb[0,10,0,11,0,1,1,2]
+pabsb m64.ub[0,10,0,245,0,1,255,254] mm.ub[0,41,79,119,161,199,241,23] => 1.sb[0,10,0,11,0,1,1,2]
+#
+pabsb xmm.ub[0,10,0,245,0,1,255,254,1,255,254,0,10,0,245,0] xmm.ub[0,40,80,120,160,200,240,24,3,2,1,0,255,254,253,252] => 1.sb[0,10,0,11,0,1,1,2,1,1,2,0,10,0,11,0]
+pabsb m128.ub[0,10,0,245,0,1,255,254,10,0,245,0,1,254,0] xmm.ub[0,41,79,119,161,199,241,23,0,31,69,109,151,189,231,13] => 1.sb[0,10,0,11,0,1,1,2,10,0,11,0,1,2,0]
+#
+#
+#
+pabsw mm.sw[0,10,0,-11] mm.sw[999,987,986,985] => 1.sw[0,10,0,11]
+pabsw m64.sw[0,1000,0,-1111] mm.sw[909,907,906,905] => 1.sw[0,1000,0,1111]
+#
+pabsw xmm.sw[0,10,0,-11,1,0,-1,0] xmm.sw[999,987,986,985,888,887,886,885] => 1.sw[0,10,0,11,1,0,1,0]
+pabsw m128.sw[0,1000,0,-1111,11,0,-11,0] xmm.sw[909,907,906,905,809,808,807,806] => 1.sw[0,1000,0,1111,11,0,11]
+#
+#
+#
+pabsd mm.sd[0,10000] mm.sd[-5555,-6666] => 1.sd[0,10000]
+pabsd m64.sd[-11111,0] mm.sd[-7777,-8888] => 1.sd[11111,0]
+#
+pabsd xmm.sd[0,14000,-10700,0] xmm.sd[-5555,-6666,-7777,-8888] => 1.sd[0,14000,10700,0]
+pabsd m128.sd[-11111,0,0,1111] xmm.sd[-9999,-10101,-11111,-22222] => 1.sd[11111,0,0,1111]
+#
+#
+#
+palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
+palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
+palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
+palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
+palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
+palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
+palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
+palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
+palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
+palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
+palignr imm8[10] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655443322]
+palignr imm8[11] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433]
+palignr imm8[12] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544]
+palignr imm8[13] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655]
+palignr imm8[14] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766]
+palignr imm8[15] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77]
+palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+#
+palignr imm8[0] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
+palignr imm8[1] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
+palignr imm8[2] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
+palignr imm8[3] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
+palignr imm8[4] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
+palignr imm8[5] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
+palignr imm8[6] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
+palignr imm8[7] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
+palignr imm8[8] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
+palignr imm8[9] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
+palignr imm8[10] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655443322]
+palignr imm8[11] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433]
+palignr imm8[12] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544]
+palignr imm8[13] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x776655]
+palignr imm8[14] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766]
+palignr imm8[15] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77]
+palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[53] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[91] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[137] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[193] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[241] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+palignr imm8[255] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
+#
+palignr imm8[0] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[5940417471140883427,2114202203853458723]
+palignr imm8[1] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2545220547074121835,440604166586370189]
+palignr imm8[2] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[10170063027109847264,6991307731704737800]
+palignr imm8[3] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[616187561003071328,2477267993116521456]
+palignr imm8[4] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17296229551762872887,11899179844356220851]
+palignr imm8[5] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12965872729475674266,11215408247145846567]
+palignr imm8[6] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2860894107828703856,16905287193340550487]
+palignr imm8[7] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6280186048908436306,930727406554121757]
+palignr imm8[8] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2114202203853458723,7713798215990141190]
+palignr imm8[9] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[440604166586370189,2840378191760400993]
+palignr imm8[10] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6991307731704737800,17304917796414268706]
+palignr imm8[11] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2477267993116521456,9579199748148730789]
+palignr imm8[12] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11899179844356220851,3640298450912602779]
+palignr imm8[13] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11215408247145846567,2103890142923787498]
+palignr imm8[14] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[16905287193340550487,6061056220056742668]
+palignr imm8[15] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[930727406554121757,15371943530938247019]
+palignr imm8[16] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[7713798215990141190,3446753574200340519]
+palignr imm8[17] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2840378191760400993,13463881149220080]
+palignr imm8[18] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17304917796414268706,52593285739140]
+palignr imm8[19] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[9579199748148730789,205442522418]
+palignr imm8[20] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3640298450912602779,802509853]
+palignr imm8[21] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2103890142923787498,3134804]
+palignr imm8[22] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6061056220056742668,12245]
+palignr imm8[23] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[15371943530938247019,47]
+palignr imm8[24] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3446753574200340519,0]
+palignr imm8[25] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[13463881149220080,0]
+palignr imm8[26] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[52593285739140,0]
+palignr imm8[27] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[205442522418,0]
+palignr imm8[28] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[802509853,0]
+palignr imm8[29] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3134804,0]
+palignr imm8[30] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12245,0]
+palignr imm8[31] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[47,0]
+palignr imm8[32] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[33] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[53] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[91] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[137] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[193] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[241] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[255] xmm.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+#
+palignr imm8[0] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[5940417471140883427,2114202203853458723]
+palignr imm8[1] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2545220547074121835,440604166586370189]
+palignr imm8[2] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[10170063027109847264,6991307731704737800]
+palignr imm8[3] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[616187561003071328,2477267993116521456]
+palignr imm8[4] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17296229551762872887,11899179844356220851]
+palignr imm8[5] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12965872729475674266,11215408247145846567]
+palignr imm8[6] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2860894107828703856,16905287193340550487]
+palignr imm8[7] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6280186048908436306,930727406554121757]
+palignr imm8[8] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2114202203853458723,7713798215990141190]
+palignr imm8[9] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[440604166586370189,2840378191760400993]
+palignr imm8[10] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6991307731704737800,17304917796414268706]
+palignr imm8[11] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2477267993116521456,9579199748148730789]
+palignr imm8[12] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11899179844356220851,3640298450912602779]
+palignr imm8[13] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[11215408247145846567,2103890142923787498]
+palignr imm8[14] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[16905287193340550487,6061056220056742668]
+palignr imm8[15] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[930727406554121757,15371943530938247019]
+palignr imm8[16] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[7713798215990141190,3446753574200340519]
+palignr imm8[17] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2840378191760400993,13463881149220080]
+palignr imm8[18] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[17304917796414268706,52593285739140]
+palignr imm8[19] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[9579199748148730789,205442522418]
+palignr imm8[20] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3640298450912602779,802509853]
+palignr imm8[21] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[2103890142923787498,3134804]
+palignr imm8[22] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[6061056220056742668,12245]
+palignr imm8[23] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[15371943530938247019,47]
+palignr imm8[24] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3446753574200340519,0]
+palignr imm8[25] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[13463881149220080,0]
+palignr imm8[26] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[52593285739140,0]
+palignr imm8[27] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[205442522418,0]
+palignr imm8[28] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[802509853,0]
+palignr imm8[29] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[3134804,0]
+palignr imm8[30] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[12245,0]
+palignr imm8[31] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[47,0]
+palignr imm8[32] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[33] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[53] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[91] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[137] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[193] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[241] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+palignr imm8[255] m128.uq[0x52709a3760e06be3,0x1d5727b3f0088d23] xmm.uq[0x6b0cea9ba5226106,0x2fd5541d3284f027] => 2.uq[0,0]
+#
+#
+#
+pshufb mm.ub[14,6,4,3,1,0,255,128] mm.ub[50,51,52,53,54,55,56,57] => 1.ub[56,56,54,53,51,50,0,0]
+pshufb m64.ub[14,6,4,3,1,0,255,128] mm.ub[50,51,52,53,54,55,56,57] => 1.ub[56,56,54,53,51,50,0,0]
+#
+pshufb xmm.ub[63,31,15,14,8,7,1,0,255,128,127,126,123,231,213,103] xmm.ub[60,61,62,63,64,65,66,67,70,71,72,73,74,75,76,77] => 1.ub[77,77,77,76,70,67,61,60,0,0,77,76,73,0,0,67]
+pshufb m128.ub[63,31,15,14,8,7,1,0,255,128,127,126,123,231,213,103] xmm.ub[60,61,62,63,64,65,66,67,70,71,72,73,74,75,76,77] => 1.ub[77,77,77,76,70,67,61,60,0,0,77,76,73,0,0,67]
+#
+#
+#
+pmulhrsw mm.ub[14,26,34,173,181,200,255,128] mm.ub[50,151,52,153,54,155,56,157] => 1.uw[60075,17037,11146,25091]
+pmulhrsw m64.ub[14,26,34,173,181,200,255,128] mm.ub[50,151,52,153,54,155,56,157] => 1.uw[60075,17037,11146,25091]
+#
+pmulhrsw xmm.ub[14,26,34,173,181,200,255,128,24,36,44,183,191,210,9,138] xmm.ub[50,151,52,153,54,155,56,157,60,161,62,163,64,165,66,167] => 1.uw[60075,17037,11146,25091,58695,13511,8214,20937]
+pmulhrsw m128.ub[14,26,34,173,181,200,255,128,24,36,44,183,191,210,9,138] xmm.ub[50,151,52,153,54,155,56,157,60,161,62,163,64,165,66,167] => 1.uw[60075,17037,11146,25091,58695,13511,8214,20937]
+#
+#
+#
+pmaddubsw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[32767,-32768,-12730,27484]
+pmaddubsw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[32767,-32768,-12730,27484]
+#
+pmaddubsw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[32767,-32768,-12730,27484,32767,-32768,-13049,27259]
+pmaddubsw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[32767,-32768,-12730,27484,32767,-32768,-13049,27259]
+#
+#
+#
+phsubw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[-512,-25602,27903,23478]
+phsubw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[-512,-25602,27903,23478]
+#
+phsubw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[-512,-25602,-3328,-30672,27903,23478,27391,23989]
+phsubw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[-512,-25602,-3328,-30672,27903,23478,27391,23989]
+#
+#
+#
+phsubd mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1698235191,1082151370]
+phsubd m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1698235191,1082151370]
+#
+phsubd xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1698235191,-1528492107,1082151370,1115705291]
+phsubd m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1698235191,-1528492107,1082151370,1115705291]
+#
+#
+#
+phsubsw mm.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[-32768,-4418,32767,2457]
+phsubsw m64.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[-32768,-4418,32767,2457]
+#
+phsubsw xmm.sw[20000,-21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,18121,134,4552,235,6356,123,75] => 1.sw[-32768,-4418,-6121,48,32767,2457,23,5554]
+phsubsw m128.sw[20000,-21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,18121,134,4552,235,6356,123,75] => 1.sw[-32768,-4418,-6121,48,32767,2457,23,5554]
+#
+#
+#
+phaddw mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[12798,-26002,-14337,13748]
+phaddw m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sw[12798,-26002,-14337,13748]
+#
+phaddw xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[12798,-26002,15102,-31132,-14337,13748,-14337,13747]
+phaddw m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sw[12798,-26002,15102,-31132,-14337,13748,-14337,13747]
+#
+#
+#
+phaddd mm.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1724370123,444588852]
+phaddd m64.ub[127,26,128,173,181,200,255,108] mm.ub[255,151,255,153,54,155,56,255] => 1.sd[-1724370123,444588852]
+#
+phaddd xmm.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1724370123,-1558569399,444588852,444588851]
+phaddd m128.ub[127,26,128,173,181,200,255,108,127,25,128,174,180,201,255,107] xmm.ub[255,151,255,153,54,155,56,255,255,150,255,163,74,135,26,255] => 1.sd[-1724370123,-1558569399,444588852,444588851]
+#
+#
+#
+phaddsw mm.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[1121,4686,-1000,33]
+phaddsw m64.sw[20000,-21000,1245,-1212] mm.sw[-17000,18121,134,4552] => 1.sw[1121,4686,-1000,33]
+#
+phaddsw xmm.sw[20000,21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,-18121,134,4552,235,6356,123,75] => 1.sw[-32768,4686,6591,198,32767,33,91,6022]
+phaddsw m128.sw[20000,21000,1245,-1212,57,34,5788,234] xmm.sw[-17000,-18121,134,4552,235,6356,123,75] => 1.sw[-32768,4686,6591,198,32767,33,91,6022]
Added: trunk/none/tests/x86/insn_ssse3.stderr.exp
===================================================================
Added: trunk/none/tests/x86/insn_ssse3.stdout.exp
===================================================================
--- trunk/none/tests/x86/insn_ssse3.stdout.exp (rev 0)
+++ trunk/none/tests/x86/insn_ssse3.stdout.exp 2008-02-09 01:55:52 UTC (rev 7385)
@@ -0,0 +1,188 @@
+psignb_1 ... ok
+psignb_2 ... ok
+psignb_3 ... ok
+psignb_4 ... ok
+psignw_1 ... ok
+psignw_2 ... ok
+psignw_3 ... ok
+psignw_4 ... ok
+psignd_1 ... ok
+psignd_2 ... ok
+psignd_3 ... ok
+psignd_4 ... ok
+pabsb_1 ... ok
+pabsb_2 ... ok
+pabsb_3 ... ok
+pabsb_4 ... ok
+pabsw_1 ... ok
+pabsw_2 ... ok
+pabsw_3 ... ok
+pabsw_4 ... ok
+pabsd_1 ... ok
+pabsd_2 ... ok
+pabsd_3 ... ok
+pabsd_4 ... ok
+palignr_1 ... ok
+palignr_2 ... ok
+palignr_3 ... ok
+palignr_4 ... ok
+palignr_5 ... ok
+palignr_6 ... ok
+palignr_7 ... ok
+palignr_8 ... ok
+palignr_9 ... ok
+palignr_10 ... ok
+palignr_11 ... ok
+palignr_12 ... ok
+palignr_13 ... ok
+palignr_14 ... ok
+palignr_15 ... ok
+palignr_16 ... ok
+palignr_17 ... ok
+palignr_18 ... ok
+palignr_19 ... ok
+palignr_20 ... ok
+palignr_21 ... ok
+palignr_22 ... ok
+palignr_23 ... ok
+palignr_24 ... ok
+palignr_25 ... ok
+palignr_26 ... ok
+palignr_27 ... ok
+palignr_28 ... ok
+palignr_29 ... ok
+palignr_30 ... ok
+palignr_31 ... ok
+palignr_32 ... ok
+palignr_33 ... ok
+palignr_34 ... ok
+palignr_35 ... ok
+palignr_36 ... ok
+palignr_37 ... ok
+palignr_38 ... ok
+palignr_39 ... ok
+palignr_40 ... ok
+palignr_41 ... ok
+palignr_42 ... ok
+palignr_43 ... ok
+palignr_44 ... ok
+palignr_45 ... ok
+palignr_46 ... ok
+palignr_47 ... ok
+palignr_48 ... ok
+palignr_49 ... ok
+palignr_50 ... ok
+palignr_51 .....
[truncated message content] |
|
From: <sv...@va...> - 2008-02-09 01:49:29
|
Author: sewardj
Date: 2008-02-09 01:49:32 +0000 (Sat, 09 Feb 2008)
New Revision: 7384
Log:
Tool-side support for the new primops required by SSSE3 instructions.
I think this is all that is required on the tools side.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
===================================================================
--- trunk/memcheck/mc_translate.c 2008-02-08 15:17:07 UTC (rev 7383)
+++ trunk/memcheck/mc_translate.c 2008-02-09 01:49:32 UTC (rev 7384)
@@ -1924,6 +1924,7 @@
case Iop_SarN32x2:
case Iop_ShlN16x4:
case Iop_ShlN32x2:
+ case Iop_ShlN8x8:
/* Same scheme as with all other shifts. */
complainIfUndefined(mce, atom2);
return assignNew(mce, Ity_I64, binop(op, vatom1, atom2));
@@ -1963,6 +1964,7 @@
return binary16Ix4(mce, vatom1, vatom2);
case Iop_Sub32x2:
+ case Iop_Mul32x2:
case Iop_CmpGT32Sx2:
case Iop_CmpEQ32x2:
case Iop_Add32x2:
@@ -1975,8 +1977,20 @@
case Iop_InterleaveHI32x2:
case Iop_InterleaveHI16x4:
case Iop_InterleaveHI8x8:
+ case Iop_CatOddLanes16x4:
+ case Iop_CatEvenLanes16x4:
return assignNew(mce, Ity_I64, binop(op, vatom1, vatom2));
+ /* Perm8x8: rearrange values in left arg using steering values
+ from right arg. So rearrange the vbits in the same way but
+ pessimise wrt steering values. */
+ case Iop_Perm8x8:
+ return mkUifU64(
+ mce,
+ assignNew(mce, Ity_I64, binop(op, vatom1, atom2)),
+ mkPCast8x8(mce, vatom2)
+ );
+
/* V128-bit SIMD */
case Iop_ShrN16x8:
|
|
From: <sv...@va...> - 2008-02-09 01:15:59
|
Author: sewardj
Date: 2008-02-09 01:16:02 +0000 (Sat, 09 Feb 2008)
New Revision: 1809
Log:
Finalise SSSE3 support (counterpart to r1808):
* support SSSE3 for 32-bit insns
* For 128-bit variants accessing memory, generate an exception
if effective address is not 128-bit aligned
* Change CPUID output to be Core-2, so now it claims to
be a Core 2 E6600
Modified:
trunk/priv/guest-amd64/ghelpers.c
trunk/priv/guest-amd64/toIR.c
trunk/priv/guest-x86/ghelpers.c
trunk/priv/guest-x86/toIR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-x86/isel.c
Modified: trunk/priv/guest-amd64/ghelpers.c
===================================================================
--- trunk/priv/guest-amd64/ghelpers.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/guest-amd64/ghelpers.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -1758,27 +1758,32 @@
/*--- Misc integer helpers, including rotates and CPUID. ---*/
/*---------------------------------------------------------------*/
-/* Claim to be the following CPU:
- vendor_id : AuthenticAMD
- cpu family : 15
- model : 12
- model name : AMD Athlon(tm) 64 Processor 3200+
- stepping : 0
- cpu MHz : 2202.917
- cache size : 512 KB
+/* Claim to be the following CPU (2 x ...):
+ vendor_id : GenuineIntel
+ cpu family : 6
+ model : 15
+ model name : Intel(R) Core(TM)2 CPU 6600 @ 2.40GHz
+ stepping : 6
+ cpu MHz : 2394.000
+ cache size : 4096 KB
+ physical id : 0
+ siblings : 2
+ core id : 0
+ cpu cores : 2
fpu : yes
fpu_exception : yes
- cpuid level : 1
+ cpuid level : 10
wp : yes
- flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr
- pge mca cmov pat pse36 clflush mmx fxsr sse sse2
- pni syscall nx mmxext lm 3dnowext 3dnow
- bogomips : 4308.99
- TLB size : 1088 4K pages
+ flags : fpu vme de pse tsc msr pae mce cx8 apic sep
+ mtrr pge mca cmov pat pse36 clflush dts acpi
+ mmx fxsr sse sse2 ss ht tm syscall nx lm
+ constant_tsc pni monitor ds_cpl vmx est tm2
+ cx16 xtpr lahf_lm
+ bogomips : 4798.78
clflush size : 64
cache_alignment : 64
- address sizes : 40 bits physical, 48 bits virtual
- power management: ts fid vid ttp
+ address sizes : 36 bits physical, 48 bits virtual
+ power management:
*/
void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* st )
{
@@ -1790,39 +1795,72 @@
} while (0)
switch (0xFFFFFFFF & st->guest_RAX) {
- case 0x0:
- SET_ABCD(0x00000001, 0x68747541, 0x444d4163, 0x69746e65);
+ case 0x00000000:
+ SET_ABCD(0x0000000a, 0x756e6547, 0x6c65746e, 0x49656e69);
break;
- case 0x1:
- SET_ABCD(0x00000fc0, 0x00000800, 0x00000000, 0x078bfbff);
+ case 0x00000001:
+ SET_ABCD(0x000006f6, 0x00020800, 0x0000e3bd, 0xbfebfbff);
break;
- case 0x80000000:
- SET_ABCD(0x80000018, 0x68747541, 0x444d4163, 0x69746e65);
+ case 0x00000002:
+ SET_ABCD(0x05b0b101, 0x005657f0, 0x00000000, 0x2cb43049);
break;
- case 0x80000001:
- SET_ABCD(0x00000fc0, 0x0000010a, 0x00000000, 0xe1d3fbff);
+ case 0x00000003:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
break;
- case 0x80000002:
- SET_ABCD(0x20444d41, 0x6c687441, 0x74286e6f, 0x3620296d);
+ case 0x00000004:
+ SET_ABCD(0x04000121, 0x01c0003f, 0x0000003f, 0x00000001);
break;
- case 0x80000003:
- SET_ABCD(0x72502034, 0x7365636f, 0x20726f73, 0x30303233);
+ case 0x00000005:
+ SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00000020);
break;
- case 0x80000004:
- SET_ABCD(0x0000002b, 0x00000000, 0x00000000, 0x00000000);
+ case 0x00000006:
+ SET_ABCD(0x00000001, 0x00000002, 0x00000001, 0x00000000);
break;
- case 0x80000005:
- SET_ABCD(0xff08ff08, 0xff20ff20, 0x40020140, 0x40020140);
+ case 0x00000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
break;
- case 0x80000006:
- SET_ABCD(0x00000000, 0x42004200, 0x02008140, 0x00000000);
+ case 0x00000008:
+ SET_ABCD(0x00000400, 0x00000000, 0x00000000, 0x00000000);
break;
- case 0x80000007:
- SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x0000000f);
+ case 0x00000009:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
break;
- case 0x80000008:
- SET_ABCD(0x00003028, 0x00000000, 0x00000000, 0x00000000);
+ case 0x0000000a:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
break;
+ case 0x80000000:
+ SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000001:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000001, 0x20100800);
+ break;
+ case 0x80000002:
+ SET_ABCD(0x65746e49, 0x2952286c, 0x726f4320, 0x4d542865);
+ break;
+ case 0x80000003:
+ SET_ABCD(0x43203229, 0x20205550, 0x20202020, 0x20202020);
+ break;
+ case 0x80000004:
+ SET_ABCD(0x30303636, 0x20402020, 0x30342e32, 0x007a4847);
+ break;
+ case 0x80000005:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000006:
+ SET_ABCD(0x00000000, 0x00000000, 0x10008040, 0x00000000);
+ break;
+ case 0x80000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000008:
+ SET_ABCD(0x00003024, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80860000:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0xc0000000:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
+ break;
default:
SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
break;
Modified: trunk/priv/guest-amd64/toIR.c
===================================================================
--- trunk/priv/guest-amd64/toIR.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/guest-amd64/toIR.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -8467,7 +8467,24 @@
);
}
+/* Generate a SIGSEGV followed by a restart of the current instruction
+ if effective_addr is not 16-aligned. This is required behaviour
+ for some SSE3 instructions and all 128-bit SSSE3 instructions.
+ This assumes that guest_RIP_curr_instr is set correctly! */
+static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr )
+{
+ stmt(
+ IRStmt_Exit(
+ binop(Iop_CmpNE64,
+ binop(Iop_And64,mkexpr(effective_addr),mkU64(0xF)),
+ mkU64(0)),
+ Ijk_SigSEGV,
+ IRConst_U64(guest_RIP_curr_instr)
+ )
+ );
+}
+
/* Helper for deciding whether a given insn (starting at the opcode
byte) may validly be used with a LOCK prefix. The following insns
may be used with LOCK when their destination operand is in memory.
@@ -12693,7 +12710,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
delta += 3+alen;
DIP("pmaddubsw %s,%s\n", dis_buf,
@@ -12846,7 +12863,7 @@
delta += 3+1;
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
DIP("ph%s %s,%s\n", str, dis_buf,
nameXMMReg(gregOfRexRM(pfx,modrm)));
@@ -12931,7 +12948,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
delta += 3+alen;
DIP("pmulhrsw %s,%s\n", dis_buf,
@@ -13029,7 +13046,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
delta += 3+alen;
DIP("psign%s %s,%s\n", str, dis_buf,
@@ -13121,7 +13138,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
delta += 3+alen;
DIP("pabs%s %s,%s\n", str, dis_buf,
@@ -13220,7 +13237,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
d64 = (Long)insn[3+alen];
delta += 3+alen+1;
@@ -13240,7 +13257,7 @@
}
else if (d64 >= 1 && d64 <= 7) {
assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, d64) );
- assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d64) );
+ assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d64) );
}
else if (d64 == 8) {
assign( rHi, mkexpr(dLo) );
@@ -13248,7 +13265,7 @@
}
else if (d64 >= 9 && d64 <= 15) {
assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, d64-8) );
- assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d64-8) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d64-8) );
}
else if (d64 == 16) {
assign( rHi, mkexpr(dHi) );
@@ -13256,7 +13273,7 @@
}
else if (d64 >= 17 && d64 <= 23) {
assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d64-16))) );
- assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d64-16) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d64-16) );
}
else if (d64 == 24) {
assign( rHi, mkU64(0) );
@@ -13313,7 +13330,7 @@
Iop_Perm8x8,
mkexpr(dV),
binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL))
- ),
+ ),
/* mask off lanes which have (index & 0x80) == 0x80 */
unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7)))
)
@@ -13353,7 +13370,7 @@
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
addr = disAMode ( &alen, pfx, delta+3, dis_buf, 0 );
- /* FIXME: generate trap if addr is not 16-aligned */
+ gen_SEGV_if_not_16_aligned( addr );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
delta += 3+alen;
DIP("pshufb %s,%s\n", dis_buf,
Modified: trunk/priv/guest-x86/ghelpers.c
===================================================================
--- trunk/priv/guest-x86/ghelpers.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/guest-x86/ghelpers.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -2075,37 +2075,114 @@
}
}
-/* Claim to be the following SSE2-capable CPU:
+/* Claim to be the following SSSE3-capable CPU (2 x ...):
vendor_id : GenuineIntel
- cpu family : 15
- model : 2
- model name : Intel(R) Pentium(R) 4 CPU 2.40GHz
- stepping : 7
- cpu MHz : 2394.234
- cache size : 512 KB
+ cpu family : 6
+ model : 15
+ model name : Intel(R) Core(TM)2 CPU 6600 @ 2.40GHz
+ stepping : 6
+ cpu MHz : 2394.000
+ cache size : 4096 KB
+ physical id : 0
+ siblings : 2
+ core id : 0
+ cpu cores : 2
+ fpu : yes
+ fpu_exception : yes
+ cpuid level : 10
+ wp : yes
+ flags : fpu vme de pse tsc msr pae mce cx8 apic sep
+ mtrr pge mca cmov pat pse36 clflush dts acpi
+ mmx fxsr sse sse2 ss ht tm syscall nx lm
+ constant_tsc pni monitor ds_cpl vmx est tm2
+ cx16 xtpr lahf_lm
+ bogomips : 4798.78
+ clflush size : 64
+ cache_alignment : 64
+ address sizes : 36 bits physical, 48 bits virtual
+ power management:
*/
void x86g_dirtyhelper_CPUID_sse2 ( VexGuestX86State* st )
{
+# define SET_ABCD(_a,_b,_c,_d) \
+ do { st->guest_EAX = (UInt)(_a); \
+ st->guest_EBX = (UInt)(_b); \
+ st->guest_ECX = (UInt)(_c); \
+ st->guest_EDX = (UInt)(_d); \
+ } while (0)
+
switch (st->guest_EAX) {
- case 0:
- st->guest_EAX = 0x00000002;
- st->guest_EBX = 0x756e6547;
- st->guest_ECX = 0x6c65746e;
- st->guest_EDX = 0x49656e69;
+ case 0x00000000:
+ SET_ABCD(0x0000000a, 0x756e6547, 0x6c65746e, 0x49656e69);
break;
- case 1:
- st->guest_EAX = 0x00000f27;
- st->guest_EBX = 0x00010809;
- st->guest_ECX = 0x00004400;
- st->guest_EDX = 0xbfebfbff;
+ case 0x00000001:
+ SET_ABCD(0x000006f6, 0x00020800, 0x0000e3bd, 0xbfebfbff);
break;
- default:
- st->guest_EAX = 0x665b5101;
- st->guest_EBX = 0x00000000;
- st->guest_ECX = 0x00000000;
- st->guest_EDX = 0x007b7040;
+ case 0x00000002:
+ SET_ABCD(0x05b0b101, 0x005657f0, 0x00000000, 0x2cb43049);
break;
+ case 0x00000003:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000004:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000005:
+ SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00000020);
+ break;
+ case 0x00000006:
+ SET_ABCD(0x00000001, 0x00000002, 0x00000001, 0x00000000);
+ break;
+ case 0x00000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000008:
+ SET_ABCD(0x00000400, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000009:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x0000000a:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000000:
+ SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000001:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000001, 0x20100000);
+ break;
+ case 0x80000002:
+ SET_ABCD(0x65746e49, 0x2952286c, 0x726f4320, 0x4d542865);
+ break;
+ case 0x80000003:
+ SET_ABCD(0x43203229, 0x20205550, 0x20202020, 0x20202020);
+ break;
+ case 0x80000004:
+ SET_ABCD(0x30303636, 0x20402020, 0x30342e32, 0x007a4847);
+ break;
+ case 0x80000005:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000006:
+ SET_ABCD(0x00000000, 0x00000000, 0x10008040, 0x00000000);
+ break;
+ case 0x80000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000008:
+ SET_ABCD(0x00003024, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80860000:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0xc0000000:
+ SET_ABCD(0x07280202, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ default:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
}
+# undef SET_ABCD
}
Modified: trunk/priv/guest-x86/toIR.c
===================================================================
--- trunk/priv/guest-x86/toIR.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/guest-x86/toIR.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -7225,6 +7225,182 @@
}
+/* Helper for the SSSE3 (not SSE3) PMULHRSW insns. Given two 64-bit
+ values (aa,bb), computes, for each of the 4 16-bit lanes:
+
+ (((aa_lane *s32 bb_lane) >>u 14) + 1) >>u 1
+*/
+static IRExpr* dis_PMULHRSW_helper ( IRExpr* aax, IRExpr* bbx )
+{
+ IRTemp aa = newTemp(Ity_I64);
+ IRTemp bb = newTemp(Ity_I64);
+ IRTemp aahi32s = newTemp(Ity_I64);
+ IRTemp aalo32s = newTemp(Ity_I64);
+ IRTemp bbhi32s = newTemp(Ity_I64);
+ IRTemp bblo32s = newTemp(Ity_I64);
+ IRTemp rHi = newTemp(Ity_I64);
+ IRTemp rLo = newTemp(Ity_I64);
+ IRTemp one32x2 = newTemp(Ity_I64);
+ assign(aa, aax);
+ assign(bb, bbx);
+ assign( aahi32s,
+ binop(Iop_SarN32x2,
+ binop(Iop_InterleaveHI16x4, mkexpr(aa), mkexpr(aa)),
+ mkU8(16) ));
+ assign( aalo32s,
+ binop(Iop_SarN32x2,
+ binop(Iop_InterleaveLO16x4, mkexpr(aa), mkexpr(aa)),
+ mkU8(16) ));
+ assign( bbhi32s,
+ binop(Iop_SarN32x2,
+ binop(Iop_InterleaveHI16x4, mkexpr(bb), mkexpr(bb)),
+ mkU8(16) ));
+ assign( bblo32s,
+ binop(Iop_SarN32x2,
+ binop(Iop_InterleaveLO16x4, mkexpr(bb), mkexpr(bb)),
+ mkU8(16) ));
+ assign(one32x2, mkU64( (1ULL << 32) + 1 ));
+ assign(
+ rHi,
+ binop(
+ Iop_ShrN32x2,
+ binop(
+ Iop_Add32x2,
+ binop(
+ Iop_ShrN32x2,
+ binop(Iop_Mul32x2, mkexpr(aahi32s), mkexpr(bbhi32s)),
+ mkU8(14)
+ ),
+ mkexpr(one32x2)
+ ),
+ mkU8(1)
+ )
+ );
+ assign(
+ rLo,
+ binop(
+ Iop_ShrN32x2,
+ binop(
+ Iop_Add32x2,
+ binop(
+ Iop_ShrN32x2,
+ binop(Iop_Mul32x2, mkexpr(aalo32s), mkexpr(bblo32s)),
+ mkU8(14)
+ ),
+ mkexpr(one32x2)
+ ),
+ mkU8(1)
+ )
+ );
+ return
+ binop(Iop_CatEvenLanes16x4, mkexpr(rHi), mkexpr(rLo));
+}
+
+/* Helper for the SSSE3 (not SSE3) PSIGN{B,W,D} insns. Given two 64-bit
+ values (aa,bb), computes, for each lane:
+
+ if aa_lane < 0 then - bb_lane
+ else if aa_lane > 0 then bb_lane
+ else 0
+*/
+static IRExpr* dis_PSIGN_helper ( IRExpr* aax, IRExpr* bbx, Int laneszB )
+{
+ IRTemp aa = newTemp(Ity_I64);
+ IRTemp bb = newTemp(Ity_I64);
+ IRTemp zero = newTemp(Ity_I64);
+ IRTemp bbNeg = newTemp(Ity_I64);
+ IRTemp negMask = newTemp(Ity_I64);
+ IRTemp posMask = newTemp(Ity_I64);
+ IROp opSub = Iop_INVALID;
+ IROp opCmpGTS = Iop_INVALID;
+
+ switch (laneszB) {
+ case 1: opSub = Iop_Sub8x8; opCmpGTS = Iop_CmpGT8Sx8; break;
+ case 2: opSub = Iop_Sub16x4; opCmpGTS = Iop_CmpGT16Sx4; break;
+ case 4: opSub = Iop_Sub32x2; opCmpGTS = Iop_CmpGT32Sx2; break;
+ default: vassert(0);
+ }
+
+ assign( aa, aax );
+ assign( bb, bbx );
+ assign( zero, mkU64(0) );
+ assign( bbNeg, binop(opSub, mkexpr(zero), mkexpr(bb)) );
+ assign( negMask, binop(opCmpGTS, mkexpr(zero), mkexpr(aa)) );
+ assign( posMask, binop(opCmpGTS, mkexpr(aa), mkexpr(zero)) );
+
+ return
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(bb), mkexpr(posMask)),
+ binop(Iop_And64, mkexpr(bbNeg), mkexpr(negMask)) );
+
+}
+
+/* Helper for the SSSE3 (not SSE3) PABS{B,W,D} insns. Given a 64-bit
+ value aa, computes, for each lane
+
+ if aa < 0 then -aa else aa
+
+ Note that the result is interpreted as unsigned, so that the
+ absolute value of the most negative signed input can be
+ represented.
+*/
+static IRExpr* dis_PABS_helper ( IRExpr* aax, Int laneszB )
+{
+ IRTemp aa = newTemp(Ity_I64);
+ IRTemp zero = newTemp(Ity_I64);
+ IRTemp aaNeg = newTemp(Ity_I64);
+ IRTemp negMask = newTemp(Ity_I64);
+ IRTemp posMask = newTemp(Ity_I64);
+ IROp opSub = Iop_INVALID;
+ IROp opSarN = Iop_INVALID;
+
+ switch (laneszB) {
+ case 1: opSub = Iop_Sub8x8; opSarN = Iop_SarN8x8; break;
+ case 2: opSub = Iop_Sub16x4; opSarN = Iop_SarN16x4; break;
+ case 4: opSub = Iop_Sub32x2; opSarN = Iop_SarN32x2; break;
+ default: vassert(0);
+ }
+
+ assign( aa, aax );
+ assign( negMask, binop(opSarN, mkexpr(aa), mkU8(8*laneszB-1)) );
+ assign( posMask, unop(Iop_Not64, mkexpr(negMask)) );
+ assign( zero, mkU64(0) );
+ assign( aaNeg, binop(opSub, mkexpr(zero), mkexpr(aa)) );
+ return
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(aa), mkexpr(posMask)),
+ binop(Iop_And64, mkexpr(aaNeg), mkexpr(negMask)) );
+}
+
+static IRExpr* dis_PALIGNR_XMM_helper ( IRTemp hi64,
+ IRTemp lo64, Int byteShift )
+{
+ vassert(byteShift >= 1 && byteShift <= 7);
+ return
+ binop(Iop_Or64,
+ binop(Iop_Shl64, mkexpr(hi64), mkU8(8*(8-byteShift))),
+ binop(Iop_Shr64, mkexpr(lo64), mkU8(8*byteShift))
+ );
+}
+
+/* Generate a SIGSEGV followed by a restart of the current instruction
+ if effective_addr is not 16-aligned. This is required behaviour
+ for some SSE3 instructions and all 128-bit SSSE3 instructions.
+ This assumes that guest_RIP_curr_instr is set correctly! */
+static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr )
+{
+ stmt(
+ IRStmt_Exit(
+ binop(Iop_CmpNE32,
+ binop(Iop_And32,mkexpr(effective_addr),mkU32(0xF)),
+ mkU32(0)),
+ Ijk_SigSEGV,
+ IRConst_U32(guest_EIP_curr_instr)
+ )
+ );
+}
+
+
/* Helper for deciding whether a given insn (starting at the opcode
byte) may validly be used with a LOCK prefix. The following insns
may be used with LOCK when their destination operand is in memory.
@@ -11167,6 +11343,817 @@
/* --- end of the SSE3 decoder. --- */
/* ---------------------------------------------------- */
+ /* ---------------------------------------------------- */
+ /* --- start of the SSSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
+ Unsigned Bytes (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ IRTemp sVoddsSX = newTemp(Ity_I64);
+ IRTemp sVevensSX = newTemp(Ity_I64);
+ IRTemp dVoddsZX = newTemp(Ity_I64);
+ IRTemp dVevensZX = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pmaddubsw %s,%s\n", nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pmaddubsw %s,%s\n", dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ /* compute dV unsigned x sV signed */
+ assign( sVoddsSX,
+ binop(Iop_SarN16x4, mkexpr(sV), mkU8(8)) );
+ assign( sVevensSX,
+ binop(Iop_SarN16x4,
+ binop(Iop_ShlN16x4, mkexpr(sV), mkU8(8)),
+ mkU8(8)) );
+ assign( dVoddsZX,
+ binop(Iop_ShrN16x4, mkexpr(dV), mkU8(8)) );
+ assign( dVevensZX,
+ binop(Iop_ShrN16x4,
+ binop(Iop_ShlN16x4, mkexpr(dV), mkU8(8)),
+ mkU8(8)) );
+
+ putMMXReg(
+ gregOfRM(modrm),
+ binop(Iop_QAdd16Sx4,
+ binop(Iop_Mul16x4, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
+ binop(Iop_Mul16x4, mkexpr(sVevensSX), mkexpr(dVevensZX))
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
+ Unsigned Bytes (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sVoddsSX = newTemp(Ity_V128);
+ IRTemp sVevensSX = newTemp(Ity_V128);
+ IRTemp dVoddsZX = newTemp(Ity_V128);
+ IRTemp dVevensZX = newTemp(Ity_V128);
+
+ modrm = insn[3];
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pmaddubsw %s,%s\n", nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pmaddubsw %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ /* compute dV unsigned x sV signed */
+ assign( sVoddsSX,
+ binop(Iop_SarN16x8, mkexpr(sV), mkU8(8)) );
+ assign( sVevensSX,
+ binop(Iop_SarN16x8,
+ binop(Iop_ShlN16x8, mkexpr(sV), mkU8(8)),
+ mkU8(8)) );
+ assign( dVoddsZX,
+ binop(Iop_ShrN16x8, mkexpr(dV), mkU8(8)) );
+ assign( dVevensZX,
+ binop(Iop_ShrN16x8,
+ binop(Iop_ShlN16x8, mkexpr(dV), mkU8(8)),
+ mkU8(8)) );
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_QAdd16Sx8,
+ binop(Iop_Mul16x8, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
+ binop(Iop_Mul16x8, mkexpr(sVevensSX), mkexpr(dVevensZX))
+ )
+ );
+ goto decode_success;
+ }
+
+ /* ***--- these are MMX class insns introduced in SSSE3 ---*** */
+ /* 0F 38 03 = PHADDSW -- 16x4 signed qadd across from E (mem or
+ mmx) and G to G (mmx). */
+ /* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or
+ mmx) and G to G (mmx). */
+ /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G
+ to G (mmx). */
+
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
+ || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
+ HChar* str = "???";
+ IROp opV64 = Iop_INVALID;
+ IROp opCatO = Iop_CatOddLanes16x4;
+ IROp opCatE = Iop_CatEvenLanes16x4;
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+
+ modrm = insn[3];
+
+ switch (insn[2]) {
+ case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
+ case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
+ case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
+ case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
+ case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
+ case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
+ default: vassert(0);
+ }
+ if (insn[2] == 0x02 || insn[2] == 0x06) {
+ opCatO = Iop_InterleaveHI32x2;
+ opCatE = Iop_InterleaveLO32x2;
+ }
+
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("ph%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("ph%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ putMMXReg(
+ gregOfRM(modrm),
+ binop(opV64,
+ binop(opCatE,mkexpr(sV),mkexpr(dV)),
+ binop(opCatO,mkexpr(sV),mkexpr(dV))
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 03 = PHADDSW -- 16x8 signed qadd across from E (mem or
+ xmm) and G to G (xmm). */
+ /* 66 0F 38 07 = PHSUBSW -- 16x8 signed qsub across from E (mem or
+ xmm) and G to G (xmm). */
+ /* 66 0F 38 01 = PHADDW -- 16x8 add across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 05 = PHSUBW -- 16x8 sub across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 02 = PHADDD -- 32x4 add across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 06 = PHSUBD -- 32x4 sub across from E (mem or xmm) and
+ G to G (xmm). */
+
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
+ || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
+ HChar* str = "???";
+ IROp opV64 = Iop_INVALID;
+ IROp opCatO = Iop_CatOddLanes16x4;
+ IROp opCatE = Iop_CatEvenLanes16x4;
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+
+ modrm = insn[3];
+
+ switch (insn[2]) {
+ case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
+ case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
+ case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
+ case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
+ case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
+ case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
+ default: vassert(0);
+ }
+ if (insn[2] == 0x02 || insn[2] == 0x06) {
+ opCatO = Iop_InterleaveHI32x2;
+ opCatE = Iop_InterleaveLO32x2;
+ }
+
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg( eregOfRM(modrm)) );
+ DIP("ph%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ delta += 3+1;
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("ph%s %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ delta += 3+alen;
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ /* This isn't a particularly efficient way to compute the
+ result, but at least it avoids a proliferation of IROps,
+ hence avoids complication all the backends. */
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128,
+ binop(opV64,
+ binop(opCatE,mkexpr(sHi),mkexpr(sLo)),
+ binop(opCatO,mkexpr(sHi),mkexpr(sLo))
+ ),
+ binop(opV64,
+ binop(opCatE,mkexpr(dHi),mkexpr(dLo)),
+ binop(opCatO,mkexpr(dHi),mkexpr(dLo))
+ )
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and Scale
+ (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pmulhrsw %s,%s\n", nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pmulhrsw %s,%s\n", dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ putMMXReg(
+ gregOfRM(modrm),
+ dis_PMULHRSW_helper( mkexpr(sV), mkexpr(dV) )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and
+ Scale (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pmulhrsw %s,%s\n", nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pmulhrsw %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128,
+ dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ),
+ dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) )
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */
+ /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */
+ /* 0F 38 09 = PSIGND -- Packed Sign 32x2 (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (insn[2]) {
+ case 0x08: laneszB = 1; str = "b"; break;
+ case 0x09: laneszB = 2; str = "w"; break;
+ case 0x0A: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = insn[3];
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("psign%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("psign%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ putMMXReg(
+ gregOfRM(modrm),
+ dis_PSIGN_helper( mkexpr(sV), mkexpr(dV), laneszB )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 08 = PSIGNB -- Packed Sign 8x16 (XMM) */
+ /* 66 0F 38 09 = PSIGNW -- Packed Sign 16x8 (XMM) */
+ /* 66 0F 38 09 = PSIGND -- Packed Sign 32x4 (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (insn[2]) {
+ case 0x08: laneszB = 1; str = "b"; break;
+ case 0x09: laneszB = 2; str = "w"; break;
+ case 0x0A: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = insn[3];
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("psign%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("psign%s %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128,
+ dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ),
+ dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB )
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */
+ /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */
+ /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) {
+ IRTemp sV = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (insn[2]) {
+ case 0x1C: laneszB = 1; str = "b"; break;
+ case 0x1D: laneszB = 2; str = "w"; break;
+ case 0x1E: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = insn[3];
+ do_MMX_preamble();
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pabs%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pabs%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ putMMXReg(
+ gregOfRM(modrm),
+ dis_PABS_helper( mkexpr(sV), laneszB )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 1C = PABSB -- Packed Absolute Value 8x16 (XMM) */
+ /* 66 0F 38 1D = PABSW -- Packed Absolute Value 16x8 (XMM) */
+ /* 66 0F 38 1E = PABSD -- Packed Absolute Value 32x4 (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (insn[2]) {
+ case 0x1C: laneszB = 1; str = "b"; break;
+ case 0x1D: laneszB = 2; str = "w"; break;
+ case 0x1E: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = insn[3];
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pabs%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pabs%s %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128,
+ dis_PABS_helper( mkexpr(sHi), laneszB ),
+ dis_PABS_helper( mkexpr(sLo), laneszB )
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ IRTemp res = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ d32 = (UInt)insn[3+1];
+ delta += 3+1+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d32,
+ nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ d32 = (UInt)insn[3+alen];
+ delta += 3+alen+1;
+ DIP("palignr $%d%s,%s\n", (Int)d32,
+ dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ if (d32 == 0) {
+ assign( res, mkexpr(sV) );
+ }
+ else if (d32 >= 1 && d32 <= 7) {
+ assign(res,
+ binop(Iop_Or64,
+ binop(Iop_Shr64, mkexpr(sV), mkU8(8*d32)),
+ binop(Iop_Shl64, mkexpr(dV), mkU8(8*(8-d32))
+ )));
+ }
+ else if (d32 == 8) {
+ assign( res, mkexpr(dV) );
+ }
+ else if (d32 >= 9 && d32 <= 15) {
+ assign( res, binop(Iop_Shr64, mkexpr(dV), mkU8(8*(d32-8))) );
+ }
+ else if (d32 >= 16 && d32 <= 255) {
+ assign( res, mkU64(0) );
+ }
+ else
+ vassert(0);
+
+ putMMXReg( gregOfRM(modrm), mkexpr(res) );
+ goto decode_success;
+ }
+
+ /* 66 0F 3A 0F = PALIGNR -- Packed Align Right (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ IRTemp rHi = newTemp(Ity_I64);
+ IRTemp rLo = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ d32 = (UInt)insn[3+1];
+ delta += 3+1+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d32,
+ nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ d32 = (UInt)insn[3+alen];
+ delta += 3+alen+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d32,
+ dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ if (d32 == 0) {
+ assign( rHi, mkexpr(sHi) );
+ assign( rLo, mkexpr(sLo) );
+ }
+ else if (d32 >= 1 && d32 <= 7) {
+ assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, d32) );
+ assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d32) );
+ }
+ else if (d32 == 8) {
+ assign( rHi, mkexpr(dLo) );
+ assign( rLo, mkexpr(sHi) );
+ }
+ else if (d32 >= 9 && d32 <= 15) {
+ assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, d32-8) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d32-8) );
+ }
+ else if (d32 == 16) {
+ assign( rHi, mkexpr(dHi) );
+ assign( rLo, mkexpr(dLo) );
+ }
+ else if (d32 >= 17 && d32 <= 23) {
+ assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-16))) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d32-16) );
+ }
+ else if (d32 == 24) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, mkexpr(dHi) );
+ }
+ else if (d32 >= 25 && d32 <= 31) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-24))) );
+ }
+ else if (d32 >= 32 && d32 <= 255) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, mkU64(0) );
+ }
+ else
+ vassert(0);
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo))
+ );
+ goto decode_success;
+ }
+
+ /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */
+ if (sz == 4
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pshufb %s,%s\n", nameMMXReg(eregOfRM(modrm)),
+ nameMMXReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pshufb %s,%s\n", dis_buf,
+ nameMMXReg(gregOfRM(modrm)));
+ }
+
+ putMMXReg(
+ gregOfRM(modrm),
+ binop(
+ Iop_And64,
+ /* permute the lanes */
+ binop(
+ Iop_Perm8x8,
+ mkexpr(dV),
+ binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL))
+ ),
+ /* mask off lanes which have (index & 0x80) == 0x80 */
+ unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7)))
+ )
+ );
+ goto decode_success;
+ }
+
+ /* 66 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x16 (XMM) */
+ if (sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ IRTemp rHi = newTemp(Ity_I64);
+ IRTemp rLo = newTemp(Ity_I64);
+ IRTemp sevens = newTemp(Ity_I64);
+ IRTemp mask0x80hi = newTemp(Ity_I64);
+ IRTemp mask0x80lo = newTemp(Ity_I64);
+ IRTemp maskBit3hi = newTemp(Ity_I64);
+ IRTemp maskBit3lo = newTemp(Ity_I64);
+ IRTemp sAnd7hi = newTemp(Ity_I64);
+ IRTemp sAnd7lo = newTemp(Ity_I64);
+ IRTemp permdHi = newTemp(Ity_I64);
+ IRTemp permdLo = newTemp(Ity_I64);
+
+ modrm = insn[3];
+ assign( dV, getXMMReg(gregOfRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRM(modrm)) );
+ delta += 3+1;
+ DIP("pshufb %s,%s\n", nameXMMReg(eregOfRM(modrm)),
+ nameXMMReg(gregOfRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, sorb, delta+3, dis_buf );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += 3+alen;
+ DIP("pshufb %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRM(modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ assign( sevens, mkU64(0x0707070707070707ULL) );
+
+ /*
+ mask0x80hi = Not(SarN8x8(sHi,7))
+ maskBit3hi = SarN8x8(ShlN8x8(sHi,4),7)
+ sAnd7hi = And(sHi,sevens)
+ permdHi = Or( And(Perm8x8(dHi,sAnd7hi),maskBit3hi),
+ And(Perm8x8(dLo,sAnd7hi),Not(maskBit3hi)) )
+ rHi = And(permdHi,mask0x80hi)
+ */
+ assign(
+ mask0x80hi,
+ unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sHi),mkU8(7))));
+
+ assign(
+ maskBit3hi,
+ binop(Iop_SarN8x8,
+ binop(Iop_ShlN8x8,mkexpr(sHi),mkU8(4)),
+ mkU8(7)));
+
+ assign(sAnd7hi, binop(Iop_And64,mkexpr(sHi),mkexpr(sevens)));
+
+ assign(
+ permdHi,
+ binop(
+ Iop_Or64,
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7hi)),
+ mkexpr(maskBit3hi)),
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7hi)),
+ unop(Iop_Not64,mkexpr(maskBit3hi))) ));
+
+ assign(rHi, binop(Iop_And64,mkexpr(permdHi),mkexpr(mask0x80hi)) );
+
+ /* And the same for the lower half of the result. What fun. */
+
+ assign(
+ mask0x80lo,
+ unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sLo),mkU8(7))));
+
+ assign(
+ maskBit3lo,
+ binop(Iop_SarN8x8,
+ binop(Iop_ShlN8x8,mkexpr(sLo),mkU8(4)),
+ mkU8(7)));
+
+ assign(sAnd7lo, binop(Iop_And64,mkexpr(sLo),mkexpr(sevens)));
+
+ assign(
+ permdLo,
+ binop(
+ Iop_Or64,
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7lo)),
+ mkexpr(maskBit3lo)),
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7lo)),
+ unop(Iop_Not64,mkexpr(maskBit3lo))) ));
+
+ assign(rLo, binop(Iop_And64,mkexpr(permdLo),mkexpr(mask0x80lo)) );
+
+ putXMMReg(
+ gregOfRM(modrm),
+ binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo))
+ );
+ goto decode_success;
+ }
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
after_sse_decoders:
/* ---------------------------------------------------- */
Modified: trunk/priv/host-amd64/hdefs.c
===================================================================
--- trunk/priv/host-amd64/hdefs.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/host-amd64/hdefs.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -2692,6 +2692,9 @@
case Ijk_SigTRAP:
*p++ = 0xBD;
p = emit32(p, VEX_TRC_JMP_SIGTRAP); break;
+ case Ijk_SigSEGV:
+ *p++ = 0xBD;
+ p = emit32(p, VEX_TRC_JMP_SIGSEGV); break;
case Ijk_Ret:
case Ijk_Call:
case Ijk_Boring:
Modified: trunk/priv/host-x86/isel.c
===================================================================
--- trunk/priv/host-x86/isel.c 2008-02-06 11:42:45 UTC (rev 1808)
+++ trunk/priv/host-x86/isel.c 2008-02-09 01:16:02 UTC (rev 1809)
@@ -2324,6 +2324,12 @@
fn = (HWord)h_generic_calc_InterleaveHI32x2; goto binnish;
case Iop_InterleaveLO32x2:
fn = (HWord)h_generic_calc_InterleaveLO32x2; goto binnish;
+ case Iop_CatOddLanes16x4:
+ fn = (HWord)h_generic_calc_CatOddLanes16x4; goto binnish;
+ case Iop_CatEvenLanes16x4:
+ fn = (HWord)h_generic_calc_CatEvenLanes16x4; goto binnish;
+ case Iop_Perm8x8:
+ fn = (HWord)h_generic_calc_Perm8x8; goto binnish;
case Iop_Max8Ux8:
fn = (HWord)h_generic_calc_Max8Ux8; goto binnish;
@@ -2336,6 +2342,8 @@
case Iop_Mul16x4:
fn = (HWord)h_generic_calc_Mul16x4; goto binnish;
+ case Iop_Mul32x2:
+ fn = (HWord)h_generic_calc_Mul32x2; goto binnish;
case Iop_MulHi16Sx4:
fn = (HWord)h_generic_calc_MulHi16Sx4; goto binnish;
case Iop_MulHi16Ux4:
@@ -2401,6 +2409,8 @@
fn = (HWord)h_generic_calc_ShlN32x2; goto shifty;
case Iop_ShlN16x4:
fn = (HWord)h_generic_calc_ShlN16x4; goto shifty;
+ case Iop_ShlN8x8:
+ fn = (HWord)h_generic_calc_ShlN8x8; goto shifty;
case Iop_ShrN32x2:
fn = (HWord)h_generic_calc_ShrN32x2; goto shifty;
case Iop_ShrN16x4:
|