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From: <sv...@va...> - 2007-05-06 17:44:22
|
Author: sewardj
Date: 2007-05-06 18:44:16 +0100 (Sun, 06 May 2007)
New Revision: 1766
Log:
Followup to r1765: fix some comments, and rearrange fields in struct
RRegState so as to fit it into 16 bytes.
Modified:
branches/CGTUNE/priv/host-generic/reg_alloc2.c
Modified: branches/CGTUNE/priv/host-generic/reg_alloc2.c
===================================================================
--- branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 15:21:57 UTC (rev 1765)
+++ branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 17:44:16 UTC (rev 1766)
@@ -56,9 +56,6 @@
/* TODO 27 Oct 04:
- (Critical): Need a way to statically establish the vreg classes,
- else we can't allocate spill slots properly.
-
Better consistency checking from what isMove tells us.
We can possibly do V-V coalescing even when the src is spilled,
@@ -66,10 +63,6 @@
Note that state[].hreg is the same as the available real regs.
- Check whether rreg preferencing has any beneficial effect.
-
- Remove preferencing fields in VRegInfo, if not used.
-
Generally rationalise data structures. */
@@ -109,20 +102,14 @@
updated as the allocator processes instructions. */
typedef
struct {
- /* FIELDS WHICH DO NOT CHANGE */
+ /* ------ FIELDS WHICH DO NOT CHANGE ------ */
/* Which rreg is this for? */
HReg rreg;
/* Is this involved in any HLRs? (only an optimisation hint) */
Bool has_hlrs;
- /* FIELDS WHICH DO CHANGE */
- /* What's it's current disposition? */
- enum { Free, /* available for use */
- Unavail, /* in a real-reg live range */
- Bound /* in use (holding value of some vreg) */
- }
- disp;
- /* If RRegBound, what vreg is it bound to? */
- HReg vreg;
+ /* ------ FIELDS WHICH DO CHANGE ------ */
+ /* 6 May 07: rearranged fields below so the whole struct fits
+ into 16 bytes on both x86 and amd64. */
/* Used when .disp == Bound and we are looking for vregs to
spill. */
Bool is_spill_cand;
@@ -131,6 +118,14 @@
vreg. Is safely left at False, and becomes True after a
spill store or reload for this rreg. */
Bool eq_spill_slot;
+ /* What's it's current disposition? */
+ enum { Free, /* available for use */
+ Unavail, /* in a real-reg live range */
+ Bound /* in use (holding value of some vreg) */
+ }
+ disp;
+ /* If .disp == Bound, what vreg is it bound to? */
+ HReg vreg;
}
RRegState;
@@ -1043,9 +1038,9 @@
vreg_state[hregNumber(vregD)] = toShort(m);
vreg_state[hregNumber(vregS)] = INVALID_RREG_NO;
- /* FIXME check this. This rreg has become associated with a different
- vreg and hence with a different spill slot. Play safe. */
- rreg_state[m].eq_spill_slot = False;
+ /* This rreg has become associated with a different vreg and
+ hence with a different spill slot. Play safe. */
+ rreg_state[m].eq_spill_slot = False;
/* Move on to the next insn. We skip the post-insn stuff for
fixed registers, since this move should not interact with
@@ -1242,7 +1237,7 @@
rreg_state[k].eq_spill_slot = True;
} else {
rreg_state[k].eq_spill_slot = False;
- }
+ }
continue;
}
|
|
From: <sv...@va...> - 2007-05-06 15:22:01
|
Author: sewardj
Date: 2007-05-06 16:21:57 +0100 (Sun, 06 May 2007)
New Revision: 1765
Log:
During register allocation, keep track of which (real) registers have
the same value as their associated spill slot. Then, if a register
needs to be freed up for some reason, and that register has the same
value as its spill slot, there is no need to produce a spill store.
This substantially reduces the number of spill store instructions
created. Overall gives a 1.9% generated code size reduction for
perf/bz2 running on x86.
Modified:
branches/CGTUNE/priv/host-generic/reg_alloc2.c
Modified: branches/CGTUNE/priv/host-generic/reg_alloc2.c
===================================================================
--- branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 13:16:29 UTC (rev 1764)
+++ branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 15:21:57 UTC (rev 1765)
@@ -126,6 +126,11 @@
/* Used when .disp == Bound and we are looking for vregs to
spill. */
Bool is_spill_cand;
+ /* Optimisation: used when .disp == Bound. Indicates when the
+ rreg has the same value as the spill slot for the associated
+ vreg. Is safely left at False, and becomes True after a
+ spill store or reload for this rreg. */
+ Bool eq_spill_slot;
}
RRegState;
@@ -339,6 +344,8 @@
{
# define N_SPILL64S (LibVEX_N_SPILL_BYTES / 8)
+ const Bool eq_spill_opt = True;
+
/* Iterators and temporaries. */
Int ii, j, k, m, spillee, k_suboptimal;
HReg rreg, vreg, vregS, vregD;
@@ -462,6 +469,7 @@
rreg_state[j].disp = Free;
rreg_state[j].vreg = INVALID_HREG;
rreg_state[j].is_spill_cand = False;
+ rreg_state[j].eq_spill_slot = False;
}
for (j = 0; j < n_vregs; j++)
@@ -783,7 +791,7 @@
two spill slots.
Do a rank-based allocation of vregs to spill slot numbers. We
- put as few values as possible in spill slows, but nevertheless
+ put as few values as possible in spill slots, but nevertheless
need to have a spill slot available for all vregs, just in case.
*/
/* max_ss_no = -1; */
@@ -956,8 +964,10 @@
/* Sanity check 3: all vreg-rreg bindings must bind registers
of the same class. */
for (j = 0; j < n_rregs; j++) {
- if (rreg_state[j].disp != Bound)
+ if (rreg_state[j].disp != Bound) {
+ vassert(rreg_state[j].eq_spill_slot == False);
continue;
+ }
vassert(hregClass(rreg_state[j].rreg)
== hregClass(rreg_state[j].vreg));
vassert( hregIsVirtual(rreg_state[j].vreg));
@@ -1033,6 +1043,10 @@
vreg_state[hregNumber(vregD)] = toShort(m);
vreg_state[hregNumber(vregS)] = INVALID_RREG_NO;
+ /* FIXME check this. This rreg has become associated with a different
+ vreg and hence with a different spill slot. Play safe. */
+ rreg_state[m].eq_spill_slot = False;
+
/* Move on to the next insn. We skip the post-insn stuff for
fixed registers, since this move should not interact with
them in any way. */
@@ -1052,6 +1066,7 @@
vassert(IS_VALID_VREGNO(vreg));
if (vreg_lrs[vreg].dead_before <= ii) {
rreg_state[j].disp = Free;
+ rreg_state[j].eq_spill_slot = False;
m = hregNumber(rreg_state[j].vreg);
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = INVALID_RREG_NO;
@@ -1115,13 +1130,17 @@
vreg_state[m] = INVALID_RREG_NO;
if (vreg_lrs[m].dead_before > ii) {
vassert(vreg_lrs[m].reg_class != HRcINVALID);
- EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
- vreg_lrs[m].spill_offset,
- mode64 ) );
+ if ((!eq_spill_opt) || !rreg_state[k].eq_spill_slot) {
+ EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
+ }
+ rreg_state[k].eq_spill_slot = True;
}
}
rreg_state[k].disp = Unavail;
rreg_state[k].vreg = INVALID_HREG;
+ rreg_state[k].eq_spill_slot = False;
/* check for further rregs entering HLRs at this point */
rreg_lrs_la_next++;
@@ -1170,6 +1189,10 @@
if (IS_VALID_RREGNO(k)) {
vassert(rreg_state[k].disp == Bound);
addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
+ /* If this rreg is written or modified, mark it as different
+ from any spill slot value. */
+ if (reg_usage.mode[j] != HRmRead)
+ rreg_state[k].eq_spill_slot = False;
continue;
} else {
vassert(k == INVALID_RREG_NO);
@@ -1205,13 +1228,22 @@
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = toShort(k);
addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
- /* Generate a reload if needed. */
+ /* Generate a reload if needed. This only creates needed
+ reloads because the live range builder for vregs will
+ guarantee that the first event for a vreg is a write.
+ Hence, if this reference is not a write, it cannot be
+ the first reference for this vreg, and so a reload is
+ indeed needed. */
if (reg_usage.mode[j] != HRmWrite) {
vassert(vreg_lrs[m].reg_class != HRcINVALID);
EMIT_INSTR( (*genReload)( rreg_state[k].rreg,
vreg_lrs[m].spill_offset,
mode64 ) );
- }
+ rreg_state[k].eq_spill_slot = True;
+ } else {
+ rreg_state[k].eq_spill_slot = False;
+ }
+
continue;
}
@@ -1272,15 +1304,19 @@
live vreg. */
vassert(vreg_lrs[m].dead_before > ii);
vassert(vreg_lrs[m].reg_class != HRcINVALID);
- EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
- vreg_lrs[m].spill_offset,
- mode64 ) );
+ if ((!eq_spill_opt) || !rreg_state[spillee].eq_spill_slot) {
+ EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
+ }
/* Update the rreg_state to reflect the new assignment for this
rreg. */
rreg_state[spillee].vreg = vreg;
vreg_state[m] = INVALID_RREG_NO;
+ rreg_state[spillee].eq_spill_slot = False; /* be safe */
+
m = hregNumber(vreg);
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = toShort(spillee);
@@ -1292,6 +1328,7 @@
EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg,
vreg_lrs[m].spill_offset,
mode64 ) );
+ rreg_state[spillee].eq_spill_slot = True;
}
/* So after much twisting and turning, we have vreg mapped to
@@ -1344,6 +1381,7 @@
vassert(rreg_state[k].disp == Unavail);
rreg_state[k].disp = Free;
rreg_state[k].vreg = INVALID_HREG;
+ rreg_state[k].eq_spill_slot = False;
/* check for further rregs leaving HLRs at this point */
rreg_lrs_db_next++;
|
|
From: <js...@ac...> - 2007-05-06 13:33:09
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-05-06 09:00:01 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) |
|
From: <sv...@va...> - 2007-05-06 13:22:23
|
Author: sewardj Date: 2007-05-06 14:22:23 +0100 (Sun, 06 May 2007) New Revision: 6732 Log: Swizzle external: svn propset svn:externals "VEX svn://svn.valgrind.org/vex/branches/CGTUNE" . Modified: branches/CGTUNE/ Property changes on: branches/CGTUNE ___________________________________________________________________ Name: svn:externals - VEX svn://svn.valgrind.org/vex/trunk + VEX svn://svn.valgrind.org/vex/branches/CGTUNE |
|
From: <sv...@va...> - 2007-05-06 13:19:52
|
Author: sewardj Date: 2007-05-06 14:19:50 +0100 (Sun, 06 May 2007) New Revision: 6731 Log: Make a copy of trunk r6730, for the purposes of various kinds of code generator tuning experiments. Added: branches/CGTUNE/ Copied: branches/CGTUNE (from rev 6730, trunk) |
|
From: <sv...@va...> - 2007-05-06 13:16:32
|
Author: sewardj Date: 2007-05-06 14:16:29 +0100 (Sun, 06 May 2007) New Revision: 1764 Log: Make a copy of trunk r1763, for the purposes of various kinds of code generator tuning experiments. Added: branches/CGTUNE/ Copied: branches/CGTUNE (from rev 1763, trunk) |
|
From: <sv...@va...> - 2007-05-06 11:28:23
|
Author: sewardj
Date: 2007-05-06 12:28:18 +0100 (Sun, 06 May 2007)
New Revision: 6730
Log:
Update.
Modified:
trunk/docs/internals/3_2_BUGSTATUS.txt
Modified: trunk/docs/internals/3_2_BUGSTATUS.txt
===================================================================
--- trunk/docs/internals/3_2_BUGSTATUS.txt 2007-05-05 16:46:21 UTC (rev 6729)
+++ trunk/docs/internals/3_2_BUGSTATUS.txt 2007-05-06 11:28:18 UTC (rev 6730)
@@ -32,8 +32,9 @@
and makes a valid MPI program crash.
vx1735 vx1750 32 141790 Missing amd64 x87 insns (FCOM, FCOMPP)
+vx1761 vx1762 32 n-i-bz Missing amd64 x87 insns (FCOMP)
-r6608 pending 32 n-i-bz intercept for __memmove_chk
+r6608 r6723 32 n-i-bz intercept for __memmove_chk
r6593 r6711 32 139363 callgrind: fix --collect-systime=yes
with "no instrumentation" mode
@@ -47,7 +48,7 @@
r6631 pending 142186 add I2C ioctl support
-Ashley logfile qualifiers in coredumps patch
+XXX Ashley logfile qualifiers in coredumps patch
r6612 r6718 32 142228 RedHat8: complaint of elf_dynamic_do_rela
r6646 r6718 32 142229 RedHat8: unexpected "write(buf) points
@@ -66,8 +67,7 @@
vx1740 vx1754 32 n-i-bz handle REX.W fsqrt
-Make configure check try for -fno-stack-protector (users, 26 Feb)
-#144112
+r6721 r6724 32 144112 undefined reference to __stack_chk_fail
possible false errors on amd64 cmpq/jae, cmpq/jbe
@@ -100,9 +100,18 @@
vx1749 vx1758 32 143907 sahf/lahf on amd64
-XXX copy spill area size, aspacem #segs and #segnames from trunk
+r6728 r6279 32 n-i-bz ppc-linux startup stack overflow fix
+XXX increase #segs and #segnames from 5000/1000 ?
+
+vx1759,r6722
+ vx1760,r6725 n-i-bz gcc-4.2 build fixes
+
+XXX 143924: --db-attach=yes and --trace-children=yes
+
+
+
//// maybe do not fix in 3.2 branch
64 bit DWARF in unwind (r6610) (definitely merge (??))
@@ -114,12 +123,10 @@
r6706 pending no n-i-bz memcheck: wrap getenv/setenv/putenv
-143924: --db-attach=yes and --trace-children=yes
+3.2.4 criteria: FC7 runs, SuSE 10.3a? runs, gcc-4.2 works OK
-3.2.4 criteria: FC7 runs, SuSE 10.3a? runs
-
------- Bugs reported and fixed in 3.2.3 ------
TRUNK 32BRANCH PRI BUG# WHAT
|
|
From: Tom H. <th...@cy...> - 2007-05-06 02:23:54
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Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-05-06 03:10:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
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From: Tom H. <th...@cy...> - 2007-05-06 02:17:25
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Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-05-06 03:05:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
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From: Tom H. <th...@cy...> - 2007-05-06 02:10:57
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Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-05-06 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 294 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
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From: <js...@ac...> - 2007-05-06 00:16:50
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Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2007-05-06 02:00:01 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 226 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |