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From: <js...@ac...> - 2007-04-29 13:04:03
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-04-29 09:00:01 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) none/tests/pth_detached (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sun Apr 29 09:12:08 2007 --- new.short Sun Apr 29 09:24:16 2007 *************** *** 8,10 **** ! == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) --- 8,10 ---- ! == 219 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) *************** *** 25,26 **** --- 25,27 ---- none/tests/ppc32/test_gx (stdout) + none/tests/pth_detached (stdout) |
|
From: <sv...@va...> - 2007-04-29 10:39:17
|
Author: sewardj
Date: 2007-04-29 11:39:16 +0100 (Sun, 29 Apr 2007)
New Revision: 1758
Log:
Merge r1749 (Implement lahf/sahf on amd64. Also set NDEP on x86 sahf.
Fixes #143907.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 10:34:42 UTC (rev 1757)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 10:39:16 UTC (rev 1758)
@@ -7122,52 +7122,58 @@
}
-//.. static
-//.. void codegen_SAHF ( void )
-//.. {
-//.. /* Set the flags to:
-//.. (x86g_calculate_flags_all() & X86G_CC_MASK_O) -- retain the old O flag
-//.. | (%AH & (X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A
-//.. |X86G_CC_MASK_P|X86G_CC_MASK_C)
-//.. */
-//.. UInt mask_SZACP = X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A
-//.. |X86G_CC_MASK_C|X86G_CC_MASK_P;
-//.. IRTemp oldflags = newTemp(Ity_I32);
-//.. assign( oldflags, mk_x86g_calculate_eflags_all() );
-//.. stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) ));
-//.. stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) ));
-//.. stmt( IRStmt_Put( OFFB_CC_DEP1,
-//.. binop(Iop_Or32,
-//.. binop(Iop_And32, mkexpr(oldflags), mkU32(X86G_CC_MASK_O)),
-//.. binop(Iop_And32,
-//.. binop(Iop_Shr32, getIReg(4, R_EAX), mkU8(8)),
-//.. mkU32(mask_SZACP))
-//.. )
-//.. ));
-//.. }
-//..
-//..
-//.. //-- static
-//.. //-- void codegen_LAHF ( UCodeBlock* cb )
-//.. //-- {
-//.. //-- Int t = newTemp(cb);
-//.. //--
-//.. //-- /* Pushed arg is ignored, it just provides somewhere to put the
-//.. //-- return value. */
-//.. //-- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t);
-//.. //-- uInstr0(cb, CALLM_S, 0);
-//.. //-- uInstr1(cb, PUSH, 4, TempReg, t);
-//.. //-- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_LAHF));
-//.. //-- uFlagsRWU(cb, FlagsSZACP, FlagsEmpty, FlagsEmpty);
-//.. //-- uInstr1(cb, POP, 4, TempReg, t);
-//.. //-- uInstr0(cb, CALLM_E, 0);
-//.. //--
-//.. //-- /* At this point, the %ah sub-register in %eax has been updated,
-//.. //-- the rest is the same, so do a PUT of the whole thing. */
-//.. //-- uInstr2(cb, PUT, 4, TempReg, t, ArchReg, R_EAX);
-//.. //-- }
-//.. //--
+static
+void codegen_SAHF ( void )
+{
+ /* Set the flags to:
+ (amd64g_calculate_flags_all() & AMD64G_CC_MASK_O)
+ -- retain the old O flag
+ | (%AH & (AMD64G_CC_MASK_S|AMD64G_CC_MASK_Z|AMD64G_CC_MASK_A
+ |AMD64G_CC_MASK_P|AMD64G_CC_MASK_C)
+ */
+ ULong mask_SZACP = AMD64G_CC_MASK_S|AMD64G_CC_MASK_Z|AMD64G_CC_MASK_A
+ |AMD64G_CC_MASK_C|AMD64G_CC_MASK_P;
+ IRTemp oldflags = newTemp(Ity_I64);
+ assign( oldflags, mk_amd64g_calculate_rflags_all() );
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(oldflags), mkU64(AMD64G_CC_MASK_O)),
+ binop(Iop_And64,
+ binop(Iop_Shr64, getIReg64(R_RAX), mkU8(8)),
+ mkU64(mask_SZACP))
+ )
+ ));
+}
+
+static
+void codegen_LAHF ( void )
+{
+ /* AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF) */
+ IRExpr* rax_with_hole;
+ IRExpr* new_byte;
+ IRExpr* new_rax;
+ ULong mask_SZACP = AMD64G_CC_MASK_S|AMD64G_CC_MASK_Z|AMD64G_CC_MASK_A
+ |AMD64G_CC_MASK_C|AMD64G_CC_MASK_P;
+
+ IRTemp flags = newTemp(Ity_I64);
+ assign( flags, mk_amd64g_calculate_rflags_all() );
+
+ rax_with_hole
+ = binop(Iop_And64, getIReg64(R_RAX), mkU64(~0xFF00ULL));
+ new_byte
+ = binop(Iop_Or64, binop(Iop_And64, mkexpr(flags), mkU64(mask_SZACP)),
+ mkU64(1<<1));
+ new_rax
+ = binop(Iop_Or64, rax_with_hole,
+ binop(Iop_Shl64, new_byte, mkU8(8)));
+ putIReg64(R_RAX, new_rax);
+}
+
+
static
ULong dis_cmpxchg_G_E ( /*OUT*/Bool* ok,
Prefix pfx,
@@ -12355,16 +12361,16 @@
/* ------------------------ FPU ops -------------------- */
-//.. case 0x9E: /* SAHF */
-//.. codegen_SAHF();
-//.. DIP("sahf\n");
-//.. break;
-//..
-//.. //-- case 0x9F: /* LAHF */
-//.. //-- codegen_LAHF ( cb );
-//.. //-- DIP("lahf\n");
-//.. //-- break;
-//.. //--
+ case 0x9E: /* SAHF */
+ codegen_SAHF();
+ DIP("sahf\n");
+ break;
+
+ case 0x9F: /* LAHF */
+ codegen_LAHF();
+ DIP("lahf\n");
+ break;
+
case 0x9B: /* FWAIT */
/* ignore? */
DIP("fwait\n");
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:34:42 UTC (rev 1757)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:39:16 UTC (rev 1758)
@@ -6145,6 +6145,7 @@
IRTemp oldflags = newTemp(Ity_I32);
assign( oldflags, mk_x86g_calculate_eflags_all() );
stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) ));
stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) ));
stmt( IRStmt_Put( OFFB_CC_DEP1,
binop(Iop_Or32,
|
|
From: <sv...@va...> - 2007-04-29 10:34:43
|
Author: sewardj
Date: 2007-04-29 11:34:42 +0100 (Sun, 29 Apr 2007)
New Revision: 1757
Log:
Merge r1748 (x86 front end: Fix various cases where the instruction
decoder asserted/paniced instead of doing the normal SIGILL thing.
Fixes #143354.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:28:33 UTC (rev 1756)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:34:42 UTC (rev 1757)
@@ -295,14 +295,6 @@
return newIRTemp( irbb->tyenv, ty );
}
-/* Bomb out if we can't handle something. */
-__attribute__ ((noreturn))
-static void unimplemented ( HChar* str )
-{
- vex_printf("x86toIR: unimplemented feature\n");
- vpanic(str);
-}
-
/* Various simple conversions */
static UInt extend_s_8to32( UInt x )
@@ -1504,9 +1496,8 @@
if (index_r == R_ESP && base_r == R_EBP) {
UInt d = getUDisp32(delta);
- DIS(buf, "%s0x%x()", sorbTxt(sorb), d);
+ DIS(buf, "%s0x%x(,,)", sorbTxt(sorb), d);
*len = 6;
- vpanic("disAMode(x86):untested amode: 8");
return disAMode_copy2tmp(
handleSegOverride(sorb, mkU32(d)));
}
@@ -2926,7 +2917,7 @@
Int sz, HChar* name, UChar sorb )
{
IRTemp t_inc = newTemp(Ity_I32);
- vassert(sorb == 0);
+ vassert(sorb == 0); /* hmm. so what was the point of passing it in? */
dis_string_op_increment(sz, t_inc);
dis_OP( sz, t_inc );
DIP("%s%c\n", name, nameISize(sz));
@@ -7338,13 +7329,11 @@
goto decode_success;
}
}
- unimplemented("x86 segment override (SEG=CS) prefix");
- /*NOTREACHED*/
- break;
+ /* All other CS override cases are not handled */
+ goto decode_failure;
case 0x36: /* %SS: */
- unimplemented("x86 segment override (SEG=SS) prefix");
- /*NOTREACHED*/
- break;
+ /* SS override cases are not handled */
+ goto decode_failure;
default:
break;
}
@@ -11715,6 +11704,7 @@
case 0x9D: /* POPF */
vassert(sz == 2 || sz == 4);
+ if (sz != 4) goto decode_failure;
vassert(sz == 4); // until we know a sz==2 test case exists
t1 = newTemp(Ity_I32); t2 = newTemp(Ity_I32);
assign(t2, getIReg(4, R_ESP));
@@ -11902,6 +11892,7 @@
case 0x9C: /* PUSHF */ {
vassert(sz == 2 || sz == 4);
+ if (sz != 4) goto decode_failure;
vassert(sz == 4); // wait for sz==2 test case
t1 = newTemp(Ity_I32);
@@ -12003,26 +11994,36 @@
case 0xA4: /* MOVS, no REP prefix */
case 0xA5:
+ if (sorb != 0)
+ goto decode_failure; /* else dis_string_op asserts */
dis_string_op( dis_MOVS, ( opc == 0xA4 ? 1 : sz ), "movs", sorb );
break;
case 0xA6: /* CMPSb, no REP prefix */
case 0xA7:
- dis_string_op( dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb );
- break;
+ if (sorb != 0)
+ goto decode_failure; /* else dis_string_op asserts */
+ dis_string_op( dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb );
+ break;
case 0xAA: /* STOS, no REP prefix */
case 0xAB:
+ if (sorb != 0)
+ goto decode_failure; /* else dis_string_op asserts */
dis_string_op( dis_STOS, ( opc == 0xAA ? 1 : sz ), "stos", sorb );
break;
case 0xAC: /* LODS, no REP prefix */
case 0xAD:
+ if (sorb != 0)
+ goto decode_failure; /* else dis_string_op asserts */
dis_string_op( dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", sorb );
break;
case 0xAE: /* SCAS, no REP prefix */
case 0xAF:
+ if (sorb != 0)
+ goto decode_failure; /* else dis_string_op asserts */
dis_string_op( dis_SCAS, ( opc == 0xAE ? 1 : sz ), "scas", sorb );
break;
@@ -12073,7 +12074,7 @@
/* REPNE prefix insn */
case 0xF2: {
Addr32 eip_orig = guest_EIP_bbstart + delta - 1;
- vassert(sorb == 0);
+ if (sorb != 0) goto decode_failure;
abyte = getIByte(delta); delta++;
if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; }
@@ -12115,7 +12116,7 @@
for the rest, it means REP) */
case 0xF3: {
Addr32 eip_orig = guest_EIP_bbstart + delta - 1;
- vassert(sorb == 0);
+ if (sorb != 0) goto decode_failure;
abyte = getIByte(delta); delta++;
if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; }
|
|
From: <sv...@va...> - 2007-04-29 10:28:33
|
Author: sewardj
Date: 2007-04-29 11:28:33 +0100 (Sun, 29 Apr 2007)
New Revision: 1756
Log:
Merge r1747 (Fold Add8(t,t) ==> t << 1. Fixes #143817 (Unused
bitfield pad bits confuse memcheck))
Modified:
branches/VEX_3_2_BRANCH/priv/ir/iropt.c
Modified: branches/VEX_3_2_BRANCH/priv/ir/iropt.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/ir/iropt.c 2007-04-29 10:20:05 UTC (rev 1755)
+++ branches/VEX_3_2_BRANCH/priv/ir/iropt.c 2007-04-29 10:28:33 UTC (rev 1756)
@@ -1431,6 +1431,18 @@
IRExpr_Const(IRConst_U8(1)));
} else
+ /* Add8(t,t) ==> t << 1; rationale as for Add32(t,t) above. */
+ if (e->Iex.Binop.op == Iop_Add8
+ && e->Iex.Binop.arg1->tag == Iex_Tmp
+ && e->Iex.Binop.arg2->tag == Iex_Tmp
+ && e->Iex.Binop.arg1->Iex.Tmp.tmp
+ == e->Iex.Binop.arg2->Iex.Tmp.tmp) {
+ e2 = IRExpr_Binop(Iop_Shl8,
+ e->Iex.Binop.arg1,
+ IRExpr_Const(IRConst_U8(1)));
+ } else
+ /* NB no Add16(t,t) case yet as no known test case exists */
+
/* Or64/Add64(x,0) ==> x */
if ((e->Iex.Binop.op == Iop_Add64 || e->Iex.Binop.op == Iop_Or64)
&& e->Iex.Binop.arg2->tag == Iex_Const
|
|
From: <sv...@va...> - 2007-04-29 10:20:07
|
Author: sewardj
Date: 2007-04-29 11:20:05 +0100 (Sun, 29 Apr 2007)
New Revision: 1755
Log:
Merge r1742 and r1743 (x86 and amd64 front ends: synthesise SIGILL in
the normal way for some obscure invalid instruction cases, rather than
asserting, as happened in #143079 and #142279.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 10:07:20 UTC (rev 1754)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 10:20:05 UTC (rev 1755)
@@ -2924,6 +2924,7 @@
case 3: break; // SBB
case 4: op8 = Iop_And8; break; case 5: op8 = Iop_Sub8; break;
case 6: op8 = Iop_Xor8; break; case 7: op8 = Iop_Sub8; break;
+ /*NOTREACHED*/
default: vpanic("dis_Grp1(amd64): unhandled case");
}
@@ -2991,7 +2992,7 @@
ULong dis_Grp2 ( Prefix pfx,
Long delta, UChar modrm,
Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr,
- HChar* shift_expr_txt )
+ HChar* shift_expr_txt, Bool* decode_OK )
{
/* delta on entry points at the modrm byte. */
HChar dis_buf[50];
@@ -3002,6 +3003,8 @@
IRTemp dst1 = newTemp(ty);
IRTemp addr = IRTemp_INVALID;
+ *decode_OK = True;
+
vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
/* Put value to shift/rotate in dst0. */
@@ -3023,8 +3026,13 @@
isRotateC = False;
switch (gregLO3ofRM(modrm)) { case 2: case 3: isRotateC = True; }
+ if (gregLO3ofRM(modrm) == 6) {
+ *decode_OK = False;
+ return delta;
+ }
+
if (!isShift && !isRotate && !isRotateC) {
- vex_printf("\ncase %d\n", gregLO3ofRM(modrm));
+ /*NOTREACHED*/
vpanic("dis_Grp2(Reg): unhandled case(amd64)");
}
@@ -3098,6 +3106,7 @@
case 4: op64 = Iop_Shl64; break;
case 5: op64 = Iop_Shr64; break;
case 7: op64 = Iop_Sar64; break;
+ /*NOTREACHED*/
default: vpanic("dis_Grp2:shift"); break;
}
@@ -3432,7 +3441,7 @@
/* Group 3 extended opcodes. */
static
-ULong dis_Grp3 ( Prefix pfx, Int sz, Long delta )
+ULong dis_Grp3 ( Prefix pfx, Int sz, Long delta, Bool* decode_OK )
{
Long d64;
UChar modrm;
@@ -3442,6 +3451,7 @@
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
IRTemp dst1, src, dst0;
+ *decode_OK = True;
modrm = getUChar(delta);
if (epartIsReg(modrm)) {
switch (gregLO3ofRM(modrm)) {
@@ -3459,6 +3469,9 @@
nameIRegE(sz, pfx, modrm));
break;
}
+ case 1:
+ *decode_OK = False;
+ return delta;
case 2: /* NOT */
delta++;
putIRegE(sz, pfx, modrm,
@@ -3508,9 +3521,8 @@
nameIRegE(sz, pfx, modrm));
break;
default:
- vex_printf(
- "unhandled Grp3(R) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp3(amd64)");
+ /*NOTREACHED*/
+ vpanic("Grp3(amd64,R)");
}
} else {
addr = disAMode ( &len, pfx, delta, dis_buf,
@@ -3535,7 +3547,9 @@
DIP("test%c $%lld, %s\n", nameISize(sz), d64, dis_buf);
break;
}
- /* probably OK, but awaiting test case */
+ case 1:
+ *decode_OK = False;
+ return delta;
case 2: /* NOT */
storeLE( mkexpr(addr), unop(mkSizedOp(ty,Iop_Not8), mkexpr(t1)));
DIP("not%c %s\n", nameISize(sz), dis_buf);
@@ -3566,9 +3580,8 @@
DIP("idiv%c %s\n", nameISize(sz), dis_buf);
break;
default:
- vex_printf(
- "unhandled Grp3(M) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp3(amd64)");
+ /*NOTREACHED*/
+ vpanic("Grp3(amd64,M)");
}
}
return delta;
@@ -3577,7 +3590,7 @@
/* Group 4 extended opcodes. */
static
-ULong dis_Grp4 ( Prefix pfx, Long delta )
+ULong dis_Grp4 ( Prefix pfx, Long delta, Bool* decode_OK )
{
Int alen;
UChar modrm;
@@ -3586,6 +3599,8 @@
IRTemp t1 = newTemp(ty);
IRTemp t2 = newTemp(ty);
+ *decode_OK = True;
+
modrm = getUChar(delta);
if (epartIsReg(modrm)) {
assign(t1, getIRegE(1, pfx, modrm));
@@ -3601,9 +3616,8 @@
setFlags_INC_DEC( False, t2, ty );
break;
default:
- vex_printf(
- "unhandled Grp4(R) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp4(amd64,R)");
+ *decode_OK = False;
+ return delta;
}
delta++;
DIP("%sb %s\n", nameGrp4(gregLO3ofRM(modrm)),
@@ -3623,9 +3637,8 @@
setFlags_INC_DEC( False, t2, ty );
break;
default:
- vex_printf(
- "unhandled Grp4(M) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp4(amd64,M)");
+ *decode_OK = False;
+ return delta;
}
delta += alen;
DIP("%sb %s\n", nameGrp4(gregLO3ofRM(modrm)), dis_buf);
@@ -3636,7 +3649,8 @@
/* Group 5 extended opcodes. */
static
-ULong dis_Grp5 ( Prefix pfx, Int sz, Long delta, DisResult* dres )
+ULong dis_Grp5 ( Prefix pfx, Int sz, Long delta,
+ DisResult* dres, Bool* decode_OK )
{
Int len;
UChar modrm;
@@ -3648,6 +3662,8 @@
IRTemp t3 = IRTemp_INVALID;
Bool showSz = True;
+ *decode_OK = True;
+
modrm = getUChar(delta);
if (epartIsReg(modrm)) {
assign(t1, getIRegE(sz,pfx,modrm));
@@ -3692,9 +3708,8 @@
showSz = False;
break;
default:
- vex_printf(
- "unhandled Grp5(R) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp5(amd64)");
+ *decode_OK = False;
+ return delta;
}
delta++;
DIP("%s%c %s\n", nameGrp5(gregLO3ofRM(modrm)),
@@ -3763,9 +3778,8 @@
}
default:
unhandled:
- vex_printf(
- "unhandled Grp5(M) case %d\n", (Int)gregLO3ofRM(modrm));
- vpanic("Grp5(amd64)");
+ *decode_OK = False;
+ return delta;
}
delta += len;
DIP("%s%c %s\n", nameGrp5(gregLO3ofRM(modrm)),
@@ -13657,7 +13671,8 @@
/* ------------------------ (Grp2 extensions) ---------- */
- case 0xC0: /* Grp2 Ib,Eb */
+ case 0xC0: { /* Grp2 Ib,Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
@@ -13665,20 +13680,24 @@
d64 = getUChar(delta + am_sz);
sz = 1;
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64 & 0xFF), NULL );
+ mkU8(d64 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
-
- case 0xC1: /* Grp2 Ib,Ev */
+ }
+ case 0xC1: { /* Grp2 Ib,Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
d_sz = 1;
d64 = getUChar(delta + am_sz);
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64 & 0xFF), NULL );
+ mkU8(d64 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
-
- case 0xD0: /* Grp2 1,Eb */
+ }
+ case 0xD0: { /* Grp2 1,Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
@@ -13686,62 +13705,82 @@
d64 = 1;
sz = 1;
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64), NULL );
+ mkU8(d64), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
-
- case 0xD1: /* Grp2 1,Ev */
+ }
+ case 0xD1: { /* Grp2 1,Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
d_sz = 0;
d64 = 1;
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64), NULL );
+ mkU8(d64), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
-
- case 0xD2: /* Grp2 CL,Eb */
+ }
+ case 0xD2: { /* Grp2 CL,Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
d_sz = 0;
sz = 1;
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- getIRegCL(), "%cl" );
+ getIRegCL(), "%cl", &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
-
- case 0xD3: /* Grp2 CL,Ev */
+ }
+ case 0xD3: { /* Grp2 CL,Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
am_sz = lengthAMode(pfx,delta);
d_sz = 0;
delta = dis_Grp2 ( pfx, delta, modrm, am_sz, d_sz, sz,
- getIRegCL(), "%cl" );
+ getIRegCL(), "%cl", &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
+ }
/* ------------------------ (Grp3 extensions) ---------- */
- case 0xF6: /* Grp3 Eb */
+ case 0xF6: { /* Grp3 Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_Grp3 ( pfx, 1, delta );
+ delta = dis_Grp3 ( pfx, 1, delta, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
- case 0xF7: /* Grp3 Ev */
+ }
+ case 0xF7: { /* Grp3 Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_Grp3 ( pfx, sz, delta );
+ delta = dis_Grp3 ( pfx, sz, delta, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
+ }
/* ------------------------ (Grp4 extensions) ---------- */
- case 0xFE: /* Grp4 Eb */
+ case 0xFE: { /* Grp4 Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_Grp4 ( pfx, delta );
+ delta = dis_Grp4 ( pfx, delta, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
+ }
/* ------------------------ (Grp5 extensions) ---------- */
- case 0xFF: /* Grp5 Ev */
+ case 0xFF: { /* Grp5 Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_Grp5 ( pfx, sz, delta, &dres );
+ delta = dis_Grp5 ( pfx, sz, delta, &dres, &decode_OK );
+ if (!decode_OK) goto decode_failure;
break;
+ }
/* ------------------------ Escapes to 2-byte opcodes -- */
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:07:20 UTC (rev 1754)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 10:20:05 UTC (rev 1755)
@@ -2126,6 +2126,7 @@
case 3: break; // SBB
case 4: op8 = Iop_And8; break; case 5: op8 = Iop_Sub8; break;
case 6: op8 = Iop_Xor8; break; case 7: op8 = Iop_Sub8; break;
+ /*NOTREACHED*/
default: vpanic("dis_Grp1: unhandled case");
}
@@ -2191,7 +2192,7 @@
UInt dis_Grp2 ( UChar sorb,
Int delta, UChar modrm,
Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr,
- HChar* shift_expr_txt )
+ HChar* shift_expr_txt, Bool* decode_OK )
{
/* delta on entry points at the modrm byte. */
HChar dis_buf[50];
@@ -2202,6 +2203,8 @@
IRTemp dst1 = newTemp(ty);
IRTemp addr = IRTemp_INVALID;
+ *decode_OK = True;
+
vassert(sz == 1 || sz == 2 || sz == 4);
/* Put value to shift/rotate in dst0. */
@@ -2223,8 +2226,13 @@
isRotateC = False;
switch (gregOfRM(modrm)) { case 2: case 3: isRotateC = True; }
+ if (gregOfRM(modrm) == 6) {
+ *decode_OK = False;
+ return delta;
+ }
+
if (!isShift && !isRotate && !isRotateC) {
- vex_printf("\ncase %d\n", gregOfRM(modrm));
+ /*NOTREACHED*/
vpanic("dis_Grp2(Reg): unhandled case(x86)");
}
@@ -2268,6 +2276,7 @@
case 4: op32 = Iop_Shl32; break;
case 5: op32 = Iop_Shr32; break;
case 7: op32 = Iop_Sar32; break;
+ /*NOTREACHED*/
default: vpanic("dis_Grp2:shift"); break;
}
@@ -2583,7 +2592,7 @@
/* Group 3 extended opcodes. */
static
-UInt dis_Grp3 ( UChar sorb, Int sz, Int delta )
+UInt dis_Grp3 ( UChar sorb, Int sz, Int delta, Bool* decode_OK )
{
UInt d32;
UChar modrm;
@@ -2592,8 +2601,10 @@
IRTemp addr;
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
- // IRTemp t2 = IRTemp_INVALID;
IRTemp dst1, src, dst0;
+
+ *decode_OK = True; /* may change this later */
+
modrm = getIByte(delta);
if (epartIsReg(modrm)) {
switch (gregOfRM(modrm)) {
@@ -2608,6 +2619,13 @@
nameIReg(sz, eregOfRM(modrm)));
break;
}
+ case 1: /* UNDEFINED */
+ /* The Intel docs imply this insn is undefined and binutils
+ agrees. Unfortunately Core 2 will run it (with who
+ knows what result?) sandpile.org reckons it's an alias
+ for case 0. We play safe. */
+ *decode_OK = False;
+ break;
case 2: /* NOT */
delta++;
putIReg(sz, eregOfRM(modrm),
@@ -2652,8 +2670,7 @@
DIP("idiv%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
break;
default:
- vex_printf(
- "unhandled Grp3(R) case %d\n", (Int)gregOfRM(modrm));
+ /* This can't happen - gregOfRM should return 0 .. 7 only */
vpanic("Grp3(x86)");
}
} else {
@@ -2671,6 +2688,10 @@
DIP("test%c $0x%x, %s\n", nameISize(sz), d32, dis_buf);
break;
}
+ case 1: /* UNDEFINED */
+ /* See comment above on R case */
+ *decode_OK = False;
+ break;
case 2: /* NOT */
storeLE( mkexpr(addr), unop(mkSizedOp(ty,Iop_Not8), mkexpr(t1)));
DIP("not%c %s\n", nameISize(sz), dis_buf);
@@ -2701,8 +2722,7 @@
DIP("idiv%c %s\n", nameISize(sz), dis_buf);
break;
default:
- vex_printf(
- "unhandled Grp3(M) case %d\n", (Int)gregOfRM(modrm));
+ /* This can't happen - gregOfRM should return 0 .. 7 only */
vpanic("Grp3(x86)");
}
}
@@ -2712,7 +2732,7 @@
/* Group 4 extended opcodes. */
static
-UInt dis_Grp4 ( UChar sorb, Int delta )
+UInt dis_Grp4 ( UChar sorb, Int delta, Bool* decode_OK )
{
Int alen;
UChar modrm;
@@ -2721,6 +2741,8 @@
IRTemp t1 = newTemp(ty);
IRTemp t2 = newTemp(ty);
+ *decode_OK = True;
+
modrm = getIByte(delta);
if (epartIsReg(modrm)) {
assign(t1, getIReg(1, eregOfRM(modrm)));
@@ -2736,9 +2758,8 @@
setFlags_INC_DEC( False, t2, ty );
break;
default:
- vex_printf(
- "unhandled Grp4(R) case %d\n", (Int)gregOfRM(modrm));
- vpanic("Grp4(x86,R)");
+ *decode_OK = False;
+ return delta;
}
delta++;
DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)),
@@ -2758,9 +2779,8 @@
setFlags_INC_DEC( False, t2, ty );
break;
default:
- vex_printf(
- "unhandled Grp4(M) case %d\n", (Int)gregOfRM(modrm));
- vpanic("Grp4(x86,M)");
+ *decode_OK = False;
+ return delta;
}
delta += alen;
DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), dis_buf);
@@ -2771,7 +2791,8 @@
/* Group 5 extended opcodes. */
static
-UInt dis_Grp5 ( UChar sorb, Int sz, Int delta, DisResult* dres )
+UInt dis_Grp5 ( UChar sorb, Int sz, Int delta,
+ DisResult* dres, Bool* decode_OK )
{
Int len;
UChar modrm;
@@ -2781,6 +2802,8 @@
IRTemp t1 = newTemp(ty);
IRTemp t2 = IRTemp_INVALID;
+ *decode_OK = True;
+
modrm = getIByte(delta);
if (epartIsReg(modrm)) {
assign(t1, getIReg(sz,eregOfRM(modrm)));
@@ -2823,9 +2846,8 @@
storeLE( mkexpr(t2), mkexpr(t1) );
break;
default:
- vex_printf(
- "unhandled Grp5(R) case %d\n", (Int)gregOfRM(modrm));
- vpanic("Grp5(x86)");
+ *decode_OK = False;
+ return delta;
}
delta++;
DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)),
@@ -2870,9 +2892,8 @@
storeLE( mkexpr(t2), mkexpr(t1) );
break;
default:
- vex_printf(
- "unhandled Grp5(M) case %d\n", (Int)gregOfRM(modrm));
- vpanic("Grp5(x86)");
+ *decode_OK = False;
+ return delta;
}
delta += len;
DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)),
@@ -12331,81 +12352,116 @@
/* ------------------------ (Grp2 extensions) ---------- */
- case 0xC0: /* Grp2 Ib,Eb */
+ case 0xC0: { /* Grp2 Ib,Eb */
+ Bool decode_OK = True;
modrm = getIByte(delta);
am_sz = lengthAMode(delta);
d_sz = 1;
d32 = getUChar(delta + am_sz);
sz = 1;
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- mkU8(d32 & 0xFF), NULL );
+ mkU8(d32 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
-
- case 0xC1: /* Grp2 Ib,Ev */
+ }
+ case 0xC1: { /* Grp2 Ib,Ev */
+ Bool decode_OK = True;
modrm = getIByte(delta);
am_sz = lengthAMode(delta);
d_sz = 1;
d32 = getUChar(delta + am_sz);
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- mkU8(d32 & 0xFF), NULL );
+ mkU8(d32 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
-
- case 0xD0: /* Grp2 1,Eb */
+ }
+ case 0xD0: { /* Grp2 1,Eb */
+ Bool decode_OK = True;
modrm = getIByte(delta);
am_sz = lengthAMode(delta);
d_sz = 0;
d32 = 1;
sz = 1;
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- mkU8(d32), NULL );
+ mkU8(d32), NULL, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
-
- case 0xD1: /* Grp2 1,Ev */
+ }
+ case 0xD1: { /* Grp2 1,Ev */
+ Bool decode_OK = True;
modrm = getUChar(delta);
am_sz = lengthAMode(delta);
d_sz = 0;
d32 = 1;
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- mkU8(d32), NULL );
+ mkU8(d32), NULL, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
-
- case 0xD2: /* Grp2 CL,Eb */
+ }
+ case 0xD2: { /* Grp2 CL,Eb */
+ Bool decode_OK = True;
modrm = getUChar(delta);
am_sz = lengthAMode(delta);
d_sz = 0;
sz = 1;
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- getIReg(1,R_ECX), "%cl" );
+ getIReg(1,R_ECX), "%cl", &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
-
- case 0xD3: /* Grp2 CL,Ev */
+ }
+ case 0xD3: { /* Grp2 CL,Ev */
+ Bool decode_OK = True;
modrm = getIByte(delta);
am_sz = lengthAMode(delta);
d_sz = 0;
delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz,
- getIReg(1,R_ECX), "%cl" );
+ getIReg(1,R_ECX), "%cl", &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
+ }
/* ------------------------ (Grp3 extensions) ---------- */
- case 0xF6: /* Grp3 Eb */
- delta = dis_Grp3 ( sorb, 1, delta );
+ case 0xF6: { /* Grp3 Eb */
+ Bool decode_OK = True;
+ delta = dis_Grp3 ( sorb, 1, delta, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
- case 0xF7: /* Grp3 Ev */
- delta = dis_Grp3 ( sorb, sz, delta );
+ }
+ case 0xF7: { /* Grp3 Ev */
+ Bool decode_OK = True;
+ delta = dis_Grp3 ( sorb, sz, delta, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
+ }
/* ------------------------ (Grp4 extensions) ---------- */
- case 0xFE: /* Grp4 Eb */
- delta = dis_Grp4 ( sorb, delta );
+ case 0xFE: { /* Grp4 Eb */
+ Bool decode_OK = True;
+ delta = dis_Grp4 ( sorb, delta, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
+ }
/* ------------------------ (Grp5 extensions) ---------- */
- case 0xFF: /* Grp5 Ev */
- delta = dis_Grp5 ( sorb, sz, delta, &dres );
+ case 0xFF: { /* Grp5 Ev */
+ Bool decode_OK = True;
+ delta = dis_Grp5 ( sorb, sz, delta, &dres, &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
break;
+ }
/* ------------------------ Escapes to 2-byte opcodes -- */
|
|
From: <sv...@va...> - 2007-04-29 10:07:21
|
Author: sewardj
Date: 2007-04-29 11:07:20 +0100 (Sun, 29 Apr 2007)
New Revision: 1754
Log:
Merge r1740 (Tolerate redundant REX.W prefix produced by Mono for
'fsqrt' (a lame kludge).)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 09:57:48 UTC (rev 1753)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 10:07:20 UTC (rev 1754)
@@ -12363,9 +12363,21 @@
case 0xDC:
case 0xDD:
case 0xDE:
- case 0xDF:
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz == 4 && haveNo66noF2noF3(pfx)) {
+ case 0xDF: {
+ Bool redundantREXWok = False;
+
+ if (haveF2orF3(pfx))
+ goto decode_failure;
+
+ /* kludge to tolerate redundant rex.w prefixes (should do this
+ properly one day) */
+ /* mono 1.1.18.1 produces 48 D9 FA, which is rex.w fsqrt */
+ if ( (opc == 0xD9 && getUChar(delta+0) == 0xFA)/*fsqrt*/ )
+ redundantREXWok = True;
+
+ if ( (sz == 4
+ || (sz == 8 && redundantREXWok))
+ && haveNo66noF2noF3(pfx)) {
Long delta0 = delta;
Bool decode_OK = False;
delta = dis_FPU ( &decode_OK, pfx, delta );
@@ -12377,6 +12389,7 @@
} else {
goto decode_failure;
}
+ }
/* ------------------------ INT ------------------------ */
|
|
From: <sv...@va...> - 2007-04-29 09:57:53
|
Author: sewardj
Date: 2007-04-29 10:57:48 +0100 (Sun, 29 Apr 2007)
New Revision: 1753
Log:
Merge r1738 (comment only changes for the ppc front end)
Merge r1739 (ppc64 code generation bug fix: When generating 64-bit
code, ensure that any addresses used in 4 or 8 byte loads or stores of
the form reg+imm have the lowest 2 bits of imm set to zero, so that
they can safely be used in ld/ldu/lda/std/stdu instructions.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2007-04-29 09:49:38 UTC (rev 1752)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2007-04-29 09:57:48 UTC (rev 1753)
@@ -3495,7 +3495,8 @@
case 0x1F: // register offset
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
break;
- case 0x3A: // immediate offset: 64bit
+ case 0x3A: // immediate offset: 64bit: ld/ldu/lwa: mask off
+ // lowest 2 bits of immediate before forming EA
simm16 = simm16 & 0xFFFFFFFC;
default: // immediate offset
assign( EA, ea_rAor0_simm( rA_addr, simm16 ) );
@@ -3687,9 +3688,10 @@
}
break;
- /* DS Form - 64bit Loads */
+ /* DS Form - 64bit Loads. In each case EA will have been formed
+ with the lowest 2 bits masked off the immediate offset. */
case 0x3A:
- switch (b1<<1 | b0) {
+ switch ((b1<<1) | b0) {
case 0x0: // ld (Load DWord, PPC64 p472)
DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
@@ -3701,7 +3703,6 @@
return False;
}
DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
- simm16 = simm16 & ~0x3;
putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
break;
@@ -3755,7 +3756,8 @@
case 0x1F: // register offset
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
break;
- case 0x3E: // immediate offset: 64bit
+ case 0x3E: // immediate offset: 64bit: std/stdu: mask off
+ // lowest 2 bits of immediate before forming EA
simm16 = simm16 & 0xFFFFFFFC;
default: // immediate offset
assign( EA, ea_rAor0_simm( rA_addr, simm16 ) );
@@ -3884,9 +3886,10 @@
}
break;
- /* DS Form - 64bit Stores */
+ /* DS Form - 64bit Stores. In each case EA will have been formed
+ with the lowest 2 bits masked off the immediate offset. */
case 0x3E:
- switch (b1<<1 | b0) {
+ switch ((b1<<1) | b0) {
case 0x0: // std (Store DWord, PPC64 p580)
DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
storeBE( mkexpr(EA), mkexpr(rS) );
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2007-04-29 09:49:38 UTC (rev 1752)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2007-04-29 09:57:48 UTC (rev 1753)
@@ -1301,7 +1301,7 @@
Bool idxd = toBool(i->Pin.Load.src->tag == Pam_RR);
UChar sz = i->Pin.Load.sz;
UChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
- vex_printf("l%cz%s ", c_sz, idxd ? "x" : "" );
+ vex_printf("l%c%s%s ", c_sz, sz==8 ? "" : "z", idxd ? "x" : "" );
ppHRegPPC(i->Pin.Load.dst);
vex_printf(",");
ppPPCAMode(i->Pin.Load.src);
@@ -2388,8 +2388,9 @@
if (opc1 == 58 || opc1 == 62) { // ld/std: mode64 only
vassert(mode64);
- // kludge DS form: lowest 2 bits = 00
- idx &= 0xFFFC;
+ /* stay sane with DS form: lowest 2 bits must be 00. This
+ should be guaranteed to us by iselWordExpr_AMode. */
+ vassert(0 == (idx & 3));
}
p = mkFormD(p, opc1, rSD, rA, idx);
return p;
@@ -3028,6 +3029,10 @@
UInt opc1, opc2, sz = i->Pin.Load.sz;
switch (am_addr->tag) {
case Pam_IR:
+ if (mode64 && (sz == 4 || sz == 8)) {
+ /* should be guaranteed to us by iselWordExpr_AMode */
+ vassert(0 == (am_addr->Pam.IR.index & 3));
+ }
switch(sz) {
case 1: opc1 = 34; break;
case 2: opc1 = 40; break;
@@ -3099,6 +3104,10 @@
UInt opc1, opc2, sz = i->Pin.Store.sz;
switch (i->Pin.Store.dst->tag) {
case Pam_IR:
+ if (mode64 && (sz == 4 || sz == 8)) {
+ /* should be guaranteed to us by iselWordExpr_AMode */
+ vassert(0 == (am_addr->Pam.IR.index & 3));
+ }
switch(sz) {
case 1: opc1 = 38; break;
case 2: opc1 = 44; break;
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c 2007-04-29 09:49:38 UTC (rev 1752)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c 2007-04-29 09:57:48 UTC (rev 1753)
@@ -374,17 +374,26 @@
static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e );
static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e );
-/* In 64-bit mode ONLY, compute an I8 into a Compute an I8 into a
+/* In 64-bit mode ONLY, compute an I8 into a
reg-or-6-bit-unsigned-immediate, the latter being an immediate in
the range 1 .. 63 inclusive. Used for doing shift amounts. */
static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e );
static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e );
/* 32-bit mode: compute an I32 into an AMode.
- 64-bit mode: compute an I64 into an AMode. */
-static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
-static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e );
+ 64-bit mode: compute an I64 into an AMode.
+ Requires to know (xferTy) the type of data to be loaded/stored
+ using this amode. That is so that, for 64-bit code generation, any
+ PPCAMode_IR returned will have an index (immediate offset) field
+ that is guaranteed to be 4-aligned, if there is any chance that the
+ amode is to be used in ld/ldu/lda/std/stdu.
+
+ Since there are no such restrictions on 32-bit insns, xferTy is
+ ignored for 32-bit code generation. */
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType xferTy );
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy );
+
/* 32-bit mode ONLY: compute an I64 into a GPR pair. */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e );
@@ -1150,7 +1159,7 @@
/* --------- LOAD --------- */
case Iex_Load: {
HReg r_dst = newVRegI(env);
- PPCAMode* am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr );
+ PPCAMode* am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ );
if (e->Iex.Load.end != Iend_BE)
goto irreducible;
addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),
@@ -1502,7 +1511,7 @@
IRExpr_Load(Iend_BE,Ity_I16,bind(0))) );
if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
HReg r_dst = newVRegI(env);
- PPCAMode* amode = iselWordExpr_AMode( env, mi.bindee[0] );
+ PPCAMode* amode = iselWordExpr_AMode( env, mi.bindee[0], Ity_I16/*xfer*/ );
addInstr(env, PPCInstr_Load(2,r_dst,amode, mode64));
return r_dst;
}
@@ -1900,6 +1909,11 @@
return toBool(u == (ULong)i);
}
+static Bool uLong_is_4_aligned ( ULong u )
+{
+ return toBool((u & 3ULL) == 0);
+}
+
static Bool sane_AMode ( ISelEnv* env, PPCAMode* am )
{
Bool mode64 = env->mode64;
@@ -1920,20 +1934,30 @@
}
}
-static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e )
+static
+PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy )
{
- PPCAMode* am = iselWordExpr_AMode_wrk(env, e);
+ PPCAMode* am = iselWordExpr_AMode_wrk(env, e, xferTy);
vassert(sane_AMode(env, am));
return am;
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType xferTy )
{
IRType ty = typeOfIRExpr(env->type_env,e);
if (env->mode64) {
+ /* If the data load/store type is I32 or I64, this amode might
+ be destined for use in ld/ldu/lwa/st/stu. In which case
+ insist that if it comes out as an _IR, the immediate must
+ have its bottom two bits be zero. This does assume that for
+ any other type (I8/I16/I128/F32/F64/V128) the amode will not
+ be parked in any such instruction. But that seems a
+ reasonable assumption. */
+ Bool aligned4imm = toBool(xferTy == Ity_I32 || xferTy == Ity_I64);
+
vassert(ty == Ity_I64);
/* Add64(expr,i), where i == sign-extend of (i & 0xFFFF) */
@@ -1941,6 +1965,9 @@
&& e->Iex.Binop.op == Iop_Add64
&& e->Iex.Binop.arg2->tag == Iex_Const
&& e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
+ && (aligned4imm ? uLong_is_4_aligned(e->Iex.Binop.arg2
+ ->Iex.Const.con->Ico.U64)
+ : True)
&& uLong_fits_in_16_bits(e->Iex.Binop.arg2
->Iex.Const.con->Ico.U64)) {
return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
@@ -2799,7 +2826,7 @@
PPCAMode* am_addr;
HReg r_dst = newVRegF(env);
vassert(e->Iex.Load.ty == Ity_F32);
- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr);
+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F32/*xfer*/);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
return r_dst;
}
@@ -2947,7 +2974,7 @@
HReg r_dst = newVRegF(env);
PPCAMode* am_addr;
vassert(e->Iex.Load.ty == Ity_F64);
- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr);
+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F64/*xfer*/);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
return r_dst;
}
@@ -3194,7 +3221,7 @@
PPCAMode* am_addr;
HReg v_dst = newVRegV(env);
vassert(e->Iex.Load.ty == Ity_V128);
- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr);
+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_V128/*xfer*/);
addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, v_dst, am_addr));
return v_dst;
}
@@ -3601,7 +3628,7 @@
( mode64 && (tya != Ity_I64)) )
goto stmt_fail;
- am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr);
+ am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/);
if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 ||
(mode64 && (tyd == Ity_I64))) {
HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data);
|
|
From: <sv...@va...> - 2007-04-29 09:49:40
|
Author: sewardj
Date: 2007-04-29 10:49:38 +0100 (Sun, 29 Apr 2007)
New Revision: 1752
Log:
Merge r1737 (Handle the (bizarre) no-op "26 2E 64 65 90 %es:%cs:%fs:%gs:nop")
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 09:40:56 UTC (rev 1751)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 09:49:38 UTC (rev 1752)
@@ -7272,6 +7272,18 @@
switch (getIByte(delta)) {
case 0x3E: /* %DS: */
case 0x26: /* %ES: */
+ /* Sun's JVM 1.5.0 uses the following as a NOP:
+ 26 2E 64 65 90 %es:%cs:%fs:%gs:nop */
+ {
+ UChar* code = (UChar*)(guest_code + delta);
+ if (code[0] == 0x26 && code[1] == 0x2E && code[2] == 0x64
+ && code[3] == 0x65 && code[4] == 0x90) {
+ DIP("%%es:%%cs:%%fs:%%gs:nop\n");
+ delta += 5;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
case 0x64: /* %FS: */
case 0x65: /* %GS: */
sorb = getIByte(delta); delta++;
|
|
From: <sv...@va...> - 2007-04-29 09:41:00
|
Author: sewardj
Date: 2007-04-29 10:40:56 +0100 (Sun, 29 Apr 2007)
New Revision: 1751
Log:
Merge r1736 and r1741: int $3 support (x86 and amd64)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 09:28:21 UTC (rev 1750)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 09:40:56 UTC (rev 1751)
@@ -12380,6 +12380,12 @@
/* ------------------------ INT ------------------------ */
+ case 0xCC: /* INT 3 */
+ jmp_lit(Ijk_Trap, guest_RIP_bbstart + delta);
+ dres.whatNext = Dis_StopHere;
+ DIP("int $0x3\n");
+ break;
+
case 0xCD: { /* INT imm8 */
IRJumpKind jk = Ijk_Boring;
if (have66orF2orF3(pfx)) goto decode_failure;
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 09:28:21 UTC (rev 1750)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-04-29 09:40:56 UTC (rev 1751)
@@ -11208,6 +11208,12 @@
/* ------------------------ INT ------------------------ */
+ case 0xCC: /* INT 3 */
+ jmp_lit(Ijk_Trap,((Addr32)guest_EIP_bbstart)+delta);
+ dres.whatNext = Dis_StopHere;
+ DIP("int $0x3\n");
+ break;
+
case 0xCD: /* INT imm8 */
d32 = getIByte(delta); delta++;
if (d32 != 0x80) goto decode_failure;
Modified: branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c 2007-04-29 09:28:21 UTC (rev 1750)
+++ branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c 2007-04-29 09:40:56 UTC (rev 1751)
@@ -2640,6 +2640,9 @@
case Ijk_NoRedir:
*p++ = 0xBD;
p = emit32(p, VEX_TRC_JMP_NOREDIR); break;
+ case Ijk_Trap:
+ *p++ = 0xBD;
+ p = emit32(p, VEX_TRC_JMP_TRAP); break;
case Ijk_Ret:
case Ijk_Call:
case Ijk_Boring:
Modified: branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c 2007-04-29 09:28:21 UTC (rev 1750)
+++ branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c 2007-04-29 09:40:56 UTC (rev 1751)
@@ -2184,6 +2184,9 @@
case Ijk_Sys_sysenter:
*p++ = 0xBD;
p = emit32(p, VEX_TRC_JMP_SYS_SYSENTER); break;
+ case Ijk_Trap:
+ *p++ = 0xBD;
+ p = emit32(p, VEX_TRC_JMP_TRAP); break;
case Ijk_Ret:
case Ijk_Call:
case Ijk_Boring:
|
|
From: <sv...@va...> - 2007-04-29 09:28:52
|
Author: sewardj
Date: 2007-04-29 10:28:21 +0100 (Sun, 29 Apr 2007)
New Revision: 1750
Log:
Merge r1735 (Handle FCOM and FCOMPP in 64-bit mode (see #141790))
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
===================================================================
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-07 12:25:37 UTC (rev 1749)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-04-29 09:28:21 UTC (rev 1750)
@@ -4454,23 +4454,23 @@
fp_do_op_ST_ST ( "mul", Iop_MulF64, modrm - 0xC8, 0, False );
break;
+ /* Dunno if this is right */
+ case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */
+ r_dst = (UInt)modrm - 0xD0;
+ DIP("fcom %%st(0),%%st(%d)\n", r_dst);
+ /* This forces C1 to zero, which isn't right. */
+ put_C3210(
+ unop(Iop_32Uto64,
+ binop( Iop_And32,
+ binop(Iop_Shl32,
+ binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)),
+ mkU8(8)),
+ mkU32(0x4500)
+ )));
+ break;
+
//.. #if 1
//.. /* Dunno if this is right */
-//.. case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */
-//.. r_dst = (UInt)modrm - 0xD0;
-//.. DIP("fcom %%st(0),%%st(%d)\n", r_dst);
-//.. /* This forces C1 to zero, which isn't right. */
-//.. put_C3210(
-//.. binop( Iop_And32,
-//.. binop(Iop_Shl32,
-//.. binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)),
-//.. mkU8(8)),
-//.. mkU32(0x4500)
-//.. ));
-//.. break;
-//.. #endif
-//.. #if 1
-//.. /* Dunno if this is right */
//.. case 0xD8 ... 0xDF: /* FCOMP %st(?),%st(0) */
//.. r_dst = (UInt)modrm - 0xD8;
//.. DIP("fcomp %%st(0),%%st(%d)\n", r_dst);
@@ -5750,19 +5750,20 @@
fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, True );
break;
-//.. case 0xD9: /* FCOMPP %st(0),%st(1) */
-//.. DIP("fuompp %%st(0),%%st(1)\n");
-//.. /* This forces C1 to zero, which isn't right. */
-//.. put_C3210(
-//.. binop( Iop_And32,
-//.. binop(Iop_Shl32,
-//.. binop(Iop_CmpF64, get_ST(0), get_ST(1)),
-//.. mkU8(8)),
-//.. mkU32(0x4500)
-//.. ));
-//.. fp_pop();
-//.. fp_pop();
-//.. break;
+ case 0xD9: /* FCOMPP %st(0),%st(1) */
+ DIP("fcompp %%st(0),%%st(1)\n");
+ /* This forces C1 to zero, which isn't right. */
+ put_C3210(
+ unop(Iop_32Uto64,
+ binop( Iop_And32,
+ binop(Iop_Shl32,
+ binop(Iop_CmpF64, get_ST(0), get_ST(1)),
+ mkU8(8)),
+ mkU32(0x4500)
+ )));
+ fp_pop();
+ fp_pop();
+ break;
case 0xE0 ... 0xE7: /* FSUBRP %st(0),%st(?) */
fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, True );
|
|
From: Tom H. <th...@cy...> - 2007-04-29 02:31:03
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2007-04-29 03:15:02 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 256 tests, 27 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-pool-0 (stderr) memcheck/tests/leak-pool-1 (stderr) memcheck/tests/leak-pool-2 (stderr) memcheck/tests/leak-pool-3 (stderr) memcheck/tests/leak-pool-4 (stderr) memcheck/tests/leak-pool-5 (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/long_namespace_xml (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/xor-undef-x86 (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: Tom H. <th...@cy...> - 2007-04-29 02:23:57
|
Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-04-29 03:10:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
|
From: Tom H. <th...@cy...> - 2007-04-29 02:11:08
|
Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-04-29 03:05:04 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo gcc -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -o nibz_bennee_mmap nibz_bennee_mmap.o if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -MT slahf-amd64.o -MD -MP -MF ".deps/slahf-amd64.Tpo" -c -o slahf-amd64.o slahf-amd64.c; \ then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi /tmp/ccbDcYbQ.s: Assembler messages: /tmp/ccbDcYbQ.s:18: Error: suffix or operands invalid for `lahf' /tmp/ccbDcYbQ.s:28: Error: suffix or operands invalid for `lahf' /tmp/ccbDcYbQ.s:34: Error: suffix or operands invalid for `sahf' /tmp/ccbDcYbQ.s:36: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 rm insn_sse3.c insn_sse.c insn_mmx.c insn_fpu.c insn_sse2.c insn_basic.c make[5]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind' make: *** [check] Error 2 ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo gcc -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -o nibz_bennee_mmap nibz_bennee_mmap.o if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -MT slahf-amd64.o -MD -MP -MF ".deps/slahf-amd64.Tpo" -c -o slahf-amd64.o slahf-amd64.c; \ then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi /tmp/ccvwyIhh.s: Assembler messages: /tmp/ccvwyIhh.s:18: Error: suffix or operands invalid for `lahf' /tmp/ccvwyIhh.s:28: Error: suffix or operands invalid for `lahf' /tmp/ccvwyIhh.s:34: Error: suffix or operands invalid for `sahf' /tmp/ccvwyIhh.s:36: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 rm insn_sse3.c insn_sse.c insn_mmx.c insn_fpu.c insn_sse2.c insn_basic.c make[5]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind' make: *** [check] Error 2 ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sun Apr 29 03:08:04 2007 --- new.short Sun Apr 29 03:10:59 2007 *************** *** 10,16 **** then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi ! /tmp/ccvwyIhh.s: Assembler messages: ! /tmp/ccvwyIhh.s:18: Error: suffix or operands invalid for `lahf' ! /tmp/ccvwyIhh.s:28: Error: suffix or operands invalid for `lahf' ! /tmp/ccvwyIhh.s:34: Error: suffix or operands invalid for `sahf' ! /tmp/ccvwyIhh.s:36: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 --- 10,16 ---- then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi ! /tmp/ccbDcYbQ.s: Assembler messages: ! /tmp/ccbDcYbQ.s:18: Error: suffix or operands invalid for `lahf' ! /tmp/ccbDcYbQ.s:28: Error: suffix or operands invalid for `lahf' ! /tmp/ccbDcYbQ.s:34: Error: suffix or operands invalid for `sahf' ! /tmp/ccbDcYbQ.s:36: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 |
|
From: Tom H. <th...@cy...> - 2007-04-29 02:05:42
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-04-29 03:00:02 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo gcc -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -o nibz_bennee_mmap nibz_bennee_mmap.o if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -MT slahf-amd64.o -MD -MP -MF ".deps/slahf-amd64.Tpo" -c -o slahf-amd64.o slahf-amd64.c; \ then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi /tmp/ccfMbkjn.s: Assembler messages: /tmp/ccfMbkjn.s:27: Error: suffix or operands invalid for `lahf' /tmp/ccfMbkjn.s:37: Error: suffix or operands invalid for `lahf' /tmp/ccfMbkjn.s:43: Error: suffix or operands invalid for `sahf' /tmp/ccfMbkjn.s:45: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 rm insn_sse3.c insn_sse.c insn_mmx.c insn_fpu.c insn_sse2.c insn_basic.c make[5]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind' make: *** [check] Error 2 ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo gcc -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -o nibz_bennee_mmap nibz_bennee_mmap.o if gcc -DHAVE_CONFIG_H -I. -I. -I../../.. -Winline -Wall -Wshadow -g -I../../../include -Wno-long-long -Wdeclaration-after-statement -MT slahf-amd64.o -MD -MP -MF ".deps/slahf-amd64.Tpo" -c -o slahf-amd64.o slahf-amd64.c; \ then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi /tmp/ccCkP6gW.s: Assembler messages: /tmp/ccCkP6gW.s:27: Error: suffix or operands invalid for `lahf' /tmp/ccCkP6gW.s:37: Error: suffix or operands invalid for `lahf' /tmp/ccCkP6gW.s:43: Error: suffix or operands invalid for `sahf' /tmp/ccCkP6gW.s:45: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 rm insn_sse3.c insn_sse.c insn_mmx.c insn_fpu.c insn_sse2.c insn_basic.c make[5]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests/amd64' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/vgtest/2007-04-29/valgrind' make: *** [check] Error 2 ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sun Apr 29 03:02:49 2007 --- new.short Sun Apr 29 03:05:33 2007 *************** *** 10,16 **** then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi ! /tmp/ccCkP6gW.s: Assembler messages: ! /tmp/ccCkP6gW.s:27: Error: suffix or operands invalid for `lahf' ! /tmp/ccCkP6gW.s:37: Error: suffix or operands invalid for `lahf' ! /tmp/ccCkP6gW.s:43: Error: suffix or operands invalid for `sahf' ! /tmp/ccCkP6gW.s:45: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 --- 10,16 ---- then mv -f ".deps/slahf-amd64.Tpo" ".deps/slahf-amd64.Po"; else rm -f ".deps/slahf-amd64.Tpo"; exit 1; fi ! /tmp/ccfMbkjn.s: Assembler messages: ! /tmp/ccfMbkjn.s:27: Error: suffix or operands invalid for `lahf' ! /tmp/ccfMbkjn.s:37: Error: suffix or operands invalid for `lahf' ! /tmp/ccfMbkjn.s:43: Error: suffix or operands invalid for `sahf' ! /tmp/ccfMbkjn.s:45: Error: suffix or operands invalid for `lahf' make[5]: *** [slahf-amd64.o] Error 1 |
|
From: <js...@ac...> - 2007-04-29 00:19:31
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2007-04-29 02:00:01 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 226 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |