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From: <sv...@va...> - 2007-01-10 19:30:25
|
Author: sewardj
Date: 2007-01-10 19:30:19 +0000 (Wed, 10 Jan 2007)
New Revision: 6505
Log:
Merge r6504 (ifort 9.1 on amd64 suppression)
Modified:
trunk/xfree-4.supp
Modified: trunk/xfree-4.supp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/xfree-4.supp 2007-01-10 18:32:36 UTC (rev 6504)
+++ trunk/xfree-4.supp 2007-01-10 19:30:19 UTC (rev 6505)
@@ -236,5 +236,17 @@
obj:/usr/X11*/lib*/libX11.so*
}
=20
+
##----------------------------------------------------------------------=
##
+# Completely inappropriate place, but ...
=20
+{
+ ifort-9.X-on-amd64-#1
+ Memcheck:Addr8
+ fun:unaligned_bigint
+ fun:hash
+ fun:for__add_to_lf_table
+}
+
+##----------------------------------------------------------------------=
##
+
|
|
From: <sv...@va...> - 2007-01-10 18:32:58
|
Author: sewardj
Date: 2007-01-10 18:32:36 +0000 (Wed, 10 Jan 2007)
New Revision: 6504
Log:
ifort 9.1 on amd64 suppression
Modified:
branches/VALGRIND_3_2_BRANCH/xfree-4.supp
Modified: branches/VALGRIND_3_2_BRANCH/xfree-4.supp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/xfree-4.supp 2007-01-10 15:43:36 UTC (re=
v 6503)
+++ branches/VALGRIND_3_2_BRANCH/xfree-4.supp 2007-01-10 18:32:36 UTC (re=
v 6504)
@@ -237,5 +237,17 @@
obj:/usr/X11*/lib*/libX11.so*
}
=20
+
##----------------------------------------------------------------------=
##
+# Completely inappropriate place, but ...
=20
+{
+ ifort-9.X-on-amd64-#1
+ Memcheck:Addr8
+ fun:unaligned_bigint
+ fun:hash
+ fun:for__add_to_lf_table
+}
+
+##----------------------------------------------------------------------=
##
+
|
|
From: <sv...@va...> - 2007-01-10 15:43:37
|
Author: sewardj
Date: 2007-01-10 15:43:36 +0000 (Wed, 10 Jan 2007)
New Revision: 6503
Log:
Merge r6502 (Generate valid XML even for very long fn names)
Modified:
branches/VALGRIND_3_2_BRANCH/coregrind/m_debuginfo/debuginfo.c
Modified: branches/VALGRIND_3_2_BRANCH/coregrind/m_debuginfo/debuginfo.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/coregrind/m_debuginfo/debuginfo.c 2007-0=
1-10 15:42:15 UTC (rev 6502)
+++ branches/VALGRIND_3_2_BRANCH/coregrind/m_debuginfo/debuginfo.c 2007-0=
1-10 15:43:36 UTC (rev 6503)
@@ -589,38 +589,73 @@
}
=20
=20
-/* Print into buf info on code address, function name and filename */
+/* VG_(describe_IP): print into buf info on code address, function
+ name and filename. */
=20
+/* Copy str into buf starting at n, but not going past buf[n_buf-1]
+ and always ensuring that buf is zero-terminated. */
+
static Int putStr ( Int n, Int n_buf, Char* buf, Char* str )=20
{
+ vg_assert(n_buf > 0);
+ vg_assert(n >=3D 0 && n < n_buf);
for (; n < n_buf-1 && *str !=3D 0; n++,str++)
buf[n] =3D *str;
+ vg_assert(n >=3D 0 && n < n_buf);
buf[n] =3D '\0';
return n;
}
-static Int putStrEsc ( Int n, Int n_buf, Char* buf, Char* str )=20
+
+/* Same as putStr, but escaping chars for XML output, and
+ also not adding more than count chars to n_buf. */
+
+static Int putStrEsc ( Int n, Int n_buf, Int count, Char* buf, Char* str=
)=20
{
Char alt[2];
+ vg_assert(n_buf > 0);
+ vg_assert(count >=3D 0 && count < n_buf);
+ vg_assert(n >=3D 0 && n < n_buf);
for (; *str !=3D 0; str++) {
+ vg_assert(count >=3D 0);
+ if (count <=3D 0)
+ goto done;
switch (*str) {
- case '&': n =3D putStr( n, n_buf, buf, "&"); break;
- case '<': n =3D putStr( n, n_buf, buf, "<"); break;
- case '>': n =3D putStr( n, n_buf, buf, ">"); break;
- default: alt[0] =3D *str;
- alt[1] =3D 0;
- n =3D putStr( n, n_buf, buf, alt );
- break;
+ case '&':=20
+ if (count < 5) goto done;
+ n =3D putStr( n, n_buf, buf, "&");=20
+ count -=3D 5;
+ break;
+ case '<':=20
+ if (count < 4) goto done;
+ n =3D putStr( n, n_buf, buf, "<");=20
+ count -=3D 4;
+ break;
+ case '>':=20
+ if (count < 4) goto done;
+ n =3D putStr( n, n_buf, buf, ">");=20
+ count -=3D 4;
+ break;
+ default:
+ if (count < 1) goto done;
+ alt[0] =3D *str;
+ alt[1] =3D 0;
+ n =3D putStr( n, n_buf, buf, alt );
+ count -=3D 1;
+ break;
}
}
+ done:
+ vg_assert(count >=3D 0); /* should not go -ve in loop */
+ vg_assert(n >=3D 0 && n < n_buf);
return n;
}
=20
Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf)
{
# define APPEND(_str) \
- n =3D putStr(n, n_buf, buf, _str);
-# define APPEND_ESC(_str) \
- n =3D putStrEsc(n, n_buf, buf, _str);
+ n =3D putStr(n, n_buf, buf, _str)
+# define APPEND_ESC(_count,_str) \
+ n =3D putStrEsc(n, n_buf, (_count), buf, (_str))
# define BUF_LEN 4096
=20
UInt lineno;=20
@@ -645,7 +680,12 @@
HChar* maybe_newline =3D human_readable ? "\n " : "";
HChar* maybe_newline2 =3D human_readable ? "\n " : "";
=20
- /* Print in XML format, dumping in as much info as we know. */
+ /* Print in XML format, dumping in as much info as we know.
+ Ensure all tags are balanced even if the individual strings
+ are too long. Allocate 1/10 of BUF_LEN to the object name,
+ 6/10s to the function name, 1/10 to the directory name and
+ 1/10 to the file name, leaving 1/10 for all the fixed-length
+ stuff. */
APPEND("<frame>");
VG_(sprintf)(ibuf,"<ip>0x%llx</ip>", (ULong)eip);
APPEND(maybe_newline);
@@ -653,25 +693,25 @@
if (know_objname) {
APPEND(maybe_newline);
APPEND("<obj>");
- APPEND_ESC(buf_obj);
+ APPEND_ESC(1*BUF_LEN/10, buf_obj);
APPEND("</obj>");
}
if (know_fnname) {
APPEND(maybe_newline);
APPEND("<fn>");
- APPEND_ESC(buf_fn);
+ APPEND_ESC(6*BUF_LEN/10, buf_fn);
APPEND("</fn>");
}
if (know_srcloc) {
if (know_dirinfo) {
APPEND(maybe_newline);
APPEND("<dir>");
- APPEND(buf_dirname);
+ APPEND_ESC(1*BUF_LEN/10, buf_dirname);
APPEND("</dir>");
}
APPEND(maybe_newline);
APPEND("<file>");
- APPEND_ESC(buf_srcloc);
+ APPEND_ESC(1*BUF_LEN/10, buf_srcloc);
APPEND("</file>");
APPEND(maybe_newline);
APPEND("<line>");
|
|
From: <sv...@va...> - 2007-01-10 15:42:25
|
Author: sewardj
Date: 2007-01-10 15:42:15 +0000 (Wed, 10 Jan 2007)
New Revision: 6502
Log:
Generate valid XML even for very long fn names - always ensure tags
have matching closing tags.
Modified:
trunk/coregrind/m_debuginfo/debuginfo.c
Modified: trunk/coregrind/m_debuginfo/debuginfo.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_debuginfo/debuginfo.c 2007-01-10 13:04:52 UTC (rev =
6501)
+++ trunk/coregrind/m_debuginfo/debuginfo.c 2007-01-10 15:42:15 UTC (rev =
6502)
@@ -744,38 +744,73 @@
}
=20
=20
-/* Print into buf info on code address, function name and filename */
+/* VG_(describe_IP): print into buf info on code address, function
+ name and filename. */
=20
+/* Copy str into buf starting at n, but not going past buf[n_buf-1]
+ and always ensuring that buf is zero-terminated. */
+
static Int putStr ( Int n, Int n_buf, Char* buf, Char* str )=20
{
+ vg_assert(n_buf > 0);
+ vg_assert(n >=3D 0 && n < n_buf);
for (; n < n_buf-1 && *str !=3D 0; n++,str++)
buf[n] =3D *str;
+ vg_assert(n >=3D 0 && n < n_buf);
buf[n] =3D '\0';
return n;
}
-static Int putStrEsc ( Int n, Int n_buf, Char* buf, Char* str )=20
+
+/* Same as putStr, but escaping chars for XML output, and
+ also not adding more than count chars to n_buf. */
+
+static Int putStrEsc ( Int n, Int n_buf, Int count, Char* buf, Char* str=
)=20
{
Char alt[2];
+ vg_assert(n_buf > 0);
+ vg_assert(count >=3D 0 && count < n_buf);
+ vg_assert(n >=3D 0 && n < n_buf);
for (; *str !=3D 0; str++) {
+ vg_assert(count >=3D 0);
+ if (count <=3D 0)
+ goto done;
switch (*str) {
- case '&': n =3D putStr( n, n_buf, buf, "&"); break;
- case '<': n =3D putStr( n, n_buf, buf, "<"); break;
- case '>': n =3D putStr( n, n_buf, buf, ">"); break;
- default: alt[0] =3D *str;
- alt[1] =3D 0;
- n =3D putStr( n, n_buf, buf, alt );
- break;
+ case '&':=20
+ if (count < 5) goto done;
+ n =3D putStr( n, n_buf, buf, "&");=20
+ count -=3D 5;
+ break;
+ case '<':=20
+ if (count < 4) goto done;
+ n =3D putStr( n, n_buf, buf, "<");=20
+ count -=3D 4;
+ break;
+ case '>':=20
+ if (count < 4) goto done;
+ n =3D putStr( n, n_buf, buf, ">");=20
+ count -=3D 4;
+ break;
+ default:
+ if (count < 1) goto done;
+ alt[0] =3D *str;
+ alt[1] =3D 0;
+ n =3D putStr( n, n_buf, buf, alt );
+ count -=3D 1;
+ break;
}
}
+ done:
+ vg_assert(count >=3D 0); /* should not go -ve in loop */
+ vg_assert(n >=3D 0 && n < n_buf);
return n;
}
=20
Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf)
{
# define APPEND(_str) \
- n =3D putStr(n, n_buf, buf, _str);
-# define APPEND_ESC(_str) \
- n =3D putStrEsc(n, n_buf, buf, _str);
+ n =3D putStr(n, n_buf, buf, _str)
+# define APPEND_ESC(_count,_str) \
+ n =3D putStrEsc(n, n_buf, (_count), buf, (_str))
# define BUF_LEN 4096
=20
UInt lineno;=20
@@ -802,7 +837,12 @@
HChar* maybe_newline =3D human_readable ? "\n " : "";
HChar* maybe_newline2 =3D human_readable ? "\n " : "";
=20
- /* Print in XML format, dumping in as much info as we know. */
+ /* Print in XML format, dumping in as much info as we know.
+ Ensure all tags are balanced even if the individual strings
+ are too long. Allocate 1/10 of BUF_LEN to the object name,
+ 6/10s to the function name, 1/10 to the directory name and
+ 1/10 to the file name, leaving 1/10 for all the fixed-length
+ stuff. */
APPEND("<frame>");
VG_(sprintf)(ibuf,"<ip>0x%llx</ip>", (ULong)eip);
APPEND(maybe_newline);
@@ -810,25 +850,25 @@
if (know_objname) {
APPEND(maybe_newline);
APPEND("<obj>");
- APPEND_ESC(buf_obj);
+ APPEND_ESC(1*BUF_LEN/10, buf_obj);
APPEND("</obj>");
}
if (know_fnname) {
APPEND(maybe_newline);
APPEND("<fn>");
- APPEND_ESC(buf_fn);
+ APPEND_ESC(6*BUF_LEN/10, buf_fn);
APPEND("</fn>");
}
if (know_srcloc) {
if (know_dirinfo) {
APPEND(maybe_newline);
APPEND("<dir>");
- APPEND(buf_dirname);
+ APPEND_ESC(1*BUF_LEN/10, buf_dirname);
APPEND("</dir>");
}
APPEND(maybe_newline);
APPEND("<file>");
- APPEND_ESC(buf_srcloc);
+ APPEND_ESC(1*BUF_LEN/10, buf_srcloc);
APPEND("</file>");
APPEND(maybe_newline);
APPEND("<line>");
|
|
From: <sv...@va...> - 2007-01-10 13:04:57
|
Author: njn
Date: 2007-01-10 13:04:52 +0000 (Wed, 10 Jan 2007)
New Revision: 6501
Log:
Specialise some of the value-error C helpers, for common cases. This
reduces code expansion by about 5%, and speed by about 1%, judging from t=
he
perf suite.
Modified:
branches/ORIGIN_TRACKING/memcheck/mc_include.h
branches/ORIGIN_TRACKING/memcheck/mc_main.c
branches/ORIGIN_TRACKING/memcheck/mc_translate.c
branches/ORIGIN_TRACKING/memcheck/tests/origin-yes.c
Modified: branches/ORIGIN_TRACKING/memcheck/mc_include.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ORIGIN_TRACKING/memcheck/mc_include.h 2007-01-10 12:06:01 UT=
C (rev 6500)
+++ branches/ORIGIN_TRACKING/memcheck/mc_include.h 2007-01-10 13:04:52 UT=
C (rev 6501)
@@ -299,10 +299,21 @@
/*------------------------------------------------------------*/
=20
/* Functions defined in mc_main.c */
+extern VG_REGPARM(0) void MC_(helperc_value_error_0_origins_szWord) ( vo=
id );
+extern VG_REGPARM(0) void MC_(helperc_value_error_0_origins_sz0) ( vo=
id );
extern VG_REGPARM(1) void MC_(helperc_value_error_0_origins) ( HWord );
+
+extern VG_REGPARM(1) void MC_(helperc_value_error_1_origin_szWord) ( HWo=
rd );
+extern VG_REGPARM(1) void MC_(helperc_value_error_1_origin_sz0) ( HWo=
rd );
extern VG_REGPARM(2) void MC_(helperc_value_error_1_origin) ( HWord, HW=
ord );
+
+extern VG_REGPARM(2) void MC_(helperc_value_error_2_origins_szWord) ( HW=
ord,
+ HW=
ord );
+extern VG_REGPARM(2) void MC_(helperc_value_error_2_origins_sz0) ( HW=
ord,
+ HW=
ord );
extern VG_REGPARM(3) void MC_(helperc_value_error_2_origins) ( HWord, HW=
ord,
- HWord );
+ HW=
ord );
+
extern VG_REGPARM(3) void MC_(helperc_value_error_3_origins) ( HWord, HW=
ord,
HWord, HW=
ord );
extern VG_REGPARM(3) void MC_(helperc_value_error_4_origins) ( HWord, HW=
ord,
Modified: branches/ORIGIN_TRACKING/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ORIGIN_TRACKING/memcheck/mc_main.c 2007-01-10 12:06:01 UTC (=
rev 6500)
+++ branches/ORIGIN_TRACKING/memcheck/mc_main.c 2007-01-10 13:04:52 UTC (=
rev 6501)
@@ -4288,28 +4288,65 @@
mc_record_value_error ( VG_(get_running_tid)(), (Int)szB, origins, n_=
origins );
}
=20
-VG_REGPARM(1) void MC_(helperc_value_error_0_origins) ( HWord szB )
-{
- mc_helperc_value_error_N_origins(szB, NULL, 0);
+// Here we specialise the common cases (0, 1 and 2 origins with szB of 0=
and
+// VG_WORDSIZE) to reduce the number of args passed. Remaining cases ar=
e
+// done with the more general functions.
+
+// Zero origins
+VG_REGPARM(0) void MC_(helperc_value_error_0_origins_szWord) ( void ) {
+ mc_helperc_value_error_N_origins(VG_WORDSIZE, NULL, 0);
}
+VG_REGPARM(0) void MC_(helperc_value_error_0_origins_sz0) ( void ) {
+ mc_helperc_value_error_N_origins(0, NULL, 0);
+}
+VG_REGPARM(1) void MC_(helperc_value_error_0_origins) ( HWord szB ) {
+ mc_helperc_value_error_N_origins(szB, NULL, 0);
+}
=20
+// One origin
+VG_REGPARM(1) void MC_(helperc_value_error_1_origin_szWord) (=20
+ HWord origin_hword0 ) {
+ HWord origin_hwords[1];
+ origin_hwords[0] =3D origin_hword0;
+ mc_helperc_value_error_N_origins(VG_WORDSIZE, origin_hwords, 1);
+}
+VG_REGPARM(1) void MC_(helperc_value_error_1_origin_sz0) (=20
+ HWord origin_hword0 ) {
+ HWord origin_hwords[1];
+ origin_hwords[0] =3D origin_hword0;
+ mc_helperc_value_error_N_origins(0, origin_hwords, 1);
+}
VG_REGPARM(2) void MC_(helperc_value_error_1_origin) ( HWord szB,
- HWord origin_hword0 )
-{
+ HWord origin_hword0 ) {
HWord origin_hwords[1];
origin_hwords[0] =3D origin_hword0;
- mc_helperc_value_error_N_origins(szB, origin_hwords, 1);
+ mc_helperc_value_error_N_origins(szB, origin_hwords, 1);
}
=20
+// Two origins
+VG_REGPARM(2) void MC_(helperc_value_error_2_origins_szWord) (
+ HWord origin_hword0, HWord origin_hword1 ) {
+ HWord origin_hwords[2];
+ origin_hwords[0] =3D origin_hword0;
+ origin_hwords[1] =3D origin_hword1;
+ mc_helperc_value_error_N_origins(VG_WORDSIZE, origin_hwords, 2);
+}
+VG_REGPARM(2) void MC_(helperc_value_error_2_origins_sz0) (
+ HWord origin_hword0, HWord origin_hword1 ) {
+ HWord origin_hwords[2];
+ origin_hwords[0] =3D origin_hword0;
+ origin_hwords[1] =3D origin_hword1;
+ mc_helperc_value_error_N_origins(0, origin_hwords, 2);
+}
VG_REGPARM(3) void MC_(helperc_value_error_2_origins) ( HWord szB,
- HWord origin_hword0, HWord origin_hword1 )
-{
+ HWord origin_hword0, HWord origin_hword1 ) {
HWord origin_hwords[2];
origin_hwords[0] =3D origin_hword0;
origin_hwords[1] =3D origin_hword1;
- mc_helperc_value_error_N_origins(szB, origin_hwords, 2);
+ mc_helperc_value_error_N_origins(szB, origin_hwords, 2);
}
=20
+// More than two origins
VG_REGPARM(3) void MC_(helperc_value_error_3_origins) ( HWord szB,
HWord origin_hword0, HWord origin_hword1,
HWord origin_hword2)
@@ -4320,7 +4357,6 @@
origin_hwords[2] =3D origin_hword2;
mc_helperc_value_error_N_origins(szB, origin_hwords, 3);
}
-
VG_REGPARM(3) void MC_(helperc_value_error_4_origins) ( HWord szB,
HWord origin_hword0, HWord origin_hword1,
HWord origin_hword2, HWord origin_hword3)
@@ -4332,7 +4368,6 @@
origin_hwords[3] =3D origin_hword3;
mc_helperc_value_error_N_origins(szB, origin_hwords, 4);
}
-
VG_REGPARM(3) void MC_(helperc_value_error_5_origins) ( HWord szB,
HWord origin_hword0, HWord origin_hword1,
HWord origin_hword2, HWord origin_hword3,
@@ -4346,7 +4381,6 @@
origin_hwords[4] =3D origin_hword4;
mc_helperc_value_error_N_origins(szB, origin_hwords, 5);
}
-
VG_REGPARM(3) void MC_(helperc_value_error_6_origins) ( HWord szB,
HWord origin_hword0, HWord origin_hword1,
HWord origin_hword2, HWord origin_hword3,
Modified: branches/ORIGIN_TRACKING/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ORIGIN_TRACKING/memcheck/mc_translate.c 2007-01-10 12:06:01 =
UTC (rev 6500)
+++ branches/ORIGIN_TRACKING/memcheck/mc_translate.c 2007-01-10 13:04:52 =
UTC (rev 6501)
@@ -812,6 +812,7 @@
=20
// XXX: there's an off-by-one error in percentify -- if I use 6 inste=
ad
// of 5 here, the buffers get overrun. (there's one in snprintf, too=
)
+ // [XXX: the snprintf one has been fixed, I think]
VG_(percentify)(origin_tracking_2, n_total, 1, 7, perc2);
VG_(percentify)(origin_tracking_1, n_total, 1, 7, perc1);
VG_(percentify)(origin_tracking_0, n_total, 1, 7, perc0);
@@ -896,8 +897,6 @@
// are all 8-bits.
static void getOriginTmps(MCEnv* mce, IRTemp currTemp, OriginsList* orig=
inTmps)
{
- // XXX: write a test that adds a whole lot of undefined numbers, and
- // should be able to give origins for all of them.
// XXX: write a test where two undefined chars are compared, but they=
're
// recently converted from 32-bit values and so can be identified.
OriginsList worklist_actual, *worklist =3D &worklist_actual;
@@ -1247,23 +1246,67 @@
szHWordExpr =3D mkIRExpr_HWord( sz );
=20
if (0 =3D=3D n_origins_found) {
- fn_name =3D "MC_(helperc_value_error_0_origins)";
- fn_ptr =3D &MC_(helperc_value_error_0_origins);
- regparms =3D 1;
- arg_vec =3D mkIRExprVec_1(szHWordExpr);
+ if (VG_WORDSIZE =3D=3D sz) {
+ // Specialise the word-sized case
+ fn_name =3D "MC_(helperc_value_error_0_origins_szWord)";
+ fn_ptr =3D &MC_(helperc_value_error_0_origins_szWord);
+ regparms =3D 0;
+ arg_vec =3D mkIRExprVec_0();
+ } else if (0 =3D=3D sz) {
+ // Specialise the cond case
+ fn_name =3D "MC_(helperc_value_error_0_origins_sz0)";
+ fn_ptr =3D &MC_(helperc_value_error_0_origins_sz0);
+ regparms =3D 0;
+ arg_vec =3D mkIRExprVec_0();
+ } else {
+ fn_name =3D "MC_(helperc_value_error_0_origins)";
+ fn_ptr =3D &MC_(helperc_value_error_0_origins);
+ regparms =3D 1;
+ arg_vec =3D mkIRExprVec_1(szHWordExpr);
+ }
=20
} else if (1 =3D=3D n_origins_found) {
- fn_name =3D "MC_(helperc_value_error_1_origin)";
- fn_ptr =3D &MC_(helperc_value_error_1_origin);
- regparms =3D 2;
- arg_vec =3D mkIRExprVec_2(szHWordExpr, mkexpr(originTmps.tmps[0])=
);
+ if (VG_WORDSIZE =3D=3D sz) {
+ // Specialise the word-sized case
+ fn_name =3D "MC_(helperc_value_error_1_origin_szWord)";
+ fn_ptr =3D &MC_(helperc_value_error_1_origin_szWord);
+ regparms =3D 1;
+ arg_vec =3D mkIRExprVec_1(mkexpr(originTmps.tmps[0]));
+ } else if (0 =3D=3D sz) {
+ // Specialise the cond case
+ fn_name =3D "MC_(helperc_value_error_1_origin_sz0)";
+ fn_ptr =3D &MC_(helperc_value_error_1_origin_sz0);
+ regparms =3D 1;
+ arg_vec =3D mkIRExprVec_1(mkexpr(originTmps.tmps[0]));
+ } else {
+ fn_name =3D "MC_(helperc_value_error_1_origin)";
+ fn_ptr =3D &MC_(helperc_value_error_1_origin);
+ regparms =3D 2;
+ arg_vec =3D mkIRExprVec_2(szHWordExpr, mkexpr(originTmps.tmps[=
0]));
+ }
=20
} else if (2 =3D=3D n_origins_found) {
- fn_name =3D "MC_(helperc_value_error_2_origins)";
- fn_ptr =3D &MC_(helperc_value_error_2_origins);
- regparms =3D 3;
- arg_vec =3D mkIRExprVec_3(szHWordExpr, mkexpr(originTmps.tmps[0])=
,
- mkexpr(originTmps.tmps[1]));
+ if (VG_WORDSIZE =3D=3D sz) {
+ // Specialise the word-sized case
+ fn_name =3D "MC_(helperc_value_error_2_origins_szWord)";
+ fn_ptr =3D &MC_(helperc_value_error_2_origins_szWord);
+ regparms =3D 2;
+ arg_vec =3D mkIRExprVec_2(mkexpr(originTmps.tmps[0]),
+ mkexpr(originTmps.tmps[1]));
+ } else if (0 =3D=3D sz) {
+ // Specialise the cond case
+ fn_name =3D "MC_(helperc_value_error_2_origins_sz0)";
+ fn_ptr =3D &MC_(helperc_value_error_2_origins_sz0);
+ regparms =3D 2;
+ arg_vec =3D mkIRExprVec_2(mkexpr(originTmps.tmps[0]),
+ mkexpr(originTmps.tmps[1]));
+ } else {
+ fn_name =3D "MC_(helperc_value_error_2_origins)";
+ fn_ptr =3D &MC_(helperc_value_error_2_origins);
+ regparms =3D 3;
+ arg_vec =3D mkIRExprVec_3(szHWordExpr, mkexpr(originTmps.tmps[=
0]),
+ mkexpr(originTmps.tmps[1]=
));
+ }
} else if (3 =3D=3D n_origins_found) {
fn_name =3D "MC_(helperc_value_error_3_origins)";
fn_ptr =3D &MC_(helperc_value_error_3_origins);
Modified: branches/ORIGIN_TRACKING/memcheck/tests/origin-yes.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ORIGIN_TRACKING/memcheck/tests/origin-yes.c 2007-01-10 12:06=
:01 UTC (rev 6500)
+++ branches/ORIGIN_TRACKING/memcheck/tests/origin-yes.c 2007-01-10 13:04=
:52 UTC (rev 6501)
@@ -17,6 +17,8 @@
=20
int main(void)
{
+ assert(1 =3D=3D sizeof(char));
+ assert(2 =3D=3D sizeof(short));
assert(4 =3D=3D sizeof(int));
assert(8 =3D=3D sizeof(long long));
=20
@@ -30,6 +32,29 @@
x +=3D (undef_stack_int =3D=3D 0x12345678 ? 10 : 21);
}
=20
+ // Stack, 32-bit, recently modified
+ // XXX: this should work, as the unmodified version should be visible
+ // within the IRSB. Same for the next two cases -- what's going wron=
g?
+ {
+ int modified_undef_stack_int;
+ modified_undef_stack_int++;
+ x +=3D (modified_undef_stack_int =3D=3D 0x1234 ? 11 : 22);
+ }
+ =20
+ // Stack, 16-bit from (recently) 32-bit
+ {
+ int undef_stack_int;
+ short undef_stack_short =3D (short)undef_stack_int;
+ x +=3D (undef_stack_short =3D=3D 0x1234 ? 11 : 22);
+ }
+ =20
+ // Stack, 8-bit from (recently) 32-bit
+ {
+ int undef_stack_int;
+ char undef_stack_char =3D (char)undef_stack_int;
+ x +=3D (undef_stack_char =3D=3D 0x12 ? 11 : 22);
+ }
+ =20
// Stack, 64-bit
{
long long undef_stack_longlong;
|
|
From: <sv...@va...> - 2007-01-10 12:06:03
|
Author: njn
Date: 2007-01-10 12:06:01 +0000 (Wed, 10 Jan 2007)
New Revision: 6500
Log:
Some notes and stuff.
Modified:
branches/ORIGIN_TRACKING/memcheck/mc_main.c
Modified: branches/ORIGIN_TRACKING/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ORIGIN_TRACKING/memcheck/mc_main.c 2007-01-10 04:57:27 UTC (=
rev 6499)
+++ branches/ORIGIN_TRACKING/memcheck/mc_main.c 2007-01-10 12:06:01 UTC (=
rev 6500)
@@ -33,9 +33,11 @@
// XXX: origin-tracking todo:
// - try recording ExeContexts for stack allocation sites, alter the
// new_mem_stack* events to allow the origin_low32 to be passed in.
-// - do timings, to work out how much slow-down it causes. Specialise
-// the helperc functions some if possible. Work out if checking
-// clo_undef_origins frequently slows things down much.
+// - do timings:
+// - to work out how much slow-down it causes. =20
+// - Specialise the helperc functions some if possible.
+// - Work out if checking clo_undef_origins frequently slows things do=
wn
+// much. [seemingly not]
=20
#include "pub_tool_basics.h"
#include "pub_tool_aspacemgr.h"
@@ -1815,10 +1817,6 @@
/*--- Stack pointer adjustment ---*/
/*------------------------------------------------------------*/
=20
-// XXX: should try recording code addresses for stack allocations, to gi=
ve
-// a 1-deep stack trace. Hmm, but difficult because code addresses are
-// word-sized. We'd need an ip_low32-to-ip table...
-
static void VG_REGPARM(1) mc_new_mem_stack_4(Addr new_SP)
{
PROF_EVENT(110, "new_mem_stack_4");
@@ -2998,7 +2996,7 @@
=20
static void mc_pp_origins ( ExeContext* origins[], Int n_origins )
{
- // XXX: in origin-yes, get two origins for the 64-bit stack case --
+ // XXX: in origin-yes, we get two origins for the 64-bit stack case -=
-
// should remove dup'd origins from the list.
=20
// XXX: is this XML-isation good enough?
|
|
From: <js...@ac...> - 2007-01-10 06:51:00
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-01-10 09:00:02 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 217 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) |
|
From: <sv...@va...> - 2007-01-10 05:22:06
|
Author: sewardj
Date: 2007-01-10 05:22:03 +0000 (Wed, 10 Jan 2007)
New Revision: 1724
Log:
Merge r1722 (Implement FXSAVE on amd64.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h 2007-01-10 05:13:42 =
UTC (rev 1723)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h 2007-01-10 05:22:03 =
UTC (rev 1724)
@@ -149,6 +149,8 @@
=20
extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
=20
+extern void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State*, HWord );
+
extern ULong amd64g_dirtyhelper_RDTSC ( void );
=20
//extern void amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
@@ -165,7 +167,6 @@
//extern VexEmWarn=20
// amd64g_dirtyhelper_FLDENV ( VexGuestAMD64State*, HWord );
=20
-//extern void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State*, HWord );
=20
=20
/*---------------------------------------------------------*/
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2007-01-10 05:13:=
42 UTC (rev 1723)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2007-01-10 05:22:=
03 UTC (rev 1724)
@@ -1391,6 +1391,162 @@
}
=20
=20
+/* Create an x87 FPU state from the guest state, as close as
+ we can approximate it. */
+static
+void do_get_x87 ( /*IN*/VexGuestAMD64State* vex_state,
+ /*OUT*/UChar* x87_state )
+{
+ Int i, stno, preg;
+ UInt tagw;
+ ULong* vexRegs =3D (ULong*)(&vex_state->guest_FPREG[0]);
+ UChar* vexTags =3D (UChar*)(&vex_state->guest_FPTAG[0]);
+ Fpu_State* x87 =3D (Fpu_State*)x87_state;
+ UInt ftop =3D vex_state->guest_FTOP;
+ UInt c3210 =3D vex_state->guest_FC3210;
+
+ for (i =3D 0; i < 14; i++)
+ x87->env[i] =3D 0;
+
+ x87->env[1] =3D x87->env[3] =3D x87->env[5] =3D x87->env[13] =3D 0xFF=
FF;
+ x87->env[FP_ENV_STAT]=20
+ =3D toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
+ x87->env[FP_ENV_CTRL]=20
+ =3D toUShort(amd64g_create_fpucw( vex_state->guest_FPROUND ));
+
+ /* Dump the register stack in ST order. */
+ tagw =3D 0;
+ for (stno =3D 0; stno < 8; stno++) {
+ preg =3D (stno + ftop) & 7;
+ if (vexTags[preg] =3D=3D 0) {
+ /* register is empty */
+ tagw |=3D (3 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],=20
+ &x87->reg[10*stno] );
+ } else {
+ /* register is full. */
+ tagw |=3D (0 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],=20
+ &x87->reg[10*stno] );
+ }
+ }
+ x87->env[FP_ENV_TAG] =3D toUShort(tagw);
+}
+
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (reads guest state, writes guest mem) */
+/* NOTE: only handles 32-bit format (no REX.W on the insn) */
+void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State* gst, HWord addr )
+{
+ /* Derived from values obtained from
+ vendor_id : AuthenticAMD
+ cpu family : 15
+ model : 12
+ model name : AMD Athlon(tm) 64 Processor 3200+
+ stepping : 0
+ cpu MHz : 2200.000
+ cache size : 512 KB
+ */
+ /* Somewhat roundabout, but at least it's simple. */
+ Fpu_State tmp;
+ UShort* addrS =3D (UShort*)addr;
+ UChar* addrC =3D (UChar*)addr;
+ U128* xmm =3D (U128*)(addr + 160);
+ UInt mxcsr;
+ UShort fp_tags;
+ UInt summary_tags;
+ Int r, stno;
+ UShort *srcS, *dstS;
+
+ do_get_x87( gst, (UChar*)&tmp );
+ mxcsr =3D amd64g_create_mxcsr( gst->guest_SSEROUND );
+
+ /* Now build the proper fxsave image from the x87 image we just
+ made. */
+
+ addrS[0] =3D tmp.env[FP_ENV_CTRL]; /* FCW: fpu control word */
+ addrS[1] =3D tmp.env[FP_ENV_STAT]; /* FCW: fpu status word */
+
+ /* set addrS[2] in an endian-independent way */
+ summary_tags =3D 0;
+ fp_tags =3D tmp.env[FP_ENV_TAG];
+ for (r =3D 0; r < 8; r++) {
+ if ( ((fp_tags >> (2*r)) & 3) !=3D 3 )
+ summary_tags |=3D (1 << r);
+ }
+ addrC[4] =3D toUChar(summary_tags); /* FTW: tag summary byte */
+ addrC[5] =3D 0; /* pad */
+
+ /* FOP: faulting fpu opcode. From experimentation, the real CPU
+ does not write this field. (?!) */
+ addrS[3] =3D 0; /* BOGUS */
+
+ /* RIP (Last x87 instruction pointer). From experimentation, the
+ real CPU does not write this field. (?!) */
+ addrS[4] =3D 0; /* BOGUS */
+ addrS[5] =3D 0; /* BOGUS */
+ addrS[6] =3D 0; /* BOGUS */
+ addrS[7] =3D 0; /* BOGUS */
+
+ /* RDP (Last x87 data pointer). From experimentation, the real CPU
+ does not write this field. (?!) */
+ addrS[8] =3D 0; /* BOGUS */
+ addrS[9] =3D 0; /* BOGUS */
+ addrS[10] =3D 0; /* BOGUS */
+ addrS[11] =3D 0; /* BOGUS */
+
+ addrS[12] =3D toUShort(mxcsr); /* MXCSR */
+ addrS[13] =3D toUShort(mxcsr >> 16);
+
+ addrS[14] =3D 0xFFFF; /* MXCSR mask (lo16) */
+ addrS[15] =3D 0x0000; /* MXCSR mask (hi16) */
+
+ /* Copy in the FP registers, in ST order. */
+ for (stno =3D 0; stno < 8; stno++) {
+ srcS =3D (UShort*)(&tmp.reg[10*stno]);
+ dstS =3D (UShort*)(&addrS[16 + 8*stno]);
+ dstS[0] =3D srcS[0];
+ dstS[1] =3D srcS[1];
+ dstS[2] =3D srcS[2];
+ dstS[3] =3D srcS[3];
+ dstS[4] =3D srcS[4];
+ dstS[5] =3D 0;
+ dstS[6] =3D 0;
+ dstS[7] =3D 0;
+ }
+
+ /* That's the first 160 bytes of the image done. Now only %xmm0
+ .. %xmm15 remain to be copied. If the host is big-endian, these
+ need to be byte-swapped. */
+ vassert(host_is_little_endian());
+
+# define COPY_U128(_dst,_src) \
+ do { _dst[0] =3D _src[0]; _dst[1] =3D _src[1]; \
+ _dst[2] =3D _src[2]; _dst[3] =3D _src[3]; } \
+ while (0)
+
+ COPY_U128( xmm[0], gst->guest_XMM0 );
+ COPY_U128( xmm[1], gst->guest_XMM1 );
+ COPY_U128( xmm[2], gst->guest_XMM2 );
+ COPY_U128( xmm[3], gst->guest_XMM3 );
+ COPY_U128( xmm[4], gst->guest_XMM4 );
+ COPY_U128( xmm[5], gst->guest_XMM5 );
+ COPY_U128( xmm[6], gst->guest_XMM6 );
+ COPY_U128( xmm[7], gst->guest_XMM7 );
+ COPY_U128( xmm[8], gst->guest_XMM8 );
+ COPY_U128( xmm[9], gst->guest_XMM9 );
+ COPY_U128( xmm[10], gst->guest_XMM10 );
+ COPY_U128( xmm[11], gst->guest_XMM11 );
+ COPY_U128( xmm[12], gst->guest_XMM12 );
+ COPY_U128( xmm[13], gst->guest_XMM13 );
+ COPY_U128( xmm[14], gst->guest_XMM14 );
+ COPY_U128( xmm[15], gst->guest_XMM15 );
+
+# undef COPY_U128
+}
+
+
/* DIRTY HELPER (writes guest state) */
/* Initialise the x87 FPU state as per 'finit'. */
void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* gst )
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-01-10 05:13:42 U=
TC (rev 1723)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-01-10 05:22:03 U=
TC (rev 1724)
@@ -8415,90 +8415,87 @@
=20
insn =3D (UChar*)&guest_code[delta];
=20
-//.. /* Treat fxsave specially. It should be doable even on an SSE0
-//.. (Pentium-II class) CPU. Hence be prepared to handle it on
-//.. any subarchitecture variant.
-//.. */
-//..=20
-//.. /* 0F AE /0 =3D FXSAVE m512 -- write x87 and SSE state to memory=
*/
-//.. if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
-//.. && !epartIsReg(insn[2]) && gregOfRM(insn[2]) =3D=3D 0) {
-//.. modrm =3D getUChar(delta+2);
-//.. vassert(sz =3D=3D 4);
-//.. vassert(!epartIsReg(modrm));
-//..=20
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//..=20
-//.. DIP("fxsave %s\n", dis_buf);
-//..=20
-//.. /* Uses dirty helper:=20
-//.. void x86g_do_FXSAVE ( VexGuestX86State*, UInt ) */
-//.. IRDirty* d =3D unsafeIRDirty_0_N (=20
-//.. 0/*regparms*/,=20
-//.. "x86g_dirtyhelper_FXSAVE",=20
-//.. &x86g_dirtyhelper_FXSAVE,
-//.. mkIRExprVec_1( mkexpr(addr) )
-//.. );
-//.. d->needsBBP =3D True;
-//..=20
-//.. /* declare we're writing memory */
-//.. d->mFx =3D Ifx_Write;
-//.. d->mAddr =3D mkexpr(addr);
-//.. d->mSize =3D 512;
-//..=20
-//.. /* declare we're reading guest state */
-//.. d->nFxState =3D 7;
-//..=20
-//.. d->fxState[0].fx =3D Ifx_Read;
-//.. d->fxState[0].offset =3D OFFB_FTOP;
-//.. d->fxState[0].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[1].fx =3D Ifx_Read;
-//.. d->fxState[1].offset =3D OFFB_FPREGS;
-//.. d->fxState[1].size =3D 8 * sizeof(ULong);
-//..=20
-//.. d->fxState[2].fx =3D Ifx_Read;
-//.. d->fxState[2].offset =3D OFFB_FPTAGS;
-//.. d->fxState[2].size =3D 8 * sizeof(UChar);
-//..=20
-//.. d->fxState[3].fx =3D Ifx_Read;
-//.. d->fxState[3].offset =3D OFFB_FPROUND;
-//.. d->fxState[3].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[4].fx =3D Ifx_Read;
-//.. d->fxState[4].offset =3D OFFB_FC3210;
-//.. d->fxState[4].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[5].fx =3D Ifx_Read;
-//.. d->fxState[5].offset =3D OFFB_XMM0;
-//.. d->fxState[5].size =3D 8 * sizeof(U128);
-//..=20
-//.. d->fxState[6].fx =3D Ifx_Read;
-//.. d->fxState[6].offset =3D OFFB_SSEROUND;
-//.. d->fxState[6].size =3D sizeof(UInt);
-//..=20
-//.. /* Be paranoid ... this assertion tries to ensure the 8 %xmm
-//.. images are packed back-to-back. If not, the value of
-//.. d->fxState[5].size is wrong. */
-//.. vassert(16 =3D=3D sizeof(U128));
-//.. vassert(OFFB_XMM7 =3D=3D (OFFB_XMM0 + 7 * 16));
-//..=20
-//.. stmt( IRStmt_Dirty(d) );
-//..=20
-//.. goto decode_success;
-//.. }
-//..=20
-//.. /* ------ SSE decoder main ------ */
-//..=20
-//.. /* Skip parts of the decoder which don't apply given the stated
-//.. guest subarchitecture. */
-//.. if (subarch =3D=3D VexSubArchX86_sse0)
-//.. goto after_sse_decoders;
-//.. =20
-//.. /* Otherwise we must be doing sse1 or sse2, so we can at least t=
ry
-//.. for SSE1 here. */
+ /* FXSAVE is spuriously at the start here only because it is
+ thusly placed in guest-x86/toIR.c. */
=20
+ /* 0F AE /0 =3D FXSAVE m512 -- write x87 and SSE state to memory.
+ Note that REX.W 0F AE /0 writes a slightly different format and
+ we don't handle that here. */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
+ && !epartIsReg(insn[2]) && gregOfRexRM(pfx,insn[2]) =3D=3D 0) {
+ IRDirty* d;
+ modrm =3D getUChar(delta+2);
+ vassert(sz =3D=3D 4);
+ vassert(!epartIsReg(modrm));
+ /* REX.W must not be set. That should be assured us by sz =3D=3D =
4
+ above. */
+ vassert(!(pfx & PFX_REXW));
+
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+
+ DIP("fxsave %s\n", dis_buf);
+
+ /* Uses dirty helper:=20
+ void amd64g_do_FXSAVE ( VexGuestAMD64State*, UInt ) */
+ d =3D unsafeIRDirty_0_N (=20
+ 0/*regparms*/,=20
+ "amd64g_dirtyhelper_FXSAVE",=20
+ &amd64g_dirtyhelper_FXSAVE,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->needsBBP =3D True;
+
+ /* declare we're writing memory */
+ d->mFx =3D Ifx_Write;
+ d->mAddr =3D mkexpr(addr);
+ d->mSize =3D 512;
+
+ /* declare we're reading guest state */
+ d->nFxState =3D 7;
+
+ d->fxState[0].fx =3D Ifx_Read;
+ d->fxState[0].offset =3D OFFB_FTOP;
+ d->fxState[0].size =3D sizeof(UInt);
+
+ d->fxState[1].fx =3D Ifx_Read;
+ d->fxState[1].offset =3D OFFB_FPREGS;
+ d->fxState[1].size =3D 8 * sizeof(ULong);
+
+ d->fxState[2].fx =3D Ifx_Read;
+ d->fxState[2].offset =3D OFFB_FPTAGS;
+ d->fxState[2].size =3D 8 * sizeof(UChar);
+
+ d->fxState[3].fx =3D Ifx_Read;
+ d->fxState[3].offset =3D OFFB_FPROUND;
+ d->fxState[3].size =3D sizeof(ULong);
+
+ d->fxState[4].fx =3D Ifx_Read;
+ d->fxState[4].offset =3D OFFB_FC3210;
+ d->fxState[4].size =3D sizeof(ULong);
+
+ d->fxState[5].fx =3D Ifx_Read;
+ d->fxState[5].offset =3D OFFB_XMM0;
+ d->fxState[5].size =3D 16 * sizeof(U128);
+
+ d->fxState[6].fx =3D Ifx_Read;
+ d->fxState[6].offset =3D OFFB_SSEROUND;
+ d->fxState[6].size =3D sizeof(ULong);
+
+ /* Be paranoid ... this assertion tries to ensure the 16 %xmm
+ images are packed back-to-back. If not, the value of
+ d->fxState[5].size is wrong. */
+ vassert(16 =3D=3D sizeof(U128));
+ vassert(OFFB_XMM15 =3D=3D (OFFB_XMM0 + 15 * 16));
+
+ stmt( IRStmt_Dirty(d) );
+
+ goto decode_success;
+ }
+
+ /* ------ SSE decoder main ------ */
+
/* 0F 58 =3D ADDPS -- add 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
&& insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
|
Author: sewardj
Date: 2007-01-10 05:13:42 +0000 (Wed, 10 Jan 2007)
New Revision: 1723
Log:
Update copyright dates.
Modified:
branches/VEX_3_2_BRANCH/LICENSE.README
branches/VEX_3_2_BRANCH/auxprogs/genoffsets.c
branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-arm/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-arm/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-arm/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.c
branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.h
branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.c
branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.h
branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
branches/VEX_3_2_BRANCH/priv/guest-x86/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.h
branches/VEX_3_2_BRANCH/priv/host-amd64/isel.c
branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.h
branches/VEX_3_2_BRANCH/priv/host-arm/isel.c
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.c
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.h
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h
branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c
branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.h
branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c
branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c
branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.h
branches/VEX_3_2_BRANCH/priv/host-x86/isel.c
branches/VEX_3_2_BRANCH/priv/ir/irdefs.c
branches/VEX_3_2_BRANCH/priv/ir/irmatch.c
branches/VEX_3_2_BRANCH/priv/ir/irmatch.h
branches/VEX_3_2_BRANCH/priv/ir/iropt.c
branches/VEX_3_2_BRANCH/priv/ir/iropt.h
branches/VEX_3_2_BRANCH/priv/main/vex_globals.c
branches/VEX_3_2_BRANCH/priv/main/vex_globals.h
branches/VEX_3_2_BRANCH/priv/main/vex_main.c
branches/VEX_3_2_BRANCH/priv/main/vex_util.c
branches/VEX_3_2_BRANCH/priv/main/vex_util.h
branches/VEX_3_2_BRANCH/pub/libvex.h
branches/VEX_3_2_BRANCH/pub/libvex_basictypes.h
branches/VEX_3_2_BRANCH/pub/libvex_emwarn.h
branches/VEX_3_2_BRANCH/pub/libvex_guest_amd64.h
branches/VEX_3_2_BRANCH/pub/libvex_guest_arm.h
branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc32.h
branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc64.h
branches/VEX_3_2_BRANCH/pub/libvex_guest_x86.h
branches/VEX_3_2_BRANCH/pub/libvex_ir.h
branches/VEX_3_2_BRANCH/pub/libvex_trc_values.h
branches/VEX_3_2_BRANCH/test_main.c
Modified: branches/VEX_3_2_BRANCH/LICENSE.README
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/LICENSE.README 2007-01-10 04:59:33 UTC (rev 1=
722)
+++ branches/VEX_3_2_BRANCH/LICENSE.README 2007-01-10 05:13:42 UTC (rev 1=
723)
@@ -2,7 +2,7 @@
This directory and its children contain LibVEX, a library for dynamic
binary instrumentation and translation.
=20
-Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/auxprogs/genoffsets.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/auxprogs/genoffsets.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/auxprogs/genoffsets.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h 2007-01-10 04:59:33 =
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/gdefs.h 2007-01-10 05:13:42 =
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2007-01-10 04:59:=
33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/ghelpers.c 2007-01-10 05:13:=
42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-arm/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-arm/gdefs.h 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-arm/gdefs.h 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-arm/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-arm/ghelpers.c 2007-01-10 04:59:33=
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-arm/ghelpers.c 2007-01-10 05:13:42=
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-arm/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-arm/toIR.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-arm/toIR.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.c 2007-01-10 04:5=
9:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.c 2007-01-10 05:1=
3:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.h 2007-01-10 04:5=
9:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-generic/bb_to_IR.h 2007-01-10 05:1=
3:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.c 2007-01-10=
04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.c 2007-01-10=
05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.h 2007-01-10=
04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-generic/g_generic_x87.h 2007-01-10=
05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c 2007-01-10 04:59:33=
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c 2007-01-10 05:13:42=
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/gdefs.h 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/gdefs.h 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2007-01-10 04:59:33=
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2007-01-10 05:13:42=
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.c 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.h 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-amd64/hdefs.h 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-amd64/isel.c 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-amd64/isel.c 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.h 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-arm/hdefs.h 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-arm/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-arm/isel.c 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-arm/isel.c 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.c 2007-01-10=
04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.c 2007-01-10=
05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.h 2007-01-10=
04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_regs.h 2007-01-10=
05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c 2007-01-=
10 04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c 2007-01-=
10 05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h 2007-01-=
10 04:59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h 2007-01-=
10 05:13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c 2007-01-10 04:=
59:33 UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c 2007-01-10 05:=
13:42 UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.h 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.h 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/isel.c 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.c 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.h 2007-01-10 04:59:33 UTC=
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-x86/hdefs.h 2007-01-10 05:13:42 UTC=
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-x86/isel.c 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/host-x86/isel.c 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/irdefs.c 2007-01-10 04:59:33 UTC (rev=
1722)
+++ branches/VEX_3_2_BRANCH/priv/ir/irdefs.c 2007-01-10 05:13:42 UTC (rev=
1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/irmatch.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/irmatch.c 2007-01-10 04:59:33 UTC (re=
v 1722)
+++ branches/VEX_3_2_BRANCH/priv/ir/irmatch.c 2007-01-10 05:13:42 UTC (re=
v 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/irmatch.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/irmatch.h 2007-01-10 04:59:33 UTC (re=
v 1722)
+++ branches/VEX_3_2_BRANCH/priv/ir/irmatch.h 2007-01-10 05:13:42 UTC (re=
v 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/iropt.c 2007-01-10 04:59:33 UTC (rev =
1722)
+++ branches/VEX_3_2_BRANCH/priv/ir/iropt.c 2007-01-10 05:13:42 UTC (rev =
1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/iropt.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/iropt.h 2007-01-10 04:59:33 UTC (rev =
1722)
+++ branches/VEX_3_2_BRANCH/priv/ir/iropt.h 2007-01-10 05:13:42 UTC (rev =
1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/main/vex_globals.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/main/vex_globals.c 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/main/vex_globals.c 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/main/vex_globals.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/main/vex_globals.h 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/main/vex_globals.h 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/main/vex_main.c 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/main/vex_main.c 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/main/vex_util.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/main/vex_util.c 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/main/vex_util.c 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/priv/main/vex_util.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/main/vex_util.h 2007-01-10 04:59:33 UTC =
(rev 1722)
+++ branches/VEX_3_2_BRANCH/priv/main/vex_util.h 2007-01-10 05:13:42 UTC =
(rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex.h 2007-01-10 04:59:33 UTC (rev 172=
2)
+++ branches/VEX_3_2_BRANCH/pub/libvex.h 2007-01-10 05:13:42 UTC (rev 172=
3)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_basictypes.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_basictypes.h 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_basictypes.h 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_emwarn.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_emwarn.h 2007-01-10 04:59:33 UTC (=
rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_emwarn.h 2007-01-10 05:13:42 UTC (=
rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_guest_amd64.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_guest_amd64.h 2007-01-10 04:59:33 =
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_guest_amd64.h 2007-01-10 05:13:42 =
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_guest_arm.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_guest_arm.h 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_guest_arm.h 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc32.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc32.h 2007-01-10 04:59:33 =
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc32.h 2007-01-10 05:13:42 =
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc64.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc64.h 2007-01-10 04:59:33 =
UTC (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_guest_ppc64.h 2007-01-10 05:13:42 =
UTC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_guest_x86.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_guest_x86.h 2007-01-10 04:59:33 UT=
C (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_guest_x86.h 2007-01-10 05:13:42 UT=
C (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2007-01-10 04:59:33 UTC (rev =
1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2007-01-10 05:13:42 UTC (rev =
1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/pub/libvex_trc_values.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_trc_values.h 2007-01-10 04:59:33 U=
TC (rev 1722)
+++ branches/VEX_3_2_BRANCH/pub/libvex_trc_values.h 2007-01-10 05:13:42 U=
TC (rev 1723)
@@ -10,7 +10,7 @@
This file is part of LibVEX, a library for dynamic binary
instrumentation and translation.
=20
- Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved.
=20
This library is made available under a dual licensing scheme.
=20
Modified: branches/VEX_3_2_BRANCH/test_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/test_main.c 2007-01-10 04:59:33 UTC (rev 1722=
)
+++ branches/VEX_3_2_BRANCH/test_main.c 2007-01-10 05:13:42 UTC (rev 1723=
)
@@ -417,7 +417,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
=20
- Copyright (C) 2000-2006 Julian Seward=20
+ Copyright (C) 2000-2007 Julian Seward=20
js...@ac...
=20
This program is free software; you can redistribute it and/or
|
|
From: <js...@ac...> - 2007-01-10 05:13:45
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2007-01-10 04:30:01 GMT Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 250 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <sv...@va...> - 2007-01-10 04:59:37
|
Author: sewardj
Date: 2007-01-10 04:59:33 +0000 (Wed, 10 Jan 2007)
New Revision: 1722
Log:
Implement FXSAVE on amd64. Mysteriously my Athlon64 does not seem to
write all the fields that the AMD documentation says it should: it
skips ROP, RIP and RDP, so vex's implementation writes zeroes there.
Modified:
trunk/priv/guest-amd64/gdefs.h
trunk/priv/guest-amd64/ghelpers.c
trunk/priv/guest-amd64/toIR.c
Modified: trunk/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/gdefs.h 2007-01-09 15:20:07 UTC (rev 1721)
+++ trunk/priv/guest-amd64/gdefs.h 2007-01-10 04:59:33 UTC (rev 1722)
@@ -150,6 +150,8 @@
=20
extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
=20
+extern void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State*, HWord );
+
extern ULong amd64g_dirtyhelper_RDTSC ( void );
=20
//extern void amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
@@ -166,7 +168,6 @@
//extern VexEmWarn=20
// amd64g_dirtyhelper_FLDENV ( VexGuestAMD64State*, HWord );
=20
-//extern void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State*, HWord );
=20
=20
/*---------------------------------------------------------*/
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2007-01-09 15:20:07 UTC (rev 1721)
+++ trunk/priv/guest-amd64/ghelpers.c 2007-01-10 04:59:33 UTC (rev 1722)
@@ -1391,6 +1391,162 @@
}
=20
=20
+/* Create an x87 FPU state from the guest state, as close as
+ we can approximate it. */
+static
+void do_get_x87 ( /*IN*/VexGuestAMD64State* vex_state,
+ /*OUT*/UChar* x87_state )
+{
+ Int i, stno, preg;
+ UInt tagw;
+ ULong* vexRegs =3D (ULong*)(&vex_state->guest_FPREG[0]);
+ UChar* vexTags =3D (UChar*)(&vex_state->guest_FPTAG[0]);
+ Fpu_State* x87 =3D (Fpu_State*)x87_state;
+ UInt ftop =3D vex_state->guest_FTOP;
+ UInt c3210 =3D vex_state->guest_FC3210;
+
+ for (i =3D 0; i < 14; i++)
+ x87->env[i] =3D 0;
+
+ x87->env[1] =3D x87->env[3] =3D x87->env[5] =3D x87->env[13] =3D 0xFF=
FF;
+ x87->env[FP_ENV_STAT]=20
+ =3D toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
+ x87->env[FP_ENV_CTRL]=20
+ =3D toUShort(amd64g_create_fpucw( vex_state->guest_FPROUND ));
+
+ /* Dump the register stack in ST order. */
+ tagw =3D 0;
+ for (stno =3D 0; stno < 8; stno++) {
+ preg =3D (stno + ftop) & 7;
+ if (vexTags[preg] =3D=3D 0) {
+ /* register is empty */
+ tagw |=3D (3 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],=20
+ &x87->reg[10*stno] );
+ } else {
+ /* register is full. */
+ tagw |=3D (0 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],=20
+ &x87->reg[10*stno] );
+ }
+ }
+ x87->env[FP_ENV_TAG] =3D toUShort(tagw);
+}
+
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (reads guest state, writes guest mem) */
+/* NOTE: only handles 32-bit format (no REX.W on the insn) */
+void amd64g_dirtyhelper_FXSAVE ( VexGuestAMD64State* gst, HWord addr )
+{
+ /* Derived from values obtained from
+ vendor_id : AuthenticAMD
+ cpu family : 15
+ model : 12
+ model name : AMD Athlon(tm) 64 Processor 3200+
+ stepping : 0
+ cpu MHz : 2200.000
+ cache size : 512 KB
+ */
+ /* Somewhat roundabout, but at least it's simple. */
+ Fpu_State tmp;
+ UShort* addrS =3D (UShort*)addr;
+ UChar* addrC =3D (UChar*)addr;
+ U128* xmm =3D (U128*)(addr + 160);
+ UInt mxcsr;
+ UShort fp_tags;
+ UInt summary_tags;
+ Int r, stno;
+ UShort *srcS, *dstS;
+
+ do_get_x87( gst, (UChar*)&tmp );
+ mxcsr =3D amd64g_create_mxcsr( gst->guest_SSEROUND );
+
+ /* Now build the proper fxsave image from the x87 image we just
+ made. */
+
+ addrS[0] =3D tmp.env[FP_ENV_CTRL]; /* FCW: fpu control word */
+ addrS[1] =3D tmp.env[FP_ENV_STAT]; /* FCW: fpu status word */
+
+ /* set addrS[2] in an endian-independent way */
+ summary_tags =3D 0;
+ fp_tags =3D tmp.env[FP_ENV_TAG];
+ for (r =3D 0; r < 8; r++) {
+ if ( ((fp_tags >> (2*r)) & 3) !=3D 3 )
+ summary_tags |=3D (1 << r);
+ }
+ addrC[4] =3D toUChar(summary_tags); /* FTW: tag summary byte */
+ addrC[5] =3D 0; /* pad */
+
+ /* FOP: faulting fpu opcode. From experimentation, the real CPU
+ does not write this field. (?!) */
+ addrS[3] =3D 0; /* BOGUS */
+
+ /* RIP (Last x87 instruction pointer). From experimentation, the
+ real CPU does not write this field. (?!) */
+ addrS[4] =3D 0; /* BOGUS */
+ addrS[5] =3D 0; /* BOGUS */
+ addrS[6] =3D 0; /* BOGUS */
+ addrS[7] =3D 0; /* BOGUS */
+
+ /* RDP (Last x87 data pointer). From experimentation, the real CPU
+ does not write this field. (?!) */
+ addrS[8] =3D 0; /* BOGUS */
+ addrS[9] =3D 0; /* BOGUS */
+ addrS[10] =3D 0; /* BOGUS */
+ addrS[11] =3D 0; /* BOGUS */
+
+ addrS[12] =3D toUShort(mxcsr); /* MXCSR */
+ addrS[13] =3D toUShort(mxcsr >> 16);
+
+ addrS[14] =3D 0xFFFF; /* MXCSR mask (lo16) */
+ addrS[15] =3D 0x0000; /* MXCSR mask (hi16) */
+
+ /* Copy in the FP registers, in ST order. */
+ for (stno =3D 0; stno < 8; stno++) {
+ srcS =3D (UShort*)(&tmp.reg[10*stno]);
+ dstS =3D (UShort*)(&addrS[16 + 8*stno]);
+ dstS[0] =3D srcS[0];
+ dstS[1] =3D srcS[1];
+ dstS[2] =3D srcS[2];
+ dstS[3] =3D srcS[3];
+ dstS[4] =3D srcS[4];
+ dstS[5] =3D 0;
+ dstS[6] =3D 0;
+ dstS[7] =3D 0;
+ }
+
+ /* That's the first 160 bytes of the image done. Now only %xmm0
+ .. %xmm15 remain to be copied. If the host is big-endian, these
+ need to be byte-swapped. */
+ vassert(host_is_little_endian());
+
+# define COPY_U128(_dst,_src) \
+ do { _dst[0] =3D _src[0]; _dst[1] =3D _src[1]; \
+ _dst[2] =3D _src[2]; _dst[3] =3D _src[3]; } \
+ while (0)
+
+ COPY_U128( xmm[0], gst->guest_XMM0 );
+ COPY_U128( xmm[1], gst->guest_XMM1 );
+ COPY_U128( xmm[2], gst->guest_XMM2 );
+ COPY_U128( xmm[3], gst->guest_XMM3 );
+ COPY_U128( xmm[4], gst->guest_XMM4 );
+ COPY_U128( xmm[5], gst->guest_XMM5 );
+ COPY_U128( xmm[6], gst->guest_XMM6 );
+ COPY_U128( xmm[7], gst->guest_XMM7 );
+ COPY_U128( xmm[8], gst->guest_XMM8 );
+ COPY_U128( xmm[9], gst->guest_XMM9 );
+ COPY_U128( xmm[10], gst->guest_XMM10 );
+ COPY_U128( xmm[11], gst->guest_XMM11 );
+ COPY_U128( xmm[12], gst->guest_XMM12 );
+ COPY_U128( xmm[13], gst->guest_XMM13 );
+ COPY_U128( xmm[14], gst->guest_XMM14 );
+ COPY_U128( xmm[15], gst->guest_XMM15 );
+
+# undef COPY_U128
+}
+
+
/* DIRTY HELPER (writes guest state) */
/* Initialise the x87 FPU state as per 'finit'. */
void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* gst )
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2007-01-09 15:20:07 UTC (rev 1721)
+++ trunk/priv/guest-amd64/toIR.c 2007-01-10 04:59:33 UTC (rev 1722)
@@ -8427,90 +8427,87 @@
=20
insn =3D (UChar*)&guest_code[delta];
=20
-//.. /* Treat fxsave specially. It should be doable even on an SSE0
-//.. (Pentium-II class) CPU. Hence be prepared to handle it on
-//.. any subarchitecture variant.
-//.. */
-//..=20
-//.. /* 0F AE /0 =3D FXSAVE m512 -- write x87 and SSE state to memory=
*/
-//.. if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
-//.. && !epartIsReg(insn[2]) && gregOfRM(insn[2]) =3D=3D 0) {
-//.. modrm =3D getUChar(delta+2);
-//.. vassert(sz =3D=3D 4);
-//.. vassert(!epartIsReg(modrm));
-//..=20
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//..=20
-//.. DIP("fxsave %s\n", dis_buf);
-//..=20
-//.. /* Uses dirty helper:=20
-//.. void x86g_do_FXSAVE ( VexGuestX86State*, UInt ) */
-//.. IRDirty* d =3D unsafeIRDirty_0_N (=20
-//.. 0/*regparms*/,=20
-//.. "x86g_dirtyhelper_FXSAVE",=20
-//.. &x86g_dirtyhelper_FXSAVE,
-//.. mkIRExprVec_1( mkexpr(addr) )
-//.. );
-//.. d->needsBBP =3D True;
-//..=20
-//.. /* declare we're writing memory */
-//.. d->mFx =3D Ifx_Write;
-//.. d->mAddr =3D mkexpr(addr);
-//.. d->mSize =3D 512;
-//..=20
-//.. /* declare we're reading guest state */
-//.. d->nFxState =3D 7;
-//..=20
-//.. d->fxState[0].fx =3D Ifx_Read;
-//.. d->fxState[0].offset =3D OFFB_FTOP;
-//.. d->fxState[0].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[1].fx =3D Ifx_Read;
-//.. d->fxState[1].offset =3D OFFB_FPREGS;
-//.. d->fxState[1].size =3D 8 * sizeof(ULong);
-//..=20
-//.. d->fxState[2].fx =3D Ifx_Read;
-//.. d->fxState[2].offset =3D OFFB_FPTAGS;
-//.. d->fxState[2].size =3D 8 * sizeof(UChar);
-//..=20
-//.. d->fxState[3].fx =3D Ifx_Read;
-//.. d->fxState[3].offset =3D OFFB_FPROUND;
-//.. d->fxState[3].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[4].fx =3D Ifx_Read;
-//.. d->fxState[4].offset =3D OFFB_FC3210;
-//.. d->fxState[4].size =3D sizeof(UInt);
-//..=20
-//.. d->fxState[5].fx =3D Ifx_Read;
-//.. d->fxState[5].offset =3D OFFB_XMM0;
-//.. d->fxState[5].size =3D 8 * sizeof(U128);
-//..=20
-//.. d->fxState[6].fx =3D Ifx_Read;
-//.. d->fxState[6].offset =3D OFFB_SSEROUND;
-//.. d->fxState[6].size =3D sizeof(UInt);
-//..=20
-//.. /* Be paranoid ... this assertion tries to ensure the 8 %xmm
-//.. images are packed back-to-back. If not, the value of
-//.. d->fxState[5].size is wrong. */
-//.. vassert(16 =3D=3D sizeof(U128));
-//.. vassert(OFFB_XMM7 =3D=3D (OFFB_XMM0 + 7 * 16));
-//..=20
-//.. stmt( IRStmt_Dirty(d) );
-//..=20
-//.. goto decode_success;
-//.. }
-//..=20
-//.. /* ------ SSE decoder main ------ */
-//..=20
-//.. /* Skip parts of the decoder which don't apply given the stated
-//.. guest subarchitecture. */
-//.. if (subarch =3D=3D VexSubArchX86_sse0)
-//.. goto after_sse_decoders;
-//.. =20
-//.. /* Otherwise we must be doing sse1 or sse2, so we can at least t=
ry
-//.. for SSE1 here. */
+ /* FXSAVE is spuriously at the start here only because it is
+ thusly placed in guest-x86/toIR.c. */
=20
+ /* 0F AE /0 =3D FXSAVE m512 -- write x87 and SSE state to memory.
+ Note that REX.W 0F AE /0 writes a slightly different format and
+ we don't handle that here. */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
+ && !epartIsReg(insn[2]) && gregOfRexRM(pfx,insn[2]) =3D=3D 0) {
+ IRDirty* d;
+ modrm =3D getUChar(delta+2);
+ vassert(sz =3D=3D 4);
+ vassert(!epartIsReg(modrm));
+ /* REX.W must not be set. That should be assured us by sz =3D=3D =
4
+ above. */
+ vassert(!(pfx & PFX_REXW));
+
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+
+ DIP("fxsave %s\n", dis_buf);
+
+ /* Uses dirty helper:=20
+ void amd64g_do_FXSAVE ( VexGuestAMD64State*, UInt ) */
+ d =3D unsafeIRDirty_0_N (=20
+ 0/*regparms*/,=20
+ "amd64g_dirtyhelper_FXSAVE",=20
+ &amd64g_dirtyhelper_FXSAVE,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->needsBBP =3D True;
+
+ /* declare we're writing memory */
+ d->mFx =3D Ifx_Write;
+ d->mAddr =3D mkexpr(addr);
+ d->mSize =3D 512;
+
+ /* declare we're reading guest state */
+ d->nFxState =3D 7;
+
+ d->fxState[0].fx =3D Ifx_Read;
+ d->fxState[0].offset =3D OFFB_FTOP;
+ d->fxState[0].size =3D sizeof(UInt);
+
+ d->fxState[1].fx =3D Ifx_Read;
+ d->fxState[1].offset =3D OFFB_FPREGS;
+ d->fxState[1].size =3D 8 * sizeof(ULong);
+
+ d->fxState[2].fx =3D Ifx_Read;
+ d->fxState[2].offset =3D OFFB_FPTAGS;
+ d->fxState[2].size =3D 8 * sizeof(UChar);
+
+ d->fxState[3].fx =3D Ifx_Read;
+ d->fxState[3].offset =3D OFFB_FPROUND;
+ d->fxState[3].size =3D sizeof(ULong);
+
+ d->fxState[4].fx =3D Ifx_Read;
+ d->fxState[4].offset =3D OFFB_FC3210;
+ d->fxState[4].size =3D sizeof(ULong);
+
+ d->fxState[5].fx =3D Ifx_Read;
+ d->fxState[5].offset =3D OFFB_XMM0;
+ d->fxState[5].size =3D 16 * sizeof(U128);
+
+ d->fxState[6].fx =3D Ifx_Read;
+ d->fxState[6].offset =3D OFFB_SSEROUND;
+ d->fxState[6].size =3D sizeof(ULong);
+
+ /* Be paranoid ... this assertion tries to ensure the 16 %xmm
+ images are packed back-to-back. If not, the value of
+ d->fxState[5].size is wrong. */
+ vassert(16 =3D=3D sizeof(U128));
+ vassert(OFFB_XMM15 =3D=3D (OFFB_XMM0 + 15 * 16));
+
+ stmt( IRStmt_Dirty(d) );
+
+ goto decode_success;
+ }
+
+ /* ------ SSE decoder main ------ */
+
/* 0F 58 =3D ADDPS -- add 32Fx4 from R/M to R */
if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
&& insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
|
|
From: <sv...@va...> - 2007-01-10 04:57:29
|
Author: sewardj
Date: 2007-01-10 04:57:27 +0000 (Wed, 10 Jan 2007)
New Revision: 6499
Log:
Regtest for FXSAVE on amd64.
Added:
trunk/memcheck/tests/amd64/fxsave-amd64.c
trunk/memcheck/tests/amd64/fxsave-amd64.stderr.exp
trunk/memcheck/tests/amd64/fxsave-amd64.stdout.exp
trunk/memcheck/tests/amd64/fxsave-amd64.vgtest
Modified:
trunk/memcheck/tests/amd64/Makefile.am
Modified: trunk/memcheck/tests/amd64/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/Makefile.am 2007-01-09 20:41:41 UTC (rev 6=
498)
+++ trunk/memcheck/tests/amd64/Makefile.am 2007-01-10 04:57:27 UTC (rev 6=
499)
@@ -11,10 +11,11 @@
bt_everything.stderr.exp bt_everything.stdout.exp \
bt_everything.vgtest \
bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \
+ fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \
more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest
=20
-check_PROGRAMS =3D bt_everything bug132146 more_x87_fp sse_memory
+check_PROGRAMS =3D bt_everything bug132146 fxsave-amd64 more_x87_fp sse_=
memory
=20
AM_CPPFLAGS =3D -I$(top_srcdir)/include
AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/inc=
lude
Added: trunk/memcheck/tests/amd64/fxsave-amd64.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/fxsave-amd64.c (re=
v 0)
+++ trunk/memcheck/tests/amd64/fxsave-amd64.c 2007-01-10 04:57:27 UTC (re=
v 6499)
@@ -0,0 +1,79 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+
+const unsigned int vec0[4]
+ =3D { 0x12345678, 0x11223344, 0x55667788, 0x87654321 };
+
+const unsigned int vec1[4]
+ =3D { 0xABCDEF01, 0xAABBCCDD, 0xEEFF0011, 0x10FEDCBA };
+
+/* set up the FP and SSE state, and then dump it. */
+void do_fxsave ( void* p )
+{
+ asm __volatile__("finit");
+ asm __volatile__("fldpi");
+ asm __volatile__("fld1");
+ asm __volatile__("fldln2");
+ asm __volatile__("fldlg2");
+ asm __volatile__("fld %st(3)");
+ asm __volatile__("fld %st(3)");
+ asm __volatile__("fld1");
+ asm __volatile__("movups (%0), %%xmm0" : : "r"(&vec0[0]) : "xmm0" );
+ asm __volatile__("movups (%0), %%xmm1" : : "r"(&vec1[0]) : "xmm1" );
+ asm __volatile__("xorps %xmm2, %xmm2");
+ asm __volatile__("movaps %xmm0, %xmm3");
+ asm __volatile__("movaps %xmm1, %xmm4");
+ asm __volatile__("movaps %xmm2, %xmm5");
+ asm __volatile__("movaps %xmm0, %xmm6");
+ asm __volatile__("movaps %xmm1, %xmm7");
+ asm __volatile__("movaps %xmm1, %xmm8");
+ asm __volatile__("movaps %xmm2, %xmm9");
+ asm __volatile__("movaps %xmm0, %xmm10");
+ asm __volatile__("movaps %xmm1, %xmm11");
+ asm __volatile__("movaps %xmm1, %xmm12");
+ asm __volatile__("movaps %xmm2, %xmm13");
+ asm __volatile__("movaps %xmm0, %xmm14");
+ asm __volatile__("movaps %xmm1, %xmm15");
+ asm __volatile__("fxsave (%0)" : : "r" (p) : "memory" );
+}
+
+int isFPLsbs ( int i )
+{
+ int q;
+ q =3D 32; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 48; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 64; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 80; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 96; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 112; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 128; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ q =3D 144; if (i =3D=3D q || i =3D=3D q+1) return 1;
+ return 0;
+}
+
+int main ( int argc, char** argv )
+{
+ int i, j;
+ unsigned char* buf =3D malloc(512);
+ int xx =3D 1; /* argc > 1;
+ printf("Re-run with any arg to suppress least-significant\n"
+ " 16 bits of FP numbers\n");
+ */
+ for (i =3D 0; i < 512; i++)
+ buf[i] =3D 0x55;
+
+ do_fxsave(buf);
+ for (j =3D 0; j < 512; j++) {
+ i =3D (j & 0xFFF0) + (15 - (j & 0xF));
+ if ((j % 16) =3D=3D 0)
+ printf("%3d ", j);
+ if (xx && isFPLsbs(i))
+ printf("xx ");
+ else
+ printf("%02x ", buf[i]);
+ if (j > 0 && ((j % 16) =3D=3D 15))
+ printf("\n");
+ }
+ return 0;
+}
Added: trunk/memcheck/tests/amd64/fxsave-amd64.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Added: trunk/memcheck/tests/amd64/fxsave-amd64.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/fxsave-amd64.stdout.exp =
(rev 0)
+++ trunk/memcheck/tests/amd64/fxsave-amd64.stdout.exp 2007-01-10 04:57:2=
7 UTC (rev 6499)
@@ -0,0 +1,32 @@
+ 0 00 00 00 00 00 00 00 00 00 00 00 fe 08 00 03 7f=20
+ 16 00 00 ff ff 00 00 1f 80 00 00 00 00 00 00 00 00=20
+ 32 00 00 00 00 00 00 3f ff 80 00 00 00 00 00 xx xx=20
+ 48 00 00 00 00 00 00 3f ff 80 00 00 00 00 00 xx xx=20
+ 64 00 00 00 00 00 00 40 00 c9 0f da a2 21 68 xx xx=20
+ 80 00 00 00 00 00 00 3f fd 9a 20 9a 84 fb cf xx xx=20
+ 96 00 00 00 00 00 00 3f fe b1 72 17 f7 d1 cf xx xx=20
+112 00 00 00 00 00 00 3f ff 80 00 00 00 00 00 xx xx=20
+128 00 00 00 00 00 00 40 00 c9 0f da a2 21 68 xx xx=20
+144 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xx xx=20
+160 87 65 43 21 55 66 77 88 11 22 33 44 12 34 56 78=20
+176 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00=20
+208 87 65 43 21 55 66 77 88 11 22 33 44 12 34 56 78=20
+224 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00=20
+256 87 65 43 21 55 66 77 88 11 22 33 44 12 34 56 78=20
+272 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+288 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00=20
+320 87 65 43 21 55 66 77 88 11 22 33 44 12 34 56 78=20
+336 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+352 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00=20
+384 87 65 43 21 55 66 77 88 11 22 33 44 12 34 56 78=20
+400 10 fe dc ba ee ff 00 11 aa bb cc dd ab cd ef 01=20
+416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
+432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
+448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
+464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
+480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
+496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55=20
Added: trunk/memcheck/tests/amd64/fxsave-amd64.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/amd64/fxsave-amd64.vgtest =
(rev 0)
+++ trunk/memcheck/tests/amd64/fxsave-amd64.vgtest 2007-01-10 04:57:27 UT=
C (rev 6499)
@@ -0,0 +1,2 @@
+prog: fxsave-amd64
+vgopts: -q
|
|
From: Tom H. <to...@co...> - 2007-01-10 03:55:44
|
Nightly build on dunsmere ( athlon, Fedora Core 6 ) started at 2007-01-10 03:30:06 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 252 tests, 5 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
|
From: Tom H. <th...@cy...> - 2007-01-10 03:31:40
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-01-10 03:00:02 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 283 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: Tom H. <th...@cy...> - 2007-01-10 03:24:07
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2007-01-10 03:15:07 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo /tmp/cc9ez6eK.s:4393: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:4513: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:4633: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:4753: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:4873: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:4993: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:5113: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/cc9ez6eK.s:5233: Error: no such instruction: `fisttpq -56(%ebp)' make[5]: *** [insn_sse3.o] Error 1 rm insn_mmx.c insn_sse2.c insn_fpu.c insn_mmxext.c insn_sse.c insn_sse3.c insn_cmov.c insn_basic.c make[5]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests/x86' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests/x86' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/valgrind.29962/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/valgrind.29962/valgrind' make: *** [check] Error 2 ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo /tmp/ccUvLqwx.s:4393: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:4513: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:4633: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:4753: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:4873: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:4993: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:5113: Error: no such instruction: `fisttpq -56(%ebp)' /tmp/ccUvLqwx.s:5233: Error: no such instruction: `fisttpq -56(%ebp)' make[5]: *** [insn_sse3.o] Error 1 rm insn_mmx.c insn_sse2.c insn_fpu.c insn_mmxext.c insn_sse.c insn_sse3.c insn_cmov.c insn_basic.c make[5]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests/x86' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests/x86' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/valgrind.29962/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/valgrind.29962/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/valgrind.29962/valgrind' make: *** [check] Error 2 ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Jan 10 03:19:36 2007 --- new.short Wed Jan 10 03:23:53 2007 *************** *** 7,16 **** Last 20 lines of verbose log follow echo ! /tmp/ccUvLqwx.s:4393: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:4513: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:4633: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:4753: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:4873: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:4993: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:5113: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/ccUvLqwx.s:5233: Error: no such instruction: `fisttpq -56(%ebp)' make[5]: *** [insn_sse3.o] Error 1 --- 7,16 ---- Last 20 lines of verbose log follow echo ! /tmp/cc9ez6eK.s:4393: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:4513: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:4633: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:4753: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:4873: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:4993: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:5113: Error: no such instruction: `fisttpq -56(%ebp)' ! /tmp/cc9ez6eK.s:5233: Error: no such instruction: `fisttpq -56(%ebp)' make[5]: *** [insn_sse3.o] Error 1 |
|
From: Tom H. <th...@cy...> - 2007-01-10 03:23:27
|
Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-01-10 03:10:04 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 281 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 281 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Jan 10 03:16:44 2007 --- new.short Wed Jan 10 03:23:17 2007 *************** *** 8,10 **** ! == 281 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) --- 8,10 ---- ! == 281 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) *************** *** 14,15 **** --- 14,16 ---- none/tests/mremap2 (stdout) + none/tests/pth_detached (stdout) |
|
From: Tom H. <th...@cy...> - 2007-01-10 03:17:23
|
Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-01-10 03:05:04 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 281 tests, 5 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <js...@ac...> - 2007-01-10 01:36:11
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2007-01-10 02:00:02 CET Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 223 tests, 6 stderr failures, 3 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/res_search (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 223 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Jan 10 02:08:18 2007 --- new.short Wed Jan 10 02:17:05 2007 *************** *** 8,10 **** ! == 223 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) --- 8,10 ---- ! == 223 tests, 6 stderr failures, 3 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) *************** *** 17,18 **** --- 17,19 ---- none/tests/mremap2 (stdout) + none/tests/res_search (stdout) |