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From: <sv...@va...> - 2006-12-27 23:59:32
|
Author: sewardj
Date: 2006-12-27 23:59:31 +0000 (Wed, 27 Dec 2006)
New Revision: 1709
Log:
Enable support for altivec prefetches: dss, dst, dstt, dstst, dststt.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-12-27 21:38:35 UTC (rev 1708)
+++ trunk/priv/guest-ppc/toIR.c 2006-12-27 23:59:31 UTC (rev 1709)
@@ -6708,14 +6708,12 @@
case 0x156: // dst (Data Stream Touch, AV p115)
DIP("dst%s r%u,r%u,%d\n", flag_T ? "t" : "",
rA_addr, rB_addr, STRM);
- DIP(" =3D> not implemented\n");
- return False;
+ break;
=20
case 0x176: // dstst (Data Stream Touch for Store, AV p117)
DIP("dstst%s r%u,r%u,%d\n", flag_T ? "t" : "",
rA_addr, rB_addr, STRM);
- DIP(" =3D> not implemented\n");
- return False;
+ break;
=20
case 0x336: // dss (Data Stream Stop, AV p114)
if (rA_addr !=3D 0 || rB_addr !=3D 0) {
@@ -6724,12 +6722,10 @@
}
if (flag_A =3D=3D 0) {
DIP("dss %d\n", STRM);
- DIP(" =3D> not implemented\n");
} else {
DIP("dssall\n");
- DIP(" =3D> not implemented\n");
}
- return False;
+ break;
=20
default:
vex_printf("dis_av_datastream(ppc)(opc2)\n");
|
|
From: <sv...@va...> - 2006-12-27 23:19:14
|
Author: njn
Date: 2006-12-27 23:19:10 +0000 (Wed, 27 Dec 2006)
New Revision: 6449
Log:
Remove dead code.
Modified:
trunk/memcheck/mc_main.c
Modified: trunk/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_main.c 2006-12-27 21:39:18 UTC (rev 6448)
+++ trunk/memcheck/mc_main.c 2006-12-27 23:19:10 UTC (rev 6449)
@@ -3566,7 +3566,6 @@
=20
static Char* mc_get_error_name ( Error* err )
{
- Char* s;
switch (VG_(get_error_kind)(err)) {
case Err_RegParam: return "Param";
case Err_MemParam: return "Param";
@@ -3603,7 +3602,6 @@
}
default: VG_(tool_panic)("get_error_name: unexpected =
type");
}
- VG_(printf)(s);
}
=20
static void mc_print_extra_suppression_info ( Error* err )
|
|
From: <sv...@va...> - 2006-12-27 21:39:20
|
Author: sewardj
Date: 2006-12-27 21:39:18 +0000 (Wed, 27 Dec 2006)
New Revision: 6448
Log:
Merge r6447 (Test lvxl and stvxl.)
Modified:
branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-insns.c
branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-vmx.stdout.exp
Modified: branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-insns.c 2006-12-27 2=
1:22:18 UTC (rev 6447)
+++ branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-insns.c 2006-12-27 2=
1:39:18 UTC (rev 6448)
@@ -3051,11 +3051,17 @@
__asm__ __volatile__ ("lvx 17,14,15");
}
=20
+static void test_lvxl (void)
+{
+ __asm__ __volatile__ ("lvxl 17,14,15");
+}
+
static test_t tests_ald_ops_two[] =3D {
{ &test_lvebx , " lvebx", },
{ &test_lvehx , " lvehx", },
{ &test_lvewx , " lvewx", },
{ &test_lvx , " lvx", },
+ { &test_lvxl , " lvxl", },
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
@@ -3081,11 +3087,17 @@
__asm__ __volatile__ ("stvx 14,15,16");
}
=20
+static void test_stvxl (void)
+{
+ __asm__ __volatile__ ("stvxl 14,15,16");
+}
+
static test_t tests_ast_ops_three[] =3D {
{ &test_stvebx , " stvebx", },
{ &test_stvehx , " stvehx", },
{ &test_stvewx , " stvewx", },
{ &test_stvx , " stvx", },
+ { &test_stvxl , " stvxl", },
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
Modified: branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-vmx.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-vmx.stdout.exp 2006-=
12-27 21:22:18 UTC (rev 6447)
+++ branches/VALGRIND_3_2_BRANCH/none/tests/ppc32/jm-vmx.stdout.exp 2006-=
12-27 21:39:18 UTC (rev 6448)
@@ -1474,6 +1474,13 @@
lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
=20
+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+
Altivec store insns with three register args:
stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01000000 0000=
0000 00000000 00000000 (00000000)
stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01000000 0000=
0008 00000000 00000000 (00000000)
@@ -1503,6 +1510,13 @@
stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
=20
+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+
Altivec floating point arith insns with three args:
Altivec floating point arith insns with two args:
vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff=
02bfffff
@@ -3019,4 +3033,4 @@
vctsxs: ffbfffff ( nan), 18 =3D> 00000000 ( 0.000000e+00)=
(00000000)
vctsxs: ffbfffff ( nan), 27 =3D> 00000000 ( 0.000000e+00)=
(00000000)
=20
-All done. Tested 161 different instructions
+All done. Tested 163 different instructions
|
|
From: <sv...@va...> - 2006-12-27 21:38:41
|
Author: sewardj
Date: 2006-12-27 21:38:35 +0000 (Wed, 27 Dec 2006)
New Revision: 1708
Log:
Merge r1707 (Enable lvxl and stvxl.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 21:21:14 UTC=
(rev 1707)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 21:38:35 UTC=
(rev 1708)
@@ -6862,10 +6862,9 @@
break;
=20
case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
- // XXX: lvxl gives explicit control over cache block replacement
DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
+ break;
=20
default:
vex_printf("dis_av_load(ppc)(opc2)\n");
@@ -6950,12 +6949,9 @@
break;
=20
case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
- // XXX: stvxl can give explicit control over cache block replacemen=
t
DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-// STORE(vS, 16, addr_align( mkexpr(EA), 16 ));
-// break;
+ storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+ break;
=20
default:
vex_printf("dis_av_store(ppc)(opc2)\n");
|
|
From: <sv...@va...> - 2006-12-27 21:22:22
|
Author: sewardj
Date: 2006-12-27 21:22:18 +0000 (Wed, 27 Dec 2006)
New Revision: 6447
Log:
Test lvxl and stvxl.
Modified:
trunk/none/tests/ppc32/jm-insns.c
trunk/none/tests/ppc32/jm-vmx.stdout.exp
Modified: trunk/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-insns.c 2006-12-27 18:40:47 UTC (rev 6446)
+++ trunk/none/tests/ppc32/jm-insns.c 2006-12-27 21:22:18 UTC (rev 6447)
@@ -3051,11 +3051,17 @@
__asm__ __volatile__ ("lvx 17,14,15");
}
=20
+static void test_lvxl (void)
+{
+ __asm__ __volatile__ ("lvxl 17,14,15");
+}
+
static test_t tests_ald_ops_two[] =3D {
{ &test_lvebx , " lvebx", },
{ &test_lvehx , " lvehx", },
{ &test_lvewx , " lvewx", },
{ &test_lvx , " lvx", },
+ { &test_lvxl , " lvxl", },
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
@@ -3081,11 +3087,17 @@
__asm__ __volatile__ ("stvx 14,15,16");
}
=20
+static void test_stvxl (void)
+{
+ __asm__ __volatile__ ("stvxl 14,15,16");
+}
+
static test_t tests_ast_ops_three[] =3D {
{ &test_stvebx , " stvebx", },
{ &test_stvehx , " stvehx", },
{ &test_stvewx , " stvewx", },
{ &test_stvx , " stvx", },
+ { &test_stvxl , " stvxl", },
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
Modified: trunk/none/tests/ppc32/jm-vmx.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-vmx.stdout.exp 2006-12-27 18:40:47 UTC (rev=
6446)
+++ trunk/none/tests/ppc32/jm-vmx.stdout.exp 2006-12-27 21:22:18 UTC (rev=
6447)
@@ -1474,6 +1474,13 @@
lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
=20
+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+
Altivec store insns with three register args:
stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01000000 0000=
0000 00000000 00000000 (00000000)
stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01000000 0000=
0008 00000000 00000000 (00000000)
@@ -1503,6 +1510,13 @@
stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
=20
+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f =3D> 01020304 0506=
0708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff =3D> f1f2f3f4 f5f6=
f7f8 f9fafbfc fefdfeff (00000000)
+
Altivec floating point arith insns with three args:
Altivec floating point arith insns with two args:
vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff=
02bfffff
@@ -3019,4 +3033,4 @@
vctsxs: ffbfffff ( nan), 18 =3D> 00000000 ( 0.000000e+00)=
(00000000)
vctsxs: ffbfffff ( nan), 27 =3D> 00000000 ( 0.000000e+00)=
(00000000)
=20
-All done. Tested 161 different instructions
+All done. Tested 163 different instructions
|
|
From: <sv...@va...> - 2006-12-27 21:21:19
|
Author: sewardj
Date: 2006-12-27 21:21:14 +0000 (Wed, 27 Dec 2006)
New Revision: 1707
Log:
Enable lvxl and stvxl.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-12-27 19:04:45 UTC (rev 1706)
+++ trunk/priv/guest-ppc/toIR.c 2006-12-27 21:21:14 UTC (rev 1707)
@@ -6902,10 +6902,9 @@
break;
=20
case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
- // XXX: lvxl gives explicit control over cache block replacement
DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
+ break;
=20
default:
vex_printf("dis_av_load(ppc)(opc2)\n");
@@ -6990,12 +6989,9 @@
break;
=20
case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
- // XXX: stvxl can give explicit control over cache block replacemen=
t
DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-// STORE(vS, 16, addr_align( mkexpr(EA), 16 ));
-// break;
+ storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+ break;
=20
default:
vex_printf("dis_av_store(ppc)(opc2)\n");
|
|
From: <sv...@va...> - 2006-12-27 19:04:47
|
Author: sewardj
Date: 2006-12-27 19:04:45 +0000 (Wed, 27 Dec 2006)
New Revision: 1706
Log:
Merge r1705 (Implement mfspr 268 and 269. Fixes #139050.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h
branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h 2006-12-27 18:39:46 UT=
C (rev 1705)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/gdefs.h 2006-12-27 19:04:45 UT=
C (rev 1706)
@@ -147,6 +147,8 @@
=20
extern ULong ppcg_dirtyhelper_MFTB ( void );
=20
+extern UInt ppc32g_dirtyhelper_MFSPR_268_269 ( UInt );
+
extern void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_idx, UInt sh,
UInt shift_right );
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c 2006-12-27 18:39:46=
UTC (rev 1705)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/ghelpers.c 2006-12-27 19:04:45=
UTC (rev 1706)
@@ -100,6 +100,24 @@
=20
=20
/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially transparent) */
+UInt ppc32g_dirtyhelper_MFSPR_268_269 ( UInt r269 )
+{
+# if defined(__powerpc__) || defined(_AIX)
+ UInt spr;
+ if (r269) {
+ __asm__ __volatile__("mfspr %0,269" : "=3Db"(spr));
+ } else {
+ __asm__ __volatile__("mfspr %0,268" : "=3Db"(spr));
+ }
+ return spr;
+# else
+ return 0;
+# endif
+}
+
+
+/* CALLED FROM GENERATED CODE */
/* DIRTY HELPER (reads guest state, writes guest mem) */
void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_off, UInt sh, UInt shift_right )
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 18:39:46 UTC=
(rev 1705)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-27 19:04:45 UTC=
(rev 1706)
@@ -5307,6 +5307,28 @@
/* Signed */False) );
break;
=20
+ /* Even a lowly PPC7400 can run the associated helper, so no
+ obvious need for feature testing at this point. */
+ case 268 /* 0x10C */:
+ case 269 /* 0x10D */: {
+ UInt arg =3D SPR=3D=3D268 ? 0 : 1;
+ IRTemp val =3D newTemp(Ity_I32);
+ IRExpr** args =3D mkIRExprVec_1( mkU32(arg) );
+ IRDirty* d =3D unsafeIRDirty_1_N(
+ val,
+ 0/*regparms*/,
+ "ppc32g_dirtyhelper_MFSPR_268_269",
+ fnptr_to_fnentry
+ (&ppc32g_dirtyhelper_MFSPR_268_269),
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg( rD_addr, mkexpr(val) );
+ DIP("mfspr r%u,%u", rD_addr, (UInt)SPR);
+ break;
+ }
+
default:
vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR);
return False;
|
|
From: <sv...@va...> - 2006-12-27 18:40:52
|
Author: sewardj
Date: 2006-12-27 18:40:47 +0000 (Wed, 27 Dec 2006)
New Revision: 6446
Log:
Add regtest for #139050.
Added:
trunk/none/tests/ppc32/bug139050-ppc32.c
trunk/none/tests/ppc32/bug139050-ppc32.stderr.exp
trunk/none/tests/ppc32/bug139050-ppc32.stdout.exp
trunk/none/tests/ppc32/bug139050-ppc32.vgtest
Modified:
trunk/none/tests/ppc32/Makefile.am
Modified: trunk/none/tests/ppc32/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/Makefile.am 2006-12-27 05:21:14 UTC (rev 6445)
+++ trunk/none/tests/ppc32/Makefile.am 2006-12-27 18:40:47 UTC (rev 6446)
@@ -2,6 +2,8 @@
noinst_SCRIPTS =3D filter_stderr
=20
EXTRA_DIST =3D $(noinst_SCRIPTS) \
+ bug139050-ppc32.stdout.exp bug139050-ppc32.stderr.exp \
+ bug139050-ppc32.vgtest \
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
@@ -17,6 +19,7 @@
xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest
=20
check_PROGRAMS =3D \
+ bug139050-ppc32 \
ldstrev lsw jm-insns mftocrf mcrfs round test_fx test_gx \
testVMX twi xlc_dbl_u32
=20
Added: trunk/none/tests/ppc32/bug139050-ppc32.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/bug139050-ppc32.c (rev=
0)
+++ trunk/none/tests/ppc32/bug139050-ppc32.c 2006-12-27 18:40:47 UTC (rev=
6446)
@@ -0,0 +1,34 @@
+
+#include <stdio.h>
+#include <assert.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+=20
+static ULong GetCPU_ClockCyclesSinceStartup(void)=20
+ {=20
+ UInt uTimeBaseLow;=20
+ UInt uTimeBaseHigh;=20
+ UInt uCheck;=20
+ __asm__ __volatile__("1: mfspr %0,269\n\t"=20
+ " mfspr %1,268\n\t"=20
+ " mfspr %2,269\n\t"=20
+ " cmpw %2, %0\n\t"=20
+ " bne 1b"=20
+ : "=3Dr" (uTimeBaseHigh),=20
+ "=3Dr" (uTimeBaseLow),=20
+ "=3Dr" (uCheck)
+ : /*in*/
+ : /*trash*/ "cr0","cr7" );
+
+ return (((ULong)(uTimeBaseHigh) << 32) | uTimeBaseLow);=20
+ }=20
+=20
+ int main(int argc, char** argv)=20
+ {=20
+ ULong cys =3D GetCPU_ClockCyclesSinceStartup();
+ /* implausible that machine has been up less than 4G cycles */
+ assert(cys > (1ULL << 32));
+ printf("success\n");
+ return 0;=20
+ }
Added: trunk/none/tests/ppc32/bug139050-ppc32.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Added: trunk/none/tests/ppc32/bug139050-ppc32.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/bug139050-ppc32.stdout.exp =
(rev 0)
+++ trunk/none/tests/ppc32/bug139050-ppc32.stdout.exp 2006-12-27 18:40:47=
UTC (rev 6446)
@@ -0,0 +1 @@
+success
Added: trunk/none/tests/ppc32/bug139050-ppc32.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/bug139050-ppc32.vgtest =
(rev 0)
+++ trunk/none/tests/ppc32/bug139050-ppc32.vgtest 2006-12-27 18:40:47 UTC=
(rev 6446)
@@ -0,0 +1,2 @@
+prog: bug139050-ppc32
+vgopts: -q
|
|
From: <sv...@va...> - 2006-12-27 18:39:47
|
Author: sewardj
Date: 2006-12-27 18:39:46 +0000 (Wed, 27 Dec 2006)
New Revision: 1705
Log:
Implement mfspr 268 and 269. Fixes #139050.
Modified:
trunk/priv/guest-ppc/gdefs.h
trunk/priv/guest-ppc/ghelpers.c
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/gdefs.h 2006-12-27 04:52:17 UTC (rev 1704)
+++ trunk/priv/guest-ppc/gdefs.h 2006-12-27 18:39:46 UTC (rev 1705)
@@ -148,6 +148,8 @@
=20
extern ULong ppcg_dirtyhelper_MFTB ( void );
=20
+extern UInt ppc32g_dirtyhelper_MFSPR_268_269 ( UInt );
+
extern void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_idx, UInt sh,
UInt shift_right );
Modified: trunk/priv/guest-ppc/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/ghelpers.c 2006-12-27 04:52:17 UTC (rev 1704)
+++ trunk/priv/guest-ppc/ghelpers.c 2006-12-27 18:39:46 UTC (rev 1705)
@@ -100,6 +100,24 @@
=20
=20
/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially transparent) */
+UInt ppc32g_dirtyhelper_MFSPR_268_269 ( UInt r269 )
+{
+# if defined(__powerpc__) || defined(_AIX)
+ UInt spr;
+ if (r269) {
+ __asm__ __volatile__("mfspr %0,269" : "=3Db"(spr));
+ } else {
+ __asm__ __volatile__("mfspr %0,268" : "=3Db"(spr));
+ }
+ return spr;
+# else
+ return 0;
+# endif
+}
+
+
+/* CALLED FROM GENERATED CODE */
/* DIRTY HELPER (reads guest state, writes guest mem) */
void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_off, UInt sh, UInt shift_right )
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-12-27 04:52:17 UTC (rev 1704)
+++ trunk/priv/guest-ppc/toIR.c 2006-12-27 18:39:46 UTC (rev 1705)
@@ -5347,6 +5347,28 @@
putIReg( rD_addr, getGST( PPC_GST_SPRG3_RO ) );
break;
=20
+ /* Even a lowly PPC7400 can run the associated helper, so no
+ obvious need for feature testing at this point. */
+ case 268 /* 0x10C */:
+ case 269 /* 0x10D */: {
+ UInt arg =3D SPR=3D=3D268 ? 0 : 1;
+ IRTemp val =3D newTemp(Ity_I32);
+ IRExpr** args =3D mkIRExprVec_1( mkU32(arg) );
+ IRDirty* d =3D unsafeIRDirty_1_N(
+ val,
+ 0/*regparms*/,
+ "ppc32g_dirtyhelper_MFSPR_268_269",
+ fnptr_to_fnentry
+ (vbi, &ppc32g_dirtyhelper_MFSPR_268_269),
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg( rD_addr, mkexpr(val) );
+ DIP("mfspr r%u,%u", rD_addr, (UInt)SPR);
+ break;
+ }
+
default:
vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR);
return False;
|
|
From: <js...@ac...> - 2006-12-27 05:59:20
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2006-12-27 09:00:01 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 215 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 215 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) none/tests/tls (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Dec 27 09:18:00 2006 --- new.short Wed Dec 27 09:34:36 2006 *************** *** 8,10 **** ! == 215 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) --- 8,10 ---- ! == 215 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) *************** *** 25,27 **** none/tests/ppc32/test_gx (stdout) - none/tests/tls (stdout) --- 25,26 ---- |
|
From: <sv...@va...> - 2006-12-27 05:21:16
|
Author: sewardj
Date: 2006-12-27 05:21:14 +0000 (Wed, 27 Dec 2006)
New Revision: 6445
Log:
Merge r6444 (Print a marginally more helpful error message if UME (ELF
loading) fails.)
Modified:
branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c
Modified: branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c 2006-12-27 05:18:33 UT=
C (rev 6444)
+++ branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c 2006-12-27 05:21:14 UT=
C (rev 6445)
@@ -71,8 +71,14 @@
static void check_mmap(SysRes res, Addr base, SizeT len)
{
if (res.isError) {
- VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME with error=
%d.\n",=20
- (ULong)base, (Long)len, res.val);
+ VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME "
+ "with error %d (%s).\n",=20
+ (ULong)base, (Long)len,=20
+ res.val, VG_(strerror)(res.val) );
+ if (res.val =3D=3D VKI_EINVAL) {
+ VG_(printf)("valgrind: this can be caused by executables with "
+ "very large text, data or bss segments.\n");
+ }
VG_(exit)(1);
}
}
|
|
From: <sv...@va...> - 2006-12-27 05:18:35
|
Author: sewardj
Date: 2006-12-27 05:18:33 +0000 (Wed, 27 Dec 2006)
New Revision: 6444
Log:
Print a marginally more helpful error message if UME (ELF loading) fails.
Modified:
trunk/coregrind/m_ume.c
Modified: trunk/coregrind/m_ume.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_ume.c 2006-12-27 04:35:52 UTC (rev 6443)
+++ trunk/coregrind/m_ume.c 2006-12-27 05:18:33 UTC (rev 6444)
@@ -77,6 +77,10 @@
"with error %d (%s).\n",=20
(ULong)base, (Long)len,=20
res.err, VG_(strerror)(res.err) );
+ if (res.err =3D=3D VKI_EINVAL) {
+ VG_(printf)("valgrind: this can be caused by executables with "
+ "very large text, data or bss segments.\n");
+ }
VG_(exit)(1);
}
}
|
|
From: <js...@ac...> - 2006-12-27 05:05:13
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2006-12-27 04:30:01 GMT Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 250 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 250 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Wed Dec 27 04:48:18 2006 --- new.short Wed Dec 27 05:05:23 2006 *************** *** 10,12 **** ! == 250 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) --- 10,12 ---- ! == 250 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/leak-tree (stderr) *************** *** 18,20 **** none/tests/mremap2 (stdout) - none/tests/pth_detached (stdout) --- 18,19 ---- |
|
From: <sv...@va...> - 2006-12-27 04:52:22
|
Author: sewardj
Date: 2006-12-27 04:52:17 +0000 (Wed, 27 Dec 2006)
New Revision: 1704
Log:
Merge r1677 (comment-only change: IR comments)
Modified:
branches/VEX_3_2_BRANCH/pub/libvex_ir.h
Modified: branches/VEX_3_2_BRANCH/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2006-12-27 04:21:05 UTC (rev =
1703)
+++ branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2006-12-27 04:52:17 UTC (rev =
1704)
@@ -49,8 +49,150 @@
=20
#include "libvex_basictypes.h"
=20
+ =20
+/*---------------------------------------------------------------*/
+/*--- High-level IR description ---*/
+/*---------------------------------------------------------------*/
=20
+/* Vex IR is an architecture-neutral intermediate representation.
+ Unlike some IRs in systems similar to Vex, it is not like assembly
+ language (ie. a list of instructions). Rather, it is more like the
+ IR that might be used in a compiler.
=20
+ Code blocks
+ ~~~~~~~~~~~
+ The code is broken into small code blocks (type: 'IRBB'). Each
+ code block typically represents from 1 to perhaps 50 instructions.
+ IRBBs are single-entry, multiple-exit code blocks. Each IRBB
+ contains three things:
+ - a type environment, which indicates the type of each temporary
+ value present in the IRBB
+ - a list of statements, which represent code
+ - a jump that exits from the end the IRBB
+ Because the blocks are multiple-exit, there can be additional
+ conditional exit statements that cause control to leave the IRBB
+ before the final exit.
+
+ Statements and expressions
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~
+ Statements (type 'IRStmt') represent operations with side-effects,
+ eg. guest register writes, stores, and assignments to temporaries.
+ Expressions (type 'IRExpr') represent operations without
+ side-effects, eg. arithmetic operations, loads, constants.
+ Expressions can contain sub-expressions, forming expression trees,
+ eg. (3 + (4 * load(addr1)).
+
+ Storage of guest state
+ ~~~~~~~~~~~~~~~~~~~~~~
+ The "guest state" contains the guest registers of the guest machine
+ (ie. the machine that we are simulating). It is stored by default
+ in a block of memory supplied by the user of the VEX library,
+ generally referred to as the guest state (area). To operate on
+ these registers, one must first read ("Get") them from the guest
+ state into a temporary value. Afterwards, one can write ("Put")
+ them back into the guest state.
+
+ Get and Put are characterised by a byte offset into the guest
+ state, a small integer which effectively gives the identity of the
+ referenced guest register, and a type, which indicates the size of
+ the value to be transferred.
+
+ The basic "Get" and "Put" operations are sufficient to model normal
+ fixed registers on the guest. Selected areas of the guest state
+ can be treated as a circular array of registers (type: 'IRArray'),
+ which can be indexed at run-time. This is done with the "GetI" and
+ "PutI" primitives. This is necessary to describe rotating register
+ files, for example the x87 FPU stack, SPARC register windows, and
+ the Itanium register files.
+
+ Examples, and flattened vs. unflattened code
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ For example, consider this x86 instruction:
+ =20
+ addl %eax, %ebx
+
+ One Vex IR translation for this code would be this:
+
+ ------ IMark(0x24F275, 7) ------
+ t3 =3D GET:I32(0) # get %eax, a 32-bit integer
+ t2 =3D GET:I32(12) # get %ebx, a 32-bit integer
+ t1 =3D Add32(t3,t2) # addl
+ PUT(0) =3D t1 # put %eax
+
+ (For simplicity, this ignores the effects on the condition codes, and
+ the update of the instruction pointer.)
+
+ The "IMark" is an IR statement that doesn't represent actual code.
+ Instead it indicates the address and length of the original
+ instruction. The numbers 0 and 12 are offsets into the guest state
+ for %eax and %ebx. The full list of offsets for an architecture
+ <ARCH> can be found in the type VexGuest<ARCH>State in the file
+ VEX/pub/libvex_guest_<ARCH>.h.
+
+ The five statements in this example are:
+ - the IMark
+ - three assignments to temporaries
+ - one register write (put)
+
+ The six expressions in this example are:
+ - two register reads (gets)
+ - one arithmetic (add) operation
+ - three temporaries (two nested within the Add32, one in the PUT)
+
+ The above IR is "flattened", ie. all sub-expressions are "atoms",
+ either constants or temporaries. An equivalent, unflattened version
+ would be:
+ =20
+ PUT(0) =3D Add32(GET:I32(0), GET:I32(12))
+
+ IR is guaranteed to be flattened at instrumentation-time. This makes
+ instrumentation easier. Equivalent flattened and unflattened IR
+ typically results in the same generated code.
+
+ Another example, this one showing loads and stores:
+
+ addl %edx,4(%eax)
+
+ This becomes (again ignoring condition code and instruction pointer
+ updates):
+
+ ------ IMark(0x4000ABA, 3) ------
+ t3 =3D Add32(GET:I32(0),0x4:I32)
+ t2 =3D LDle:I32(t3)
+ t1 =3D GET:I32(8)
+ t0 =3D Add32(t2,t1)
+ STle(t3) =3D t0
+
+ The "le" in "LDle" and "STle" is short for "little-endian".
+
+ No need for deallocations
+ ~~~~~~~~~~~~~~~~~~~~~~~~~
+ Although there are allocation functions for various data structures
+ in this file, there are no deallocation functions. This is because
+ Vex uses a memory allocation scheme that automatically reclaims the
+ memory used by allocated structures once translation is completed.
+ This makes things easier for tools that instruments/transforms code
+ blocks.
+
+ SSAness and typing
+ ~~~~~~~~~~~~~~~~~~
+ The IR is fully typed. For every IRBB (IR block) it is possible to
+ say unambiguously whether or not it is correctly typed.
+ Incorrectly typed IR has no meaning and the VEX will refuse to
+ process it. At various points during processing VEX typechecks the
+ IR and aborts if any violations are found. This seems overkill but
+ makes it a great deal easier to build a reliable JIT.
+
+ IR also has the SSA property. SSA stands for Static Single
+ Assignment, and what it means is that each IR temporary may be
+ assigned to only once. This idea became widely used in compiler
+ construction in the mid to late 90s. It makes many IR-level
+ transformations/code improvements easier, simpler and faster.
+ Whenever it typechecks an IR block, VEX also checks the SSA
+ property holds, and will abort if not so. So SSAness is
+ mechanically and rigidly enforced.
+*/
+
/*---------------------------------------------------------------*/
/*--- Type definitions for the IR ---*/
/*---------------------------------------------------------------*/
@@ -79,6 +221,8 @@
=20
/* ------------------ Types ------------------ */
=20
+/* A type indicates the size of a value, and whether it's an integer, a
+ float, or a vector (SIMD) value. */
typedef=20
enum {=20
Ity_INVALID=3D0x10FFF,
@@ -94,22 +238,29 @@
}
IRType;
=20
+/* Pretty-print an IRType */
extern void ppIRType ( IRType );
-extern Int sizeofIRType ( IRType );
=20
+/* Get the size (in bytes) of an IRType */=20
+extern Int sizeofIRType ( IRType );
=20
+
/* ------------------ Endianness ------------------ */
=20
+/* IREndness is used in load IRExprs and store IRStmts. */
typedef
enum {=20
Iend_LE=3D22, /* little endian */
- Iend_BE=3D33 /* big endian */
+ Iend_BE=3D33 /* big endian */
}
IREndness;
=20
=20
/* ------------------ Constants ------------------ */
=20
+/* IRConsts are used within 'Const' and 'Exit' IRExprs. */
+
+/* The various kinds of constant. */
typedef
enum {=20
Ico_U1=3D0x12000,
@@ -120,11 +271,15 @@
Ico_F64, /* 64-bit IEEE754 floating */
Ico_F64i, /* 64-bit unsigned int to be interpreted literally
as a IEEE754 double value. */
- Ico_V128 /* 128-bit restricted vector constant, with 1 bit for
- each of 16 byte lanes */
+ Ico_V128 /* 128-bit restricted vector constant, with 1 bit
+ (repeated 8 times) for each of the 16 x 1-byte lanes=
*/
}
IRConstTag;
=20
+/* A constant. Stored as a tagged union. 'tag' indicates what kind of
+ constant this is. 'Ico' is the union that holds the fields. If an
+ IRConst 'c' has c.tag equal to Ico_U32, then it's a 32-bit constant,
+ and its value can be accessed with 'c.Ico.U32'. */
typedef
struct _IRConst {
IRConstTag tag;
@@ -136,11 +291,12 @@
ULong U64;
Double F64;
ULong F64i;
- UShort V128;
+ UShort V128; /* 16-bit value; see Ico_V128 comment above */
} Ico;
}
IRConst;
=20
+/* IRConst constructors */
extern IRConst* IRConst_U1 ( Bool );
extern IRConst* IRConst_U8 ( UChar );
extern IRConst* IRConst_U16 ( UShort );
@@ -150,9 +306,13 @@
extern IRConst* IRConst_F64i ( ULong );
extern IRConst* IRConst_V128 ( UShort );
=20
+/* Deep-copy an IRConst */
extern IRConst* dopyIRConst ( IRConst* );
=20
+/* Pretty-print an IRConst */
extern void ppIRConst ( IRConst* );
+
+/* Compare two IRConsts for equality */
extern Bool eqIRConst ( IRConst*, IRConst* );
=20
=20
@@ -181,20 +341,26 @@
}
IRCallee;
=20
+/* Create an IRCallee. */
extern IRCallee* mkIRCallee ( Int regparms, HChar* name, void* addr );
=20
+/* Deep-copy an IRCallee. */
extern IRCallee* dopyIRCallee ( IRCallee* );
=20
+/* Pretty-print an IRCallee. */
extern void ppIRCallee ( IRCallee* );
=20
=20
/* ------------------ Guest state arrays ------------------ */
=20
+/* This describes a section of the guest state that we want to
+ be able to index at run time, so as to be able to describe=20
+ indexed or rotating register files on the guest. */
typedef
struct {
- Int base;
- IRType elemTy;
- Int nElems;
+ Int base; /* guest state offset of start of indexed area */
+ IRType elemTy; /* type of each element in the indexed area */
+ Int nElems; /* number of elements in the indexed area */
}
IRArray;
=20
@@ -208,10 +374,12 @@
=20
/* ------------------ Temporaries ------------------ */
=20
-/* The IR optimiser relies on the fact that IRTemps are 32-bit
- ints. Do not change them to be ints of any other size. */
+/* This represents a temporary, eg. t1. The IR optimiser relies on the
+ fact that IRTemps are 32-bit ints. Do not change them to be ints of
+ any other size. */
typedef UInt IRTemp;
=20
+/* Pretty-print an IRTemp. */
extern void ppIRTemp ( IRTemp );
=20
#define IRTemp_INVALID ((IRTemp)0xFFFFFFFF)
@@ -219,6 +387,16 @@
=20
/* --------------- Primops (arity 1,2,3 and 4) --------------- */
=20
+/* Primitive operations that are used in Unop, Binop, Triop and Qop
+ IRExprs. Once we take into account integer, floating point and SIMD
+ operations of all the different sizes, there are quite a lot of them.
+ Most instructions supported by the architectures that Vex supports
+ (x86, PPC, etc) are represented. Some more obscure ones (eg. cpuid)
+ are not; they are instead handled with dirty helpers that emulate
+ their functionality. Such obscure ones are thus not directly visible
+ in the IR, but their effects on guest state (memory and registers)=20
+ are made visible via the annotations in IRDirty structures.
+*/
typedef
enum {=20
/* -- Do not change this ordering. The IR generators rely on
@@ -264,8 +442,8 @@
/* As a sop to Valgrind-Memcheck, the following are useful. */
Iop_CmpNEZ8, Iop_CmpNEZ16, Iop_CmpNEZ32, Iop_CmpNEZ64,
=20
- /* PowerPC-style 3-way integer comparisons. Without them it is di=
fficult
- to simulate PPC efficiently.
+ /* PowerPC-style 3-way integer comparisons. Without them it is
+ difficult to simulate PPC efficiently.
op(x,y) | x < y =3D 0x8 else=20
| x > y =3D 0x4 else
| x =3D=3D y =3D 0x2
@@ -666,6 +844,7 @@
}
IROp;
=20
+/* Pretty-print an op. */
extern void ppIROp ( IROp );
=20
=20
@@ -695,157 +874,222 @@
=20
=20
/* ------------------ Expressions ------------------ */
-/*=20
- Some details of expression semantics:
=20
- IRExpr_GetI (also IRStmt_PutI)
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- These allow circular indexing into parts of the guest state, which
- is essential for modelling situations where the identity of guest
- registers is not known until run time. One example is the x87 FP
- register stack.
+/* The different kinds of expressions. Their meaning is explained below
+ in the comments for IRExpr. */
+typedef
+ enum {=20
+ Iex_Binder,
+ Iex_Get,
+ Iex_GetI,
+ Iex_Tmp,
+ Iex_Qop,
+ Iex_Triop,
+ Iex_Binop,
+ Iex_Unop,
+ Iex_Load,
+ Iex_Const,
+ Iex_Mux0X,
+ Iex_CCall
+ }
+ IRExprTag;
=20
- The part of the guest state to be treated as a circular array is
- described in an IRArray structure attached to the GetI/PutI.
- IRArray holds the offset of the first element in the array, the
- type of each element, and the number of elements.
+/* An expression. Stored as a tagged union. 'tag' indicates what kind
+ of expression this is. 'Iex' is the union that holds the fields. If
+ an IRExpr 'e' has e.tag equal to Iex_Load, then it's a load
+ expression, and the fields can be accessed with
+ 'e.Iex.Load.<fieldname>'.
=20
- The array index is indicated rather indirectly, in a way which
- makes optimisation easy: as the sum of variable part (the 'ix'
- field) and a constant offset (the 'bias' field).
+ For each kind of expression, we show what it looks like when
+ pretty-printed with ppIRExpr().
+*/
+typedef
+ struct _IRExpr
+ IRExpr;
=20
- Since the indexing is circular, the actual array index to use
- is computed as (ix + bias) % number-of-elements-in-the-array.
+struct _IRExpr {
+ IRExprTag tag;
+ union {
+ /* Used only in pattern matching within Vex. Should not be seen
+ outside of Vex. */
+ struct {
+ Int binder;
+ } Binder;
=20
- Here's an example. The description
+ /* Read a guest register, at a fixed offset in the guest state.
+ ppIRExpr output: GET:<ty>(<offset>), eg. GET:I32(0)
+ */
+ struct {
+ Int offset; /* Offset into the guest state */
+ IRType ty; /* Type of the value being read */
+ } Get;
=20
- (96:8xF64)[t39,-7]
+ /* Read a guest register at a non-fixed offset in the guest
+ state. This allows circular indexing into parts of the guest
+ state, which is essential for modelling situations where the
+ identity of guest registers is not known until run time. One
+ example is the x87 FP register stack.
=20
- describes an array of 8 F64-typed values, the guest-state-offset
- of the first being 96. This array is being indexed at
- (t39 - 7) % 8.
+ The part of the guest state to be treated as a circular array
+ is described in the IRArray 'descr' field. It holds the
+ offset of the first element in the array, the type of each
+ element, and the number of elements.
=20
- It is important to get the array size/type exactly correct since IR
- optimisation looks closely at such info in order to establish
- aliasing/non-aliasing between seperate GetI and PutI events, which
- is used to establish when they can be reordered, etc. Putting
- incorrect info in will lead to obscure IR optimisation bugs.
+ The array index is indicated rather indirectly, in a way
+ which makes optimisation easy: as the sum of variable part
+ (the 'ix' field) and a constant offset (the 'bias' field).
=20
- IRExpr_CCall
- ~~~~~~~~~~~~
- The name is the C helper function; the backends will call back to
- the front ends to get the address of a host-code helper function to
- be called.
+ Since the indexing is circular, the actual array index to use
+ is computed as (ix + bias) % num-of-elems-in-the-array.
=20
- The args are a NULL-terminated array of arguments. The stated
- return IRType, and the implied argument types, must match that of
- the function being called well enough so that the back end can
- actually generate correct code for the call.
+ Here's an example. The description
=20
- The called function **must** satisfy the following:
+ (96:8xF64)[t39,-7]
=20
- * no side effects -- must be a pure function, the result of which
- depends only on the passed parameters.
+ describes an array of 8 F64-typed values, the
+ guest-state-offset of the first being 96. This array is
+ being indexed at (t39 - 7) % 8.
=20
- * it may not look at, nor modify, any of the guest state since that
- would hide guest state transitions from instrumenters
+ It is important to get the array size/type exactly correct
+ since IR optimisation looks closely at such info in order to
+ establish aliasing/non-aliasing between seperate GetI and
+ PutI events, which is used to establish when they can be
+ reordered, etc. Putting incorrect info in will lead to
+ obscure IR optimisation bugs.
=20
- * it may not access guest memory, since that would hide guest
- memory transactions from the instrumenters
+ ppIRExpr output: GETI<descr>[<ix>,<bias]
+ eg. GETI(128:8xI8)[t1,0]
+ */
+ struct {
+ IRArray* descr; /* Part of guest state treated as circular */
+ IRExpr* ix; /* Variable part of index into array */
+ Int bias; /* Constant offset part of index into array *=
/
+ } GetI;
=20
- This is restrictive, but makes the semantics clean, and does
- not interfere with IR optimisation.
+ /* The value held by a temporary.
+ ppIRExpr output: t<tmp>, eg. t1
+ */
+ struct {
+ IRTemp tmp; /* The temporary number */
+ } Tmp;
=20
- If you want to call a helper which can mess with guest state and/or
- memory, instead use IRStmt_Dirty. This is a lot more flexible, but
- you pay for that flexibility in that you have to give a bunch of
- details about what the helper does (and you better be telling the
- truth, otherwise any derived instrumentation will be wrong). Also
- IRStmt_Dirty inhibits various IR optimisations and so can cause
- quite poor code to be generated. Try to avoid it. */
+ /* A quaternary operation.
+ ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>, <arg4>),
+ eg. MAddF64r32(t1, t2, t3, t4)
+ */
+ struct {
+ IROp op; /* op-code */
+ IRExpr* arg1; /* operand 1 */
+ IRExpr* arg2; /* operand 2 */
+ IRExpr* arg3; /* operand 3 */
+ IRExpr* arg4; /* operand 4 */
+ } Qop;
=20
-/* The possible kinds of expressions are as follows: */
-typedef
- enum {=20
- Iex_Binder, /* Used only in pattern matching. =20
- Not an expression. */
- Iex_Get, /* read guest state, fixed offset */
- Iex_GetI, /* read guest state, run-time offset */
- Iex_Tmp, /* value of temporary */
- Iex_Qop, /* quaternary operation */
- Iex_Triop, /* ternary operation */
- Iex_Binop, /* binary operation */
- Iex_Unop, /* unary operation */
- Iex_Load, /* read from memory */=20
- Iex_Const, /* constant-valued expression */
- Iex_Mux0X, /* ternary if-then-else operator (STRICT) */
- Iex_CCall /* call to pure (side-effect-free) helper fn */
- }
- IRExprTag;
+ /* A ternary operation.
+ ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>),
+ eg. MulF64(1, 2.0, 3.0)
+ */
+ struct {
+ IROp op; /* op-code */
+ IRExpr* arg1; /* operand 1 */
+ IRExpr* arg2; /* operand 2 */
+ IRExpr* arg3; /* operand 3 */
+ } Triop;
=20
-typedef=20
- struct _IRExpr {
- IRExprTag tag;
- union {
- struct {
- Int binder;
- } Binder;
- struct {
- Int offset;
- IRType ty;
- } Get;
- struct {
- IRArray* descr;
- struct _IRExpr* ix;
- Int bias;
- } GetI;
- struct {
- IRTemp tmp;
- } Tmp;
- struct {
- IROp op;
- struct _IRExpr* arg1;
- struct _IRExpr* arg2;
- struct _IRExpr* arg3;
- struct _IRExpr* arg4;
- } Qop;
- struct {
- IROp op;
- struct _IRExpr* arg1;
- struct _IRExpr* arg2;
- struct _IRExpr* arg3;
- } Triop;
- struct {
- IROp op;
- struct _IRExpr* arg1;
- struct _IRExpr* arg2;
- } Binop;
- struct {
- IROp op;
- struct _IRExpr* arg;
- } Unop;
- struct {
- IREndness end;
- IRType ty;
- struct _IRExpr* addr;
- } Load;
- struct {
- IRConst* con;
- } Const;
- struct {
- IRCallee* cee;
- IRType retty;
- struct _IRExpr** args;
- } CCall;
- struct {
- struct _IRExpr* cond;
- struct _IRExpr* expr0;
- struct _IRExpr* exprX;
- } Mux0X;
- } Iex;
- }
- IRExpr;
+ /* A binary operation.
+ ppIRExpr output: <op>(<arg1>, <arg2>), eg. Add32(t1,t2)
+ */
+ struct {
+ IROp op; /* op-code */
+ IRExpr* arg1; /* operand 1 */
+ IRExpr* arg2; /* operand 2 */
+ } Binop;
=20
+ /* A unary operation.
+ ppIRExpr output: <op>(<arg>), eg. Neg8(t1)
+ */
+ struct {
+ IROp op; /* op-code */
+ IRExpr* arg; /* operand */
+ } Unop;
+
+ /* A load from memory.
+ ppIRExpr output: LD<end>:<ty>(<addr>), eg. LDle:I32(t1)
+ */
+ struct {
+ IREndness end; /* Endian-ness of the load */
+ IRType ty; /* Type of the loaded value */
+ IRExpr* addr; /* Address being loaded from */
+ } Load;
+
+ /* A constant-valued expression.
+ ppIRExpr output: <con>, eg. 0x4:I32
+ */
+ struct {
+ IRConst* con; /* The constant itself */
+ } Const;
+
+ /* A call to a pure (no side-effects) helper C function.
+
+ With the 'cee' field, 'name' is the function's name. It is
+ only used for pretty-printing purposes. The address to call
+ (host address, of course) is stored in the 'addr' field
+ inside 'cee'.
+
+ The 'args' field is a NULL-terminated array of arguments.
+ The stated return IRType, and the implied argument types,
+ must match that of the function being called well enough so
+ that the back end can actually generate correct code for the
+ call.
+
+ The called function **must** satisfy the following:
+
+ * no side effects -- must be a pure function, the result of
+ which depends only on the passed parameters.
+
+ * it may not look at, nor modify, any of the guest state
+ since that would hide guest state transitions from
+ instrumenters
+
+ * it may not access guest memory, since that would hide
+ guest memory transactions from the instrumenters
+
+ This is restrictive, but makes the semantics clean, and does
+ not interfere with IR optimisation.
+
+ If you want to call a helper which can mess with guest state
+ and/or memory, instead use Ist_Dirty. This is a lot more
+ flexible, but you have to give a bunch of details about what
+ the helper does (and you better be telling the truth,
+ otherwise any derived instrumentation will be wrong). Also
+ Ist_Dirty inhibits various IR optimisations and so can cause
+ quite poor code to be generated. Try to avoid it.
+
+ ppIRExpr output: <cee>(<args>):<retty>
+ eg. foo{0x80489304}(t1, t2):I32
+ */
+ struct {
+ IRCallee* cee; /* Function to call. */
+ IRType retty; /* Type of return value. */
+ IRExpr** args; /* Vector of argument expressions. */
+ } CCall;
+
+ /* A ternary if-then-else operator. It returns expr0 if cond is
+ zero, exprX otherwise. Note that it is STRICT, ie. both
+ expr0 and exprX are evaluated in all cases.
+
+ ppIRExpr output: Mux0X(<cond>,<expr0>,<exprX>),
+ eg. Mux0X(t6,t7,t8)
+ */
+ struct {
+ IRExpr* cond; /* Condition */
+ IRExpr* expr0; /* True expression */
+ IRExpr* exprX; /* False expression */
+ } Mux0X;
+ } Iex;
+};
+
+/* Expression constructors. */
extern IRExpr* IRExpr_Binder ( Int binder );
extern IRExpr* IRExpr_Get ( Int off, IRType ty );
extern IRExpr* IRExpr_GetI ( IRArray* descr, IRExpr* ix, Int bias );
@@ -861,13 +1105,14 @@
extern IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** arg=
s );
extern IRExpr* IRExpr_Mux0X ( IRExpr* cond, IRExpr* expr0, IRExpr* expr=
X );
=20
+/* Deep-copy an IRExpr. */
extern IRExpr* dopyIRExpr ( IRExpr* );
=20
+/* Pretty-print an IRExpr. */
extern void ppIRExpr ( IRExpr* );
=20
-/* NULL-terminated IRExpr expression vectors, suitable for use as arg
- lists in clean/dirty helper calls. */
-
+/* NULL-terminated IRExpr vector constructors, suitable for
+ use as arg lists in clean/dirty helper calls. */
extern IRExpr** mkIRExprVec_0 ( void );
extern IRExpr** mkIRExprVec_1 ( IRExpr* );
extern IRExpr** mkIRExprVec_2 ( IRExpr*, IRExpr* );
@@ -876,11 +1121,15 @@
extern IRExpr** mkIRExprVec_5 ( IRExpr*, IRExpr*,=20
IRExpr*, IRExpr*, IRExpr* );
=20
+/* IRExpr copiers:
+ - sopy: shallow-copy (ie. create a new vector that shares the
+ elements with the original).
+ - dopy: deep-copy (ie. create a completely new vector). */
extern IRExpr** sopyIRExprVec ( IRExpr** );
extern IRExpr** dopyIRExprVec ( IRExpr** );
=20
/* Make a constant expression from the given host word taking into
- account of course the host word size. */
+ account (of course) the host word size. */
extern IRExpr* mkIRExpr_HWord ( HWord );
=20
/* Convenience function for constructing clean helper calls. */
@@ -890,8 +1139,8 @@
IRExpr** args );
=20
=20
-/* Convenience functions for atoms, that is, IRExprs which
- are either Iex_Tmp or Iex_Const. */
+/* Convenience functions for atoms (IRExprs which are either Iex_Tmp or
+ * Iex_Const). */
static inline Bool isIRAtom ( IRExpr* e ) {
return toBool(e->tag =3D=3D Iex_Tmp || e->tag =3D=3D Iex_Const);
}
@@ -906,17 +1155,17 @@
/* This describes hints which can be passed to the dispatcher at guest
control-flow transfer points.
=20
- Re Ijk_Invalidate: the guest state _must_ have two
- pseudo-registers, guest_TISTART and guest_TILEN, which specify the
- start and length of the region to be invalidated. These are both
- the size of a guest word. It is the responsibility of the relevant
- toIR.c to ensure that these are filled in with suitable values
- before issuing a jump of kind Ijk_TInval. =20
+ Re Ijk_TInval: the guest state _must_ have two pseudo-registers,
+ guest_TISTART and guest_TILEN, which specify the start and length
+ of the region to be invalidated. These are both the size of a
+ guest word. It is the responsibility of the relevant toIR.c to
+ ensure that these are filled in with suitable values before issuing
+ a jump of kind Ijk_TInval.
=20
Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a
- pseudo-register guest_EMWARN, which is 32-bits regardless of
- the host or guest word size. That register should be made
- to hold an EmWarn_* value to indicate the reason for the exit.
+ pseudo-register guest_EMWARN, which is 32-bits regardless of the
+ host or guest word size. That register should be made to hold an
+ EmWarn_* value to indicate the reason for the exit.
=20
In the case of Ijk_EmFail, the exit is fatal (Vex-generated code
cannot continue) and so the jump destination can be anything.
@@ -950,24 +1199,25 @@
=20
/* ------------------ Dirty helper calls ------------------ */
=20
-/* A dirty call is a flexible mechanism for calling a helper function
- or procedure. The helper function may read, write or modify client
- memory, and may read, write or modify client state. It can take
- arguments and optionally return a value. It may return different
- results and/or do different things when called repeated with the
- same arguments, by means of storing private state.
+/* A dirty call is a flexible mechanism for calling (possibly
+ conditionally) a helper function or procedure. The helper function
+ may read, write or modify client memory, and may read, write or
+ modify client state. It can take arguments and optionally return a
+ value. It may return different results and/or do different things
+ when called repeatedly with the same arguments, by means of storing
+ private state.
=20
If a value is returned, it is assigned to the nominated return
temporary.
=20
Dirty calls are statements rather than expressions for obvious
- reasons. If a dirty call is stated as writing guest state, any
+ reasons. If a dirty call is marked as writing guest state, any
values derived from the written parts of the guest state are
invalid. Similarly, if the dirty call is stated as writing
memory, any loaded values are invalidated by it.
=20
In order that instrumentation is possible, the call must state, and
- state correctly
+ state correctly:
=20
* whether it reads, writes or modifies memory, and if so where
(only one chunk can be stated)
@@ -991,6 +1241,7 @@
=20
#define VEX_N_FXSTATE 7 /* enough for FXSAVE/FXRSTOR on x86 */
=20
+/* Effects on resources (eg. registers, memory locations) */
typedef
enum {
Ifx_None =3D 0x15000, /* no effect */
@@ -1000,6 +1251,7 @@
}
IREffect;
=20
+/* Pretty-print an IREffect */
extern void ppIREffect ( IREffect );
=20
=20
@@ -1027,16 +1279,20 @@
}
IRDirty;
=20
+/* Pretty-print a dirty call */
extern void ppIRDirty ( IRDirty* );
+
+/* Allocate an uninitialised dirty call */
extern IRDirty* emptyIRDirty ( void );
=20
+/* Deep-copy a dirty call */
extern IRDirty* dopyIRDirty ( IRDirty* );
=20
/* A handy function which takes some of the tedium out of constructing
dirty helper calls. The called function impliedly does not return
any value and has a constant-True guard. The call is marked as
accessing neither guest state nor memory (hence the "unsafe"
- designation) -- you can mess with this later if need be. A
+ designation) -- you can change this marking later if need be. A
suitable IRCallee is constructed from the supplied bits. */
extern=20
IRDirty* unsafeIRDirty_0_N ( Int regparms, HChar* name, void* addr,=20
@@ -1052,83 +1308,159 @@
=20
/* ------------------ Statements ------------------ */
=20
-/* The possible kinds of statements are as follows. Those marked
- OPTIONAL are hints of one kind or another, and as such do not
- denote any change in the guest state or of IR temporaries. They
- can therefore be omitted without changing the meaning denoted by
- the IR.=20
+/* The different kinds of statements. Their meaning is explained
+ below in the comments for IRStmt.
=20
- At the moment, the only AbiHint is one which indicates that a given
- chunk of address space has become undefined. This is used on
- amd64-linux to pass stack-redzoning hints to whoever wants to see
- them.
+ Those marked META do not represent code, but rather extra
+ information about the code. These statements can be removed
+ without affecting the functional behaviour of the code, however
+ they are required by some IR consumers such as tools that
+ instrument the code.
*/
typedef=20
enum {
- Ist_NoOp, /* OPTIONAL: no-op (usually resulting from IR
- optimisation) */
- Ist_IMark, /* OPTIONAL: instruction mark: describe addr/len of
- guest insn whose IR follows. */
- Ist_AbiHint, /* OPTIONAL: tell me something about this
- platform's ABI */
- Ist_Put, /* write guest state, fixed offset */
- Ist_PutI, /* write guest state, run-time offset */
- Ist_Tmp, /* assign value to temporary */
- Ist_Store, /* write to memory */
- Ist_Dirty, /* call complex ("dirty") helper function */
- Ist_MFence, /* memory fence */
- Ist_Exit /* conditional exit from BB */
+ Ist_NoOp,
+ Ist_IMark, /* META */
+ Ist_AbiHint, /* META */
+ Ist_Put,
+ Ist_PutI,
+ Ist_Tmp,
+ Ist_Store,
+ Ist_Dirty,
+ Ist_MFence,
+ Ist_Exit
}=20
IRStmtTag;
=20
+/* A statement. Stored as a tagged union. 'tag' indicates what kind
+ of expression this is. 'Ist' is the union that holds the fields.
+ If an IRStmt 'st' has st.tag equal to Iex_Store, then it's a store
+ statement, and the fields can be accessed with
+ 'st.Ist.Store.<fieldname>'.
+
+ For each kind of statement, we show what it looks like when
+ pretty-printed with ppIRExpr().
+*/
typedef
struct _IRStmt {
IRStmtTag tag;
union {
+ /* A no-op (usually resulting from IR optimisation). Can be
+ omitted without any effect.
+
+ ppIRExpr output: IR-NoOp
+ */
struct {
} NoOp;
+
+ /* META: instruction mark. Marks the start of the statements
+ that represent a single machine instruction (the end of
+ those statements is marked by the next IMark or the end of
+ the IRBB). Contains the address and length of the
+ instruction.
+
+ ppIRExpr output: ------ IMark(<addr>, <len>) ------,
+ eg. ------ IMark(0x4000792, 5) ------,
+ */
struct {
- Addr64 addr;
- Int len;
+ Addr64 addr; /* instruction address */
+ Int len; /* instruction length */
} IMark;
+
+ /* META: An ABI hint, which says something about this
+ platform's ABI.
+
+ At the moment, the only AbiHint is one which indicates
+ that a given chunk of address space, [base .. base+len-1],
+ has become undefined. This is used on amd64-linux and
+ some ppc variants to pass stack-redzoning hints to whoever
+ wants to see them.
+
+ ppIRExpr output: =3D=3D=3D=3D=3D=3D AbiHint(<base>, <len>) =3D=
=3D=3D=3D=3D=3D
+ eg. =3D=3D=3D=3D=3D=3D AbiHint(t1, 16) =3D=3D=3D=
=3D=3D=3D
+ */
struct {
- /* [base .. base+len-1] has become uninitialised */
- IRExpr* base;
- Int len;
+ IRExpr* base; /* Start of undefined chunk */
+ Int len; /* Length of undefined chunk */
} AbiHint;
+
+ /* Write a guest register, at a fixed offset in the guest state=
.
+ ppIRExpr output: PUT(<offset>) =3D <data>, eg. PUT(60) =3D t=
1
+ */
struct {
- Int offset;
- IRExpr* data;
+ Int offset; /* Offset into the guest state */
+ IRExpr* data; /* The value to write */
} Put;
+
+ /* Write a guest register, at a non-fixed offset in the guest
+ state. See the comment for GetI expressions for more
+ information.
+
+ ppIRExpr output: PUTI<descr>[<ix>,<bias>] =3D <data>,
+ eg. PUTI(64:8xF64)[t5,0] =3D t1
+ */
struct {
- IRArray* descr;
- IRExpr* ix;
- Int bias;
- IRExpr* data;
+ IRArray* descr; /* Part of guest state treated as circular=
*/
+ IRExpr* ix; /* Variable part of index into array */
+ Int bias; /* Constant offset part of index into arra=
y */
+ IRExpr* data; /* The value to write */
} PutI;
+
+ /* Assign a value to a temporary. ("Tmp" is not a very good
+ name for this, particularly because there is also a Tmp
+ expression kind.)
+
+ ppIRExpr output: t<tmp> =3D <data>, eg. t1 =3D 3
+ */
struct {
- IRTemp tmp;
- IRExpr* data;
+ IRTemp tmp; /* Temporary (LHS of assignment) */
+ IRExpr* data; /* Expression (RHS of assignment) */
} Tmp;
+
+ /* Write a value to memory.
+ ppIRExpr output: ST<end>(<addr>) =3D <data>, eg. STle(t1) =3D=
t2
+ */
struct {
- IREndness end;
- IRExpr* addr;
- IRExpr* data;
+ IREndness end; /* Endianness of the store */
+ IRExpr* addr; /* store address */
+ IRExpr* data; /* value to write */
} Store;
+
+ /* Call (possibly conditionally) a C function that has side
+ effects (ie. is "dirty"). See the comments above the
+ IRDirty type declaration for more information.
+
+ ppIRExpr output:
+ t<tmp> =3D DIRTY <guard> <effects>=20
+ ::: <callee>(<args>)
+ eg.
+ t1 =3D DIRTY t27 RdFX-gst(16,4) RdFX-gst(60,4)
+ ::: foo{0x380035f4}(t2)
+ */ =20
struct {
IRDirty* details;
} Dirty;
+
+ /* A memory fence.
+ ppIRExpr output: IR-MFence
+ */
struct {
} MFence;
+
+ /* Conditional exit from the middle of an IRBB.
+ ppIRExpr output: if (<guard>) goto {<jk>} <dst>
+ eg. if (t69) goto {Boring} 0x4000AAA:I32
+ */
struct {
- IRExpr* guard;
- IRJumpKind jk;
- IRConst* dst;
+ IRExpr* guard; /* Conditional expression */
+ IRJumpKind jk; /* Jump kind */
+ IRConst* dst; /* Jump target (constant only) */
} Exit;
} Ist;
}
IRStmt;
=20
+/* Statement constructors. */
extern IRStmt* IRStmt_NoOp ( void );
extern IRStmt* IRStmt_IMark ( Addr64 addr, Int len );
extern IRStmt* IRStmt_AbiHint ( IRExpr* base, Int len );
@@ -1141,17 +1473,20 @@
extern IRStmt* IRStmt_MFence ( void );
extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* d=
st );
=20
+/* Deep-copy an IRStmt. */
extern IRStmt* dopyIRStmt ( IRStmt* );
=20
+/* Pretty-print an IRStmt. */
extern void ppIRStmt ( IRStmt* );
=20
=20
/* ------------------ Basic Blocks ------------------ */
=20
-/* A bunch of statements, expressions, etc, are incomplete without an
- environment indicating the type of each IRTemp. So this provides
- one. IR temporaries are really just unsigned ints and so this
- provides an array, 0 .. n_types_used-1 of them.
+/* Type environments: a bunch of statements, expressions, etc, are
+ incomplete without an environment indicating the type of each
+ IRTemp. So this provides one. IR temporaries are really just
+ unsigned ints and so this provides an array, 0 .. n_types_used-1 of
+ them.
*/
typedef
struct {
@@ -1161,22 +1496,29 @@
}
IRTypeEnv;
=20
-extern IRTemp newIRTemp ( IRTypeEnv*, IRType );
+/* Obtain a new IRTemp */
+extern IRTemp newIRTemp ( IRTypeEnv*, IRType );
+
+/* Deep-copy a type environment */
extern IRTypeEnv* dopyIRTypeEnv ( IRTypeEnv* );
=20
+/* Pretty-print a type environment */
extern void ppIRTypeEnv ( IRTypeEnv* );
=20
=20
-/* Basic blocks contain:
- - A table giving a type for each temp
+/* Code blocks contain:
+ - A table giving a type for each temp (the "type environment")
- An expandable array of statements
- An expression of type 32 or 64 bits, depending on the
guest's word size, indicating the next destination.
- An indication of any special actions (JumpKind) needed
for this final jump.
+ =20
+ The "BB" is short for "basic block", but this is a misnomer, as an
+ IRBB can contain multiple exits.
*/
typedef
- struct _IRBB {
+ struct {
IRTypeEnv* tyenv;
IRStmt** stmts;
Int stmts_size;
@@ -1186,12 +1528,19 @@
}
IRBB;
=20
+/* Allocate a new, uninitialised IRBB */
extern IRBB* emptyIRBB ( void );
=20
+/* Deep-copy an IRBB */
extern IRBB* dopyIRBB ( IRBB* );
=20
+/* Deep-copy an IRBB, except for the statements list. */
+extern IRBB* dopyIRBBExceptStmts ( IRBB* );
+
+/* Pretty-print an IRBB */
extern void ppIRBB ( IRBB* );
=20
+/* Append an IRStmt to an IRBB */
extern void addStmtToIRBB ( IRBB*, IRStmt* );
=20
=20
|
|
From: <sv...@va...> - 2006-12-27 04:35:54
|
Author: sewardj
Date: 2006-12-27 04:35:52 +0000 (Wed, 27 Dec 2006)
New Revision: 6443
Log:
Regtest for bug 137714 (x86 MASKMOVQ/MASKMOVDQU insns)
Added:
trunk/none/tests/x86/bug137714-x86.c
trunk/none/tests/x86/bug137714-x86.stderr.exp
trunk/none/tests/x86/bug137714-x86.stdout.exp
trunk/none/tests/x86/bug137714-x86.vgtest
Modified:
trunk/none/tests/x86/Makefile.am
Modified: trunk/none/tests/x86/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/Makefile.am 2006-12-27 04:22:08 UTC (rev 6442)
+++ trunk/none/tests/x86/Makefile.am 2006-12-27 04:35:52 UTC (rev 6443)
@@ -12,6 +12,7 @@
bug126147-x86.stderr.exp bug126147-x86.stdout.exp bug126147-x86.vgtest =
\
bug132813-x86.stderr.exp bug132813-x86.stdout.exp bug132813-x86.vgtest =
\
bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest =
\
+ bug137714-x86.stderr.exp bug137714-x86.stdout.exp bug137714-x86.vgtest =
\
cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
faultstatus.disabled faultstatus.stderr.exp \
@@ -42,6 +43,7 @@
bug126147-x86 \
bug132813-x86 \
bug135421-x86 \
+ bug137714-x86 \
cmpxchg8b cpuid \
faultstatus fcmovnu fpu_lazy_eflags fxtract \
getseg incdec_alt $(INSN_TESTS) \
Added: trunk/none/tests/x86/bug137714-x86.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/bug137714-x86.c (rev 0)
+++ trunk/none/tests/x86/bug137714-x86.c 2006-12-27 04:35:52 UTC (rev 644=
3)
@@ -0,0 +1,110 @@
+
+#include <stdio.h>
+#include <malloc.h>
+#include <assert.h>
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+
+static UInt randomUInt ( void )
+{
+ static UInt n =3D 0;
+ /* From "Numerical Recipes in C" 2nd Edition */
+ n =3D 1664525UL * n + 1013904223UL;
+ return n >> 17;
+}
+
+void maskmovq_mmx ( UChar* regL, UChar* regR )
+{
+ int i;
+ UChar* dst =3D malloc(8);
+ assert(dst);
+ for (i =3D 0; i < 8; i++)
+ dst[i] =3D 17 * (i+1);
+ __asm__ __volatile__(
+ "emms\n\t"
+ "movq (%0), %%mm1\n\t"
+ "movq (%1), %%mm2\n\t"
+ "movl %2, %%edi\n\t"
+ "maskmovq %%mm1,%%mm2"
+ : /*out*/=20
+ : /*in*/ "r"(regL), "r"(regR), "r"(&dst[0])
+ : /*trash*/ "edi", "memory", "cc"
+ );
+ for (i =3D 0; i < 8; i++)
+ printf("%02x", dst[i]);
+ free(dst);
+}
+
+void maskmovdqu_sse ( UChar* regL, UChar* regR )
+{
+ int i;
+ UChar* dst =3D malloc(16);
+ assert(dst);
+ for (i =3D 0; i < 16; i++)
+ dst[i] =3D i;
+ __asm__ __volatile__(
+ "movups (%0), %%xmm1\n\t"
+ "movups (%1), %%xmm2\n\t"
+ "movl %2, %%edi\n\t"
+ "maskmovdqu %%xmm2,%%xmm1\n\t"
+ "sfence"
+ : /*out*/=20
+ : /*in*/ "r"(regL), "r"(regR), "r"(dst)
+ : /*trash*/ "edi", "memory", "cc"
+ );
+ for (i =3D 0; i < 16; i++)
+ printf("%02x", dst[i]);
+ free(dst);
+}
+
+int main ( int argc, char** argv )
+{
+ int i, j;
+
+ /* mmx test */
+ {
+ UChar* regL =3D malloc(8);
+ UChar* regR =3D malloc(8);
+ assert(regL);
+ assert(regR);
+ for (i =3D 0; i < 10; i++) {
+ for (j =3D 0; j < 8; j++) {
+ regL[j] =3D (UChar)randomUInt();
+ printf("%02x", regL[j]);
+ }
+ printf(" ");
+ for (j =3D 0; j < 8; j++) {
+ regR[j] =3D (UChar)randomUInt();
+ printf("%02x", regR[j]);
+ }
+ printf(" ");
+ maskmovq_mmx( regR, regL );
+ printf("\n");
+ }
+ }
+
+ /* sse test */
+ {
+ UChar* regL =3D malloc(16);
+ UChar* regR =3D malloc(16);
+ assert(regL);
+ assert(regR);
+ for (i =3D 0; i < 10; i++) {
+ for (j =3D 0; j < 16; j++) {
+ regL[j] =3D (UChar)randomUInt();
+ printf("%02x", regL[j]);
+ }
+ printf(" ");
+ for (j =3D 0; j < 16; j++) {
+ regR[j] =3D (UChar)randomUInt();
+ printf("%02x", regR[j]);
+ }
+ printf(" ");
+ maskmovdqu_sse( regR, regL );
+ printf("\n");
+ }
+ }
+
+ return 0;
+}
Added: trunk/none/tests/x86/bug137714-x86.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Added: trunk/none/tests/x86/bug137714-x86.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/bug137714-x86.stdout.exp =
(rev 0)
+++ trunk/none/tests/x86/bug137714-x86.stdout.exp 2006-12-27 04:35:52 UTC=
(rev 6443)
@@ -0,0 +1,20 @@
+37a8e67c2997ffec fe78fb68914bdde3 3722e6442966ffec
+96e427842e563da3 96f9e55dff19ead5 96e427442e663da3
+773ce009050f014e d4ed3569860c2f4a 773c334405667788
+a945b466477ff7b0 97b91f34d1b2e952 a9453344477ff788
+1e366994ad06eb2b e163f80ba73973a1 1e226944ad66772b
+e5e4e32e0ea1cbc2 d19434d8f1704b89 e5e4332e0e6677c2
+2fc8266f63f0a218 a9906724b7c60dfd 2fc8334463f07718
+4df75731c5319d6f c93f471b234a758f 4d2233445566776f
+af27bbf06c4208a9 b127a8877ca85f72 af22bbf055427788
+e5b0b5c4b1a25149 026e7dd32b31c977 112233c455665188
+a187cb690d7004717ddbdd08b9d3cf13 b244a13a1769cce401d5fbd2ce1bad57 b244a1=
030405060708d5fb0bce1bad0f
+0a1cfc3088ed770590622b7c323ac0f5 b8e7bfe739f9f1d64928e2eecefc8440 0001bf=
0339f9060749090a0b0c0d8440
+ed1af098222d47f96e6eb6b5abd1972c facdb31f5dc7a4b05f1b59faf0c7b349 fa01b3=
1f040506b0080959faf0c7b30f
+4fb54cf520a557e09db4a189e78cb6cb 7d2a2036c545ca09c76183caf9709d84 002a02=
3604450609c76183caf9709d84
+3421b49cc4c88b4f9ee812caac6083e7 4431ab81b7ea467304b08333abeca606 0001ab=
81b7ea460704b00a33ab0da606
+9f91cbdf540ac8d9f8be2b4ebd416193 5418f8527527fc839aba7e07cc2e32e2 5418f8=
520405fc839aba0a0bcc0d0ee2
+943b371413e0f0142cea11e8de22b5e5 b011abff4572d1cd0e35981c1e2aa62d b00102=
030472d10708350a1c1e0da62d
+18529a8e44bdea91c120e76dd3f7e2ef 5d5267db693fa7e4e4d3f44567d565fb 000167=
db043fa7e4e409f40b67d565fb
+2f0999a12d1697e73814d3af60b54cc5 5e0dd23a2701645d9f49b7566923d35f 0001d2=
3a0405645d0809b7560c230e5f
+dc95d7a1105edda81879f784494f577c b8778e70c22ceccbc34b0623ea06556e b8778e=
700405eccb080906230c0d0e0f
Added: trunk/none/tests/x86/bug137714-x86.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/bug137714-x86.vgtest (re=
v 0)
+++ trunk/none/tests/x86/bug137714-x86.vgtest 2006-12-27 04:35:52 UTC (re=
v 6443)
@@ -0,0 +1,3 @@
+prog: bug137714-x86
+prereq: ../../../tests/cputest x86-sse2
+vgopts: -q
|
|
From: <sv...@va...> - 2006-12-27 04:22:09
|
Author: sewardj
Date: 2006-12-27 04:22:08 +0000 (Wed, 27 Dec 2006)
New Revision: 6442
Log:
Merge r6441 (Handle new primop Iop_SarN8x8 introduced in vex r1702.)
Modified:
branches/VALGRIND_3_2_BRANCH/memcheck/mc_translate.c
Modified: branches/VALGRIND_3_2_BRANCH/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/memcheck/mc_translate.c 2006-12-27 01:16=
:58 UTC (rev 6441)
+++ branches/VALGRIND_3_2_BRANCH/memcheck/mc_translate.c 2006-12-27 04:22=
:08 UTC (rev 6442)
@@ -1839,6 +1839,7 @@
=20
case Iop_ShrN16x4:
case Iop_ShrN32x2:
+ case Iop_SarN8x8:
case Iop_SarN16x4:
case Iop_SarN32x2:
case Iop_ShlN16x4:
|
|
From: <sv...@va...> - 2006-12-27 04:21:14
|
Author: sewardj
Date: 2006-12-27 04:21:05 +0000 (Wed, 27 Dec 2006)
New Revision: 1703
Log:
Merge r1702 (x86 front end: Implement MASKMOVQ and MASKMOVDQU)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c
branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h
branches/VEX_3_2_BRANCH/priv/host-x86/isel.c
branches/VEX_3_2_BRANCH/priv/ir/irdefs.c
branches/VEX_3_2_BRANCH/pub/libvex_ir.h
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-27 01:15:29 UTC=
(rev 1702)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-27 04:21:05 UTC=
(rev 1703)
@@ -5679,6 +5679,38 @@
break;
}
=20
+ case 0xF7: {
+ IRTemp addr =3D newTemp(Ity_I32);
+ IRTemp regD =3D newTemp(Ity_I64);
+ IRTemp regM =3D newTemp(Ity_I64);
+ IRTemp mask =3D newTemp(Ity_I64);
+ IRTemp olddata =3D newTemp(Ity_I64);
+ IRTemp newdata =3D newTemp(Ity_I64);
+
+ modrm =3D getIByte(delta);
+ if (sz !=3D 4 || (!epartIsReg(modrm)))
+ goto mmx_decode_failure;
+ delta++;
+
+ assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) ));
+ assign( regM, getMMXReg( eregOfRM(modrm) ));
+ assign( regD, getMMXReg( gregOfRM(modrm) ));
+ assign( mask, binop(Iop_SarN8x8, mkexpr(regM), mkU8(7)) );
+ assign( olddata, loadLE( Ity_I64, mkexpr(addr) ));
+ assign( newdata,=20
+ binop(Iop_Or64,=20
+ binop(Iop_And64,=20
+ mkexpr(regD),=20
+ mkexpr(mask) ),
+ binop(Iop_And64,=20
+ mkexpr(olddata),
+ unop(Iop_Not64, mkexpr(mask)))) );
+ storeLE( mkexpr(addr), mkexpr(newdata) );
+ DIP("maskmovq %s,%s\n", nameMMXReg( eregOfRM(modrm) ),
+ nameMMXReg( gregOfRM(modrm) ) );
+ break;
+ }
+
/* --- MMX decode failure --- */
default:
mmx_decode_failure:
@@ -7670,6 +7702,16 @@
goto decode_success;
}
=20
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F F7 =3D MASKMOVQ -- 8x8 masked store */
+ if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF7) {
+ Bool ok =3D False;
+ delta =3D dis_MMX( &ok, sorb, sz, delta+1 );
+ if (!ok)
+ goto decode_failure;
+ goto decode_success;
+ }
+
/* 0F 5F =3D MAXPS -- max 32Fx4 from R/M to R */
if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5F) {
delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "maxps", Iop_Max32Fx4=
);
@@ -9314,6 +9356,50 @@
/* else fall through */
}
=20
+ /* 66 0F F7 =3D MASKMOVDQU -- store selected bytes of double quadword=
*/
+ if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF7) {
+ modrm =3D getIByte(delta+2);
+ if (sz =3D=3D 2 && epartIsReg(modrm)) {
+ IRTemp regD =3D newTemp(Ity_V128);
+ IRTemp mask =3D newTemp(Ity_V128);
+ IRTemp olddata =3D newTemp(Ity_V128);
+ IRTemp newdata =3D newTemp(Ity_V128);
+ addr =3D newTemp(Ity_I32);
+
+ assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) ));
+ assign( regD, getXMMReg( gregOfRM(modrm) ));
+
+ /* Unfortunately can't do the obvious thing with SarN8x16
+ here since that can't be re-emitted as SSE2 code - no such
+ insn. */
+ assign(=20
+ mask,=20
+ binop(Iop_64HLtoV128,
+ binop(Iop_SarN8x8,=20
+ getXMMRegLane64( eregOfRM(modrm), 1 ),=20
+ mkU8(7) ),
+ binop(Iop_SarN8x8,=20
+ getXMMRegLane64( eregOfRM(modrm), 0 ),=20
+ mkU8(7) ) ));
+ assign( olddata, loadLE( Ity_V128, mkexpr(addr) ));
+ assign( newdata,=20
+ binop(Iop_OrV128,=20
+ binop(Iop_AndV128,=20
+ mkexpr(regD),=20
+ mkexpr(mask) ),
+ binop(Iop_AndV128,=20
+ mkexpr(olddata),
+ unop(Iop_NotV128, mkexpr(mask)))) );
+ storeLE( mkexpr(addr), mkexpr(newdata) );
+
+ delta +=3D 2+1;
+ DIP("maskmovdqu %s,%s\n", nameXMMReg( eregOfRM(modrm) ),
+ nameXMMReg( gregOfRM(modrm) ) );
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
/* 66 0F E7 =3D MOVNTDQ -- for us, just a plain SSE store. */
if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xE7) {
modrm =3D getIByte(delta+2);
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c 2006-12-=
27 01:15:29 UTC (rev 1702)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.c 2006-12-=
27 04:21:05 UTC (rev 1703)
@@ -299,6 +299,11 @@
/* shifts: we don't care about out-of-range ones, since
that is dealt with at a higher level. */
=20
+static inline UChar sar8 ( UChar v, UInt n )
+{
+ return toUChar(((Char)v) >> n);
+}
+
static inline UShort shl16 ( UShort v, UInt n )
{
return toUShort(v << n);
@@ -868,6 +873,22 @@
);
}
=20
+ULong h_generic_calc_SarN8x8 ( ULong xx, UInt nn )
+{
+ /* vassert(nn < 8); */
+ nn &=3D 7;
+ return mk8x8(
+ sar8( sel8x8_7(xx), nn ),
+ sar8( sel8x8_6(xx), nn ),
+ sar8( sel8x8_5(xx), nn ),
+ sar8( sel8x8_4(xx), nn ),
+ sar8( sel8x8_3(xx), nn ),
+ sar8( sel8x8_2(xx), nn ),
+ sar8( sel8x8_1(xx), nn ),
+ sar8( sel8x8_0(xx), nn )
+ );
+}
+
/* ------------ Averaging ------------ */
=20
ULong h_generic_calc_Avg8Ux8 ( ULong xx, ULong yy )
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h 2006-12-=
27 01:15:29 UTC (rev 1702)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/h_generic_simd64.h 2006-12-=
27 04:21:05 UTC (rev 1703)
@@ -114,6 +114,7 @@
extern ULong h_generic_calc_ShrN16x4 ( ULong, UInt );
extern ULong h_generic_calc_ShrN32x2 ( ULong, UInt );
=20
+extern ULong h_generic_calc_SarN8x8 ( ULong, UInt );
extern ULong h_generic_calc_SarN16x4 ( ULong, UInt );
extern ULong h_generic_calc_SarN32x2 ( ULong, UInt );
=20
Modified: branches/VEX_3_2_BRANCH/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-x86/isel.c 2006-12-27 01:15:29 UTC =
(rev 1702)
+++ branches/VEX_3_2_BRANCH/priv/host-x86/isel.c 2006-12-27 04:21:05 UTC =
(rev 1703)
@@ -2223,6 +2223,8 @@
fn =3D (HWord)h_generic_calc_SarN32x2; goto shifty;
case Iop_SarN16x4:
fn =3D (HWord)h_generic_calc_SarN16x4; goto shifty;
+ case Iop_SarN8x8:
+ fn =3D (HWord)h_generic_calc_SarN8x8; goto shifty;
shifty: {
/* Note: the following assumes all helpers are of
signature=20
Modified: branches/VEX_3_2_BRANCH/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/ir/irdefs.c 2006-12-27 01:15:29 UTC (rev=
1702)
+++ branches/VEX_3_2_BRANCH/priv/ir/irdefs.c 2006-12-27 04:21:05 UTC (rev=
1703)
@@ -340,6 +340,7 @@
case Iop_ShlN32x2: vex_printf("ShlN32x2"); return;
case Iop_ShrN16x4: vex_printf("ShrN16x4"); return;
case Iop_ShrN32x2: vex_printf("ShrN32x2"); return;
+ case Iop_SarN8x8: vex_printf("SarN8x8"); return;
case Iop_SarN16x4: vex_printf("SarN16x4"); return;
case Iop_SarN32x2: vex_printf("SarN32x2"); return;
case Iop_QNarrow16Ux4: vex_printf("QNarrow16Ux4"); return;
@@ -1471,7 +1472,7 @@
=20
case Iop_ShlN32x2: case Iop_ShlN16x4:
case Iop_ShrN32x2: case Iop_ShrN16x4:
- case Iop_SarN32x2: case Iop_SarN16x4:
+ case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8:
BINARY(Ity_I64,Ity_I8, Ity_I64);
=20
case Iop_Shl8: case Iop_Shr8: case Iop_Sar8:
Modified: branches/VEX_3_2_BRANCH/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2006-12-27 01:15:29 UTC (rev =
1702)
+++ branches/VEX_3_2_BRANCH/pub/libvex_ir.h 2006-12-27 04:21:05 UTC (rev =
1703)
@@ -494,9 +494,9 @@
Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2,
=20
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
- Iop_ShlN16x4, Iop_ShlN32x2,
- Iop_ShrN16x4, Iop_ShrN32x2,
- Iop_SarN16x4, Iop_SarN32x2,
+ Iop_ShlN16x4, Iop_ShlN32x2,
+ Iop_ShrN16x4, Iop_ShrN32x2,
+ Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2,
=20
/* NARROWING -- narrow 2xI64 into 1xI64, hi half from left arg */
Iop_QNarrow16Ux4,
|
|
From: Tom H. <to...@co...> - 2006-12-27 03:55:14
|
Nightly build on dunsmere ( athlon, Fedora Core 6 ) started at 2006-12-27 03:30:07 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 252 tests, 5 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
|
From: Tom H. <th...@cy...> - 2006-12-27 03:24:36
|
Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2006-12-27 03:10:06 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 280 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
|
From: <sv...@va...> - 2006-12-27 01:17:02
|
Author: sewardj
Date: 2006-12-27 01:16:58 +0000 (Wed, 27 Dec 2006)
New Revision: 6441
Log:
Handle new primop Iop_SarN8x8 introduced in vex r1702.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_translate.c 2006-12-26 04:51:50 UTC (rev 6440)
+++ trunk/memcheck/mc_translate.c 2006-12-27 01:16:58 UTC (rev 6441)
@@ -1843,6 +1843,7 @@
=20
case Iop_ShrN16x4:
case Iop_ShrN32x2:
+ case Iop_SarN8x8:
case Iop_SarN16x4:
case Iop_SarN32x2:
case Iop_ShlN16x4:
|
|
From: <js...@ac...> - 2006-12-27 01:16:12
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2006-12-27 02:00:01 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 221 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <sv...@va...> - 2006-12-27 01:15:42
|
Author: sewardj
Date: 2006-12-27 01:15:29 +0000 (Wed, 27 Dec 2006)
New Revision: 1702
Log:
x86 front end: Implement MASKMOVQ (MMX class insn, introduced in SSE1)
and MASKMOVDQU (SSE class insn, introduced in SSE2).
Modified:
trunk/priv/guest-x86/toIR.c
trunk/priv/host-generic/h_generic_simd64.c
trunk/priv/host-generic/h_generic_simd64.h
trunk/priv/host-x86/isel.c
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2006-12-26 02:37:38 UTC (rev 1701)
+++ trunk/priv/guest-x86/toIR.c 2006-12-27 01:15:29 UTC (rev 1702)
@@ -5679,6 +5679,38 @@
break;
}
=20
+ case 0xF7: {
+ IRTemp addr =3D newTemp(Ity_I32);
+ IRTemp regD =3D newTemp(Ity_I64);
+ IRTemp regM =3D newTemp(Ity_I64);
+ IRTemp mask =3D newTemp(Ity_I64);
+ IRTemp olddata =3D newTemp(Ity_I64);
+ IRTemp newdata =3D newTemp(Ity_I64);
+
+ modrm =3D getIByte(delta);
+ if (sz !=3D 4 || (!epartIsReg(modrm)))
+ goto mmx_decode_failure;
+ delta++;
+
+ assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) ));
+ assign( regM, getMMXReg( eregOfRM(modrm) ));
+ assign( regD, getMMXReg( gregOfRM(modrm) ));
+ assign( mask, binop(Iop_SarN8x8, mkexpr(regM), mkU8(7)) );
+ assign( olddata, loadLE( Ity_I64, mkexpr(addr) ));
+ assign( newdata,=20
+ binop(Iop_Or64,=20
+ binop(Iop_And64,=20
+ mkexpr(regD),=20
+ mkexpr(mask) ),
+ binop(Iop_And64,=20
+ mkexpr(olddata),
+ unop(Iop_Not64, mkexpr(mask)))) );
+ storeLE( mkexpr(addr), mkexpr(newdata) );
+ DIP("maskmovq %s,%s\n", nameMMXReg( eregOfRM(modrm) ),
+ nameMMXReg( gregOfRM(modrm) ) );
+ break;
+ }
+
/* --- MMX decode failure --- */
default:
mmx_decode_failure:
@@ -7670,6 +7702,16 @@
goto decode_success;
}
=20
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F F7 =3D MASKMOVQ -- 8x8 masked store */
+ if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF7) {
+ Bool ok =3D False;
+ delta =3D dis_MMX( &ok, sorb, sz, delta+1 );
+ if (!ok)
+ goto decode_failure;
+ goto decode_success;
+ }
+
/* 0F 5F =3D MAXPS -- max 32Fx4 from R/M to R */
if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5F) {
delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "maxps", Iop_Max32Fx4=
);
@@ -9314,6 +9356,50 @@
/* else fall through */
}
=20
+ /* 66 0F F7 =3D MASKMOVDQU -- store selected bytes of double quadword=
*/
+ if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF7) {
+ modrm =3D getIByte(delta+2);
+ if (sz =3D=3D 2 && epartIsReg(modrm)) {
+ IRTemp regD =3D newTemp(Ity_V128);
+ IRTemp mask =3D newTemp(Ity_V128);
+ IRTemp olddata =3D newTemp(Ity_V128);
+ IRTemp newdata =3D newTemp(Ity_V128);
+ addr =3D newTemp(Ity_I32);
+
+ assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) ));
+ assign( regD, getXMMReg( gregOfRM(modrm) ));
+
+ /* Unfortunately can't do the obvious thing with SarN8x16
+ here since that can't be re-emitted as SSE2 code - no such
+ insn. */
+ assign(=20
+ mask,=20
+ binop(Iop_64HLtoV128,
+ binop(Iop_SarN8x8,=20
+ getXMMRegLane64( eregOfRM(modrm), 1 ),=20
+ mkU8(7) ),
+ binop(Iop_SarN8x8,=20
+ getXMMRegLane64( eregOfRM(modrm), 0 ),=20
+ mkU8(7) ) ));
+ assign( olddata, loadLE( Ity_V128, mkexpr(addr) ));
+ assign( newdata,=20
+ binop(Iop_OrV128,=20
+ binop(Iop_AndV128,=20
+ mkexpr(regD),=20
+ mkexpr(mask) ),
+ binop(Iop_AndV128,=20
+ mkexpr(olddata),
+ unop(Iop_NotV128, mkexpr(mask)))) );
+ storeLE( mkexpr(addr), mkexpr(newdata) );
+
+ delta +=3D 2+1;
+ DIP("maskmovdqu %s,%s\n", nameXMMReg( eregOfRM(modrm) ),
+ nameXMMReg( gregOfRM(modrm) ) );
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
/* 66 0F E7 =3D MOVNTDQ -- for us, just a plain SSE store. */
if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xE7) {
modrm =3D getIByte(delta+2);
Modified: trunk/priv/host-generic/h_generic_simd64.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-generic/h_generic_simd64.c 2006-12-26 02:37:38 UTC (r=
ev 1701)
+++ trunk/priv/host-generic/h_generic_simd64.c 2006-12-27 01:15:29 UTC (r=
ev 1702)
@@ -299,6 +299,11 @@
/* shifts: we don't care about out-of-range ones, since
that is dealt with at a higher level. */
=20
+static inline UChar sar8 ( UChar v, UInt n )
+{
+ return toUChar(((Char)v) >> n);
+}
+
static inline UShort shl16 ( UShort v, UInt n )
{
return toUShort(v << n);
@@ -868,6 +873,22 @@
);
}
=20
+ULong h_generic_calc_SarN8x8 ( ULong xx, UInt nn )
+{
+ /* vassert(nn < 8); */
+ nn &=3D 7;
+ return mk8x8(
+ sar8( sel8x8_7(xx), nn ),
+ sar8( sel8x8_6(xx), nn ),
+ sar8( sel8x8_5(xx), nn ),
+ sar8( sel8x8_4(xx), nn ),
+ sar8( sel8x8_3(xx), nn ),
+ sar8( sel8x8_2(xx), nn ),
+ sar8( sel8x8_1(xx), nn ),
+ sar8( sel8x8_0(xx), nn )
+ );
+}
+
/* ------------ Averaging ------------ */
=20
ULong h_generic_calc_Avg8Ux8 ( ULong xx, ULong yy )
Modified: trunk/priv/host-generic/h_generic_simd64.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-generic/h_generic_simd64.h 2006-12-26 02:37:38 UTC (r=
ev 1701)
+++ trunk/priv/host-generic/h_generic_simd64.h 2006-12-27 01:15:29 UTC (r=
ev 1702)
@@ -114,6 +114,7 @@
extern ULong h_generic_calc_ShrN16x4 ( ULong, UInt );
extern ULong h_generic_calc_ShrN32x2 ( ULong, UInt );
=20
+extern ULong h_generic_calc_SarN8x8 ( ULong, UInt );
extern ULong h_generic_calc_SarN16x4 ( ULong, UInt );
extern ULong h_generic_calc_SarN32x2 ( ULong, UInt );
=20
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2006-12-26 02:37:38 UTC (rev 1701)
+++ trunk/priv/host-x86/isel.c 2006-12-27 01:15:29 UTC (rev 1702)
@@ -2223,6 +2223,8 @@
fn =3D (HWord)h_generic_calc_SarN32x2; goto shifty;
case Iop_SarN16x4:
fn =3D (HWord)h_generic_calc_SarN16x4; goto shifty;
+ case Iop_SarN8x8:
+ fn =3D (HWord)h_generic_calc_SarN8x8; goto shifty;
shifty: {
/* Note: the following assumes all helpers are of
signature=20
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2006-12-26 02:37:38 UTC (rev 1701)
+++ trunk/priv/ir/irdefs.c 2006-12-27 01:15:29 UTC (rev 1702)
@@ -340,6 +340,7 @@
case Iop_ShlN32x2: vex_printf("ShlN32x2"); return;
case Iop_ShrN16x4: vex_printf("ShrN16x4"); return;
case Iop_ShrN32x2: vex_printf("ShrN32x2"); return;
+ case Iop_SarN8x8: vex_printf("SarN8x8"); return;
case Iop_SarN16x4: vex_printf("SarN16x4"); return;
case Iop_SarN32x2: vex_printf("SarN32x2"); return;
case Iop_QNarrow16Ux4: vex_printf("QNarrow16Ux4"); return;
@@ -1477,7 +1478,7 @@
=20
case Iop_ShlN32x2: case Iop_ShlN16x4:
case Iop_ShrN32x2: case Iop_ShrN16x4:
- case Iop_SarN32x2: case Iop_SarN16x4:
+ case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8:
BINARY(Ity_I64,Ity_I8, Ity_I64);
=20
case Iop_Shl8: case Iop_Shr8: case Iop_Sar8:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2006-12-26 02:37:38 UTC (rev 1701)
+++ trunk/pub/libvex_ir.h 2006-12-27 01:15:29 UTC (rev 1702)
@@ -681,9 +681,9 @@
Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2,
=20
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
- Iop_ShlN16x4, Iop_ShlN32x2,
- Iop_ShrN16x4, Iop_ShrN32x2,
- Iop_SarN16x4, Iop_SarN32x2,
+ Iop_ShlN16x4, Iop_ShlN32x2,
+ Iop_ShrN16x4, Iop_ShrN32x2,
+ Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2,
=20
/* NARROWING -- narrow 2xI64 into 1xI64, hi half from left arg */
Iop_QNarrow16Ux4,
|