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From: Bryan M. <om...@br...> - 2006-08-04 20:37:47
|
Fellow Valgrinders, please check my small web page for the details: http://www.brainmurders.eclipse.co.uk/covergrind.html >From the web page: ------------------ Covergrind is a code coverage tool for the excellent Valgrind framework. Rather than having to link against strange libraries or compile in various support, Covergrind uses run time instrumentation in order to work out which parts of your source code are traversed. There have been comments made about how trivial it would be to use the Valgrind framework to construct such a tool but I wasn't able to find one so here is mine to share. ------------------ Basically does what it says - run your program with Covergrind and it will output a list of filenames and line number ranges in a simple man/machine readable format so you can check your code coverage. I am hoping to put a simple GUI together to read the output and colour source files accordingly but I haven't got there yet (I normally do low level and device driver stuff so go easy on me :P). The main advantage of this tool (beyond the standard Valgrind advantages of not having to mess around with your source code or build system) is that it is lightweight compared to Memcheck or Callgrind, mainly because it is only providing a single tiny set of functionality. A secondary advantage is that if you are set up to Valgrind your code, you are also set up to Covergrind it... Only tested on x86_64 so far but may well work on other platforms. Feel free to give it a spin and post your experiences to the list. As ever, I welcome your comments and bug reports. Bryan "Brain Murders" Meredith ps. Julian/Nick - happy to change the name if you are uncomfortable with it for ANY reason. |
|
From: <sv...@va...> - 2006-08-04 14:51:24
|
Author: sewardj
Date: 2006-08-04 15:51:19 +0100 (Fri, 04 Aug 2006)
New Revision: 1636
Log:
64-bit equivalent to r1635: handle all SSE3 instructions except
monitor and mwait in 64-bit mode. Regression tests to follow soon.
Modified:
trunk/priv/guest-amd64/toIR.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2006-08-03 15:03:19 UTC (rev 1635)
+++ trunk/priv/guest-amd64/toIR.c 2006-08-04 14:51:19 UTC (rev 1636)
@@ -5127,6 +5127,13 @@
loadLE(Ity_I32, mkexpr(addr))));
break;
=20
+ case 1: /* FISTTPL m32 (SSE3) */
+ DIP("fisttpl %s\n", dis_buf);
+ storeLE( mkexpr(addr),=20
+ binop(Iop_F64toI32, mkU32(Irrm_ZERO), get_ST(0))=
);
+ fp_pop();
+ break;
+
case 2: /* FIST m32 */
DIP("fistl %s\n", dis_buf);
storeLE( mkexpr(addr),=20
@@ -5444,6 +5451,13 @@
put_ST(0, loadLE(Ity_F64, mkexpr(addr)));
break;
=20
+ case 1: /* FISTTPQ m64 (SSE3) */
+ DIP("fistppll %s\n", dis_buf);
+ storeLE( mkexpr(addr),=20
+ binop(Iop_F64toI64, mkU32(Irrm_ZERO), get_ST(0))=
);
+ fp_pop();
+ break;
+
case 2: /* FST double-real */
DIP("fstl %s\n", dis_buf);
storeLE(mkexpr(addr), get_ST(0));
@@ -5776,6 +5790,14 @@
loadLE(Ity_I16, mkexpr(addr)))));
break;
=20
+ case 1: /* FISTTPS m16 (SSE3) */
+ DIP("fisttps %s\n", dis_buf);
+ storeLE( mkexpr(addr),=20
+ unop(Iop_32to16,
+ binop(Iop_F64toI32, mkU32(Irrm_ZERO), get_S=
T(0))) );
+ fp_pop();
+ break;
+
//.. case 2: /* FIST m16 */
//.. DIP("fistp %s\n", dis_buf);
//.. storeLE( mkexpr(addr),=20
@@ -11745,11 +11767,255 @@
goto decode_success;
}
=20
-
/* ---------------------------------------------------- */
/* --- end of the SSE/SSE2 decoder. --- */
/* ---------------------------------------------------- */
=20
+ /* ---------------------------------------------------- */
+ /* --- start of the SSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* F3 0F 12 =3D MOVSLDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (2:2:0:0). */
+ /* F3 0F 16 =3D MOVSHDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (3:3:1:1). */
+ if (haveF3no66noF2(pfx) && sz =3D=3D 4
+ && insn[0] =3D=3D 0x0F && (insn[1] =3D=3D 0x12 || insn[1] =3D=3D =
0x16)) {
+ IRTemp s3, s2, s1, s0;
+ IRTemp sV =3D newTemp(Ity_V128);
+ Bool isH =3D insn[1] =3D=3D 0x16;
+ s3 =3D s2 =3D s1 =3D s0 =3D IRTemp_INVALID;
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l',
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l',
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ breakup128to32s( sV, &s3, &s2, &s1, &s0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ isH ? mk128from32s( s3, s3, s1, s1 )
+ : mk128from32s( s2, s2, s0, s0 ) );
+ goto decode_success;
+ }
+
+ /* F2 0F 12 =3D MOVDDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (0:1:0:1). */
+ if (haveF2no66noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x12) {
+ IRTemp sV =3D newTemp(Ity_V128);
+ IRTemp d0 =3D newTemp(Ity_I64);
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("movddup %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ assign ( d0, unop(Iop_V128to64, mkexpr(sV)) );
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( d0, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movddup %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ binop(Iop_64HLtoV128,mkexpr(d0),mkexpr(d0)) );
+ goto decode_success;
+ }
+
+ /* F2 0F D0 =3D ADDSUBPS -- 32x4 +/-/+/- from E (mem or xmm) to G (xm=
m). */
+ if (haveF2no66noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD0) {
+ IRTemp a3, a2, a1, a0, s3, s2, s1, s0;
+ IRTemp eV =3D newTemp(Ity_V128);
+ IRTemp gV =3D newTemp(Ity_V128);
+ IRTemp addV =3D newTemp(Ity_V128);
+ IRTemp subV =3D newTemp(Ity_V128);
+ a3 =3D a2 =3D a1 =3D a0 =3D s3 =3D s2 =3D s1 =3D s0 =3D IRTemp_INV=
ALID;
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("addsubps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("addsubps %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ assign( addV, binop(Iop_Add32Fx4, mkexpr(gV), mkexpr(eV)) );
+ assign( subV, binop(Iop_Sub32Fx4, mkexpr(gV), mkexpr(eV)) );
+
+ breakup128to32s( addV, &a3, &a2, &a1, &a0 );
+ breakup128to32s( subV, &s3, &s2, &s1, &s0 );
+
+ putXMMReg( gregOfRexRM(pfx,modrm), mk128from32s( a3, s2, a1, s0 ))=
;
+ goto decode_success;
+ }
+
+ /* 66 0F D0 =3D ADDSUBPD -- 64x4 +/- from E (mem or xmm) to G (xmm). =
*/
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD0) {
+ IRTemp eV =3D newTemp(Ity_V128);
+ IRTemp gV =3D newTemp(Ity_V128);
+ IRTemp addV =3D newTemp(Ity_V128);
+ IRTemp subV =3D newTemp(Ity_V128);
+ IRTemp a1 =3D newTemp(Ity_I64);
+ IRTemp s0 =3D newTemp(Ity_I64);
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("addsubpd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("addsubpd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ assign( addV, binop(Iop_Add64Fx2, mkexpr(gV), mkexpr(eV)) );
+ assign( subV, binop(Iop_Sub64Fx2, mkexpr(gV), mkexpr(eV)) );
+
+ assign( a1, unop(Iop_V128HIto64, mkexpr(addV) ));
+ assign( s0, unop(Iop_V128to64, mkexpr(subV) ));
+
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ binop(Iop_64HLtoV128, mkexpr(a1), mkexpr(s0)) );
+ goto decode_success;
+ }
+
+ /* F2 0F 7D =3D HSUBPS -- 32x4 sub across from E (mem or xmm) to G (x=
mm). */
+ /* F2 0F 7C =3D HADDPS -- 32x4 add across from E (mem or xmm) to G (x=
mm). */
+ if (haveF2no66noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && (insn[1] =3D=3D 0x7C || insn[1] =3D=3D =
0x7D)) {
+ IRTemp e3, e2, e1, e0, g3, g2, g1, g0;
+ IRTemp eV =3D newTemp(Ity_V128);
+ IRTemp gV =3D newTemp(Ity_V128);
+ IRTemp leftV =3D newTemp(Ity_V128);
+ IRTemp rightV =3D newTemp(Ity_V128);
+ Bool isAdd =3D insn[1] =3D=3D 0x7C;
+ HChar* str =3D isAdd ? "add" : "sub";
+ e3 =3D e2 =3D e1 =3D e0 =3D g3 =3D g2 =3D g1 =3D g0 =3D IRTemp_INV=
ALID;
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("h%sps %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("h%sps %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ breakup128to32s( eV, &e3, &e2, &e1, &e0 );
+ breakup128to32s( gV, &g3, &g2, &g1, &g0 );
+
+ assign( leftV, mk128from32s( e2, e0, g2, g0 ) );
+ assign( rightV, mk128from32s( e3, e1, g3, g1 ) );
+
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4,=20
+ mkexpr(leftV), mkexpr(rightV) ) );
+ goto decode_success;
+ }
+
+ /* 66 0F 7D =3D HSUBPD -- 64x2 sub across from E (mem or xmm) to G (x=
mm). */
+ /* 66 0F 7C =3D HADDPD -- 64x2 add across from E (mem or xmm) to G (x=
mm). */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && (insn[1] =3D=3D 0x7C || insn[1] =3D=3D =
0x7D)) {
+ IRTemp e1 =3D newTemp(Ity_I64);
+ IRTemp e0 =3D newTemp(Ity_I64);
+ IRTemp g1 =3D newTemp(Ity_I64);
+ IRTemp g0 =3D newTemp(Ity_I64);
+ IRTemp eV =3D newTemp(Ity_V128);
+ IRTemp gV =3D newTemp(Ity_V128);
+ IRTemp leftV =3D newTemp(Ity_V128);
+ IRTemp rightV =3D newTemp(Ity_V128);
+ Bool isAdd =3D insn[1] =3D=3D 0x7C;
+ HChar* str =3D isAdd ? "add" : "sub";
+
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
+ DIP("h%spd %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("h%spd %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+
+ assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ assign( e1, unop(Iop_V128HIto64, mkexpr(eV) ));
+ assign( e0, unop(Iop_V128to64, mkexpr(eV) ));
+ assign( g1, unop(Iop_V128HIto64, mkexpr(gV) ));
+ assign( g0, unop(Iop_V128to64, mkexpr(gV) ));
+
+ assign( leftV, binop(Iop_64HLtoV128, mkexpr(e0),mkexpr(g0)) );
+ assign( rightV, binop(Iop_64HLtoV128, mkexpr(e1),mkexpr(g1)) );
+
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2,=20
+ mkexpr(leftV), mkexpr(rightV) ) );
+ goto decode_success;
+ }
+
+ /* F2 0F F0 =3D LDDQU -- move from E (mem or xmm) to G (xmm). */
+ if (haveF2no66noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF0) {
+ modrm =3D insn[2];
+ if (epartIsReg(modrm)) {
+ goto decode_failure;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),=20
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("lddqu %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta +=3D 2+alen;
+ }
+ goto decode_success;
+ }
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
/*after_sse_decoders:*/
=20
/* Get the primary opcode. */
|
|
From: <sv...@va...> - 2006-08-04 12:42:13
|
Author: sewardj
Date: 2006-08-04 13:42:06 +0100 (Fri, 04 Aug 2006)
New Revision: 5996
Log:
Update expected output following Graydon H's leak checker fixes.
Modified:
trunk/memcheck/tests/mempool.stderr.exp
Modified: trunk/memcheck/tests/mempool.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/mempool.stderr.exp 2006-08-01 17:26:38 UTC (rev =
5995)
+++ trunk/memcheck/tests/mempool.stderr.exp 2006-08-04 12:42:06 UTC (rev =
5996)
@@ -35,7 +35,25 @@
by 0x........: main (mempool.c:148)
=20
=20
-100,028 (20 direct, 100,008 indirect) bytes in 1 blocks are definitely l=
ost in loss record 2 of 3
+10 bytes in 1 blocks are definitely lost in loss record 2 of 5
+ at 0x........: allocate (mempool.c:99)
+ by 0x........: test (mempool.c:135)
+ by 0x........: main (mempool.c:148)
+
+
+10 bytes in 1 blocks are definitely lost in loss record 3 of 5
+ at 0x........: allocate (mempool.c:99)
+ by 0x........: test (mempool.c:115)
+ by 0x........: main (mempool.c:148)
+
+
+20 bytes in 1 blocks are definitely lost in loss record 4 of 5
+ at 0x........: allocate (mempool.c:99)
+ by 0x........: test (mempool.c:116)
+ by 0x........: main (mempool.c:148)
+
+
+28 (20 direct, 8 indirect) bytes in 1 blocks are definitely lost in loss=
record 5 of 5
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: make_pool (mempool.c:37)
by 0x........: test (mempool.c:111)
|
|
From: <js...@ac...> - 2006-08-04 09:00:11
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2006-08-04 09:00:02 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 206 tests, 11 stderr failures, 5 stdout failures, 0 posttest failures == memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) |
|
From: Nicholas N. <nj...@cs...> - 2006-08-04 03:41:27
|
On Fri, 4 Aug 2006, Julian Seward wrote: >> Are you planning to merge this to the stable branch? > > Yes, definitely. Yes, I'd like to ship 3.2.1 in the next three weeks > or so. 3.2.0 seems pretty stable but there have been a couple of things > cropped up, not least that the latest binutils completely breaks 3.2.0 > by using a new previously unheard-of (at least by me :) form on no-ops > on x86 and amd64. Good. > Any other specific bugs you think we should try to fix for 3.2.1 ? Nope. Nick |
|
From: <js...@ac...> - 2006-08-04 02:58:46
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2006-08-04 03:30:01 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 235 tests, 5 stderr failures, 0 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) |
|
From: Tom H. <to...@co...> - 2006-08-04 02:45:40
|
Nightly build on dunsmere ( athlon, Fedora Core 5 ) started at 2006-08-04 03:30:05 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 237 tests, 5 stderr failures, 0 stdout failures, 0 posttest failures == memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) |
|
From: Tom H. <th...@cy...> - 2006-08-04 02:32:34
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2006-08-04 03:15:02 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 236 tests, 19 stderr failures, 0 stdout failures, 0 posttest failures == memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/mempool (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/xml1 (stderr) |
|
From: Tom H. <th...@cy...> - 2006-08-04 02:26:47
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2006-08-04 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 260 tests, 5 stderr failures, 0 stdout failures, 0 posttest failures == memcheck/tests/mempool (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) |
|
From: Tom H. <th...@cy...> - 2006-08-04 02:25:49
|
Nightly build on dellow ( x86_64, Fedora Core 5 ) started at 2006-08-04 03:10:06 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 260 tests, 3 stderr failures, 0 stdout failures, 0 posttest failures == memcheck/tests/mempool (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) |
|
From: Julian S. <js...@ac...> - 2006-08-04 00:13:06
|
> Are you planning to merge this to the stable branch? Yes, definitely. Yes, I'd like to ship 3.2.1 in the next three weeks or so. 3.2.0 seems pretty stable but there have been a couple of things cropped up, not least that the latest binutils completely breaks 3.2.0 by using a new previously unheard-of (at least by me :) form on no-ops on x86 and amd64. Any other specific bugs you think we should try to fix for 3.2.1 ? J |
|
From: Nicholas N. <nj...@cs...> - 2006-08-04 00:02:55
|
On Thu, 3 Aug 2006 sv...@va... wrote: > Log: > Handle all SSE3 instructions except monitor and mwait. 64-bit > equivalents to follow soon. Are you planning to merge this to the stable branch? I think it's a good idea, it's not strictly a bug-fix but it seems like it would be good to get it out there sooner in 3.2.1 rather than waiting for a 3.3.0 release. Nick |