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|
From: Nicholas N. <nj...@cs...> - 2006-03-06 23:36:54
|
On Mon, 6 Mar 2006, Bart Van Assche wrote: > As far as I know there is currently one thread-related event that > is tracked by valgrind, and that is track_post_thread_create. I found > the following statement in file coregrind/m_syswrap/thread_wrapper(): > VG_TRACK ( post_thread_create, tst->os_state.parent, tid ); That sounds right. There was post_mutex_lock and others but they're currently not working. > I'm sorry to say but none of both approaches is sufficient. The > problem is that there exist functions like pthread_cond_wait(). The > drd tool has to be notified both after pthread_cond_wait() unlocks its > mutex and after pthread_cond_wait() locked its mutex again. I think > the only way to implement this properly is via a thread model. Perhaps I missed some email about this -- this tool is a data-race detector, right? How is it different to Helgrind? Nick |
|
From: Josef W. <Jos...@gm...> - 2006-03-06 23:15:56
|
On Monday 06 March 2006 22:49, you wrote: > Certainly it's true that the 'end' parameter is unnecessary since all > IR loads/stores contain the endianness, so you can just call load_le > or load_be like in memcheck. > > > I just see that it is not easy (or even impossible?) to get the guest > > endiness at instrumentation time. > > Huh? Not so; see above. Ah, sorry, yes. I was confused. So to clarify (for myself, too): to get rid of the endianness parameter in the callback, one would write two versions of the callback, one for BE and one for LE, and instrument a callback to the correct version depending on the endianness given for the IR. > Because it means the meaning of any IR load/store can be then known > just by inspecting the load/store, and not looking at any other info. Agree. Simply forget my confused suggestion :-) > Anyway, who says the guest only has one endianness? On ppc we have > (eg) lwz and lwbrx, which give both endiannesses. Ah, thanks. I did not know. Josef |
|
From: Julian S. <js...@ac...> - 2006-03-06 21:50:01
|
> > +static VG_REGPARM(3) void trace_load(Addr addr, SizeT size, IREndness
> > end)
>
> Hmm...
> Why adding this additional parameter "end" to every load/store callback?
> Isn't the endiness supposed to be constant at least in one program run?
> In general it is always better for performance to do as little as possible
> in a callback, therefore this remark (which is not really relevant here).
Certainly it's true that the 'end' parameter is unnecessary since all=20
IR loads/stores contain the endianness, so you can just call load_le=20
or load_be like in memcheck.=20
> I just see that it is not easy (or even impossible?) to get the guest
> endiness at instrumentation time.
Huh? Not so; see above.
> Julian: Why was this done this way? Wouldn't it be better to add the
> guest endiness to VexGuestLayout instead of (redundantly) to every
> Load/Store IR?
Because it means the meaning of any IR load/store can be then known=20
just by inspecting the load/store, and not looking at any other info.
Anyway, who says the guest only has one endianness? On ppc we have
(eg) lwz and lwbrx, which give both endiannesses.
> > +static void print_jumpkind(Int kind)
> > +{
> > + =C2=A0/* Print Jump Kind. You could print what you like later. */
> > + =C2=A0switch (kind)
> > + =C2=A0 =C2=A0{
> > + =C2=A0 =C2=A0case Ijk_Boring:
> > + =C2=A0 =C2=A0case Ijk_TInval:
> > + =C2=A0 =C2=A0case Ijk_Ret:
> > + =C2=A0 =C2=A0case Ijk_Call:
> > + =C2=A0 =C2=A0case Ijk_Sys_syscall:
> > + =C2=A0 =C2=A0case Ijk_Sys_int128:
> > + =C2=A0 =C2=A0case Ijk_Sys_int32:
> > + =C2=A0 =C2=A0case Ijk_Sys_sysenter:
> > + =C2=A0 =C2=A0case Ijk_EmWarn:
> > + =C2=A0 =C2=A0 =C2=A0VG_(printf)("G\n");
>
> What is the semantic of "G"? If it is "gap in instruction stream",
> Boring/Ret/Call probably should not output it.
I agree.
Also TInval should not output it, since that's just the implementation
for 'icbi'. You need to define what "gap in instruction stream"
really means. A system call?
> > + =C2=A0if (VG_(get_fnname_if_entry)(instruction,
> > func_name_buf,sizeof(func_name_buf))) + =C2=A0 =C2=A0VG_(printf)(" ;
> > %s",func_name_buf);
>
> This is quite expensive to do for every instruction executed. And it is
> really easy to move to instrumentation time: provide a flag "this is a
> function entry" to the callback.
Agree.
J
|
|
From: Josef W. <Jos...@gm...> - 2006-03-06 20:17:12
|
Hi,
On Monday 06 March 2006 09:01, Yao Qi wrote:
> +static void print_data (Addr addr, HWord size, IREndness end)
> {
> - VG_(printf)("load : %p, %d\n", addr, size);
> ...
Why not keep the data size as part of the output for a memory access?
I see that the size can be computed from the length of the data, which is p=
rinted
at the end; but it is easier to look at a real number, and to parse it eg. =
with a
PERL script...
> +static VG_REGPARM(3) void trace_load(Addr addr, SizeT size, IREndness en=
d)
Hmm...
Why adding this additional parameter "end" to every load/store callback?
Isn't the endiness supposed to be constant at least in one program run?
In general it is always better for performance to do as little as possible
in a callback, therefore this remark (which is not really relevant here).
I just see that it is not easy (or even impossible?) to get the guest=20
endiness at instrumentation time.
Julian: Why was this done this way? Wouldn't it be better to add the
guest endiness to VexGuestLayout instead of (redundantly) to every
Load/Store IR?
> +static void print_jumpkind(Int kind)
> +{
> + =C2=A0/* Print Jump Kind. You could print what you like later. */
> + =C2=A0switch (kind)
> + =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0case Ijk_Boring:
> + =C2=A0 =C2=A0case Ijk_TInval:
> + =C2=A0 =C2=A0case Ijk_Ret:
> + =C2=A0 =C2=A0case Ijk_Call:
> + =C2=A0 =C2=A0case Ijk_Sys_syscall:
> + =C2=A0 =C2=A0case Ijk_Sys_int128:
> + =C2=A0 =C2=A0case Ijk_Sys_int32:
> + =C2=A0 =C2=A0case Ijk_Sys_sysenter:
> + =C2=A0 =C2=A0case Ijk_EmWarn:
> + =C2=A0 =C2=A0 =C2=A0VG_(printf)("G\n");
What is the semantic of "G"? If it is "gap in instruction stream", Boring/R=
et/Call
probably should not output it.
> + =C2=A0VG_(printf)("%c ", instr_record);
> + =C2=A0/* Print instruction address. */
> + =C2=A0if (instr_record =3D=3D 'J')=20
> + =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0VG_(printf)("%p ", instruction);
> + =C2=A0 =C2=A0 =C2=A0instr_record =3D 'I';
> + =C2=A0 =C2=A0}
> + =C2=A0else VG_(printf)("%p ", instruction);
What is the difference between "I" and "J"? I seem to remember that "J" sho=
uld print
the address. I think it would be better to only have one format here: alway=
s print the
instruction address. IMHO it is better to not confuse a tutorial with such =
issues. The
idea of "instr_record" really is difficult to grasp.
> + =C2=A0if (VG_(get_fnname_if_entry)(instruction, func_name_buf,sizeof(fu=
nc_name_buf)))
> + =C2=A0 =C2=A0VG_(printf)(" ; %s",func_name_buf);
This is quite expensive to do for every instruction executed. And it is rea=
lly easy
to move to instrumentation time: provide a flag "this is a function entry" =
to the callback.=20
> + =C2=A0 /* Only collect the sequential instructions in one BB to make su=
re
> + =C2=A0 =C2=A0 =C2=A0that all the instructions in one BB are sequential.=
*/
> + =C2=A0 if (lk_clo_trace_instrs)
> + =C2=A0 =C2=A0 VG_(clo_vex_control).guest_chase_thresh =3D 0;
Why is this important to the tool?
> + =C2=A0 VG_(printf)("H vaglrind-itrace\n");
And this?
Josef
|
|
From: <sv...@va...> - 2006-03-06 20:04:06
|
Author: sewardj
Date: 2006-03-06 20:03:43 +0000 (Mon, 06 Mar 2006)
New Revision: 1590
Log:
Merge r1533 (Implement clflush).
Modified:
branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 19:23:30 U=
TC (rev 1589)
+++ branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 20:03:43 U=
TC (rev 1590)
@@ -395,6 +395,8 @@
#define OFFB_XMM15 offsetof(VexGuestAMD64State,guest_XMM15)
=20
#define OFFB_EMWARN offsetof(VexGuestAMD64State,guest_EMWARN)
+#define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART)
+#define OFFB_TILEN offsetof(VexGuestAMD64State,guest_TILEN)
=20
=20
/*------------------------------------------------------------*/
@@ -11417,25 +11419,40 @@
//.. //-- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf );
//.. //-- goto decode_success;
//.. //-- }
-//.. //--=20
-//.. //-- /* CLFLUSH -- flush cache line */
-//.. //-- if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
-//.. //-- && (!epartIsReg(insn[2]))
-//.. //-- && (gregOfRM(insn[2]) =3D=3D 7))
-//.. //-- {
-//.. //-- vg_assert(sz =3D=3D 4);
-//.. //-- pair =3D disAMode ( cb, sorb, eip+2, dis_buf );
-//.. //-- t1 =3D LOW24(pair);
-//.. //-- eip +=3D 2+HI8(pair);
-//.. //-- uInstr3(cb, SSE2a_MemRd, 0, /* ignore sz for internal o=
ps */
-//.. //-- Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
-//.. //-- Lit16, (UShort)insn[2],
-//.. //-- TempReg, t1 );
-//.. //-- DIP("clflush %s\n", dis_buf);
-//.. //-- goto decode_success;
-//.. //-- }
=20
+ /* 0F AE /7 =3D CLFLUSH -- flush cache line */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE
+ && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) =3D=3D 7) {
=20
+ /* This is something of a hack. We need to know the size of the
+ cache line containing addr. Since we don't (easily), assume
+ 256 on the basis that no real cache would have a line that
+ big. It's safe to invalidate more stuff than we need, just
+ inefficient. */
+ ULong lineszB =3D 256ULL;
+
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+
+ /* Round addr down to the start of the containing block. */
+ stmt( IRStmt_Put(
+ OFFB_TISTART,
+ binop( Iop_And64,=20
+ mkexpr(addr),=20
+ mkU64( ~(lineszB-1) ))) );
+
+ stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
+
+ irbb->jumpkind =3D Ijk_TInval;
+ irbb->next =3D mkU64(guest_RIP_bbstart+delta);
+ dres.whatNext =3D Dis_StopHere;
+
+ DIP("clflush %s\n", dis_buf);
+ goto decode_success;
+ }
+
+
/* ---------------------------------------------------- */
/* --- end of the SSE/SSE2 decoder. --- */
/* ---------------------------------------------------- */
|
|
From: <sv...@va...> - 2006-03-06 19:50:16
|
Author: sewardj
Date: 2006-03-06 19:50:06 +0000 (Mon, 06 Mar 2006)
New Revision: 5715
Log:
A test for fcmovnu.
Added:
trunk/none/tests/x86/fcmovnu.c
trunk/none/tests/x86/fcmovnu.stderr.exp
trunk/none/tests/x86/fcmovnu.stdout.exp
trunk/none/tests/x86/fcmovnu.vgtest
Modified:
trunk/none/tests/x86/Makefile.am
Modified: trunk/none/tests/x86/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/Makefile.am 2006-03-06 19:36:30 UTC (rev 5714)
+++ trunk/none/tests/x86/Makefile.am 2006-03-06 19:50:06 UTC (rev 5715)
@@ -10,6 +10,7 @@
cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
faultstatus.vgtest faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
fpu_lazy_eflags.stderr.exp fpu_lazy_eflags.stdout.exp \
fpu_lazy_eflags.vgtest \
fxtract.stdout.exp fxtract.stderr.exp fxtract.vgtest \
@@ -30,7 +31,7 @@
=20
check_PROGRAMS =3D \
badseg bt_everything bt_literal cmpxchg8b cpuid \
- faultstatus fpu_lazy_eflags fxtract \
+ faultstatus fcmovnu fpu_lazy_eflags fxtract \
getseg incdec_alt $(INSN_TESTS) \
lahf looper int pushpopseg sbbmisc \
seg_override sigcontext smc1 yield
Added: trunk/none/tests/x86/fcmovnu.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/fcmovnu.c (rev 0)
+++ trunk/none/tests/x86/fcmovnu.c 2006-03-06 19:50:06 UTC (rev 5715)
@@ -0,0 +1,24 @@
+
+#include <stdio.h>
+
+double zzz;
+
+int main ( void )
+{
+ zzz =3D 1.234;
+ printf("zzz =3D %f\n", zzz);
+ __asm__ __volatile__(
+ "finit\n\t"
+ "fldpi\n\t"
+ "fldl2e\n\t"
+ "pushl %esi\n\t"
+ "movl $0,%esi\n\t"
+ "add %esi,%esi\n\t"
+ "fcmovnu %st(1), %st(0)\n\t"
+ "fstl zzz\n\t"
+ "finit\n\t"
+ "popl %esi\n\t"
+ );
+ printf("zzz =3D %f\n", zzz);
+ return 0;
+}
Added: trunk/none/tests/x86/fcmovnu.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/fcmovnu.stderr.exp (rev =
0)
+++ trunk/none/tests/x86/fcmovnu.stderr.exp 2006-03-06 19:50:06 UTC (rev =
5715)
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/x86/fcmovnu.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/fcmovnu.stdout.exp (rev =
0)
+++ trunk/none/tests/x86/fcmovnu.stdout.exp 2006-03-06 19:50:06 UTC (rev =
5715)
@@ -0,0 +1,2 @@
+zzz =3D 1.234000
+zzz =3D 1.442695
Added: trunk/none/tests/x86/fcmovnu.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/x86/fcmovnu.vgtest (rev 0)
+++ trunk/none/tests/x86/fcmovnu.vgtest 2006-03-06 19:50:06 UTC (rev 5715=
)
@@ -0,0 +1 @@
+prog: fcmovnu
|
|
From: <sv...@va...> - 2006-03-06 19:36:33
|
Author: sewardj
Date: 2006-03-06 19:36:30 +0000 (Mon, 06 Mar 2006)
New Revision: 5714
Log:
Test for fcmovnu.
Added:
trunk/none/tests/amd64/fcmovnu.c
trunk/none/tests/amd64/fcmovnu.stderr.exp
trunk/none/tests/amd64/fcmovnu.stdout.exp
trunk/none/tests/amd64/fcmovnu.vgtest
Modified:
trunk/none/tests/amd64/Makefile.am
Modified: trunk/none/tests/amd64/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/Makefile.am 2006-03-06 11:41:52 UTC (rev 5713)
+++ trunk/none/tests/amd64/Makefile.am 2006-03-06 19:36:30 UTC (rev 5714)
@@ -6,6 +6,7 @@
=20
EXTRA_DIST =3D $(noinst_SCRIPTS) \
faultstatus.vgtest faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
$(addsuffix .stderr.exp,$(INSN_TESTS)) \
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
@@ -16,7 +17,7 @@
=20
=20
check_PROGRAMS =3D \
- faultstatus $(INSN_TESTS) looper jrcxz smc1 shrld
+ faultstatus fcmovnu $(INSN_TESTS) looper jrcxz smc1 shrld
=20
AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/inc=
lude
@FLAG_M64@
Added: trunk/none/tests/amd64/fcmovnu.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/fcmovnu.c (rev 0)
+++ trunk/none/tests/amd64/fcmovnu.c 2006-03-06 19:36:30 UTC (rev 5714)
@@ -0,0 +1,24 @@
+
+#include <stdio.h>
+
+double zzz;
+
+int main ( void )
+{
+ zzz =3D 1.234;
+ printf("zzz =3D %f\n", zzz);
+ __asm__ __volatile__(
+ "finit\n\t"
+ "fldpi\n\t"
+ "fldl2e\n\t"
+ "pushq %r15\n\t"
+ "movq $0,%r15\n\t"
+ "add %r15,%r15\n\t"
+ "fcmovnu %st(1), %st(0)\n\t"
+ "fstl zzz\n\t"
+ "finit\n\t"
+ "popq %r15\n\t"
+ );
+ printf("zzz =3D %f\n", zzz);
+ return 0;
+}
Added: trunk/none/tests/amd64/fcmovnu.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/fcmovnu.stderr.exp (re=
v 0)
+++ trunk/none/tests/amd64/fcmovnu.stderr.exp 2006-03-06 19:36:30 UTC (re=
v 5714)
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/amd64/fcmovnu.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/fcmovnu.stdout.exp (re=
v 0)
+++ trunk/none/tests/amd64/fcmovnu.stdout.exp 2006-03-06 19:36:30 UTC (re=
v 5714)
@@ -0,0 +1,2 @@
+zzz =3D 1.234000
+zzz =3D 1.442695
Added: trunk/none/tests/amd64/fcmovnu.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/fcmovnu.vgtest (rev 0)
+++ trunk/none/tests/amd64/fcmovnu.vgtest 2006-03-06 19:36:30 UTC (rev 57=
14)
@@ -0,0 +1 @@
+prog: fcmovnu
|
|
From: <sv...@va...> - 2006-03-06 19:23:35
|
Author: sewardj
Date: 2006-03-06 19:23:30 +0000 (Mon, 06 Mar 2006)
New Revision: 1589
Log:
Merge r1587 (Implement fcmovnu.)
Modified:
branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 19:17:17 U=
TC (rev 1588)
+++ branches/VEX_3_1_BRANCH/priv/guest-amd64/toIR.c 2006-03-06 19:23:30 U=
TC (rev 1589)
@@ -5108,6 +5108,20 @@
);
break;
=20
+ case 0xD8 ... 0xDF: /* FCMOVNU ST(i), ST(0) */
+ r_src =3D (UInt)modrm - 0xD8;
+ DIP("fcmovnu %%st(%u), %%st(0)\n", r_src);
+ put_ST_UNCHECKED(
+ 0,=20
+ IRExpr_Mux0X(=20
+ unop(Iop_1Uto8,
+ mk_amd64g_calculate_condition(AMD64CondNP)),=20
+ get_ST(0),=20
+ get_ST(r_src)
+ )
+ );
+ break;
+
case 0xE2:
DIP("fnclex\n");
break;
|
|
From: <sv...@va...> - 2006-03-06 19:17:21
|
Author: sewardj
Date: 2006-03-06 19:17:17 +0000 (Mon, 06 Mar 2006)
New Revision: 1588
Log:
Fix debug printing.
Modified:
trunk/priv/guest-x86/toIR.c
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2006-03-06 19:05:07 UTC (rev 1587)
+++ trunk/priv/guest-x86/toIR.c 2006-03-06 19:17:17 UTC (rev 1588)
@@ -4221,7 +4221,7 @@
=20
case 0xD8 ... 0xDF: /* FCMOVU ST(i), ST(0) */
r_src =3D (UInt)modrm - 0xD8;
- DIP("fcmovnu %%st(%d), %%st(0)\n", (Int)r_src);
+ DIP("fcmovu %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,=20
IRExpr_Mux0X(=20
unop(Iop_1Uto8,
|
|
From: <sv...@va...> - 2006-03-06 19:05:16
|
Author: sewardj
Date: 2006-03-06 19:05:07 +0000 (Mon, 06 Mar 2006)
New Revision: 1587
Log:
Implement fcmovnu.
Modified:
trunk/priv/guest-amd64/toIR.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2006-03-06 14:32:00 UTC (rev 1586)
+++ trunk/priv/guest-amd64/toIR.c 2006-03-06 19:05:07 UTC (rev 1587)
@@ -5189,6 +5189,20 @@
);
break;
=20
+ case 0xD8 ... 0xDF: /* FCMOVNU ST(i), ST(0) */
+ r_src =3D (UInt)modrm - 0xD8;
+ DIP("fcmovnu %%st(%u), %%st(0)\n", r_src);
+ put_ST_UNCHECKED(
+ 0,=20
+ IRExpr_Mux0X(=20
+ unop(Iop_1Uto8,
+ mk_amd64g_calculate_condition(AMD64CondNP)),=20
+ get_ST(0),=20
+ get_ST(r_src)
+ )
+ );
+ break;
+
case 0xE2:
DIP("fnclex\n");
break;
|
|
From: Bart V. A. <bar...@gm...> - 2006-03-06 18:32:26
|
As far as I know there is currently one thread-related event that is tracked by valgrind, and that is track_post_thread_create. I found the following statement in file coregrind/m_syswrap/thread_wrapper(): VG_TRACK ( post_thread_create, tst->os_state.parent, tid ); You explained me also another approach, that is, instrumenting functions by commenting out the stuff between #if 0 / #endif in file coregrind/vg_preloaded.c. I'm sorry to say but none of both approaches is sufficient. The problem is that there exist functions like pthread_cond_wait(). The drd tool has to be notified both after pthread_cond_wait() unlocks its mutex and after pthread_cond_wait() locked its mutex again. I think the only way to implement this properly is via a thread model. On 3/6/06, Julian Seward <js...@ac...> wrote: > > Would it be more robust to have the core hand events both to the tool > and to the thread model? That means tools can get thread events even > if the thread model isn't operating. My impression from Bart is that > drd just wants to know about thread-sync points, and at least for > handling pthreads, we don't need a thread model involved for that. |
|
From: Duncan S. <bal...@fr...> - 2006-03-06 16:01:37
|
> > I don't really see a problem with leaking information into the kernel. It > > seems like a particularly safe place to send stuff! > > This is a fallacy. The kernel is a particularly *dangerous* place. > > First of all, the kernel has deliberate "observation points" *designed* > to expose what is going on: ptrace, strace, /proc/<pid>, /bin/ps, > /bin/top, etc. Yes, but if you have sufficient privileges to use them against a program, you already have sufficient privileges to eg attach a debugger to it and rummage around directly. > Second, the Linux kernel is somewhat blase about all its > privileges: it has no internal protection domains, "firewalls", etc. Are you worried about local attackers, or rather that your uninitialised bytes might accidentally be sent off in an ethernet packet or something like that? > Yes, in theory the kernel can do anything to destroy information security; > but there is no need for user-mode code to tempt the kernel and/or > make it easy for such lapses. s/easy/easier/ Although it may not appear that way, I have a plenty of sympathy for your "code hygiene" argument. Ciao, Duncan. |
|
From: John R.
|
Duncan Sands wrote: > Hi Nick, >>So I think the current policy is to only check the arguments that are used >>by the kernel, and that the mmap() wrapper was not implementing that policy >>correctly. I also appreciate John's point about leaking information into >>the kernel. > > > I don't really see a problem with leaking information into the kernel. It > seems like a particularly safe place to send stuff! This is a fallacy. The kernel is a particularly *dangerous* place. First of all, the kernel has deliberate "observation points" *designed* to expose what is going on: ptrace, strace, /proc/<pid>, /bin/ps, /bin/top, etc. Second, the Linux kernel is somewhat blase about all its privileges: it has no internal protection domains, "firewalls", etc. Yes, in theory the kernel can do anything to destroy information security; but there is no need for user-mode code to tempt the kernel and/or make it easy for such lapses. -- |
|
From: Julian S. <js...@ac...> - 2006-03-06 15:23:09
|
On Monday 06 March 2006 15:07, Tom Hughes wrote: > In message <200...@fr...> > > Duncan Sands <bal...@fr...> wrote: > >> > [arg checking for sys_clone] > >> > >> Duncan - I've just realised #117564 is exactly the problem you're > >> talking about. See https://bugs.kde.org/show_bug.cgi?id=117564 > >> You might want to look at Jeroen's patch, which is attached to > >> said web page. > > > > I see he chose to use PRRAn; I was planning to introduce a more > > descriptive name. Besides that, it looks good at first glance. Except PRRAn is used without a guarding check of if (VG_(tdict).track_pre_reg_read). Maybe you could invent a new macro with a better name and which incorporates that check. > If you are playing with the clone argument checking, be very > careful about cutting and pasting from one platform to another > as the arguments are in different orders on different platforms... Yes - I remember you fixed some swamp-age to do with this. > PS: I hope to find time to do something soon. Am hoping to finalise 3.1.1 in the next day or so, so as to ship it around Friday. If you have something by then, fine, else we can ship a fix in 3.2.0 (mid-late April). J |
|
From: Tom H. <to...@co...> - 2006-03-06 15:07:56
|
In message <200...@fr...>
Duncan Sands <bal...@fr...> wrote:
>> > [arg checking for sys_clone]
>>
>> Duncan - I've just realised #117564 is exactly the problem you're
>> talking about. See https://bugs.kde.org/show_bug.cgi?id=117564
>> You might want to look at Jeroen's patch, which is attached to
>> said web page.
>
> I see he chose to use PRRAn; I was planning to introduce a more
> descriptive name. Besides that, it looks good at first glance.
If you are playing with the clone argument checking, be very
careful about cutting and pasting from one platform to another
as the arguments are in different orders on different platforms...
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
|
|
From: Duncan S. <bal...@fr...> - 2006-03-06 14:51:59
|
> > [arg checking for sys_clone] > > Duncan - I've just realised #117564 is exactly the problem you're > talking about. See https://bugs.kde.org/show_bug.cgi?id=117564 > You might want to look at Jeroen's patch, which is attached to > said web page. I see he chose to use PRRAn; I was planning to introduce a more descriptive name. Besides that, it looks good at first glance. Ciao, D. PS: I hope to find time to do something soon. |
|
From: Julian S. <js...@ac...> - 2006-03-06 14:41:29
|
> [arg checking for sys_clone] Duncan - I've just realised #117564 is exactly the problem you're talking about. See https://bugs.kde.org/show_bug.cgi?id=117564 You might want to look at Jeroen's patch, which is attached to said web page. J |
|
From: <sv...@va...> - 2006-03-06 14:32:11
|
Author: sewardj
Date: 2006-03-06 14:32:00 +0000 (Mon, 06 Mar 2006)
New Revision: 1586
Log:
Merge r1585 (3DNow! prefetch insn (prefetch, prefetchw))
Modified:
branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c 2006-03-06 14:07:58 UTC=
(rev 1585)
+++ branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c 2006-03-06 14:32:00 UTC=
(rev 1586)
@@ -7970,6 +7970,29 @@
goto decode_success;
}
=20
+ /* 0F 0D /0 =3D PREFETCH m8 -- 3DNow! prefetch */
+ /* 0F 0D /1 =3D PREFETCHW m8 -- ditto, with some other hint */
+ if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x0D
+ && !epartIsReg(insn[2])=20
+ && gregOfRM(insn[2]) >=3D 0 && gregOfRM(insn[2]) <=3D 1) {
+ HChar* hintstr =3D "??";
+
+ modrm =3D getIByte(delta+2);
+ vassert(!epartIsReg(modrm));
+
+ addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
+ delta +=3D 2+alen;
+
+ switch (gregOfRM(modrm)) {
+ case 0: hintstr =3D ""; break;
+ case 1: hintstr =3D "w"; break;
+ default: vassert(0); /*NOTREACHED*/
+ }
+
+ DIP("prefetch%s %s\n", hintstr, dis_buf);
+ goto decode_success;
+ }
+
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F F6 =3D PSADBW -- sum of 8Ux8 absolute differences */
if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF6) {
|
|
From: <sv...@va...> - 2006-03-06 14:08:07
|
Author: sewardj
Date: 2006-03-06 14:07:58 +0000 (Mon, 06 Mar 2006)
New Revision: 1585
Log:
Implement 3DNow! prefetch insn (prefetch, prefetchw). Fixes #120410.
Modified:
trunk/priv/guest-x86/toIR.c
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2006-03-06 13:42:01 UTC (rev 1584)
+++ trunk/priv/guest-x86/toIR.c 2006-03-06 14:07:58 UTC (rev 1585)
@@ -8101,6 +8101,29 @@
goto decode_success;
}
=20
+ /* 0F 0D /0 =3D PREFETCH m8 -- 3DNow! prefetch */
+ /* 0F 0D /1 =3D PREFETCHW m8 -- ditto, with some other hint */
+ if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x0D
+ && !epartIsReg(insn[2])=20
+ && gregOfRM(insn[2]) >=3D 0 && gregOfRM(insn[2]) <=3D 1) {
+ HChar* hintstr =3D "??";
+
+ modrm =3D getIByte(delta+2);
+ vassert(!epartIsReg(modrm));
+
+ addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
+ delta +=3D 2+alen;
+
+ switch (gregOfRM(modrm)) {
+ case 0: hintstr =3D ""; break;
+ case 1: hintstr =3D "w"; break;
+ default: vassert(0); /*NOTREACHED*/
+ }
+
+ DIP("prefetch%s %s\n", hintstr, dis_buf);
+ goto decode_success;
+ }
+
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F F6 =3D PSADBW -- sum of 8Ux8 absolute differences */
if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF6) {
|
|
From: <sv...@va...> - 2006-03-06 13:42:11
|
Author: sewardj
Date: 2006-03-06 13:42:01 +0000 (Mon, 06 Mar 2006)
New Revision: 1584
Log:
Merge r1583 (fix for 8-bit xadd G,E)
Modified:
branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c 2006-03-06 13:35:42 UTC=
(rev 1583)
+++ branches/VEX_3_1_BRANCH/priv/guest-x86/toIR.c 2006-03-06 13:42:01 UTC=
(rev 1584)
@@ -6202,7 +6202,7 @@
=20
=20
static
-UInt dis_xadd_G_E ( UChar sorb, Int sz, Int delta0 )
+UInt dis_xadd_G_E ( UChar sorb, Int sz, Int delta0, Bool* decodeOK )
{
Int len;
UChar rm =3D getIByte(delta0);
@@ -6217,7 +6217,9 @@
IRTemp tmpt1 =3D newTemp(ty);
=20
if (epartIsReg(rm)) {
- unimplemented("x86 xadd instruction with register operand");
+ *decodeOK =3D False;
+ return delta0;
+ /* Currently we don't handle xadd_G_E with register operand. */
#if 0
uInstr2(cb, GET, sz, ArchReg, eregOfRM(rm), TempReg, tmpd);
uInstr2(cb, GET, sz, ArchReg, gregOfRM(rm), TempReg, tmpt);
@@ -6239,6 +6241,7 @@
putIReg(sz, gregOfRM(rm), mkexpr(tmpd));
DIP("xadd%c %s, %s\n",
nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf);
+ *decodeOK =3D True;
return len+delta0;
}
}
@@ -12359,12 +12362,18 @@
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- XADD -=3D-=3D-=3D-=3D-=3D-=
=3D-=3D-=3D-=3D-=3D */
=20
-//-- case 0xC0: /* XADD Gb,Eb */
-//-- eip =3D dis_xadd_G_E ( cb, sorb, 1, eip );
-//-- break;
- case 0xC1: /* XADD Gv,Ev */
- delta =3D dis_xadd_G_E ( sorb, sz, delta );
+ case 0xC0: { /* XADD Gb,Eb */
+ Bool decodeOK;
+ delta =3D dis_xadd_G_E ( sorb, 1, delta, &decodeOK );
+ if (!decodeOK) goto decode_failure;
break;
+ }
+ case 0xC1: { /* XADD Gv,Ev */
+ Bool decodeOK;
+ delta =3D dis_xadd_G_E ( sorb, sz, delta, &decodeOK );
+ if (!decodeOK) goto decode_failure;
+ break;
+ }
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- MMXery =3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
=20
|
|
From: <sv...@va...> - 2006-03-06 13:35:57
|
Author: sewardj
Date: 2006-03-06 13:35:42 +0000 (Mon, 06 Mar 2006)
New Revision: 1583
Log:
Handle byte-size 'xadd reg,mem'. Also, don't bomb out for the
unhandled 'xadd reg,reg' case; instead synth a SIGILL in the usual
way. Fixes #121662.
Modified:
trunk/priv/guest-x86/toIR.c
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2006-03-06 13:16:18 UTC (rev 1582)
+++ trunk/priv/guest-x86/toIR.c 2006-03-06 13:35:42 UTC (rev 1583)
@@ -6299,7 +6299,7 @@
=20
=20
static
-UInt dis_xadd_G_E ( UChar sorb, Int sz, Int delta0 )
+UInt dis_xadd_G_E ( UChar sorb, Int sz, Int delta0, Bool* decodeOK )
{
Int len;
UChar rm =3D getIByte(delta0);
@@ -6314,7 +6314,9 @@
IRTemp tmpt1 =3D newTemp(ty);
=20
if (epartIsReg(rm)) {
- unimplemented("x86 xadd instruction with register operand");
+ *decodeOK =3D False;
+ return delta0;
+ /* Currently we don't handle xadd_G_E with register operand. */
#if 0
uInstr2(cb, GET, sz, ArchReg, eregOfRM(rm), TempReg, tmpd);
uInstr2(cb, GET, sz, ArchReg, gregOfRM(rm), TempReg, tmpt);
@@ -6336,6 +6338,7 @@
putIReg(sz, gregOfRM(rm), mkexpr(tmpd));
DIP("xadd%c %s, %s\n",
nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf);
+ *decodeOK =3D True;
return len+delta0;
}
}
@@ -12491,12 +12494,18 @@
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- XADD -=3D-=3D-=3D-=3D-=3D-=
=3D-=3D-=3D-=3D-=3D */
=20
-//-- case 0xC0: /* XADD Gb,Eb */
-//-- eip =3D dis_xadd_G_E ( cb, sorb, 1, eip );
-//-- break;
- case 0xC1: /* XADD Gv,Ev */
- delta =3D dis_xadd_G_E ( sorb, sz, delta );
+ case 0xC0: { /* XADD Gb,Eb */
+ Bool decodeOK;
+ delta =3D dis_xadd_G_E ( sorb, 1, delta, &decodeOK );
+ if (!decodeOK) goto decode_failure;
break;
+ }
+ case 0xC1: { /* XADD Gv,Ev */
+ Bool decodeOK;
+ delta =3D dis_xadd_G_E ( sorb, sz, delta, &decodeOK );
+ if (!decodeOK) goto decode_failure;
+ break;
+ }
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- MMXery =3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
=20
|
|
From: <sv...@va...> - 2006-03-06 13:16:22
|
Author: sewardj
Date: 2006-03-06 13:16:18 +0000 (Mon, 06 Mar 2006)
New Revision: 1582
Log:
Merge r1569 (Redo x86g_calculate_FXTRACT to only use integer arithmetic.)
Modified:
branches/VEX_3_1_BRANCH/priv/guest-x86/ghelpers.c
Modified: branches/VEX_3_1_BRANCH/priv/guest-x86/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/guest-x86/ghelpers.c 2006-03-06 12:41:39=
UTC (rev 1581)
+++ branches/VEX_3_1_BRANCH/priv/guest-x86/ghelpers.c 2006-03-06 13:16:18=
UTC (rev 1582)
@@ -1250,11 +1250,10 @@
otherwise. */
ULong x86g_calculate_FXTRACT ( ULong arg, UInt getExp )
{
- ULong uSig;
- Long sSig;
- Double dSig, dExp;
+ ULong uSig, uExp;
+ /* Long sSig; */
Int sExp, i;
- UInt sign;
+ UInt sign, expExp;
=20
/*
S 7FF 0------0 infinity
@@ -1269,6 +1268,7 @@
const ULong negZero =3D 0x8000000000000000ULL;
const ULong bit51 =3D 1ULL << 51;
const ULong bit52 =3D 1ULL << 52;
+ const ULong sigMask =3D bit52 - 1;
=20
/* Mimic PIII behaviour for special cases. */
if (arg =3D=3D posInf)
@@ -1286,7 +1286,7 @@
sign =3D ((UInt)(arg >> 63)) & 1;
=20
/* Mask off exponent & sign. uSig is in range 0 .. 2^52-1. */
- uSig =3D arg & (bit52 - 1);
+ uSig =3D arg & sigMask;
=20
/* Get the exponent. */
sExp =3D ((Int)(arg >> 52)) & 0x7FF;
@@ -1310,20 +1310,45 @@
}
=20
/* Roll in the sign. */
- sSig =3D uSig;
- if (sign) sSig =3D- sSig;
+ /* sSig =3D uSig; */
+ /* if (sign) sSig =3D- sSig; */
=20
/* Convert sig into a double. This should be an exact conversion.
Then divide by 2^52, which should give a value in the range 1.0
to 2.0-epsilon, at least for normalised args. */
- dSig =3D (Double)sSig;
- dSig /=3D 67108864.0; /* 2^26 */
- dSig /=3D 67108864.0; /* 2^26 */
+ /* dSig =3D (Double)sSig; */
+ /* dSig /=3D 67108864.0; */ /* 2^26 */
+ /* dSig /=3D 67108864.0; */ /* 2^26 */
+ uSig &=3D sigMask;
+ uSig |=3D 0x3FF0000000000000ULL;
+ if (sign)
+ uSig ^=3D negZero;
=20
/* Convert exp into a double. Also an exact conversion. */
- dExp =3D (Double)(sExp - 1023);
+ /* dExp =3D (Double)(sExp - 1023); */
+ sExp -=3D 1023;
+ if (sExp =3D=3D 0) {
+ uExp =3D 0;
+ } else {
+ uExp =3D sExp < 0 ? -sExp : sExp;
+ expExp =3D 0x3FF +52;
+ /* 1 <=3D uExp <=3D 1074 */
+ /* Skip first 42 iterations of normalisation loop as we know they
+ will always happen */
+ uExp <<=3D 42;
+ expExp -=3D 42;
+ for (i =3D 0; i < 52-42; i++) {
+ if (uExp & bit52)
+ break;
+ uExp <<=3D 1;
+ expExp--;
+ }
+ uExp &=3D sigMask;
+ uExp |=3D ((ULong)expExp) << 52;
+ if (sExp < 0) uExp ^=3D negZero;
+ }
=20
- return *(ULong*)(getExp ? &dExp : &dSig);
+ return getExp ? uExp : uSig;
}
=20
=20
@@ -1442,7 +1467,7 @@
{
Int stno, preg;
UInt tag;
- Double* vexRegs =3D (Double*)(&vex_state->guest_FPREG[0]);
+ ULong* vexRegs =3D (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags =3D (UChar*)(&vex_state->guest_FPTAG[0]);
Fpu_State* x87 =3D (Fpu_State*)x87_state;
UInt ftop =3D (x87->env[FP_ENV_STAT] >> 11) & 7;
@@ -1464,7 +1489,7 @@
of sync, in that it thinks all FP registers are defined by
this helper, but in reality some have not been updated. */
if (moveRegs)
- vexRegs[preg] =3D 0.0;
+ vexRegs[preg] =3D 0; /* IEEE754 64-bit zero */
vexTags[preg] =3D 0;
} else {
/* register is non-empty */
@@ -1502,7 +1527,7 @@
{
Int i, stno, preg;
UInt tagw;
- Double* vexRegs =3D (Double*)(&vex_state->guest_FPREG[0]);
+ ULong* vexRegs =3D (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags =3D (UChar*)(&vex_state->guest_FPTAG[0]);
Fpu_State* x87 =3D (Fpu_State*)x87_state;
UInt ftop =3D vex_state->guest_FTOP;
|
|
From: <sv...@va...> - 2006-03-06 12:41:48
|
Author: sewardj
Date: 2006-03-06 12:41:39 +0000 (Mon, 06 Mar 2006)
New Revision: 1581
Log:
gcc-2.96 build fix
Modified:
branches/VEX_3_1_BRANCH/priv/ir/irdefs.c
Modified: branches/VEX_3_1_BRANCH/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_1_BRANCH/priv/ir/irdefs.c 2006-03-05 19:20:08 UTC (rev=
1580)
+++ branches/VEX_3_1_BRANCH/priv/ir/irdefs.c 2006-03-06 12:41:39 UTC (rev=
1581)
@@ -75,8 +75,8 @@
=20
void ppIRConst ( IRConst* con )
{
+ union { ULong i64; Double f64; } u;
vassert(sizeof(ULong) =3D=3D sizeof(Double));
- union { ULong i64; Double f64; } u;
switch (con->tag) {
case Ico_U1: vex_printf( "%d:I1", con->Ico.U1 ? 1 : 0); b=
reak;
case Ico_U8: vex_printf( "0x%x:I8", (UInt)(con->Ico.U8)); b=
reak;
|
|
From: <sv...@va...> - 2006-03-06 11:41:58
|
Author: sewardj
Date: 2006-03-06 11:41:52 +0000 (Mon, 06 Mar 2006)
New Revision: 5713
Log:
Update.
Modified:
trunk/docs/internals/3_1_BUGSTATUS.txt
Modified: trunk/docs/internals/3_1_BUGSTATUS.txt
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/docs/internals/3_1_BUGSTATUS.txt 2006-03-04 02:31:52 UTC (rev 5=
712)
+++ trunk/docs/internals/3_1_BUGSTATUS.txt 2006-03-06 11:41:52 UTC (rev 5=
713)
@@ -67,6 +67,7 @@
many vx1577 119482 ppc32: mtfsb1
many wontfix 120277 ppc32: fres, fctid, fctidz, frsqrte=20
[skip for 3.1.1 unless gcc/glibc requires i=
t]
+vx1579 vx1580 n-i-bz ppc32/64: mtocrf/mfocrf
=20
v5629 v5680 n-i-bz Dave Nomura extra suppression
=20
|
|
From: Julian S. <js...@ac...> - 2006-03-06 11:27:06
|
> I believe the idea was that the thread model would be an idealised > generic representation of threads and thread related objects existed > that was not tied to any particular implementation like pthreads. > > The thread model code would take care of the issuing the core thread > warning messages and of notifying the tools of thread events. > > [...] > I think the problem is that it is nowhere as simple as mapping each > function call to an event - there are sorts of implied changes in > state and so on. > > For example waiting on a CV unlocks the associated mutex, which your > patch won't currently notify about. Hmm yes I see. Looks like there's a lot of good stuff in m_pthreadmodel.c and m_threadmodel.c which we should bring back to life. I'm inclined to wait until Bart has a better picture of what drd really needs by way of thread events, and then maybe rearrange this stuff accordingly. J |