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From: <sv...@va...> - 2005-10-12 16:45:31
|
Author: njn
Date: 2005-10-12 17:45:17 +0100 (Wed, 12 Oct 2005)
New Revision: 4913
Log:
Tiny comment/code layout tweaks; no functional change.
Modified:
trunk/cachegrind/cg_main.c
Modified: trunk/cachegrind/cg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/cg_main.c 2005-10-12 16:16:03 UTC (rev 4912)
+++ trunk/cachegrind/cg_main.c 2005-10-12 16:45:17 UTC (rev 4913)
@@ -495,9 +495,10 @@
if (Ist_IMark =3D=3D st->tag) n_instrs++;
}
=20
- // Check that the BB has never been translated before. If this
- // assertion fails, there has been some screwup in translation
- // discard/invalidation management.
+ // Check that we don't have an entry for this BB in the instr-info ta=
ble.
+ // If this assertion fails, there has been some screwup: some
+ // translations must have been discarded but Cachegrind hasn't discar=
ded
+ // the corresponding entries in the instr-info table.
bbInfo =3D (BB_info*)VG_(HT_lookup)(instr_info_table, origAddr);
tl_assert(NULL =3D=3D bbInfo);
=20
@@ -514,13 +515,11 @@
=20
=20
static
-void init_instr_info( /*OUT*/instr_info* n,=20
- Addr instr_addr, Int instr_len )
+void init_instr_info( instr_info* n, Addr instr_addr, Int instr_len )
{
- lineCC* parent =3D get_lineCC(instr_addr);
- n->instr_addr =3D instr_addr;
- n->instr_len =3D instr_len;
- n->parent =3D parent;
+ n->instr_addr =3D instr_addr;
+ n->instr_len =3D instr_len;
+ n->parent =3D get_lineCC(instr_addr);
}
=20
static void showEvent ( Event* ev )
|
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 16:39:14
|
On Wed, 12 Oct 2005, Josef Weidendorfer wrote: >> The saving comes from doing fewer C calls from the instrumented code. > > I thought these are already quite optimized, with parameters in registers > and so on. Are multiple C calls so expensive because all the registers > have to be saved before and restored afterwards (including flags, > x87-state, ...)? That, and it's just more control transfers. As Julian said it saves about 3--5% so it's not a huge saving. > Ah, what was OSet about? An ordered set? > How is that implemented? With an AVL tree? Yes and yes. > In Callgrind, I often use resizable hash tables. I thought myself of using > these instead. Do you see a problem with hash tables? Not really. It's the usual trade-offs -- all data structures have certain characteristics, the best one to use depends on the situation. Having said that, I put a lot of effort into OSet to give it a general and clean interface as well as making it fast (the original implementation was borrowed from elsewhere). The intention was for it to be the generic data structure of first choice for use within Valgrind, to replace VgHashTable which can have scaling issues because it's not resizable. I thought about doing a resizable hash table instead but then Julian found the AVL tree implementation so I used that. VgHashTable still does better in some circumstances (eg. tracking heap blocks in Memcheck), but its interface isn't as nice. One nice thing about changing Cachegrind to an OSet is that all the entries in the cachegrind.out file will be sorted; this isn't terribly important but does make them easier to read. Nick |
|
From: Josef W. <Jos...@gm...> - 2005-10-12 16:36:07
|
On Wednesday 12 October 2005 17:25, Nicholas Nethercote wrote: > Besides, who knows if that loop is a big cost? Someone should profile > Cachegrind with Cachegrind to work out where the main costs are in > cg_sim.c. Yes. Or use OProfile. set[] with typical associativity 8 fits into a cache line itself. > It would require un-macrofying cachesim_*_doref so that the > counts get attributed to individual lines. I did this in Callgrind 0.10.0 already. It is a little bit slower, but way easier to look at. BTW, Cache simulation is switched off by default in Callgrind. See section "Write Through Cache Simulation" in http://cvs.sourceforge.net/viewcvs.py/kcachegrind/clg3/src/sim.c?rev=1.11&view=auto I use a little different interface (returning an enum), but that should be easy to rewrite to fit cachegrind. Josef |
|
From: Josef W. <Jos...@gm...> - 2005-10-12 16:19:05
|
On Wednesday 12 October 2005 17:10, Julian Seward wrote: > I did have a different speedup idea however. I don't know if it > is valid, but might be worth looking into. > > cg_sim.c simulates general 2^n-way associative caches. Doing > that involves endlessly rearranging entries in this set[] array > when a tag matches set[i] for i > 0. In that case (which > is the second most common case after matching set[0]) the > section set[0 .. i] is rotated to put set[i] at the start. > > This seems expensive, and it could be that simply swapping > set[i] and set[i-1] would be cheaper -- it would remove the > loop setup/control overhead whilst still bringing a popular > line to the top quickly given a sequence of references to it. Do you want to unroll case i==1 ? Swapping set[i] and set[i-1] would be only valid for i==1. At the end, set[0] always has to hold the least recent access. Cachegrind (and Callgrind) currently simulates LRU replacement. So set[] is ordered according access time. If you do not rotate, you violate this property. Of course, Cachegrind could use a pseudo-LRU replacement strategy. This will lead to slightly changed hit/miss numbers. AFAIK, hardware cache implementations often do not use real LRU, as this is quite expensive. Another thing: With C++ and templates, we could get rid of the loop (and macro) by letting the compiler generate unrolled code for a fixed number of associativities. Is there any hope that tools can use C++ in the future? > What I can't figure out is if this would change the actual > simulated behaviour or not. It's clear that the 'A miss' > case needs to remain as it is in order to cause an entry to > fall off the end of the array. I you do not rotate in all cases, the entry which will fall off on a miss, will not always be the one which was accessed the longest time ago. Josef |
|
From: <sv...@va...> - 2005-10-12 16:16:07
|
Author: sewardj
Date: 2005-10-12 17:16:03 +0100 (Wed, 12 Oct 2005)
New Revision: 4912
Log:
Get rid of bbSeenBefore and associated logic: it appears to be
irrelevant.
Modified:
trunk/cachegrind/cg_main.c
Modified: trunk/cachegrind/cg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/cg_main.c 2005-10-12 12:53:20 UTC (rev 4911)
+++ trunk/cachegrind/cg_main.c 2005-10-12 16:16:03 UTC (rev 4912)
@@ -471,9 +471,6 @@
/* Number instr_info bins 'used' so far. */
Int bbInfo_i;
=20
- /* Not sure what this is for (jrs 20051009) */
- Bool bbSeenBefore;
-
/* The output BB being constructed. */
IRBB* bbOut;
}
@@ -485,7 +482,7 @@
/*------------------------------------------------------------*/
=20
static
-BB_info* get_BB_info(IRBB* bbIn, Addr origAddr, /*OUT*/Bool* bbSeenBefor=
e)
+BB_info* get_BB_info(IRBB* bbIn, Addr origAddr)
{
Int i, n_instrs;
IRStmt* st;
@@ -498,42 +495,32 @@
if (Ist_IMark =3D=3D st->tag) n_instrs++;
}
=20
- // Get the BB_info
+ // Check that the BB has never been translated before. If this
+ // assertion fails, there has been some screwup in translation
+ // discard/invalidation management.
bbInfo =3D (BB_info*)VG_(HT_lookup)(instr_info_table, origAddr);
- *bbSeenBefore =3D ( NULL =3D=3D bbInfo ? False : True );
- if (*bbSeenBefore) {
- // BB must have been translated before, but flushed from the TT
- tl_assert(bbInfo->n_instrs =3D=3D n_instrs );
- BB_retranslations++;
- } else {
- // BB never translated before (at this address, at least; could h=
ave
- // been unloaded and then reloaded elsewhere in memory)
- bbInfo =3D VG_(calloc)(1, sizeof(BB_info) + n_instrs*sizeof(instr_=
info));=20
- bbInfo->BB_addr =3D origAddr;
- bbInfo->n_instrs =3D n_instrs;
- VG_(HT_add_node)( instr_info_table, (VgHashNode*)bbInfo );
- distinct_instrs++;
- }
+ tl_assert(NULL =3D=3D bbInfo);
+
+ // BB has never translated before (at this address, at least; could
+ // have been unloaded and then reloaded elsewhere in memory).
+ bbInfo =3D VG_(calloc)(1, sizeof(BB_info) + n_instrs*sizeof(instr_inf=
o));=20
+ bbInfo->BB_addr =3D origAddr;
+ bbInfo->n_instrs =3D n_instrs;
+ VG_(HT_add_node)( instr_info_table, (VgHashNode*)bbInfo );
+ distinct_instrs++;
+
return bbInfo;
}
=20
=20
static
-void init_instr_info( instr_info* n, Bool bbSeenBefore,
+void init_instr_info( /*OUT*/instr_info* n,=20
Addr instr_addr, Int instr_len )
{
- if (bbSeenBefore) {
- tl_assert( n->instr_addr =3D=3D instr_addr );
- tl_assert( n->instr_len =3D=3D instr_len );
- // Don't check that (n->parent =3D=3D parent)... it's conceivable =
that
- // the debug info might change; the other asserts should be enoug=
h to
- // detect anything strange.
- } else {
- lineCC* parent =3D get_lineCC(instr_addr);
- n->instr_addr =3D instr_addr;
- n->instr_len =3D instr_len;
- n->parent =3D parent;
- }
+ lineCC* parent =3D get_lineCC(instr_addr);
+ n->instr_addr =3D instr_addr;
+ n->instr_len =3D instr_len;
+ n->parent =3D parent;
}
=20
static void showEvent ( Event* ev )
@@ -634,7 +621,7 @@
/* allocate an instr_info and fill in its addr/size. */
i_node =3D reserve_instr_info( cgs );
tl_assert(i_node);
- init_instr_info( i_node, cgs->bbSeenBefore,
+ init_instr_info( i_node,
(Addr)cgs->events[i].iaddr, /* i addr */
cgs->events[i].size /* i size */);
} else {
@@ -690,14 +677,14 @@
=20
i_node2 =3D reserve_instr_info( cgs );
tl_assert(i_node2);
- init_instr_info( i_node2, cgs->bbSeenBefore,
+ init_instr_info( i_node2,
(Addr)cgs->events[i+1].iaddr, /* i addr =
*/
cgs->events[i+1].size /* i size */);
i_node2_expr =3D mkIRExpr_HWord( (HWord)i_node2 );
=20
i_node3 =3D reserve_instr_info( cgs );
tl_assert(i_node3);
- init_instr_info( i_node3, cgs->bbSeenBefore,
+ init_instr_info( i_node3,
(Addr)cgs->events[i+2].iaddr, /* i addr =
*/
cgs->events[i+2].size /* i size */);
i_node3_expr =3D mkIRExpr_HWord( (HWord)i_node3 );
@@ -714,7 +701,7 @@
helperAddr =3D &log_2I_0D_cache_access;
i_node2 =3D reserve_instr_info( cgs );
tl_assert(i_node2);
- init_instr_info( i_node2, cgs->bbSeenBefore,
+ init_instr_info( i_node2,
(Addr)cgs->events[i+1].iaddr, /* i addr =
*/
cgs->events[i+1].size /* i size */);
i_node2_expr =3D mkIRExpr_HWord( (HWord)i_node2 );
@@ -860,7 +847,7 @@
=20
// Set up running state and get block info
cgs.events_used =3D 0;
- cgs.bbInfo =3D get_BB_info(bbIn, (Addr)cia, &cgs.bbSeenBefore);
+ cgs.bbInfo =3D get_BB_info(bbIn, (Addr)cia);
cgs.bbInfo_i =3D 0;
=20
if (DEBUG_CG)
@@ -1328,7 +1315,9 @@
/*--- Discarding BB info ---*/
/*--------------------------------------------------------------------*/
=20
-// Called when a translation is invalidated due to code unloading.
+// Called when a translation is removed from the translation cache for
+// any reason at all: to free up space, because the guest code was
+// unmapped or modified, or for any arbitrary reason.
static void cg_discard_basic_block_info ( VexGuestExtents vge )
{
VgHashNode* bbInfo;
|
|
From: Josef W. <Jos...@gm...> - 2005-10-12 15:41:38
|
On Wednesday 12 October 2005 16:37, Nicholas Nethercote wrote: > On Wed, 12 Oct 2005, Josef Weidendorfer wrote: > > I wonder why you pulled the data size out of the instruction info into > > a parameter. Are there cases on ppc32 where one instruction does > > multiple data accesses with different sizes? > > Julian and I discussed these changes a bit. I can't recall if we saw it > in practice, but it seemed like a dangerous assumption to have. OK. For Super-CISC architectures VG will support in the future ;-) > > In callgrind, I did something similar in the last version: > > Generate helpers into the cache simulator before every Ist_Exit, > > and at end of a BB. For this, I also added 0I1Dr and so on. > > Why did you get rid of xI2D? Is this forced because of the maximum > > number of helper arguments, or because of profiling (i.e. it is > > not worth it)? > > I think the latter; Julian found the most common 2 and 3 event sequences. Either way; I think I can do the same in Callgrind. > > Not bad. I did not expect that putting 2 or 3 Ir's into one helper > > call would provide such a speedup; especially, as the number of calls > > into the cache simulator itself (cachesim_I1_doref) are the same. > > The saving comes from doing fewer C calls from the instrumented code. I thought these are already quite optimized, with parameters in registers and so on. Are multiple C calls so expensive because all the registers have to be saved before and restored afterwards (including flags, x87-state, ...)? > >> This commit also changes the type of the tool interface function > >> 'tool_discard_basic_block_info' and clarifies its meaning. See > >> comments in include/pub_tool_tooliface.h. > > > > BTW: Callgrind does not use tool_discard_basic_block_info at all: > > I keep (dso, offset) instead of pure addresses in my structs. > > This way, all the counters can stay attributed to debug info, and > > it can cope quite fine with remapping of the same dso at different > > addresses, using the same counters. > > Cachegrind stores the access/hit/miss counters in cost centres (CCs) which > are indexed by source location (filename, function name, line number). It > stores other information (eg. instruction address and length) on a > per-instruction basis in the instr-info table, which is just used to > reduce the number of parameters passed to the C calls. It is these > instr-info nodes that must be removed when translations are discarded; > the CCs are still valid because they are in terms of source code locations > and thus unaffected by code loading/unloading. Ah, yes, OK. You changed this some time ago, didn't you? I had the old way in mind. > So when the BB gets re-translated, its instr-info nodes entry shouldn't be > there. In practice, it sometimes was there which was why I added this > bbSeenBefore. But it turns out that m_transtab was not calling > discard_basic_block_info() when translations were discarded due to the > table being full, but only when code was unloaded due to munmap()... so > some BB instr-info entries were erroneously being left behind in the > table. Julian fixed that, and so now bbSeenBefore is never true, so it > can be removed. Make sense? Yes, now I see. If a tool would like to get rid of some private structures in response to a munmap (of e.g. code), it should track the munmap instead. There is no issue with adding a boolean to discard_basic_block_info(), as this could provoke the same problem as you had. > BTW Josef I have another Cachegrind patch that I will commit in the next > few days when I have time. It replaces the three-level hash table with an > OSet, which makes the code simpler and should scale better. Ah, what was OSet about? An ordered set? How is that implemented? With an AVL tree? In Callgrind, I often use resizable hash tables. I thought myself of using these instead. Do you see a problem with hash tables? Josef > Nick |
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 15:26:05
|
On Wed, 12 Oct 2005, Julian Seward wrote: > I did have a different speedup idea however. I don't know if it > is valid, but might be worth looking into. > > cg_sim.c simulates general 2^n-way associative caches. Doing > that involves endlessly rearranging entries in this set[] array > when a tag matches set[i] for i > 0. In that case (which > is the second most common case after matching set[0]) the > section set[0 .. i] is rotated to put set[i] at the start. > > This seems expensive, and it could be that simply swapping > set[i] and set[i-1] would be cheaper -- it would remove the > loop setup/control overhead whilst still bringing a popular > line to the top quickly given a sequence of references to it. > > What I can't figure out is if this would change the actual > simulated behaviour or not. Sounds like it would -- it wouldn't be LRU any more. Besides, who knows if that loop is a big cost? Someone should profile Cachegrind with Cachegrind to work out where the main costs are in cg_sim.c. It would require un-macrofying cachesim_*_doref so that the counts get attributed to individual lines. Nick |
|
From: Julian S. <js...@ac...> - 2005-10-12 15:14:01
|
> > or because of profiling (i.e. it is not worth it)? > > yes. It's clear we could do a bit better on ppc with a couple > more combinations, but I don't think it's worth the extra code > bloat. What is there currently captures the majority of the > opportunities for merging already. I did have a different speedup idea however. I don't know if it is valid, but might be worth looking into. cg_sim.c simulates general 2^n-way associative caches. Doing that involves endlessly rearranging entries in this set[] array when a tag matches set[i] for i > 0. In that case (which is the second most common case after matching set[0]) the section set[0 .. i] is rotated to put set[i] at the start. This seems expensive, and it could be that simply swapping set[i] and set[i-1] would be cheaper -- it would remove the loop setup/control overhead whilst still bringing a popular line to the top quickly given a sequence of references to it. What I can't figure out is if this would change the actual simulated behaviour or not. It's clear that the 'A miss' case needs to remain as it is in order to cause an entry to fall off the end of the array. J |
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 14:40:36
|
On Wed, 12 Oct 2005, Julian Seward wrote: >> void (*tool_discard_basic_block_info)(VexGuestExtents, Bool isUnmapped) > > That sounds reasonable to me (cachegrind can ignore the bool) > (except I would invert the sense of the bool), but let's see > what Nick has to say. It might be useful to some tools, but Cachegrind doesn't need it, as I explained in my other message. Nick |
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 14:39:01
|
On Wed, 12 Oct 2005, Tom Hughes wrote: >>> Add -Wdeclaration-after-statement >> >> Ehm .. gcc-3.3.3 on both x86 and ppc32 have never heard of this. >> You sure it isn't a gcc4ism? > > Quite probably... I'll sort it out. I think it came in with 3.4.0. Nick |
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 14:38:08
|
On Wed, 12 Oct 2005, Josef Weidendorfer wrote:
> I wonder why you pulled the data size out of the instruction info into
> a parameter. Are there cases on ppc32 where one instruction does
> multiple data accesses with different sizes?
Julian and I discussed these changes a bit. I can't recall if we saw it
in practice, but it seemed like a dangerous assumption to have.
> In callgrind, I did something similar in the last version:
> Generate helpers into the cache simulator before every Ist_Exit,
> and at end of a BB. For this, I also added 0I1Dr and so on.
> Why did you get rid of xI2D? Is this forced because of the maximum
> number of helper arguments, or because of profiling (i.e. it is
> not worth it)?
I think the latter; Julian found the most common 2 and 3 event sequences.
> Not bad. I did not expect that putting 2 or 3 Ir's into one helper
> call would provide such a speedup; especially, as the number of calls
> into the cache simulator itself (cachesim_I1_doref) are the same.
The saving comes from doing fewer C calls from the instrumented code.
>> This commit also changes the type of the tool interface function
>> 'tool_discard_basic_block_info' and clarifies its meaning. See
>> comments in include/pub_tool_tooliface.h.
>
> BTW: Callgrind does not use tool_discard_basic_block_info at all:
> I keep (dso, offset) instead of pure addresses in my structs.
> This way, all the counters can stay attributed to debug info, and
> it can cope quite fine with remapping of the same dso at different
> addresses, using the same counters.
Cachegrind stores the access/hit/miss counters in cost centres (CCs) which
are indexed by source location (filename, function name, line number). It
stores other information (eg. instruction address and length) on a
per-instruction basis in the instr-info table, which is just used to
reduce the number of parameters passed to the C calls. It is these
instr-info nodes that must be removed when translations are discarded;
the CCs are still valid because they are in terms of source code locations
and thus unaffected by code loading/unloading.
>> +/* A struct which holds all the running state during instrumentation.
>> + Mostly to avoid passing loads of parameters everywhere. */
>> +typedef
>> + struct {
>> ...
>> + /* Not sure what this is for (jrs 20051009) */
>> + Bool bbSeenBefore;
>
> This is set to true if a BB is instrumented more than once, e.g.
> because of a flush of the translation cache. As Cachegrinds
> data structures for this BB are still intact, you can use this
> for sanity checks.
Actually, when a translation is discarded the BB's instr-info nodes get
removed from the instr-info table. From cg_discard_basic_block_info():
// Get BB info, remove from table, free BB info. Simple!
bbInfo = VG_(HT_remove)(instr_info_table, (UWord)vge.base[0]);
tl_assert(NULL != bbInfo);
So when the BB gets re-translated, its instr-info nodes entry shouldn't be
there. In practice, it sometimes was there which was why I added this
bbSeenBefore. But it turns out that m_transtab was not calling
discard_basic_block_info() when translations were discarded due to the
table being full, but only when code was unloaded due to munmap()... so
some BB instr-info entries were erroneously being left behind in the
table. Julian fixed that, and so now bbSeenBefore is never true, so it
can be removed. Make sense?
BTW Josef I have another Cachegrind patch that I will commit in the next
few days when I have time. It replaces the three-level hash table with an
OSet, which makes the code simpler and should scale better.
Nick
|
|
From: Julian S. <js...@ac...> - 2005-10-12 14:34:28
|
> void (*tool_discard_basic_block_info)(VexGuestExtents, Bool isUnmapped) That sounds reasonable to me (cachegrind can ignore the bool) (except I would invert the sense of the bool), but let's see what Nick has to say. J |
|
From: Julian S. <js...@ac...> - 2005-10-12 14:29:14
|
> I wonder why you pulled the data size out of the instruction info into > a parameter. Fundamentally, it's not really meaningful to say that an instruction has a specific data size. The data size is a property of each memory reference that an insn might make, but it is not a property of the insn itself. > Are there cases on ppc32 where one instruction does > multiple data accesses with different sizes? There is lsw, for which the amount of data transferred to/from memory is not known until run time (0-128 bytes). > Why did you get rid of xI2D? Is this forced because of the maximum > number of helper arguments, no > or because of profiling (i.e. it is not worth it)? yes. It's clear we could do a bit better on ppc with a couple more combinations, but I don't think it's worth the extra code bloat. What is there currently captures the majority of the opportunities for merging already. > Hmmm... do you mind if I take most of your changes over to Callgrind? Please do. Note, there will be some followup commits in the next few days to do some final cleanups, but nothing major. J |
|
From: Nicholas N. <nj...@cs...> - 2005-10-12 14:26:33
|
On Wed, 12 Oct 2005, Josef Weidendorfer wrote: >> Log: >> Notify the tool via tool_discard_basic_block_info() about translations >> thrown away due to lack of space. > > I think this is bad for cachegrind, as it will loose debug info > relationship for counters, only because the translation cache is full. > If cachegrind reports a total of 20 MEvents, and for 10 MEvents the > relation to source code is lost, the whole profiling is questionable. No; I'm currently replying to your other mail where I'll address this issue... N |
|
From: Josef W. <Jos...@gm...> - 2005-10-12 14:24:17
|
On Wednesday 12 October 2005 12:51, sv...@va... wrote: > Author: sewardj > Date: 2005-10-12 11:51:01 +0100 (Wed, 12 Oct 2005) > New Revision: 4908 > > Log: > Notify the tool via tool_discard_basic_block_info() about translations > thrown away due to lack of space. I think this is bad for cachegrind, as it will loose debug info relationship for counters, only because the translation cache is full. If cachegrind reports a total of 20 MEvents, and for 10 MEvents the relation to source code is lost, the whole profiling is questionable. Better would be to add a boolean argument which specifies if the discarding was because of unmapping of the BB, i.e. void (*tool_discard_basic_block_info)(VexGuestExtents, Bool isUnmapped) Josef |
|
From: Josef W. <Jos...@gm...> - 2005-10-12 14:12:14
|
On Wednesday 12 October 2005 12:09, sv...@va... wrote:
> Author: sewardj
> Date: 2005-10-12 11:09:23 +0100 (Wed, 12 Oct 2005)
> New Revision: 4903
>
> Log:
> Redo the way cachegrind generates instrumentation code, so that it can
> deal with any IR that happens to show up. This makes it work on ppc32
> and should fix occasionally-reported bugs on x86/amd64 where it bombs
> due to having to deal with multiple date references in a single
> instruction.
Good.
I wonder why you pulled the data size out of the instruction info into
a parameter. Are there cases on ppc32 where one instruction does
multiple data accesses with different sizes?
In callgrind, I did something similar in the last version:
Generate helpers into the cache simulator before every Ist_Exit,
and at end of a BB. For this, I also added 0I1Dr and so on.
Why did you get rid of xI2D? Is this forced because of the maximum
number of helper arguments, or because of profiling (i.e. it is
not worth it)?
> The new scheme is based around the idea of a queue of memory events
> which are outstanding, in the sense that no IR has yet been generated
> to do the relevant helper calls. The presence of the queue --
> currently 16 entries deep -- gives cachegrind more scope for combining
> multiple memory references into a single helper function call. As a
> result it runs 3%-5% faster than the previous version, on x86.
Not bad. I did not expect that putting 2 or 3 Ir's into one helper
call would provide such a speedup; especially, as the number of calls
into the cache simulator itself (cachesim_I1_doref) are the same.
Hmmm... do you mind if I take most of your changes over to Callgrind?
It is easier for me to keep up with needed changes for new architectures,
if the code base is the same. Especially as I don't have a ppc32
machine available here.
> This commit also changes the type of the tool interface function
> 'tool_discard_basic_block_info' and clarifies its meaning. See
> comments in include/pub_tool_tooliface.h.
BTW: Callgrind does not use tool_discard_basic_block_info at all:
I keep (dso, offset) instead of pure addresses in my structs.
This way, all the counters can stay attributed to debug info, and
it can cope quite fine with remapping of the same dso at different
addresses, using the same counters.
> +/* A struct which holds all the running state during instrumentation.
> + Mostly to avoid passing loads of parameters everywhere. */
> +typedef
> + struct {
> ...
> + /* Not sure what this is for (jrs 20051009) */
> + Bool bbSeenBefore;
This is set to true if a BB is instrumented more than once, e.g.
because of a flush of the translation cache. As Cachegrinds
data structures for this BB are still intact, you can use this
for sanity checks.
Josef
|
|
From: <sv...@va...> - 2005-10-12 12:53:28
|
Author: sewardj
Date: 2005-10-12 13:53:20 +0100 (Wed, 12 Oct 2005)
New Revision: 4911
Log:
Build fixes for gcc-2.96. The system now builds and regtests with the
default gcc-2.96 on Red Hat 7.3.
Modified:
trunk/coregrind/m_translate.c
trunk/memcheck/mac_leakcheck.c
trunk/memcheck/mc_main.c
trunk/none/tests/mremap2.c
Modified: trunk/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_translate.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/coregrind/m_translate.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -68,43 +68,44 @@
LibVEX_default_VexArchInfo(vai);
=20
#if defined(VGA_x86)
- Bool have_sse1, have_sse2;
- UInt eax, ebx, ecx, edx;
+ { Bool have_sse1, have_sse2;
+ UInt eax, ebx, ecx, edx;
=20
- if (!VG_(has_cpuid)())
- /* we can't do cpuid at all. Give up. */
- return False;
+ if (!VG_(has_cpuid)())
+ /* we can't do cpuid at all. Give up. */
+ return False;
=20
- VG_(cpuid)(0, &eax, &ebx, &ecx, &edx);
- if (eax < 1)
- /* we can't ask for cpuid(x) for x > 0. Give up. */
- return False;
+ VG_(cpuid)(0, &eax, &ebx, &ecx, &edx);
+ if (eax < 1)
+ /* we can't ask for cpuid(x) for x > 0. Give up. */
+ return False;
=20
- /* get capabilities bits into edx */
- VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
+ /* get capabilities bits into edx */
+ VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
=20
- have_sse1 =3D (edx & (1<<25)) !=3D 0; /* True =3D> have sse insns */
- have_sse2 =3D (edx & (1<<26)) !=3D 0; /* True =3D> have sse2 insns */
+ have_sse1 =3D (edx & (1<<25)) !=3D 0; /* True =3D> have sse insns *=
/
+ have_sse2 =3D (edx & (1<<26)) !=3D 0; /* True =3D> have sse2 insns =
*/
=20
- VG_(have_mxcsr_x86) =3D 1;
+ VG_(have_mxcsr_x86) =3D 1;
=20
- if (have_sse2 && have_sse1) {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse2;
- return True;
- }
+ if (have_sse2 && have_sse1) {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse2;
+ return True;
+ }
=20
- if (have_sse1) {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse1;
- return True;
- }
+ if (have_sse1) {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse1;
+ return True;
+ }
=20
- {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse0;
- VG_(have_mxcsr_x86) =3D 0;
- return True;
+ {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse0;
+ VG_(have_mxcsr_x86) =3D 0;
+ return True;
+ }
}
=20
#elif defined(VGA_amd64)
Modified: trunk/memcheck/mac_leakcheck.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mac_leakcheck.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/memcheck/mac_leakcheck.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -83,7 +83,7 @@
static Addr* get_seg_starts ( /*OUT*/Int* n_acquired )
{
Addr* starts;
- Int n_starts, r;
+ Int n_starts, r =3D 0;
=20
n_starts =3D 1;
while (True) {
Modified: trunk/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_main.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/memcheck/mc_main.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -558,6 +558,11 @@
UWord example_a_bit,
UWord example_v_bit )
{
+ UWord a, vbits8, abits8, vbits32, v_off, a_off;
+ SecMap* sm;
+ SecMap** binder;
+ SecMap* example_dsm;
+
PROF_EVENT(150, "set_address_range_perms");
=20
/* Check the permissions make sense. */
@@ -580,35 +585,32 @@
}
}
=20
- UWord a =3D (UWord)aA;
+ a =3D (UWord)aA;
=20
# if VG_DEBUG_MEMORY >=3D 2
=20
/*------------------ debug-only case ------------------ */
- SizeT i;
+ { SizeT i;
=20
- UWord example_vbyte =3D BIT_TO_BYTE(example_v_bit);
+ UWord example_vbyte =3D BIT_TO_BYTE(example_v_bit);
=20
- tl_assert(sizeof(SizeT) =3D=3D sizeof(Addr));
+ tl_assert(sizeof(SizeT) =3D=3D sizeof(Addr));
=20
- if (0 && len >=3D 4096)
- VG_(printf)("s_a_r_p(0x%llx, %d, %d,%d)\n",=20
- (ULong)a, len, example_a_bit, example_v_bit);
+ if (0 && len >=3D 4096)
+ VG_(printf)("s_a_r_p(0x%llx, %d, %d,%d)\n",=20
+ (ULong)a, len, example_a_bit, example_v_bit);
=20
- if (len =3D=3D 0)
- return;
+ if (len =3D=3D 0)
+ return;
=20
- for (i =3D 0; i < len; i++) {
- set_abit_and_vbyte(a+i, example_a_bit, example_vbyte);
+ for (i =3D 0; i < len; i++) {
+ set_abit_and_vbyte(a+i, example_a_bit, example_vbyte);
+ }
}
=20
# else
=20
/*------------------ standard handling ------------------ */
- UWord vbits8, abits8, vbits32, v_off, a_off;
- SecMap* sm;
- SecMap** binder;
- SecMap* example_dsm;
=20
/* Decide on the distinguished secondary that we might want
to use (part of the space-compression scheme). */
@@ -778,6 +780,9 @@
static __inline__
void make_aligned_word32_writable ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off, mask;
+ SecMap* sm;
+
PROF_EVENT(300, "make_aligned_word32_writable");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -790,8 +795,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -799,14 +804,14 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the new area as uninitialised. */
((UInt*)(sm->vbyte))[v_off >> 2] =3D VGM_WORD32_INVALID;
=20
- UWord mask =3D 0x0F;
+ mask =3D 0x0F;
mask <<=3D (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */
/* mask now contains 1s where we wish to make address bits valid
(0s). */
@@ -818,6 +823,9 @@
static __inline__
void make_aligned_word32_noaccess ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off, mask;
+ SecMap* sm;
+
PROF_EVENT(310, "make_aligned_word32_noaccess");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -830,8 +838,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -839,15 +847,15 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the abandoned data as uninitialised. Probably not
necessary, but still .. */
((UInt*)(sm->vbyte))[v_off >> 2] =3D VGM_WORD32_INVALID;
=20
- UWord mask =3D 0x0F;
+ mask =3D 0x0F;
mask <<=3D (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */
/* mask now contains 1s where we wish to make address bits invalid
(1s). */
@@ -860,6 +868,9 @@
static __inline__
void make_aligned_word64_writable ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off;
+ SecMap* sm;
+
PROF_EVENT(320, "make_aligned_word64_writable");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -872,8 +883,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -881,9 +892,9 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the new area as uninitialised. */
((ULong*)(sm->vbyte))[v_off >> 3] =3D VGM_WORD64_INVALID;
@@ -897,6 +908,9 @@
static __inline__
void make_aligned_word64_noaccess ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off;
+ SecMap* sm;
+
PROF_EVENT(330, "make_aligned_word64_noaccess");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -909,8 +923,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -918,9 +932,9 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the abandoned data as uninitialised. Probably not
necessary, but still .. */
@@ -1497,13 +1511,16 @@
VG_REGPARM(1) \
ULong nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(200, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return mc_LOADVn_slow( aA, 8, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1514,15 +1531,15 @@
return (UWord)mc_LOADVn_slow( aA, 8, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
\
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly: a is suitably aligned, */ \
@@ -1544,13 +1561,16 @@
VG_REGPARM(1) \
void nAME ( Addr aA, ULong vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(210, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 8, vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1562,15 +1582,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
\
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
&& abits =3D=3D VGM_BYTE_VALID)) { \
@@ -1595,13 +1615,16 @@
VG_REGPARM(1) \
UWord nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(220, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return (UWord)mc_LOADVn_slow( aA, 4, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1612,15 +1635,15 @@
return (UWord)mc_LOADVn_slow( aA, 4, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
abits >>=3D (a & 4); \
abits &=3D 15; \
if (EXPECTED_TAKEN(abits =3D=3D VGM_NIBBLE_VALID)) { \
@@ -1650,13 +1673,16 @@
VG_REGPARM(2) \
void nAME ( Addr aA, UWord vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(230, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 4, (ULong)vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1668,15 +1694,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
abits >>=3D (a & 4); \
abits &=3D 15; \
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
@@ -1702,13 +1728,16 @@
VG_REGPARM(1) \
UWord nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; \
+ SecMap* sm; \
+ \
PROF_EVENT(240, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return (UWord)mc_LOADVn_slow( aA, 2, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1719,15 +1748,15 @@
return (UWord)mc_LOADVn_slow( aA, 2, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly: a is mapped, and the */ \
/* entire word32 it lives in is addressible. */ \
@@ -1753,13 +1782,16 @@
VG_REGPARM(2) \
void nAME ( Addr aA, UWord vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; \
+ SecMap* sm; \
+ \
PROF_EVENT(250, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 2, (ULong)vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1771,15 +1803,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
&& abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly. */ \
@@ -1802,14 +1834,17 @@
VG_REGPARM(1)
UWord MC_(helperc_LOADV1) ( Addr aA )
{
+ UWord mask, a, sec_no, v_off, a_off, abits;
+ SecMap* sm;
+
PROF_EVENT(260, "helperc_LOADV1");
=20
# if VG_DEBUG_MEMORY >=3D 2
return (UWord)mc_LOADVn_slow( aA, 1, False/*irrelevant*/ );
# else
=20
- const UWord mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
- UWord a =3D (UWord)aA;
+ mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
+ a =3D (UWord)aA;
=20
/* If any part of 'a' indicated by the mask is 1, it means 'a'
exceeds the range covered by the primary map. In which case we
@@ -1819,16 +1854,16 @@
return (UWord)mc_LOADVn_slow( aA, 1, False/*irrelevant*/ );
}
=20
- UWord sec_no =3D (UWord)(a >> 16);
+ sec_no =3D (UWord)(a >> 16);
=20
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
- UWord abits =3D (UWord)(sm->abits[a_off]);
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
+ abits =3D (UWord)(sm->abits[a_off]);
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) {
/* Handle common case quickly: a is mapped, and the entire
word32 it lives in is addressible. */
@@ -1850,14 +1885,17 @@
VG_REGPARM(2)
void MC_(helperc_STOREV1) ( Addr aA, UWord vbyte )
{
+ UWord mask, a, sec_no, v_off, a_off, abits;
+ SecMap* sm;
+
PROF_EVENT(270, "helperc_STOREV1");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 1, (ULong)vbyte, False/*irrelevant*/ );
# else
=20
- const UWord mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
- UWord a =3D (UWord)aA;
+ mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
+ a =3D (UWord)aA;
/* If any part of 'a' indicated by the mask is 1, it means 'a'
exceeds the range covered by the primary map. In which case we
defer to the slow-path case. */
@@ -1867,16 +1905,16 @@
return;
}
=20
- UWord sec_no =3D (UWord)(a >> 16);
+ sec_no =3D (UWord)(a >> 16);
=20
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
- UWord abits =3D (UWord)(sm->abits[a_off]);
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
+ abits =3D (UWord)(sm->abits[a_off]);
if (EXPECTED_TAKEN(!is_distinguished_sm(sm)=20
&& abits =3D=3D VGM_BYTE_VALID)) {
/* Handle common case quickly: a is mapped, the entire word32 it
@@ -2505,11 +2543,11 @@
=20
static void mc_fini ( Int exitcode )
{
- MAC_(common_fini)( mc_detect_memory_leaks );
-
Int i, n_accessible_dist;
SecMap* sm;
=20
+ MAC_(common_fini)( mc_detect_memory_leaks );
+
if (VG_(clo_verbosity) > 1) {
VG_(message)(Vg_DebugMsg,
" memcheck: sanity checks: %d cheap, %d expensive",
Modified: trunk/none/tests/mremap2.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/mremap2.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/none/tests/mremap2.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -100,7 +100,6 @@
int main ( void )
{
int alocal, maymove, fixed, nsi, dstpossible;
- dst_impossible =3D (char*)(&alocal) + 500 * 1000 * 1000;
int newsizes[6] =3D { 19, 20, 21, 29, 30, 31 };
=20
char* tidythis =3D NULL;
@@ -108,6 +107,8 @@
int firsttime =3D 1;
char buf[100];
=20
+ dst_impossible =3D (char*)(&alocal) + 500 * 1000 * 1000;
+
PAGE =3D sysconf(_SC_PAGESIZE);
=20
for (maymove =3D 0; maymove <=3D 1 ; maymove++) {
@@ -116,14 +117,13 @@
for (nsi =3D 0; nsi < 6; nsi++) {
for (dstpossible =3D 0; dstpossible <=3D 1; dstpossible++) {
=20
+ char* r;
int newsize =3D newsizes[nsi] * PAGE;
int flags =3D (maymove ? MREMAP_MAYMOVE : 0) |
(fixed ? MREMAP_FIXED : 0);
dst =3D dstpossible ? try_dst : dst_impossible;
src =3D setup( tidythis, tidylen );
=20
- char* r;
-
if (firsttime) {
printf("dst_possible =3D %p\n", try_dst );
printf("dst_impossible =3D %p\n", dst_impossible );
|
|
From: <sv...@va...> - 2005-10-12 11:34:37
|
Author: sewardj
Date: 2005-10-12 12:34:33 +0100 (Wed, 12 Oct 2005)
New Revision: 1419
Log:
Build fixes for gcc-2.96 (which does not allow declarations after the
first statement in a block).
Modified:
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -104,19 +104,23 @@
void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_idx, UInt sh, UInt dirn )
{
- vassert( vD_idx <=3D 31 );
- vassert( sh <=3D 15 );
- vassert( dirn <=3D 1 );
+ static
UChar ref[32] =3D { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F };
+ U128* pU128_src;
+ U128* pU128_dst;
+
+ vassert( vD_idx <=3D 31 );
+ vassert( sh <=3D 15 );
+ vassert( dirn <=3D 1 );
if (dirn =3D=3D 1) /* shift right */
- sh =3D 16-sh;
+ sh =3D 16-sh;
/* else shift left */
=20
- U128* pU128_src =3D (U128*)&ref[sh];
- U128* pU128_dst =3D &gst->guest_VR0 + (vD_idx*sizeof(gst->guest_VR0));
+ pU128_src =3D (U128*)&ref[sh];
+ pU128_dst =3D &gst->guest_VR0 + (vD_idx*sizeof(gst->guest_VR0));
=20
(*pU128_dst)[0] =3D (*pU128_src)[0];
(*pU128_dst)[1] =3D (*pU128_src)[1];
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/guest-ppc32/toIR.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -788,11 +788,12 @@
bit. Indexing as per getCRbit. */
static void putCRbit ( UInt bi, IRExpr* bit )
{
+ UInt n, off;
IRExpr* safe;
vassert(typeOfIRExpr(irbb->tyenv,bit) =3D=3D Ity_I32);
safe =3D binop(Iop_And32, bit, mkU32(1));
- UInt n =3D bi / 4;
- UInt off =3D bi % 4;
+ n =3D bi / 4;
+ off =3D bi % 4;
vassert(bi < 32);
if (off =3D=3D 3) {
/* This is the SO bit for this CR field */
@@ -1160,8 +1161,6 @@
/* Set the CR6 flags following an AltiVec compare operation. */
static void set_AV_CR6 ( IRExpr* result )
{
- vassert(typeOfIRExpr(irbb->tyenv,result) =3D=3D Ity_V128);
-
/* CR6[0:3] =3D {all_ones, 0, all_zeros, 0}
all_ones =3D (v[0] && v[1] && v[2] && v[3])
all_zeros =3D ~(v[0] || v[1] || v[2] || v[3])
@@ -1172,6 +1171,9 @@
IRTemp v3 =3D newTemp(Ity_V128);
IRTemp rOnes =3D newTemp(Ity_I8);
IRTemp rZeros =3D newTemp(Ity_I8);
+
+ vassert(typeOfIRExpr(irbb->tyenv,result) =3D=3D Ity_V128);
+
assign( v0, result );
assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
@@ -3274,9 +3276,7 @@
UChar flag_Rc =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
IRTemp sh_amt =3D newTemp(Ity_I8);
- IRTemp rb_b5 =3D newTemp(Ity_I32);
IRTemp Rs =3D newTemp(Ity_I32);
- IRTemp Rs_sh =3D newTemp(Ity_I32);
IRTemp Ra =3D newTemp(Ity_I32);
IRTemp Rb =3D newTemp(Ity_I32);
IRTemp sh_amt32 =3D newTemp(Ity_I32);
@@ -4924,12 +4924,12 @@
break;
=20
case 0x644: { // mtvscr (Move to VSCR, AV p130)
+ IRTemp vB =3D newTemp(Ity_V128);
if (vD_addr !=3D 0 || vA_addr !=3D 0) {
vex_printf("dis_av_procctl(PPC32)(opc2,dst)\n");
return False;
}
DIP("mtvscr v%d\n", vB_addr);
- IRTemp vB =3D newTemp(Ity_V128);
assign( vB, getVReg(vB_addr));
putSPR( PPC32_SPR_VSCR, unop(Iop_V128to32, mkexpr(vB)) );=20
break;
@@ -4966,13 +4966,13 @@
switch (opc2) {
=20
case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
- DIP("lvsl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
IRExpr** args =3D mkIRExprVec_3(mkU32(vD_addr), mkexpr(EA), mkU32(=
0));
IRDirty* d =3D unsafeIRDirty_0_N (
0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
&ppc32g_dirtyhelper_LVS,
args );
+ DIP("lvsl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
/* declare guest state effects */
d->needsBBP =3D True;
d->nFxState =3D 1;
@@ -4985,13 +4985,13 @@
break;
}
case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
- DIP("lvsr v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
IRExpr** args =3D mkIRExprVec_3(mkU32(vD_addr), mkexpr(EA), mkU32(=
1));
IRDirty* d =3D unsafeIRDirty_0_N (
0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
&ppc32g_dirtyhelper_LVS,
args );
+ DIP("lvsr v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
/* declare guest state effects */
d->needsBBP =3D True;
d->nFxState =3D 1;
@@ -5071,9 +5071,9 @@
=20
switch (opc2) {
case 0x087: { // stvebx (Store Vector Byte Indexed, AV p131)
- DIP("stvebx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
IRTemp eb =3D newTemp(Ity_I8);
IRTemp idx =3D newTemp(Ity_I8);
+ DIP("stvebx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
assign( eb, binop(Iop_And8, mkU8(0xF),
unop(Iop_32to8, mkexpr(EA) )) );
assign( idx, binop(Iop_Shl8, binop(Iop_Sub8, mkU8(15), mkexpr(eb))=
,
@@ -5098,9 +5098,9 @@
break;
}
case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133)
- DIP("stvewx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
IRTemp eb =3D newTemp(Ity_I8);
IRTemp idx =3D newTemp(Ity_I8);
+ DIP("stvewx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
assign( EA_aligned, binop( Iop_And32, mkexpr(EA), mkU32(0xFFFFFFFC=
) ));
assign( eb, binop(Iop_And8, mkU8(0xF),
unop(Iop_32to8, mkexpr(EA_aligned) )) );
@@ -5602,6 +5602,7 @@
UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
UChar opc2 =3D toUChar((theInstr >> 0) & 0x3F); /* theInstr[0:5]=
*/
=20
+ IRTemp zeros =3D newTemp(Ity_V128);
IRTemp vA =3D newTemp(Ity_V128);
IRTemp vB =3D newTemp(Ity_V128);
IRTemp vC =3D newTemp(Ity_V128);
@@ -5614,13 +5615,11 @@
return False;
}
=20
- IRTemp zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
=20
switch (opc2) {
/* Multiply-Add */
case 0x20: { // vmhaddshs (Multiply High, Add Signed HW Saturate, AV =
p185)
- DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
IRTemp cLo =3D newTemp(Ity_V128);
@@ -5630,6 +5629,7 @@
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
IRTemp cSigns =3D newTemp(Ity_V128);
+ DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
@@ -5654,7 +5654,6 @@
break;
}
case 0x21: { // vmhraddshs (Multiply High Round, Add Signed HW Satura=
te, AV p186)
- DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
IRTemp zKonst =3D newTemp(Ity_V128);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
@@ -5665,6 +5664,7 @@
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
IRTemp cSigns =3D newTemp(Ity_V128);
+ DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
@@ -5695,7 +5695,6 @@
break;
}
case 0x22: { // vmladduhm (Multiply Low, Add Unsigned HW Modulo, AV p=
194)
- DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
IRTemp cLo =3D newTemp(Ity_V128);
@@ -5704,6 +5703,7 @@
IRTemp bHi =3D newTemp(Ity_V128);
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
+ DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA)=
) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB)=
) );
assign( cLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vC)=
) );
@@ -5723,7 +5723,6 @@
=20
/* Multiply-Sum */
case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
- DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp zKonst =3D newTemp(Ity_V128);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
@@ -5731,6 +5730,7 @@
IRTemp odd_even =3D newTemp(Ity_V128);
IRTemp even_odd =3D newTemp(Ity_V128);
IRTemp even_even =3D newTemp(Ity_V128);
+ DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo16Ux8, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi16Ux8, mkexpr(vA), mkexpr(vB)) );
/* zKonst just used to separate the lanes out */
@@ -5754,9 +5754,9 @@
return False;
=20
case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205)
- DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
+ DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo32Ux4, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi32Ux4, mkexpr(vA), mkexpr(vB)) );
putVReg( vD_addr,
@@ -5770,9 +5770,9 @@
return False;
=20
case 0x28: { // vmsumshm (Multiply Sum Signed HW Modulo, AV p202)
- DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
+ DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo32Sx4, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi32Sx4, mkexpr(vA), mkexpr(vB)) );
putVReg( vD_addr,
@@ -5848,8 +5848,8 @@
break;
=20
case 0x1C4: { // vsl (Shift Left, AV p239)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x7),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5858,8 +5858,8 @@
break;
}
case 0x40C: { // vslo (Shift Left by Octet, AV p243)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x78),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5886,8 +5886,8 @@
break;
=20
case 0x2C4: { // vsr (Shift Right, AV p251)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x7),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5911,8 +5911,8 @@
break;
=20
case 0x44C: { // vsro (Shift Right by Octet, AV p258)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x78),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5968,11 +5968,11 @@
return True;
=20
case 0x2B: { // vperm (Permute, AV p218)
- DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
/* limited to two args for IR, so have to play games... */
IRTemp a_perm =3D newTemp(Ity_V128);
IRTemp b_perm =3D newTemp(Ity_V128);
IRTemp mask =3D newTemp(Ity_V128);
+ DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
assign( a_perm, binop(Iop_Perm, mkexpr(vA), mkexpr(vC)) );
assign( b_perm, binop(Iop_Perm, mkexpr(vB), mkexpr(vC)) );
// mask[i8] =3D (vC[i8]_4 =3D=3D 1) ? 0xFF : 0x0
@@ -6049,26 +6049,26 @@
=20
/* Splat */
case 0x20C: { // vspltb (Splat Byte, AV p245)
- DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
/* vD =3D Dup8x16( vB[UIMM_5] ) */
UChar sh_uimm =3D (15-UIMM_5)*8;
+ DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
putVReg( vD_addr, unop(Iop_Dup8x16,
unop(Iop_32to8, unop(Iop_V128to32,=20
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
break;
}
case 0x24C: { // vsplth (Splat Half Word, AV p246)
+ UChar sh_uimm =3D (7-UIMM_5)*16;
DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
- UChar sh_uimm =3D (7-UIMM_5)*16;
putVReg( vD_addr, unop(Iop_Dup16x8,
unop(Iop_32to16, unop(Iop_V128to32,=20
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
break;
}
case 0x28C: { // vspltw (Splat Word, AV p250)
- DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
/* vD =3D Dup32x4( vB[UIMM_5] ) */
UChar sh_uimm =3D (3-UIMM_5)*32;
+ DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
putVReg( vD_addr, unop(Iop_Dup32x4,
unop(Iop_V128to32,
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm)))) );
@@ -6107,6 +6107,8 @@
UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
=20
+ IRTemp signs =3D IRTemp_INVALID;
+ IRTemp zeros =3D IRTemp_INVALID;
IRTemp vA =3D newTemp(Ity_V128);
IRTemp vB =3D newTemp(Ity_V128);
assign( vA, getVReg(vA_addr));
@@ -6142,12 +6144,12 @@
return True;
=20
case 0x10E: { // vpkshus (Pack Signed HW Unsigned Saturate, AV p221)
- DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
// This insn does a signed->unsigned saturating conversion.
// Conversion done here, then uses unsigned->unsigned vpk insn:
// =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 15) )
IRTemp vA_tmp =3D newTemp(Ity_V128);
IRTemp vB_tmp =3D newTemp(Ity_V128);
+ DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
unop(Iop_NotV128,
binop(Iop_SarN16x8,
@@ -6162,12 +6164,12 @@
return True;
}
case 0x14E: { // vpkswus (Pack Signed W Unsigned Saturate, AV p223)
- DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
// This insn does a signed->unsigned saturating conversion.
// Conversion done here, then uses unsigned->unsigned vpk insn:
// =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 31) )
IRTemp vA_tmp =3D newTemp(Ity_V128);
IRTemp vB_tmp =3D newTemp(Ity_V128);
+ DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
unop(Iop_NotV128,
binop(Iop_SarN32x4,
@@ -6194,7 +6196,6 @@
return True;
=20
case 0x30E: { // vpkpx (Pack Pixel, AV p219)
- DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
/* CAB: Worth a new primop? */
/* Using shifts to compact pixel elements, then packing them them =
*/
IRTemp a1 =3D newTemp(Ity_V128);
@@ -6205,6 +6206,7 @@
IRTemp b2 =3D newTemp(Ity_V128);
IRTemp b3 =3D newTemp(Ity_V128);
IRTemp b_tmp =3D newTemp(Ity_V128);
+ DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( a1, binop(Iop_ShlN16x8,
binop(Iop_ShrN32x4, mkexpr(vA), mkU8(19)),
mkU8(10)) );
@@ -6244,8 +6246,8 @@
return False;
}
=20
- IRTemp signs =3D newTemp(Ity_V128);
- IRTemp zeros =3D newTemp(Ity_V128);
+ signs =3D newTemp(Ity_V128);
+ zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
=20
switch (opc2) {
@@ -6275,7 +6277,6 @@
break;
}
case 0x34E: { // vupkhpx (Unpack High Pixel16, AV p276)
- DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
/* CAB: Worth a new primop? */
/* Using shifts to isolate pixel elements, then expanding them */
IRTemp z0 =3D newTemp(Ity_V128);
@@ -6284,6 +6285,7 @@
IRTemp z2 =3D newTemp(Ity_V128);
IRTemp z3 =3D newTemp(Ity_V128);
IRTemp z23 =3D newTemp(Ity_V128);
+ DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
assign( z0, binop(Iop_ShlN16x8,
binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
mkU8(8)) );
@@ -6308,7 +6310,6 @@
break;
}
case 0x3CE: { // vupklpx (Unpack Low Pixel16, AV p279)
- DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
/* identical to vupkhpx, except interleaving LO */
IRTemp z0 =3D newTemp(Ity_V128);
IRTemp z1 =3D newTemp(Ity_V128);
@@ -6316,6 +6317,7 @@
IRTemp z2 =3D newTemp(Ity_V128);
IRTemp z3 =3D newTemp(Ity_V128);
IRTemp z23 =3D newTemp(Ity_V128);
+ DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
assign( z0, binop(Iop_ShlN16x8,
binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
mkU8(8)) );
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/host-ppc32/hdefs.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -1313,12 +1313,13 @@
return;
=20
case Pin_AvLdSt: {
- UChar sz =3D i->Pin.AvLdSt.sz;
+ UChar sz =3D i->Pin.AvLdSt.sz;
+ HChar* str_size;
if (i->Pin.AvLdSt.addr->tag =3D=3D Pam_IR) {
ppLoadImm(hregPPC32_GPR30(), i->Pin.AvLdSt.addr->Pam.RR.index);
vex_printf(" ; ");
}
- char* str_size =3D sz=3D=3D1 ? "eb" : sz=3D=3D2 ? "eh" : sz=3D=3D4=
? "ew" : "";
+ str_size =3D sz=3D=3D1 ? "eb" : sz=3D=3D2 ? "eh" : sz=3D=3D4 ? "ew=
" : "";
if (i->Pin.AvLdSt.isLoad)
vex_printf("lv%sx ", str_size);
else
@@ -3121,18 +3122,20 @@
vassert(sz =3D=3D 8 || sz =3D=3D 16 || sz =3D=3D 32);
=20
if (i->Pin.AvSplat.src->tag =3D=3D Pvi_Imm) {
+ Char simm5;
opc2 =3D (sz =3D=3D 8) ? 780 : (sz =3D=3D 16) ? 844 : 908; //=
8,16,32
/* expects 5-bit-signed-imm */
- Char simm5 =3D i->Pin.AvSplat.src->Pvi.Imm5s;
+ simm5 =3D i->Pin.AvSplat.src->Pvi.Imm5s;
vassert(simm5 >=3D -16 && simm5 <=3D 15);
simm5 =3D simm5 & 0x1F;
p =3D mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2 );
}
else { // Pri_Reg
+ UInt lowest_lane;
opc2 =3D (sz =3D=3D 8) ? 524 : (sz =3D=3D 16) ? 588 : 652; // =
8,16,32
vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) =3D=3D HRcVec128=
);
v_src =3D vregNo(i->Pin.AvSplat.src->Pvi.Reg);
- UInt lowest_lane =3D (128/sz)-1;
+ lowest_lane =3D (128/sz)-1;
p =3D mkFormVX( p, 4, v_dst, lowest_lane, v_src, opc2 );
}
goto done;
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/host-ppc32/isel.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -761,13 +761,13 @@
*/
static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e )
{
+ HReg r_src;
HReg dst =3D newVRegV(env);
PPC32RI* ri =3D iselIntExpr_RI(env, e);
IRType ty =3D typeOfIRExpr(env->type_env,e);
UInt sz =3D (ty =3D=3D Ity_I8) ? 8 : (ty =3D=3D Ity_I16) ? 16 : =
32;
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32);
=20
- HReg r_src;
/* special case: immediate */
if (ri->tag =3D=3D Pri_Imm) {
Int simm32 =3D (Int)ri->Pri.Imm;
@@ -815,13 +815,13 @@
{
/* CAB: Perhaps faster to store r_src multiple times (sz dependent=
),
and simply load the vector? */
-
+ HReg r_aligned16;
HReg v_src =3D newVRegV(env);
PPC32AMode *am_off12;
=20
sub_from_sp( env, 32 ); // Move SP down
/* Get a 16-aligned address within our stack space */
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off12 =3D PPC32AMode_IR( 12, r_aligned16);
=20
/* Store r_src in low word of 16-aligned mem */
@@ -1295,13 +1295,14 @@
}
=20
case Iop_V128to32: {
+ HReg r_aligned16;
HReg dst =3D newVRegI(env);
HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
PPC32AMode *am_off0, *am_off12;
sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16 );
am_off12 =3D PPC32AMode_IR( 12,r_aligned16 );
=20
@@ -1802,16 +1803,14 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLT32U
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32S
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32U)) {
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-
+ PPC32RH* ri2;
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
Bool syned =3D False;
if (e->Iex.Binop.op =3D=3D Iop_CmpLT32S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE32S) {
syned =3D True;
}
-
- PPC32RH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
-
+ ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
addInstr(env, PPC32Instr_Cmp32(syned,7,r1,ri2));
=20
switch (e->Iex.Binop.op) {
@@ -2428,6 +2427,7 @@
/* V128{HI}to64 */
case Iop_V128HIto64:
case Iop_V128to64: {
+ HReg r_aligned16;
Int off =3D e->Iex.Unop.op=3D=3DIop_V128HIto64 ? 0 : 8;
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
@@ -2436,7 +2436,7 @@
sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16 );
am_offHI =3D PPC32AMode_IR( off, r_aligned16 );
am_offLO =3D PPC32AMode_IR( off+4, r_aligned16 );
@@ -3086,20 +3086,21 @@
//.. }
=20
case Iop_32UtoV128: {
+ HReg r_aligned16, r_zeros;
HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
HReg dst =3D newVRegV(env);
PPC32AMode *am_off0, *am_off4, *am_off8, *am_off12;
sub_from_sp( env, 32 ); // Move SP down
=20
/* Get a quadword aligned address within our stack space */
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16);
am_off4 =3D PPC32AMode_IR( 4, r_aligned16);
am_off8 =3D PPC32AMode_IR( 8, r_aligned16);
am_off12 =3D PPC32AMode_IR( 12, r_aligned16);
=20
- /* Store zero's */
- HReg r_zeros =3D newVRegI(env);
+ /* Store zeros */
+ r_zeros =3D newVRegI(env);
addInstr(env, PPC32Instr_LI32(r_zeros, 0x0));
addInstr(env, PPC32Instr_Store( 4, am_off0, r_zeros ));
addInstr(env, PPC32Instr_Store( 4, am_off4, r_zeros ));
@@ -3170,14 +3171,14 @@
//.. }
//..=20
case Iop_64HLtoV128: {
- HReg r3, r2, r1, r0;
+ HReg r3, r2, r1, r0, r_aligned16;
PPC32AMode *am_off0, *am_off4, *am_off8, *am_off12;
HReg dst =3D newVRegV(env);
/* do this via the stack (easy, convenient, etc) */
sub_from_sp( env, 32 ); // Move SP down
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16);
am_off4 =3D PPC32AMode_IR( 4, r_aligned16);
am_off8 =3D PPC32AMode_IR( 8, r_aligned16);
|
|
From: <sv...@va...> - 2005-10-12 11:30:51
|
Author: tom
Date: 2005-10-12 12:30:43 +0100 (Wed, 12 Oct 2005)
New Revision: 4910
Log:
Correct variable name.
Modified:
trunk/configure.in
Modified: trunk/configure.in
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/configure.in 2005-10-12 11:27:33 UTC (rev 4909)
+++ trunk/configure.in 2005-10-12 11:30:43 UTC (rev 4910)
@@ -428,15 +428,15 @@
int main () { return 0 ; }
],
[
-no_pointer_sign=3Dyes
+declaration_after_statement=3Dyes
AC_MSG_RESULT([yes])
], [
-no_pointer_sign=3Dno
+declaration_after_statement=3Dno
AC_MSG_RESULT([no])
])
CFLAGS=3D$safe_CFLAGS
=20
-if test x$no_pointer_sign =3D xyes; then
+if test x$declaration_after_statement =3D xyes; then
CFLAGS=3D"$CFLAGS -Wdeclaration-after-statement"
fi
=20
|
|
From: <sv...@va...> - 2005-10-12 11:27:39
|
Author: tom
Date: 2005-10-12 12:27:33 +0100 (Wed, 12 Oct 2005)
New Revision: 4909
Log:
Only add -Wdeclaration-after-statement if the compiler supports it.
Modified:
trunk/Makefile.core.am
trunk/Makefile.tool-flags.am
trunk/configure.in
Modified: trunk/Makefile.core.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/Makefile.core.am 2005-10-12 10:51:01 UTC (rev 4908)
+++ trunk/Makefile.core.am 2005-10-12 11:27:33 UTC (rev 4909)
@@ -9,7 +9,7 @@
-DVGO_$(VG_OS)=3D1 \
-DVGP_$(VG_ARCH)_$(VG_OS)=3D1
=20
-BASE_AM_CFLAGS =3D @ARCH_CORE_AM_CFLAGS@ -Wmissing-prototypes -Wdeclarat=
ion-after-statement -Winline -Wall -Wshadow -O -g
+BASE_AM_CFLAGS =3D @ARCH_CORE_AM_CFLAGS@ -Wmissing-prototypes -Winline -=
Wall -Wshadow -O -g
=20
PIC_AM_CFLAGS =3D $(BASE_AM_CFLAGS) -fpic -fno-omit-frame-pointer
=20
Modified: trunk/Makefile.tool-flags.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/Makefile.tool-flags.am 2005-10-12 10:51:01 UTC (rev 4908)
+++ trunk/Makefile.tool-flags.am 2005-10-12 11:27:33 UTC (rev 4909)
@@ -5,6 +5,6 @@
-DVGP_$(VG_ARCH)_$(VG_OS)=3D1
=20
AM_CPPFLAGS =3D $(add_includes)
-AM_CFLAGS =3D $(WERROR) -Wmissing-prototypes -Wdeclaration-after-stateme=
nt -Winline -Wall -Wshadow -O -g @ARCH_TOOL_AM_CFLAGS@
+AM_CFLAGS =3D $(WERROR) -Wmissing-prototypes -Winline -Wall -Wshadow -O =
-g @ARCH_TOOL_AM_CFLAGS@
AM_CCASFLAGS =3D $(add_includes)
=20
Modified: trunk/configure.in
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/configure.in 2005-10-12 10:51:01 UTC (rev 4908)
+++ trunk/configure.in 2005-10-12 11:27:33 UTC (rev 4909)
@@ -418,6 +418,29 @@
fi
=20
=20
+# does this compiler support -Wdeclaration-after-statement ?
+AC_MSG_CHECKING([if gcc accepts -Wdeclaration-after-statement ])
+
+safe_CFLAGS=3D$CFLAGS
+CFLAGS=3D"-Wdeclaration-after-statement"
+
+AC_TRY_COMPILE(, [
+int main () { return 0 ; }
+],
+[
+no_pointer_sign=3Dyes
+AC_MSG_RESULT([yes])
+], [
+no_pointer_sign=3Dno
+AC_MSG_RESULT([no])
+])
+CFLAGS=3D$safe_CFLAGS
+
+if test x$no_pointer_sign =3D xyes; then
+ CFLAGS=3D"$CFLAGS -Wdeclaration-after-statement"
+fi
+
+
# Check for TLS support in the compiler and linker
AC_CACHE_CHECK([for TLS support], vg_cv_tls,
[AC_ARG_ENABLE(tls, [ --enable-tls platform supports=
TLS],
|
|
From: Tom H. <to...@co...> - 2005-10-12 11:25:26
|
In message <200...@ac...>
Julian Seward <js...@ac...> wrote:
>> Add -Wdeclaration-after-statement
>
> Ehm .. gcc-3.3.3 on both x86 and ppc32 have never heard of this.
> You sure it isn't a gcc4ism?
Quite probably... I'll sort it out.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
|
|
From: Julian S. <js...@ac...> - 2005-10-12 11:04:30
|
> Add -Wdeclaration-after-statement Ehm .. gcc-3.3.3 on both x86 and ppc32 have never heard of this. You sure it isn't a gcc4ism? J |
|
From: <sv...@va...> - 2005-10-12 10:51:07
|
Author: sewardj
Date: 2005-10-12 11:51:01 +0100 (Wed, 12 Oct 2005)
New Revision: 4908
Log:
Notify the tool via tool_discard_basic_block_info() about translations
thrown away due to lack of space.
Modified:
trunk/coregrind/m_transtab.c
Modified: trunk/coregrind/m_transtab.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_transtab.c 2005-10-12 10:50:56 UTC (rev 4907)
+++ trunk/coregrind/m_transtab.c 2005-10-12 10:51:01 UTC (rev 4908)
@@ -331,6 +331,11 @@
for (i =3D 0; i < N_TTES_PER_SECTOR; i++) {
if (sectors[sno].tt[i].status =3D=3D InUse) {
n_dump_osize +=3D vge_osize(§ors[sno].tt[i].vge);
+ /* Tell the tool too. */
+ if (VG_(needs).basic_block_discards) {
+ VG_TDICT_CALL( tool_discard_basic_block_info,
+ sectors[sno].tt[i].vge );
+ }
}
}
if (VG_(clo_verbosity) > 2)
|
|
From: <sv...@va...> - 2005-10-12 10:51:04
|
Author: tom
Date: 2005-10-12 11:50:56 +0100 (Wed, 12 Oct 2005)
New Revision: 4907
Log:
Fix x86 specific declaration-before-statement warnings.
Modified:
trunk/coregrind/m_syswrap/syswrap-x86-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-x86-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-x86-linux.c 2005-10-12 10:45:27 UTC=
(rev 4906)
+++ trunk/coregrind/m_syswrap/syswrap-x86-linux.c 2005-10-12 10:50:56 UTC=
(rev 4907)
@@ -115,6 +115,8 @@
static void run_a_thread_NORETURN ( Word tidW )
{
ThreadId tid =3D (ThreadId)tidW;
+ VgSchedReturnCode src;
+ Int c;
=20
VG_(debugLog)(1, "syswrap-x86-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
@@ -122,14 +124,14 @@
(ULong)tidW);
=20
/* Run the thread all the way through. */
- VgSchedReturnCode src =3D ML_(thread_wrapper)(tid); =20
+ src =3D ML_(thread_wrapper)(tid); =20
=20
VG_(debugLog)(1, "syswrap-x86-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
"ML_(thread_wrapper) done\n",
(ULong)tidW);
=20
- Int c =3D VG_(count_living_threads)();
+ c =3D VG_(count_living_threads)();
vg_assert(c >=3D 1); /* stay sane */
=20
if (c =3D=3D 1) {
@@ -146,13 +148,15 @@
=20
} else {
=20
+ ThreadState *tst;
+
VG_(debugLog)(1, "syswrap-x86-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
"not last one standing\n",
(ULong)tidW);
=20
/* OK, thread is dead, but others still exist. Just exit. */
- ThreadState *tst =3D VG_(get_ThreadState)(tid);
+ tst =3D VG_(get_ThreadState)(tid);
=20
/* This releases the run lock */
VG_(exit_thread)(tid);
@@ -220,10 +224,12 @@
*/
void VG_(main_thread_wrapper_NORETURN)(ThreadId tid)
{
+ Addr esp;
+
VG_(debugLog)(1, "syswrap-x86-linux",=20
"entering VG_(main_thread_wrapper_NORETURN)\n");
=20
- Addr esp =3D allocstack(tid);
+ esp =3D allocstack(tid);
=20
/* If we can't even allocate the first thread's stack, we're hosed.
Give up. */
|
|
From: <sv...@va...> - 2005-10-12 10:45:30
|
Author: tom
Date: 2005-10-12 11:45:27 +0100 (Wed, 12 Oct 2005)
New Revision: 4906
Log:
Fix statement-before-declaration warnings for the core code.
Modified:
trunk/coregrind/m_debuginfo/dwarf.c
trunk/coregrind/m_debuginfo/symtab.c
trunk/coregrind/m_libcfile.c
trunk/coregrind/m_main.c
trunk/coregrind/m_mallocfree.c
trunk/coregrind/m_oset.c
trunk/coregrind/m_syswrap/syswrap-amd64-linux.c
trunk/coregrind/m_syswrap/syswrap-generic.c
trunk/coregrind/m_syswrap/syswrap-linux.c
trunk/coregrind/m_syswrap/syswrap-main.c
Modified: trunk/coregrind/m_debuginfo/dwarf.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_debuginfo/dwarf.c 2005-10-12 10:32:08 UTC (rev 4905=
)
+++ trunk/coregrind/m_debuginfo/dwarf.c 2005-10-12 10:45:27 UTC (rev 4906=
)
@@ -1630,8 +1630,8 @@
=20
static Short read_Short ( UChar* data )
{
+ Short r =3D 0;
vg_assert(host_is_little_endian());
- Short r =3D 0;
r =3D data[0]=20
| ( ((UInt)data[1]) << 8 );
return r;
@@ -1639,8 +1639,8 @@
=20
static Int read_Int ( UChar* data )
{
+ Int r =3D 0;
vg_assert(host_is_little_endian());
- Int r =3D 0;
r =3D data[0]=20
| ( ((UInt)data[1]) << 8 )=20
| ( ((UInt)data[2]) << 16 )=20
@@ -1650,8 +1650,8 @@
=20
static Long read_Long ( UChar* data )
{
+ Long r =3D 0;
vg_assert(host_is_little_endian());
- Long r =3D 0;
r =3D data[0]=20
| ( ((ULong)data[1]) << 8 )=20
| ( ((ULong)data[2]) << 16 )=20
@@ -1665,8 +1665,8 @@
=20
static UShort read_UShort ( UChar* data )
{
+ UInt r =3D 0;
vg_assert(host_is_little_endian());
- UInt r =3D 0;
r =3D data[0]=20
| ( ((UInt)data[1]) << 8 );
return r;
@@ -1674,8 +1674,8 @@
=20
static UInt read_UInt ( UChar* data )
{
+ UInt r =3D 0;
vg_assert(host_is_little_endian());
- UInt r =3D 0;
r =3D data[0]=20
| ( ((UInt)data[1]) << 8 )=20
| ( ((UInt)data[2]) << 16 )=20
@@ -1685,8 +1685,8 @@
=20
static ULong read_ULong ( UChar* data )
{
+ ULong r =3D 0;
vg_assert(host_is_little_endian());
- ULong r =3D 0;
r =3D data[0]=20
| ( ((ULong)data[1]) << 8 )=20
| ( ((ULong)data[2]) << 16 )=20
@@ -2236,6 +2236,9 @@
previously-seen CIE.
*/
while (True) {
+ UChar* ciefde_start;
+ UInt ciefde_len;
+ UInt cie_pointer;
=20
/* Are we done? */
if (data =3D=3D ehframe + ehframe_sz)
@@ -2250,12 +2253,12 @@
/* Ok, we must be looking at the start of a new CIE or FDE.
Figure out which it is. */
=20
- UChar* ciefde_start =3D data;
+ ciefde_start =3D data;
if (VG_(clo_trace_cfi))=20
VG_(printf)("\ncie/fde.start =3D %p (ehframe + 0x%x)\n",=20
ciefde_start, ciefde_start - ehframe);
=20
- UInt ciefde_len =3D read_UInt(data); data +=3D sizeof(UInt);
+ ciefde_len =3D read_UInt(data); data +=3D sizeof(UInt);
if (VG_(clo_trace_cfi))=20
VG_(printf)("cie/fde.length =3D %d\n", ciefde_len);
=20
@@ -2269,7 +2272,7 @@
goto bad;
}
=20
- UInt cie_pointer =3D read_UInt(data);=20
+ cie_pointer =3D read_UInt(data);=20
data +=3D sizeof(UInt); /* XXX see XXX below */
if (VG_(clo_trace_cfi))=20
VG_(printf)("cie.pointer =3D %d\n", cie_pointer);
@@ -2277,7 +2280,9 @@
/* If cie_pointer is zero, we've got a CIE; else it's an FDE. */
if (cie_pointer =3D=3D 0) {
=20
- Int this_CIE;
+ Int this_CIE;
+ UChar cie_version;
+ UChar* cie_augmentation;
=20
/* --------- CIE --------- */
if (VG_(clo_trace_cfi))=20
@@ -2299,7 +2304,7 @@
later when looking at an FDE. */
the_CIEs[this_CIE].offset =3D ciefde_start - ehframe;
=20
- UChar cie_version =3D read_UChar(data); data +=3D sizeof(UChar)=
;
+ cie_version =3D read_UChar(data); data +=3D sizeof(UChar);
if (VG_(clo_trace_cfi))
VG_(printf)("cie.version =3D %d\n", (Int)cie_version);
if (cie_version !=3D 1) {
@@ -2307,7 +2312,7 @@
goto bad;
}
=20
- UChar* cie_augmentation =3D data;
+ cie_augmentation =3D data;
data +=3D 1 + VG_(strlen)(cie_augmentation);
if (VG_(clo_trace_cfi))=20
VG_(printf)("cie.augment =3D \"%s\"\n", cie_augmentation=
);
@@ -2408,9 +2413,13 @@
} else {
=20
UnwindContext ctx, restore_ctx;
- Int cie;
- UInt look_for;
- Bool ok;
+ Int cie;
+ UInt look_for;
+ Bool ok;
+ Addr fde_initloc;
+ UWord fde_arange;
+ UChar* fde_instrs;
+ Int fde_ilen;
=20
/* --------- FDE --------- */
=20
@@ -2433,14 +2442,14 @@
goto bad;
}
=20
- Addr fde_initloc=20
+ fde_initloc=20
=3D read_encoded_Addr(data, the_CIEs[cie].address_encoding,
&nbytes, ehframe, ehframe_addr);
data +=3D nbytes;
if (VG_(clo_trace_cfi))=20
VG_(printf)("fde.initloc =3D %p\n", (void*)fde_initloc);
=20
- UWord fde_arange=20
+ fde_arange=20
=3D read_encoded_Addr(data, the_CIEs[cie].address_encoding &=
0xf,
&nbytes, ehframe, ehframe_addr);
data +=3D nbytes;
@@ -2452,8 +2461,8 @@
data +=3D nbytes;
}
=20
- UChar* fde_instrs =3D data;
- Int fde_ilen =3D ciefde_start + ciefde_len + sizeof(UInt) =
- data;
+ fde_instrs =3D data;
+ fde_ilen =3D ciefde_start + ciefde_len + sizeof(UInt) - data;
if (VG_(clo_trace_cfi)) {
VG_(printf)("fde.instrs =3D %p\n", fde_instrs);
VG_(printf)("fde.ilen =3D %d\n", (Int)fde_ilen);
Modified: trunk/coregrind/m_debuginfo/symtab.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_debuginfo/symtab.c 2005-10-12 10:32:08 UTC (rev 490=
5)
+++ trunk/coregrind/m_debuginfo/symtab.c 2005-10-12 10:45:27 UTC (rev 490=
6)
@@ -498,6 +498,8 @@
void ML_(addCfiSI) ( SegInfo* si, CfiSI* cfisi )
{
static const Bool debug =3D False;
+ UInt new_sz, i;
+ CfiSI* new_tab;
=20
if (debug) {
VG_(printf)("adding CfiSI: ");
@@ -506,9 +508,6 @@
=20
vg_assert(cfisi->len > 0 && cfisi->len < 2000000);
=20
- UInt new_sz, i;
- CfiSI* new_tab;
-
/* Rule out ones which are completely outside the segment. These
probably indicate some kind of bug, but for the meantime ignore
them. */
Modified: trunk/coregrind/m_libcfile.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_libcfile.c 2005-10-12 10:32:08 UTC (rev 4905)
+++ trunk/coregrind/m_libcfile.c 2005-10-12 10:45:27 UTC (rev 4906)
@@ -212,8 +212,7 @@
OffT off =3D VG_(lseek)( fd, (OffT)offset, VKI_SEEK_SET);
if (off !=3D 0)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
- SysRes res =3D VG_(do_syscall3)(__NR_read, fd, (UWord)buf, count );
- return res;
+ return VG_(do_syscall3)(__NR_read, fd, (UWord)buf, count );
}
=20
/* Create and open (-rw------) a tmp file name incorporating said arg.
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-10-12 10:32:08 UTC (rev 4905)
+++ trunk/coregrind/m_main.c 2005-10-12 10:45:27 UTC (rev 4906)
@@ -114,7 +114,7 @@
=20
HChar** cpp;
HChar** ret;
- HChar* preload_tool_path;;
+ HChar* preload_tool_path;
Int envc, i;
=20
/* Alloc space for the vgpreload_core.so path and vgpreload_<tool>.so
@@ -417,6 +417,7 @@
Addr anon_start =3D clstack_start;
Addr resvn_start =3D anon_start - resvn_size;
SizeT inner_HACK =3D 0;
+ Bool ok;
=20
vg_assert(VG_IS_PAGE_ALIGNED(anon_size));
vg_assert(VG_IS_PAGE_ALIGNED(resvn_size));
@@ -434,12 +435,12 @@
=20
/* Create a shrinkable reservation followed by an anonymous
segment. Together these constitute a growdown stack. */
- Bool ok =3D VG_(am_create_reservation)(
- resvn_start,
- resvn_size -inner_HACK,
- SmUpper,=20
- anon_size +inner_HACK
- );
+ ok =3D VG_(am_create_reservation)(
+ resvn_start,
+ resvn_size -inner_HACK,
+ SmUpper,=20
+ anon_size +inner_HACK
+ );
vg_assert(ok);
/* allocate a stack - mmap enough space for the stack */
res =3D VG_(am_mmap_anon_fixed_client)(
@@ -1468,8 +1469,10 @@
results of a run which encompasses multiple processes. */
static void print_preamble(Bool logging_to_fd, const char* toolname)
{
- Int i;
- =20
+ HChar* xpre =3D VG_(clo_xml) ? " <line>" : "";
+ HChar* xpost =3D VG_(clo_xml) ? "</line>" : "";
+ Int i;
+
if (VG_(clo_xml)) {
VG_(message)(Vg_UserMsg, "<?xml version=3D\"1.0\"?>");
VG_(message)(Vg_UserMsg, "");
@@ -1479,9 +1482,6 @@
VG_(message)(Vg_UserMsg, "");
}
=20
- HChar* xpre =3D VG_(clo_xml) ? " <line>" : "";
- HChar* xpost =3D VG_(clo_xml) ? "</line>" : "";
-
if (VG_(clo_verbosity > 0)) {
=20
if (VG_(clo_xml))
Modified: trunk/coregrind/m_mallocfree.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_mallocfree.c 2005-10-12 10:32:08 UTC (rev 4905)
+++ trunk/coregrind/m_mallocfree.c 2005-10-12 10:45:27 UTC (rev 4906)
@@ -607,8 +607,8 @@
static
UInt pszB_to_listNo ( SizeT pszB )
{
+ SizeT n =3D pszB / VG_MIN_MALLOC_SZB;
vg_assert(0 =3D=3D pszB % VG_MIN_MALLOC_SZB);
- SizeT n =3D pszB / VG_MIN_MALLOC_SZB;
=20
// The first 13 lists hold blocks of size VG_MIN_MALLOC_SZB * list_nu=
m.
// The final 5 hold bigger blocks.
Modified: trunk/coregrind/m_oset.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_oset.c 2005-10-12 10:32:08 UTC (rev 4905)
+++ trunk/coregrind/m_oset.c 2005-10-12 10:45:27 UTC (rev 4906)
@@ -433,11 +433,13 @@
// avl_insert() which doesn't return a Bool.
void VG_(OSet_Insert)(AvlTree* t, void* e)
{
+ AvlNode* n;
+
vg_assert(t);
=20
// Initialise. Even though OSet_AllocNode zeroes these fields, we sh=
ould
// do it again in case a node is removed and then re-added to the tre=
e.
- AvlNode* n =3D node_of_elem(e);
+ n =3D node_of_elem(e);
n->left =3D 0;
n->right =3D 0;
n->balance =3D 0;
@@ -532,9 +534,9 @@
Int cmpres =3D cmp_key_root(t, n);
=20
if (cmpres < 0) {
+ AvlTree left_subtree;
// Remove from the left subtree
vg_assert(t->root->left);
- AvlTree left_subtree;
// Only need to set the used fields in the subtree.
left_subtree.root =3D t->root->left;
left_subtree.cmp =3D t->cmp;
Modified: trunk/coregrind/m_syswrap/syswrap-amd64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-amd64-linux.c 2005-10-12 10:32:08 U=
TC (rev 4905)
+++ trunk/coregrind/m_syswrap/syswrap-amd64-linux.c 2005-10-12 10:45:27 U=
TC (rev 4906)
@@ -107,6 +107,8 @@
static void run_a_thread_NORETURN ( Word tidW )
{
ThreadId tid =3D (ThreadId)tidW;
+ VgSchedReturnCode src;
+ Int c;
=20
VG_(debugLog)(1, "syswrap-amd64-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
@@ -114,14 +116,14 @@
(ULong)tidW);
=20
/* Run the thread all the way through. */
- VgSchedReturnCode src =3D ML_(thread_wrapper)(tid); =20
+ src =3D ML_(thread_wrapper)(tid); =20
=20
VG_(debugLog)(1, "syswrap-amd64-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
"ML_(thread_wrapper) done\n",
(ULong)tidW);
=20
- Int c =3D VG_(count_living_threads)();
+ c =3D VG_(count_living_threads)();
vg_assert(c >=3D 1); /* stay sane */
=20
if (c =3D=3D 1) {
@@ -138,13 +140,15 @@
=20
} else {
=20
+ ThreadState *tst;
+
VG_(debugLog)(1, "syswrap-amd64-linux",=20
"run_a_thread_NORETURN(tid=3D%lld): "
"not last one standing\n",
(ULong)tidW);
=20
/* OK, thread is dead, but others still exist. Just exit. */
- ThreadState *tst =3D VG_(get_ThreadState)(tid);
+ tst =3D VG_(get_ThreadState)(tid);
=20
/* This releases the run lock */
VG_(exit_thread)(tid);
@@ -220,10 +224,12 @@
*/
void VG_(main_thread_wrapper_NORETURN)(ThreadId tid)
{
+ Addr rsp;
+
VG_(debugLog)(1, "syswrap-amd64-linux",=20
"entering VG_(main_thread_wrapper_NORETURN)\n");
=20
- Addr rsp =3D allocstack(tid);
+ rsp =3D allocstack(tid);
=20
/* If we can't even allocate the first thread's stack, we're hosed.
Give up. */
Modified: trunk/coregrind/m_syswrap/syswrap-generic.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-generic.c 2005-10-12 10:32:08 UTC (=
rev 4905)
+++ trunk/coregrind/m_syswrap/syswrap-generic.c 2005-10-12 10:45:27 UTC (=
rev 4906)
@@ -1095,9 +1095,9 @@
UWord arg2, UWord arg3 )
{
SysRes r =3D res;
- vg_assert(!res.isError); /* guaranteed by caller */
Int fd1 =3D ((Int*)arg3)[0];
Int fd2 =3D ((Int*)arg3)[1];
+ vg_assert(!res.isError); /* guaranteed by caller */
POST_MEM_WRITE( arg3, 2*sizeof(int) );
if (!ML_(fd_allowed)(fd1, "socketcall.socketpair", tid, True) ||
!ML_(fd_allowed)(fd2, "socketcall.socketpair", tid, True)) {
@@ -4761,8 +4761,8 @@
int poll(struct pollfd *ufds, unsigned int nfds, int timeout)=20
*/
UInt i;
+ struct vki_pollfd* ufds =3D (struct vki_pollfd *)ARG1;
*flags |=3D SfMayBlock;
- struct vki_pollfd* ufds =3D (struct vki_pollfd *)ARG1;
PRINT("sys_poll ( %p, %d, %d )\n", ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "poll",
struct pollfd *, ufds, unsigned int, nfds, long, timeou=
t);
Modified: trunk/coregrind/m_syswrap/syswrap-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-linux.c 2005-10-12 10:32:08 UTC (re=
v 4905)
+++ trunk/coregrind/m_syswrap/syswrap-linux.c 2005-10-12 10:45:27 UTC (re=
v 4906)
@@ -54,14 +54,14 @@
// scheduler-return-code.
VgSchedReturnCode ML_(thread_wrapper)(Word /*ThreadId*/ tidW)
{
+ VgSchedReturnCode ret;
+ ThreadId tid =3D (ThreadId)tidW;
+ ThreadState* tst =3D VG_(get_ThreadState)(tid);
+
VG_(debugLog)(1, "core_os",=20
"ML_(thread_wrapper)(tid=3D%lld): entry\n",=20
(ULong)tidW);
=20
- VgSchedReturnCode ret;
- ThreadId tid =3D (ThreadId)tidW;
- ThreadState* tst =3D VG_(get_ThreadState)(tid);
-
vg_assert(tst->status =3D=3D VgTs_Init);
=20
/* make sure we get the CPU lock before doing anything significant */
Modified: trunk/coregrind/m_syswrap/syswrap-main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-main.c 2005-10-12 10:32:08 UTC (rev=
4905)
+++ trunk/coregrind/m_syswrap/syswrap-main.c 2005-10-12 10:45:27 UTC (rev=
4906)
@@ -405,10 +405,10 @@
void putSyscallStatusIntoGuestState ( /*IN*/ SyscallStatus* canonica=
l,
/*OUT*/VexGuestArchState* gst_vani=
lla )
{
+#if defined(VGP_x86_linux)
+ VexGuestX86State* gst =3D (VexGuestX86State*)gst_vanilla;
vg_assert(canonical->what =3D=3D SsSuccess=20
|| canonical->what =3D=3D SsFailure);
-#if defined(VGP_x86_linux)
- VexGuestX86State* gst =3D (VexGuestX86State*)gst_vanilla;
if (canonical->what =3D=3D SsFailure) {
/* This isn't exactly right, in that really a Failure with res
not in the range 1 .. 4095 is unrepresentable in the
@@ -419,6 +419,8 @@
}
#elif defined(VGP_amd64_linux)
VexGuestAMD64State* gst =3D (VexGuestAMD64State*)gst_vanilla;
+ vg_assert(canonical->what =3D=3D SsSuccess=20
+ || canonical->what =3D=3D SsFailure);
if (canonical->what =3D=3D SsFailure) {
/* This isn't exactly right, in that really a Failure with res
not in the range 1 .. 4095 is unrepresentable in the
@@ -432,6 +434,9 @@
VexGuestPPC32State* gst =3D (VexGuestPPC32State*)gst_vanilla;
UInt old_cr =3D LibVEX_GuestPPC32_get_CR(gst);
=20
+ vg_assert(canonical->what =3D=3D SsSuccess=20
+ || canonical->what =3D=3D SsFailure);
+
gst->guest_GPR3 =3D canonical->val;
=20
if (canonical->what =3D=3D SsFailure) {
|