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From: Greg P. <gp...@us...> - 2005-09-06 20:56:53
|
Julian Seward writes:
> Let us know of any other insns you need.
I think I'm getting the hang of vex's IR, so I should be able to
write ordinary instructions myself now. I have implementations
of lswi and stswi, though they need a bit more testing.
[lswx/stswx]
> Can you show me the insns in context? In particular it would
> be useful to know how XER is set up prior to the insns.
The uses I've seen so far are the G3 and G4 hand-written bcopy(),
which use lswx/stswx pairs for copying some parts of some lengths.
They're in the Darwin source at xnu:osfmk/ppc/commpage/bcopy_g3.s
and bcopy_g4.s .
Two excerpts are below. They include:
* G3, length <= 32 bytes
* G3, handle misaligned bytes at the start
* G4, handle misaligned bytes at the start.
I've hilited the more relevant instructions in uppercase.
#define rs r4
#define rd r12
#define rc r5
#define w1 r6
#define w2 r7
#define w3 r8
#define w4 r9
#define w5 r10
#define w6 r11
// G3 bcopy(src=r3, dst=r4 (later rd), len=r5)
bcopy_g3:
cmplwi r5,kLong // length > 32 bytes?
sub w1,r4,r3 // must move in reverse if (rd-rs)<rc
mr rd,r4 // start to move source & dest to canonic spot
bge LLong0 // skip if long operand
MTXER r5 // set length for string ops
LSWX r5,0,r3 // load bytes into r5-r12
STSWX r5,0,r4 // store them
blr
// Long operands (more than 32 bytes.)
// w1 = (rd-rs), used to check for alignment
LLong0: // enter from bcopy()
mr rs,r3 // must leave r3 alone (it is return value for memcpy)
LLong1: // enter from memcpy() and memmove()
cmplw cr1,w1,rc // set cr1 blt iff we must move reverse
rlwinm r0,w1,0,0x3 // are operands relatively word-aligned?
NEG w2,rd // prepare to align destination
cmpwi cr5,r0,0 // set cr5 beq if relatively word aligned
blt cr1,LLongReverse // handle reverse move
ANDI. w4,w2,3 // w4 <- #bytes to word align destination
beq cr5,LLongFloat // relatively aligned so use FPRs
sub rc,rc,w4 // adjust count for alignment
srwi r0,rc,5 // get #chunks to xfer (>=1)
rlwinm rc,rc,0,0x1F // mask down to leftover bytes
mtctr r0 // set up loop count
beq 1f // dest already word aligned
// Word align the destination.
MTXER w4 // byte count to xer
cmpwi r0,0 // any chunks to xfer?
LSWX w1,0,rs // move w4 bytes to align dest
add rs,rs,w4
STSWX w1,0,rd
add rd,rd,w4
beq- 2f // pathologic case, no chunks to xfer
1: [...]
// G4 bcopy, "medium" length (32..95 bytes)
// bcopy(src=rs, dst=rd, len=rc)
// Medium and long operands. Use Altivec if long enough, else scalar loops.
// w1 = (rd-rs), used to check for alignment
// cr1 = blt iff we must move reverse
LMedium:
dcbtst 0,rd // touch in destination
cmplwi cr7,rc,kLong // >= 96, long enough for vectors?
NEG w3,rd // start to compute #bytes to align destination
rlwinm r0,w1,0,0x7 // check relative 8-byte alignment
ANDI. w6,w3,7 // w6 <- #bytes to 8-byte align destination
blt cr1,LMediumReverse // handle reverse moves
rlwinm w4,w3,0,0x1F // w4 <- #bytes to 32-byte align destination
cmpwi cr6,r0,0 // set cr6 beq if relatively aligned
bge cr7,LFwdLong // long enough for vectors
// Medium length: use scalar loops.
// w6/cr0 = #bytes to 8-byte align destination
// cr6 = beq if relatively doubleword aligned
sub rc,rc,w6 // decrement length remaining
beq 1f // skip if dest already doubleword aligned
MTXER w6 // set up count for move
LSWX w1,0,rs // move w6 bytes to align destination
STSWX w1,0,rd
[...]
|
|
From: Arndt M. <amu...@is...> - 2005-09-06 15:01:54
|
Hi all! Recently, I found that helgrind is reporting an error in C++ destructor code I couldn't explain. After investigating, I came to the solution. When the destructor of an object is called every destructor of its parents classes is called prior to actual releasing the memory associated with the object. The destructor of the super-class should only see the properties of its class and therefore the environment has to be changed in order to reflect this change in properties and virtual method pointers. This change is done by writing to a location in the object's memory, (that is marked shared read-only, no locks) hence resulting in a warning, because Helgrind does not know anything about objects and destructors and that accesses of an object's memory in its destructor can not result in a data race on itself. I wrote a small example programm exhibiting this bevahior. A solution would be, to set the objects memory to NEW upon entry of the destructor, therfore avoiding false reports. I did this with help of Aspect-C++, where the need to call VALRIND_HG_* in destructors might be expressed as an aspect, but I wonder, if it would be possible in the Helgrind tool itself without reducing the performance of the tool. Any suggestions? Greetings, Arndt |
|
From: <sv...@va...> - 2005-09-06 13:04:47
|
Author: sewardj Date: 2005-09-06 14:04:40 +0100 (Tue, 06 Sep 2005) New Revision: 4609 Log: Record recently-arrived bugs. Modified: trunk/docs/internals/3_0_BUGSTATUS.txt Modified: trunk/docs/internals/3_0_BUGSTATUS.txt =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/docs/internals/3_0_BUGSTATUS.txt 2005-09-06 08:43:15 UTC (rev 4= 608) +++ trunk/docs/internals/3_0_BUGSTATUS.txt 2005-09-06 13:04:40 UTC (rev 4= 609) @@ -61,7 +61,16 @@ =20 FIXED-TRUNK: vg:4425 =20 +---------------------------------------------------------------- +111855 default suppression file is read 1 byte at a time =20 +Perhaps worth a look. + +FIXED-TRUNK: TODO + + + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D Bugs targeted for 3.1.0 and 3.0.2 = =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -114,6 +123,20 @@ FIXED-TRUNK: 4589, 4592 FIXED-30BRANCH: 4597, 4601 =20 +---------------------------------------------------------------- +111851 vex x86->IR: unhandled instruction bytes: 0x9F 0x89 + (lahf/sahf) + +FIXED-TRUNK: TODO +FIXED-30BRANCH: TODO + +---------------------------------------------------------------- +112031 iopl on AMD64 and README_MISSING_SYSCALL_OR_IOCTL update + +FIXED-TRUNK: TODO +FIXED-30BRANCH: TODO + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D Bugs targeted for 3.1.0 and 3.0.1 = =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D |
|
From: Oswald B. <os...@kd...> - 2005-09-06 11:41:28
|
On Tue, Sep 06, 2005 at 11:25:46AM +0100, sv...@va... wrote:
> Author: sewardj
> Date: 2005-09-06 11:25:46 +0100 (Tue, 06 Sep 2005)
> New Revision: 1371
>
> Log:
> Implement mftb{,u}.
>
> +# if defined(__powerpc__)
> [...]
> +# else
> + return 1ULL;
>
bleh. one could code something up based on gettimeofday (and a
micro-second increment to pretend strict monotony in case the same value
is returned twice (how fast would the machine have to be?)).
> +# endif
> +}
--
Hi! I'm a .signature virus! Copy me into your ~/.signature, please!
--
Chaos, panic, and disorder - my work here is done.
|
|
From: Julian S. <js...@ac...> - 2005-09-06 11:06:45
|
> lswx and stswx are rearing their ugly heads again. I have two > solutions coded up, but neither is great. > > 1. Abuse Mux0X by performing 128 1-byte memory ops from either > the right place in memory or a scratch location. lswx generates > about 1800 instructions, and 1400 for stswx. I figured out in principle how to do this so that it (1) only references memory it should and (2) is correctly instrumentable by memcheck. Getting sane performance out of it will involve adding a bit more magic to the IR optimiser, though. Can you show me the insns in context? In particular it would be useful to know how XER is set up prior to the insns. J |
|
From: Julian S. <js...@ac...> - 2005-09-06 10:33:50
|
> Sounds good. I found a kernel switch to disable the Altivec unit,
> so that's not blocking me anymore. The commented-out lwbrx seems
> to work after a small tweak, and a do-nothing mftb works well
> enough for the programs I'm running now.
lwbrx is done, as is mftb{,u}. We tried the do-nothing game for
the x86/amd64 equivalent (rdtsc) and you end up with hangs,
strange long delays, or divisions by zero.
> lswx and stswx are rearing their ugly heads again. I have two
> solutions coded up, but neither is great.
Yeh.
> 2. Use a dirty helper. This is fast, but for memcheck to work
> properly it really needs the "memory touched" size to be
> an expression instead of a constant. I don't know how messy
> this would be to deal with in memcheck.
The problem is that the instrumentation code generated by memcheck
depends on that size -- that is, the number needs to be known at
translation time.
I'll contemplate this.
Let us know of any other insns you need.
J
|
|
From: <sv...@va...> - 2005-09-06 10:25:49
|
Author: sewardj
Date: 2005-09-06 11:25:46 +0100 (Tue, 06 Sep 2005)
New Revision: 1371
Log:
Implement mftb{,u}.
Modified:
trunk/priv/guest-ppc32/gdefs.h
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/gdefs.h 2005-09-06 09:55:27 UTC (rev 1370)
+++ trunk/priv/guest-ppc32/gdefs.h 2005-09-06 10:25:46 UTC (rev 1371)
@@ -101,14 +101,6 @@
}
PPC32CmpF64Result;
=20
-
-/*---------------------------------------------------------*/
-/*--- ppc32 guest helpers ---*/
-/*---------------------------------------------------------*/
-
-/* --- CLEAN HELPERS --- */
-
-
/*
Enumeration for xer_ca/ov calculation helper functions
*/
@@ -129,6 +121,19 @@
};
=20
=20
+/*---------------------------------------------------------*/
+/*--- ppc32 guest helpers ---*/
+/*---------------------------------------------------------*/
+
+/* --- CLEAN HELPERS --- */
+
+/* none, right now */
+
+/* --- DIRTY HELPERS --- */
+
+extern ULong ppc32g_dirtyhelper_MFTB ( void );
+
+
#endif /* ndef __LIBVEX_GUEST_PPC32_DEFS_H */
=20
/*---------------------------------------------------------------*/
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-09-06 09:55:27 UTC (rev 1370)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-09-06 10:25:46 UTC (rev 1371)
@@ -68,7 +68,39 @@
*/
=20
=20
+/*---------------------------------------------------------------*/
+/*--- Misc integer helpers. ---*/
+/*---------------------------------------------------------------*/
=20
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-ppc32 platforms, return 1. */
+/* Reads a complete, consistent 64-bit TB value. */
+ULong ppc32g_dirtyhelper_MFTB ( void )
+{
+# if defined(__powerpc__)
+ ULong res;
+ UInt lo, hi1, hi2;
+ while (1) {
+ __asm__ __volatile__ ("\n"
+ "\tmftbu %0\n"
+ "\tmftb %1\n"
+ "\tmftbu %2\n"
+ : "=3Dr" (hi1), "=3Dr" (lo), "=3Dr" (hi2)
+ );
+ if (hi1 =3D=3D hi2) break;
+ }
+ res =3D ((ULong)hi1) << 32;
+ res |=3D (ULong)lo;
+ return res;
+# else
+ return 1ULL;
+# endif
+}
+
+
+/* Helper-function specialiser. */
+
IRExpr* guest_ppc32_spechelper ( HChar* function_name,
IRExpr** args )
{
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-06 09:55:27 UTC (rev 1370)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-06 10:25:46 UTC (rev 1371)
@@ -3446,7 +3446,7 @@
/* XFX-Form */
UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
UInt SPR =3D (theInstr >> 11) & 0x3FF; /* theInstr[11:2=
0] */
-//uu UInt TBR =3D (theInstr >> 11) & 0x3FF; /* theInstr[=
11:20] */
+ UInt TBR =3D (theInstr >> 11) & 0x3FF; /* theInstr[11:2=
0] */
UChar b20 =3D toUChar((theInstr >> 11) & 0x1); /* theInstr[11] =
*/
UInt CRM =3D (theInstr >> 12) & 0xFF; /* theInstr[12:1=
9] */
UChar b11 =3D toUChar((theInstr >> 11) & 0x1); /* theInstr[20] =
*/
@@ -3459,6 +3459,9 @@
IRTemp Rs =3D newTemp(Ity_I32);
//uu IRTemp tmp =3D newTemp(Ity_I32);
=20
+ /* Reorder TBR field as per PPC32 p475 */
+ TBR =3D ((TBR & 31) << 5) | ((TBR >> 5) & 31);
+
assign( Rs, getIReg(Rs_addr) );
=20
if (opc1 !=3D 0x1F || b0 !=3D 0) {
@@ -3569,12 +3572,34 @@
}
break;
=20
-//zz case 0x173: // mftb (Move from Time Base, PPC32 p475)
-//zz vassert(0);
-//zz=20
-//zz DIP("mftb r%d,0x%x\n", Rd_addr, TBR);
-//zz return False;
- =20
+ case 0x173: { // mftb (Move from Time Base, PPC32 p475)
+ IRTemp val =3D newTemp(Ity_I64);
+ IRExpr** args =3D mkIRExprVec_0();
+ IRDirty* d =3D unsafeIRDirty_1_N (=20
+ val,=20
+ 0/*regparms*/,=20
+ "ppc32g_dirtyhelper_MFTB",=20
+ &ppc32g_dirtyhelper_MFTB,=20
+ args=20
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+
+ switch (TBR) {
+ case 269:=20
+ putIReg( Rd_addr, unop(Iop_64HIto32, mkexpr(val)) );
+ DIP("mftbu r%d", Rd_addr);
+ break;
+ case 268:=20
+ putIReg( Rd_addr, unop(Iop_64to32, mkexpr(val)) );
+ DIP("mftb r%d", Rd_addr);
+ break;
+ default:
+ return False; /* illegal instruction */
+ }
+ break;
+ }
+
case 0x090: // mtcrf (Move to Condition Register Fields, PPC32 p477)
if (b11 !=3D 0 || b20 !=3D 0) {
vex_printf("dis_proc_ctl(PPC32)(mtcrf,b11|b20)\n");
|
|
From: <sv...@va...> - 2005-09-06 09:55:34
|
Author: sewardj
Date: 2005-09-06 10:55:27 +0100 (Tue, 06 Sep 2005)
New Revision: 1370
Log:
Remove some helper functions to do with flag handling. These are
unused because the relevant computations are now done in line.
Modified:
trunk/priv/guest-ppc32/gdefs.h
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/gdefs.h 2005-09-06 09:10:09 UTC (rev 1369)
+++ trunk/priv/guest-ppc32/gdefs.h 2005-09-06 09:55:27 UTC (rev 1370)
@@ -108,16 +108,7 @@
=20
/* --- CLEAN HELPERS --- */
=20
-// Calculate XER flags
-extern=20
-UInt ppc32g_calculate_xer_ov ( UInt op,=20
- UInt res, UInt argL, UInt argR );
=20
-extern=20
-UInt ppc32g_calculate_xer_ca ( UInt op,=20
- UInt res, UInt argL, UInt argR,=20
- UInt old_ca );
-
/*
Enumeration for xer_ca/ov calculation helper functions
*/
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-09-06 09:10:09 UTC (rev 1369)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-09-06 09:55:27 UTC (rev 1370)
@@ -68,89 +68,7 @@
*/
=20
=20
-#define INT32_MIN (-2147483647-1)
=20
-// Calculate XER_OV
-UInt ppc32g_calculate_xer_ov ( UInt op, UInt res, UInt argL, UInt argR )
-{
- switch (op) {
- case PPC32G_FLAG_OP_ADD: // addo, addc
- case PPC32G_FLAG_OP_ADDE: // addeo, addmeo, addzeo
- return ((argL^argR^-1) & (argL^res) & (1<<31)) ? 1:0;
- // i.e. ((both_same_sign) & (sign_changed) & (sign_mask))
- =20
- case PPC32G_FLAG_OP_DIVW: // divwo
- return ((argL =3D=3D INT32_MIN && argR =3D=3D -1) || argR =3D=3D 0=
) ? 1:0;
- =20
- case PPC32G_FLAG_OP_DIVWU: // divwuo
- return (argR =3D=3D 0) ? 1:0;
- =20
- case PPC32G_FLAG_OP_MULLW: { // mullwo
- /* OV true if result can't be represented in 32 bits
- i.e sHi !=3D sign extension of sLo */
- Long l_res =3D ((Long)((Int)argL)) * ((Long)((Int)argR));
- Int sHi =3D (Int)toUInt(l_res >> 32);
- Int sLo =3D (Int)l_res;
- return (sHi !=3D (sLo >> /*s*/ 31)) ? 1:0;
- }
-
- case PPC32G_FLAG_OP_NEG: // nego
- return (argL =3D=3D 0x80000000) ? 1:0;
- =20
- case PPC32G_FLAG_OP_SUBF: // subfo
- case PPC32G_FLAG_OP_SUBFC: // subfco
- case PPC32G_FLAG_OP_SUBFE: // subfeo, subfmeo, subfzeo
- return (((~argL)^argR^(-1)) & ((~argL)^res) & (1<<31)) ? 1:0;
-
- default:
- break;
- }
-
- vpanic("ppc32g_calculate_xer_ov(ppc32)");
- return 0; // notreached
-}
-
-// Calculate XER_CA
-UInt ppc32g_calculate_xer_ca ( UInt op, UInt res,
- UInt argL, UInt argR, UInt old_ca )
-{
- switch (op) {
- case PPC32G_FLAG_OP_ADD: // addc[o], addic
- return (res < argL) ? 1:0;
-
- case PPC32G_FLAG_OP_ADDE: // adde[o], addze[o], addme[o]
- return (res < argL || (old_ca=3D=3D1 && res=3D=3DargL)) ? 1:0;
-
- case PPC32G_FLAG_OP_SUBFC: // subfc[o]
- case PPC32G_FLAG_OP_SUBFI: // subfic
- return (res <=3D argR) ? 1:0;
-
- case PPC32G_FLAG_OP_SUBFE: // subfe[o], subfze[o], subfme[o]
- return ((res < argR) || (old_ca =3D=3D 1 && res =3D=3D argR)) ? 1:=
0;
-
- case PPC32G_FLAG_OP_SRAW: // sraw
- if ((argR & 0x20) =3D=3D 0) { // shift <=3D 31
- // xer_ca =3D sign && (bits_shifted_out !=3D 0)
- return (((argL & 0x80000000) &&
- ((argL & (0xFFFFFFFF >> (32-argR))) !=3D 0)) !=3D 0) ?=
1:0;
- }
- // shift > 31
- // xer_ca =3D sign && src !=3D 0
- return (((argL & 0x80000000) && (argR !=3D 0)) !=3D 0) ? 1:0;
-
- case PPC32G_FLAG_OP_SRAWI: // srawi
- // xer_ca =3D sign && (bits_shifted_out !=3D 0)
- return (((argL & 0x80000000) &&
- ((argL & (0xFFFFFFFF >> (32-argR))) !=3D 0)) !=3D 0) ? 1:=
0;
-
- default:
- break;
- }
- vpanic("ppc32g_calculate_xer_ov(ppc32)");
- return 0; // notreached
-}
-
-
IRExpr* guest_ppc32_spechelper ( HChar* function_name,
IRExpr** args )
{
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-06 09:10:09 UTC (rev 1369)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-06 09:55:27 UTC (rev 1370)
@@ -859,87 +859,6 @@
}
=20
=20
-//zz /* -------------- Evaluating the flags-thunk. -------------- */
-//zz=20
-//zz /* Calculate CR7 (IBM CR0) conditional flags */
-//zz static IRExpr* mk_ppc32g_calculate_cr7 ( void )
-//zz {
-//zz IRExpr** args =3D
-//zz mkIRExprVec_3( IRExpr_Get(OFFB_CC_OP, Ity_I32),
-//zz IRExpr_Get(OFFB_CC_DEP1, Ity_I32),
-//zz IRExpr_Get(OFFB_CC_DEP2, Ity_I32) );
-//zz IRExpr* call
-//zz =3D mkIRExprCCall(
-//zz Ity_I32,
-//zz 0/*regparm*/,=20
-//zz "ppc32g_calculate_cr7", &ppc32g_calculate_cr7,
-//zz args
-//zz );
-//zz=20
-//zz // TODO
-//zz // 02/02/05 - leaving definedness stuff 'till get memcheck working =
well.
-//zz=20
-//zz /* Exclude OP from definedness checking. We're only
-//zz interested in DEP1 and DEP2. */
-//zz // call->Iex.CCall.cee->mcx_mask =3D 1;
-//zz=20
-//zz return call;
-//zz }
-//zz=20
-//zz /* Calculate XER_OV flag */
-//zz static IRExpr* mk_ppc32g_calculate_xer_ov ( UInt op, IRExpr* res,
-//zz IRExpr* argL, IRExpr* a=
rgR )
-//zz {
-//zz IRExpr** args;
-//zz IRExpr* call;
-//zz vassert(op < PPC32G_FLAG_OP_NUMBER);
-//zz vassert(typeOfIRExpr(irbb->tyenv,res) =3D=3D Ity_I32);
-//zz vassert(typeOfIRExpr(irbb->tyenv,argL) =3D=3D Ity_I32);
-//zz vassert(typeOfIRExpr(irbb->tyenv,argR) =3D=3D Ity_I32);
-//zz=20
-//zz args =3D mkIRExprVec_4( mkU32(op), res, argL, argR );
-//zz=20
-//zz call
-//zz =3D mkIRExprCCall(
-//zz Ity_I32,
-//zz 0/*regparm*/,
-//zz "ppc32g_calculate_xer_ov", &ppc32g_calculate_xer_ov,
-//zz args
-//zz );
-//zz return binop(Iop_And32, mkU32(1), call);
-//zz }
-
-//uu /* Calculate XER_CA flag. RES is the result of applying OP to ARGL
-//uu and ARGR, and OLDCA is the old carry flag. The latter may be ze=
ro
-//uu if it is known that OP does not need to consult it. */
-//uu=20
-//uu static IRExpr* mk_ppc32g_calculate_xer_ca ( UInt op,=20
-//uu IRExpr* res,
-//uu IRExpr* argL,=20
-//uu IRExpr* argR,
-//uu IRExpr* oldca )
-//uu {
-//uu IRExpr** args;
-//uu IRExpr* call;
-//uu vassert(op < PPC32G_FLAG_OP_NUMBER);
-//uu vassert(typeOfIRExpr(irbb->tyenv,res) =3D=3D Ity_I32);
-//uu vassert(typeOfIRExpr(irbb->tyenv,argL) =3D=3D Ity_I32);
-//uu vassert(typeOfIRExpr(irbb->tyenv,argR) =3D=3D Ity_I32);
-//uu vassert(typeOfIRExpr(irbb->tyenv,oldca) =3D=3D Ity_I32);
-//uu=20
-//uu args =3D mkIRExprVec_5( mkU32(op), res, argL, argR, oldca );
-//uu=20
-//uu call
-//uu =3D mkIRExprCCall(
-//uu Ity_I32,
-//uu 0/*regparm*/,
-//uu "ppc32g_calculate_xer_ca", &ppc32g_calculate_xer_ca,
-//uu args
-//uu );
-//uu return binop(Iop_And32, mkU32(1), call);
-//uu }
-
-
/* Set the CR0 flags following an arithmetic operation.
(Condition Register CR0 Field Definition, PPC32 p60)
*/
|
|
From: <sv...@va...> - 2005-09-06 09:10:14
|
Author: sewardj
Date: 2005-09-06 10:10:09 +0100 (Tue, 06 Sep 2005)
New Revision: 1369
Log:
Reinstate lwbrx.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-08-30 02:29:42 UTC (rev 1368)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-06 09:10:09 UTC (rev 1369)
@@ -3396,42 +3396,44 @@
=20
=20
=20
-//zz /*
-//zz Integer Load/Store Reverse Instructions
-//zz */
-//zz static Bool dis_int_ldst_rev ( UInt theInstr )
-//zz {
-//zz /* X-Form */
-//zz UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr=
[26:31] */
-//zz UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr=
[21:25] */
-//zz UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr=
[21:25] */
-//zz UChar Ra_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr=
[16:20] */
-//zz UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr=
[11:15] */
-//zz UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr=
[1:10] */
-//zz UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr=
[0] */
-//zz =20
-//zz IRTemp EA =3D newTemp(Ity_I32);
-//zz IRTemp Rd =3D newTemp(Ity_I32);
-//zz IRTemp Rs =3D newTemp(Ity_I32);
-//zz IRTemp byte0 =3D newTemp(Ity_I32);
-//zz IRTemp byte1 =3D newTemp(Ity_I32);
-//zz IRTemp byte2 =3D newTemp(Ity_I32);
-//zz IRTemp byte3 =3D newTemp(Ity_I32);
-//zz IRTemp tmp16 =3D newTemp(Ity_I16);
-//zz IRTemp tmp32 =3D newTemp(Ity_I32);
-//zz=20
-//zz if (opc1 !=3D 0x1F || b0 !=3D 0) {
-//zz vex_printf("dis_int_ldst_rev(PPC32)(opc1|b0)\n");
-//zz return False;
-//zz }
-//zz =20
-//zz if (Ra_addr =3D=3D 0) {
-//zz assign( EA, getIReg(Rb_addr));
-//zz } else {
-//zz assign( EA, binop(Iop_Add32, getIReg(Ra_addr), getIReg(Rb_add=
r)) );
-//zz }
-//zz =20
-//zz switch (opc2) {
+/*
+ Integer Load/Store Reverse Instructions
+*/
+static Bool dis_int_ldst_rev ( UInt theInstr )
+{
+ /* X-Form */
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+// UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21=
:25] */
+ UChar Ra_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
+ UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
+ =20
+ IRTemp EA =3D newTemp(Ity_I32);
+// IRTemp Rd =3D newTemp(Ity_I32);
+// IRTemp Rs =3D newTemp(Ity_I32);
+// IRTemp byte0 =3D newTemp(Ity_I32);
+// IRTemp byte1 =3D newTemp(Ity_I32);
+// IRTemp byte2 =3D newTemp(Ity_I32);
+// IRTemp byte3 =3D newTemp(Ity_I32);
+// IRTemp tmp16 =3D newTemp(Ity_I16);
+// IRTemp tmp32 =3D newTemp(Ity_I32);
+ IRTemp w1 =3D newTemp(Ity_I32);
+ IRTemp w2 =3D newTemp(Ity_I32);
+
+ if (opc1 !=3D 0x1F || b0 !=3D 0) {
+ vex_printf("dis_int_ldst_rev(PPC32)(opc1|b0)\n");
+ return False;
+ }
+ =20
+ if (Ra_addr =3D=3D 0) {
+ assign( EA, getIReg(Rb_addr));
+ } else {
+ assign( EA, binop(Iop_Add32, getIReg(Ra_addr), getIReg(Rb_addr)) )=
;
+ }
+ =20
+ switch (opc2) {
//zz case 0x316: // lhbrx (Load Half Word Byte-Reverse Indexed, PPC32=
p449)
//zz vassert(0);
//zz=20
@@ -3443,25 +3445,26 @@
//zz mkexpr(byte0)) );
//zz putIReg( Rd_addr, mkexpr(Rd));
//zz break;
-//zz =20
-//zz case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459=
)
-//zz vassert(0);
-//zz=20
-//zz DIP("lwbrx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
-//zz assign( byte0, loadBE(Ity_I8, mkexpr(EA)) );
-//zz assign( byte1, loadBE(Ity_I8, binop(Iop_Add32, mkexpr(EA),mkU=
32(1))) );
-//zz assign( byte2, loadBE(Ity_I8, binop(Iop_Add32, mkexpr(EA),mkU=
32(2))) );
-//zz assign( byte3, loadBE(Ity_I8, binop(Iop_Add32, mkexpr(EA),mkU=
32(3))) );
-//zz assign( Rd, binop(Iop_Or32,
-//zz binop(Iop_Or32,
-//zz binop(Iop_Shl32, mkexpr(byte3), mkU8(=
24)),
-//zz binop(Iop_Shl32, mkexpr(byte2), mkU8(=
16))),
-//zz binop(Iop_Or32,
-//zz binop(Iop_Shl32, mkexpr(byte1), mkU8(=
8)),
-//zz mkexpr(byte0))) );
-//zz putIReg( Rd_addr, mkexpr(Rd));
-//zz break;
-//zz =20
+ =20
+ case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459)
+ DIP("lwbrx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
+ assign( w1, loadBE(Ity_I32, mkexpr(EA)) );
+ assign( w2,
+ binop(Iop_Or32,
+ binop(Iop_Shl32, mkexpr(w1), mkU8(24)),
+ binop(Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shl32, mkexpr(w1), mkU8(8)),=20
+ mkU32(0x00FF0000)),
+ binop(Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(w1), mkU8(8)),
+ mkU32(0x0000FF00)),
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(w1), mkU8(24)),
+ mkU32(0x000000FF) )
+ )))
+ );
+ putIReg( Rd_addr, mkexpr(w2));
+ break;
+ =20
//zz case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC=
32 p523)
//zz vassert(0);
//zz=20
@@ -3498,13 +3501,13 @@
//zz binop(Iop_Shr32, mkexpr(byte3), mkU8(24))=
)) );
//zz storeBE( mkexpr(EA), mkexpr(tmp32) );
//zz break;
-//zz =20
-//zz default:
-//zz vex_printf("dis_int_ldst_rev(PPC32)(opc2)\n");
-//zz return False;
-//zz }
-//zz return True;
-//zz }
+ =20
+ default:
+ vex_printf("dis_int_ldst_rev(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
=20
=20
=20
@@ -6411,12 +6414,12 @@
if (dis_int_store( theInstr )) goto decode_success;
goto decode_failure;
=20
-//zz /* Integer Load and Store with Byte Reverse Instructions */
-//zz case 0x316: case 0x216: case 0x396: // lhbrx, lwbrx, sthbrx
-//zz case 0x296: // stwbrx
-//zz if (dis_int_ldst_rev( theInstr )) goto decode_success;
-//zz goto decode_failure;
-//zz =20
+ /* Integer Load and Store with Byte Reverse Instructions */
+ case 0x316: case 0x216: case 0x396: // lhbrx, lwbrx, sthbrx
+ case 0x296: // stwbrx
+ if (dis_int_ldst_rev( theInstr )) goto decode_success;
+ goto decode_failure;
+ =20
//zz /* Integer Load and Store String Instructions */
//zz case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi
//zz case 0x295: // stswx
|
|
From: <sv...@va...> - 2005-09-06 08:43:20
|
Author: sewardj
Date: 2005-09-06 09:43:15 +0100 (Tue, 06 Sep 2005)
New Revision: 4608
Log:
Unbreak ppc32 build.
Modified:
trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c 2005-09-01 16:27:28 U=
TC (rev 4607)
+++ trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c 2005-09-06 08:43:15 U=
TC (rev 4608)
@@ -2066,7 +2066,7 @@
//.. // (__NR_reboot, sys_reboot), // 88 */Li=
nux
//.. // (__NR_readdir, old_readdir), // 89 -- s=
uperseded
=20
- GENXY(__NR_mmap, sys_mmap2), // 90
+ LINXY(__NR_mmap, sys_mmap2), // 90
GENXY(__NR_munmap, sys_munmap), // 91
//.. GENX_(__NR_truncate, sys_truncate), // 92
GENX_(__NR_ftruncate, sys_ftruncate), // 93
|
|
From: <js...@ac...> - 2005-09-06 02:58:52
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-09-06 03:30:00 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 185 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-06 02:47:33
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-09-06 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/tls (stdout) |
|
From: Tom H. <to...@co...> - 2005-09-06 02:41:00
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2005-09-06 03:30:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 187 tests, 5 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-06 02:27:41
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-09-06 03:15:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 14 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-06 02:26:39
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-09-06 03:10:07 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 2 stderr failures, 1 stdout failure ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) none/tests/x86/yield (stdout) |
|
From: Tom H. <th...@cy...> - 2005-09-06 02:20:50
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2005-09-06 03:10:07 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-06 02:18:00
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2005-09-06 03:05:10 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Greg P. <gp...@us...> - 2005-09-06 01:35:07
|
Cerion Armour-Brown writes: > On Monday 05 September 2005 04:39, Greg Parker wrote: > > The biggest problem blocking Darwin/ppc32 right now is VEX/ppc32. > > It's not yet complete enough to run Darwin's dynamic loader, and > > I don't know enough about VEX yet to fix it myself. If anyone > > out there is listening, my current requests are `lwbrx`, `mftb`, > > and `lvsl`, particularly the latter. (Unfortunately, I don't have > > any Altivec-less machines to play with, and convincing Mac OS X > > not to use it when it's present is tricky.) > > I'm about to get going with remaining ppc32 insns + altivec again - > i'll put those insns at the top of the list :-) Sounds good. I found a kernel switch to disable the Altivec unit, so that's not blocking me anymore. The commented-out lwbrx seems to work after a small tweak, and a do-nothing mftb works well enough for the programs I'm running now. lswx and stswx are rearing their ugly heads again. I have two solutions coded up, but neither is great. 1. Abuse Mux0X by performing 128 1-byte memory ops from either the right place in memory or a scratch location. lswx generates about 1800 instructions, and 1400 for stswx. It also needs cooperation from memcheck, because memcheck needs to know about the scratch byte used to load and store when it shouldn't hit the real memory. 2. Use a dirty helper. This is fast, but for memcheck to work properly it really needs the "memory touched" size to be an expression instead of a constant. I don't know how messy this would be to deal with in memcheck. However, I don't care about memcheck yet, so both solutions run well enough. -- Greg Parker gp...@us... |