You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
|
|
|
|
1
(12) |
2
(11) |
3
(8) |
|
4
(9) |
5
(10) |
6
(18) |
7
(8) |
8
(12) |
9
(23) |
10
(14) |
|
11
(15) |
12
(31) |
13
(45) |
14
(28) |
15
(20) |
16
(16) |
17
(9) |
|
18
(18) |
19
(26) |
20
(49) |
21
(14) |
22
(18) |
23
(24) |
24
(28) |
|
25
(39) |
26
(17) |
27
(27) |
28
(27) |
29
(14) |
30
(44) |
|
|
From: <sv...@va...> - 2005-09-15 21:58:55
|
Author: cerion
Date: 2005-09-15 22:58:50 +0100 (Thu, 15 Sep 2005)
New Revision: 1399
Log:
Added AltiVec permutation insns:
- vperm, vsldoi, vmrg*, vsplt*
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-15 16:28:36 UTC (rev 1398)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-15 21:58:50 UTC (rev 1399)
@@ -335,12 +335,10 @@
return toUChar((((Int)x) << 27) >> 27);
}
=20
-//zz #if 0
-//zz static UInt extend_s_8to32( UInt x )
-//zz {
-//zz return (UInt)((((Int)x) << 24) >> 24);
-//zz }
-//zz #endif
+static UInt extend_s_8to32( UChar x )
+{
+ return (UInt)((((Int)x) << 24) >> 24);
+}
=20
static UInt extend_s_16to32 ( UInt x )
{
@@ -406,6 +404,11 @@
return IRExpr_Const(IRConst_U8(i));
}
=20
+static IRExpr* mkU16 ( UInt i )
+{
+ return IRExpr_Const(IRConst_U16(i));
+}
+
static IRExpr* mkU32 ( UInt i )
{
return IRExpr_Const(IRConst_U32(i));
@@ -5774,19 +5777,40 @@
binop(Iop_AndV128, mkexpr(vB), mkexpr(vC))) );
return True;
=20
- case 0x2B: // vperm (Permute, AV p218)
- DIP("vperm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr)=
;
- DIP(" =3D> not implemented\n");
- return False;
-
+ case 0x2B: { // vperm (Permute, AV p218)
+ DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
+ /* limited to two args for IR, so have to play games... */
+ IRTemp a_perm =3D newTemp(Ity_V128);
+ IRTemp b_perm =3D newTemp(Ity_V128);
+ IRTemp mask =3D newTemp(Ity_V128);
+ assign( a_perm, binop(Iop_Perm, mkexpr(vA), mkexpr(vC)) );
+ assign( b_perm, binop(Iop_Perm, mkexpr(vB), mkexpr(vC)) );
+ // mask[i8] =3D (vC[i8]_4 =3D=3D 1) ? 0xFF : 0x0
+ assign( mask, binop(Iop_SarN8x16,
+ binop(Iop_ShlN8x16, mkexpr(vC), mkU8(3)),
+ mkU8(7)) );
+ // dst =3D (a & ~mask) | (b & mask)
+ putVReg( vD_addr, binop(Iop_OrV128,
+ binop(Iop_AndV128, mkexpr(a_perm),
+ unop(Iop_NotV128, mkexpr(mask))),
+ binop(Iop_AndV128, mkexpr(b_perm),
+ mkexpr(mask))) );
+ return True;
+ }
case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241)
if (b10 !=3D 0) {
vex_printf("dis_av_permute(PPC32)(vsldoi)\n");
return False;
}
DIP("vsldoi v%d,v%d,v%d,%d\n", vD_addr, vA_addr, vB_addr, SHB_uimm=
4);
- DIP(" =3D> not implemented\n");
- return False;
+ if (SHB_uimm4 =3D=3D 0)
+ putVReg( vD_addr, mkexpr(vA) );
+ else
+ putVReg( vD_addr,
+ binop(Iop_OrV128,
+ binop(Iop_ShlV128, mkexpr(vA), mkU8(SHB_uimm4*8)=
),
+ binop(Iop_ShrV128, mkexpr(vB), mkU8((16-SHB_uimm=
4)*8))) );
+ return True;
=20
default:
break; // Fall through...
@@ -5798,49 +5822,63 @@
/* Merge */
case 0x00C: // vmrghb (Merge High B, AV p195)
DIP("vmrghb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveHI8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x04C: // vmrghh (Merge High HW, AV p196)
DIP("vmrghh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveHI16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x08C: // vmrghw (Merge High W, AV p197)
DIP("vmrghw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveHI32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x10C: // vmrglb (Merge Low B, AV p198)
DIP("vmrglb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveLO8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x14C: // vmrglh (Merge Low HW, AV p199)
DIP("vmrglh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveLO16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x18C: // vmrglw (Merge Low W, AV p200)
DIP("vmrglw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr,
+ binop(Iop_InterleaveLO32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
+
/* Splat */
- case 0x20C: // vspltb (Splat Byte, AV p245)
+ case 0x20C: { // vspltb (Splat Byte, AV p245)
DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x24C: // vsplth (Splat Half Word, AV p246)
+ /* vD =3D Dup8x16( vB[UIMM_5] ) */
+ UChar sh_uimm =3D (15-UIMM_5)*8;
+ putVReg( vD_addr, unop(Iop_Dup8x16,
+ unop(Iop_32to8, unop(Iop_V128to32,=20
+ binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
+ break;
+ }
+ case 0x24C: { // vsplth (Splat Half Word, AV p246)
DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
- DIP(" =3D> not implemented\n");
- return False;
-
+ UChar sh_uimm =3D (7-UIMM_5)*16;
+ putVReg( vD_addr, unop(Iop_Dup16x8,
+ unop(Iop_32to16, unop(Iop_V128to32,=20
+ binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
+ break;
+ }
case 0x28C: { // vspltw (Splat Word, AV p250)
DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
/* vD =3D Dup32x4( vB[UIMM_5] ) */
- unsigned int sh_uimm =3D (3-UIMM_5)*32;
+ UChar sh_uimm =3D (3-UIMM_5)*32;
putVReg( vD_addr, unop(Iop_Dup32x4,
unop(Iop_V128to32,
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm)))) );
@@ -5848,18 +5886,18 @@
}
case 0x30C: // vspltisb (Splat Immediate Signed B, AV p247)
DIP("vspltisb v%d,%d\n", vD_addr, (Char)SIMM_8);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, unop(Iop_Dup8x16, mkU8(SIMM_8)) );
+ break;
=20
case 0x34C: // vspltish (Splat Immediate Signed HW, AV p248)
DIP("vspltish v%d,%d\n", vD_addr, (Char)SIMM_8);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, unop(Iop_Dup16x8, mkU16(extend_s_8to32(SIMM_8)))=
);
+ break;
=20
case 0x38C: // vspltisw (Splat Immediate Signed W, AV p249)
DIP("vspltisw v%d,%d\n", vD_addr, (Char)SIMM_8);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, unop(Iop_Dup32x4, mkU32(extend_s_8to32(SIMM_8)))=
);
+ break;
=20
default:
vex_printf("dis_av_permute(PPC32)(opc2)\n");
@@ -6614,14 +6652,10 @@
/* AV Permutations */
case 0x2A: // vsel
case 0x2B: // vperm
+ case 0x2C: // vsldoi
if (dis_av_permute( theInstr )) goto decode_success;
goto decode_failure;
=20
- /* AV Shift */
- case 0x2C: // vsldoi
- if (dis_av_shift( theInstr )) goto decode_success;
- goto decode_failure;
-
/* AV Floating Point Mult-Add/Sub */
case 0x2E: case 0x2F: // vmaddfp, vnmsubfp
if (dis_av_fp_arith( theInstr )) goto decode_success;
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-15 16:28:36 UTC (rev 1398)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-15 21:58:50 UTC (rev 1399)
@@ -973,13 +973,13 @@
i->Pin.AvBin32Fx4.srcR =3D srcR;
return i;
}
-PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL, HReg srcR=
) {
+PPC32Instr* PPC32Instr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl=
) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_AvPerm;
- i->Pin.AvPerm.ctl =3D ctl;
i->Pin.AvPerm.dst =3D dst;
i->Pin.AvPerm.srcL =3D srcL;
i->Pin.AvPerm.srcR =3D srcR;
+ i->Pin.AvPerm.ctl =3D ctl;
return i;
}
PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR =
) {
@@ -1636,9 +1636,9 @@
return;
case Pin_AvPerm:
addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst);
- addHRegUse(u, HRmRead, i->Pin.AvPerm.ctl);
addHRegUse(u, HRmRead, i->Pin.AvPerm.srcL);
addHRegUse(u, HRmRead, i->Pin.AvPerm.srcR);
+ addHRegUse(u, HRmRead, i->Pin.AvPerm.ctl);
return;
case Pin_AvSel:
addHRegUse(u, HRmWrite, i->Pin.AvSel.dst);
@@ -3088,10 +3088,10 @@
}
=20
case Pin_AvPerm: { // vperm
- UInt v_ctl =3D vregNo(i->Pin.AvPerm.ctl);
UInt v_dst =3D vregNo(i->Pin.AvPerm.dst);
UInt v_srcL =3D vregNo(i->Pin.AvPerm.srcL);
UInt v_srcR =3D vregNo(i->Pin.AvPerm.srcR);
+ UInt v_ctl =3D vregNo(i->Pin.AvPerm.ctl);
p =3D mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 43 );
goto done;
}
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-09-15 16:28:36 UTC (rev 1398)
+++ trunk/priv/host-ppc32/hdefs.h 2005-09-15 21:58:50 UTC (rev 1399)
@@ -670,16 +670,16 @@
} AvBin32Fx4;
/* Perm,Sel,SlDbl,Splat are all weird AV permutations */
struct {
- HReg ctl;
HReg dst;
HReg srcL;
HReg srcR;
+ HReg ctl;
} AvPerm;
struct {
- HReg ctl;
HReg dst;
HReg srcL;
HReg srcR;
+ HReg ctl;
} AvSel;
struct {
UChar shift;
@@ -742,7 +742,7 @@
extern PPC32Instr* PPC32Instr_AvBin16x8 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32x4 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
-extern PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvPerm ( HReg dst, HReg srcL, HReg src=
R, HReg ctl );
extern PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
extern PPC32Instr* PPC32Instr_AvShlDbl ( UChar shift, HReg dst, HReg s=
rcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvSplat ( UChar sz, HReg dst, PPC32VI5s=
* src );
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-15 16:28:36 UTC (rev 1398)
+++ trunk/priv/host-ppc32/isel.c 2005-09-15 21:58:50 UTC (rev 1399)
@@ -3127,10 +3127,10 @@
//.. return dst;
//.. }
=20
- case Iop_Dup32x4: {
- HReg dst =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg1);
- return dst;
- }
+ case Iop_Dup8x16:
+ case Iop_Dup16x8:
+ case Iop_Dup32x4:
+ return mk_AvDuplicateRI(env, e->Iex.Binop.arg1);
=20
default:
break;
@@ -3332,6 +3332,8 @@
//.. case Iop_QSub8Ux16: op =3D Xsse_QSUB8U; goto do_SseReRg;
//.. case Iop_QSub16Ux8: op =3D Xsse_QSUB16U; goto do_SseReRg;
=20
+ case Iop_InterleaveHI8x16: op =3D Pav_MRGHI; goto do_AvBin8x16;
+ case Iop_InterleaveLO8x16: op =3D Pav_MRGLO; goto do_AvBin8x16;
case Iop_Add8x16: op =3D Pav_ADDUM; goto do_AvBin8x16;
case Iop_QAdd8Ux16: op =3D Pav_ADDUS; goto do_AvBin8x16;
case Iop_QAdd8Sx16: op =3D Pav_ADDSS; goto do_AvBin8x16;
@@ -3355,6 +3357,8 @@
return dst;
}
=20
+ case Iop_InterleaveHI16x8: op =3D Pav_MRGHI; goto do_AvBin16x8;
+ case Iop_InterleaveLO16x8: op =3D Pav_MRGLO; goto do_AvBin16x8;
case Iop_Add16x8: op =3D Pav_ADDUM; goto do_AvBin16x8;
case Iop_QAdd16Ux8: op =3D Pav_ADDUS; goto do_AvBin16x8;
case Iop_QAdd16Sx8: op =3D Pav_ADDSS; goto do_AvBin16x8;
@@ -3382,6 +3386,8 @@
return dst;
}
=20
+ case Iop_InterleaveHI32x4: op =3D Pav_MRGHI; goto do_AvBin32x4;
+ case Iop_InterleaveLO32x4: op =3D Pav_MRGLO; goto do_AvBin32x4;
case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
case Iop_QAdd32Ux4: op =3D Pav_ADDUS; goto do_AvBin32x4;
case Iop_QAdd32Sx4: op =3D Pav_ADDSS; goto do_AvBin32x4;
@@ -3433,9 +3439,19 @@
//.. case Iop_ShrN16x8: op =3D Xsse_SHR16; goto do_SseShift;
//.. case Iop_ShrN64x2: op =3D Xsse_SHR64; goto do_SseShift;
=20
+ case Iop_ShlN8x16: op =3D Pav_SHL; goto do_AvShift8x16;
+ case Iop_SarN8x16: op =3D Pav_SAR; goto do_AvShift8x16;
+ do_AvShift8x16: {
+ HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg dst =3D newVRegV(env);
+ HReg v_shft =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_AvBin8x16(op, dst, r_src, v_shft));
+ return dst;
+ }
+
case Iop_ShrN32x4: op =3D Pav_SHR; goto do_AvShift32x4;
do_AvShift32x4: {
- HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg dst =3D newVRegV(env);
HReg v_shft =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
addInstr(env, PPC32Instr_AvBin32x4(op, dst, r_src, v_shft));
@@ -3443,14 +3459,24 @@
}
=20
case Iop_ShrV128: op =3D Pav_SHR; goto do_AvShiftV128;
+ case Iop_ShlV128: op =3D Pav_SHL; goto do_AvShiftV128;
do_AvShiftV128: {
HReg dst =3D newVRegV(env);
HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg v_shft =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
+ /* Note: shift value gets masked by 127 */
addInstr(env, PPC32Instr_AvBinary(op, dst, r_src, v_shft));
return dst;
}
=20
+ case Iop_Perm: {
+ HReg dst =3D newVRegV(env);
+ HReg v_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg v_ctl =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_AvPerm(dst, v_src, v_src, v_ctl));
+ return dst;
+ }
+
default:
break;
} /* switch (e->Iex.Binop.op) */
|
|
From: Nicholas N. <nj...@cs...> - 2005-09-15 18:26:43
|
On Wed, 14 Sep 2005, John Reiser wrote: > As for profiling a longer-running program, please suggest suitable > testcases. Konqueror is a good one, as it's quite big but is all a single process (unlike OpenOffice, for example). An interesting first run would be to start up, view a couple of websites and then close it. Vim or xedit or another editor would also be interesting -- again start up, do some stuff, shut down. Nick |
|
From: <sv...@va...> - 2005-09-15 16:28:39
|
Author: cerion
Date: 2005-09-15 17:28:36 +0100 (Thu, 15 Sep 2005)
New Revision: 1398
Log:
Couple more primops: Iop_ShlN8x16, Iop_ShrN8x16, Iop_SarN8x16
Modified:
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-09-15 16:00:58 UTC (rev 1397)
+++ trunk/priv/ir/irdefs.c 2005-09-15 16:28:36 UTC (rev 1398)
@@ -478,12 +478,15 @@
case Iop_ShlV128: vex_printf("ShlV128"); return;
case Iop_ShrV128: vex_printf("ShrV128"); return;
=20
+ case Iop_ShlN8x16: vex_printf("ShlN8x16"); return;
case Iop_ShlN16x8: vex_printf("ShlN16x8"); return;
case Iop_ShlN32x4: vex_printf("ShlN32x4"); return;
case Iop_ShlN64x2: vex_printf("ShlN64x2"); return;
+ case Iop_ShrN8x16: vex_printf("ShrN8x16"); return;
case Iop_ShrN16x8: vex_printf("ShrN16x8"); return;
case Iop_ShrN32x4: vex_printf("ShrN32x4"); return;
case Iop_ShrN64x2: vex_printf("ShrN64x2"); return;
+ case Iop_SarN8x16: vex_printf("SarN8x16"); return;
case Iop_SarN16x8: vex_printf("SarN16x8"); return;
case Iop_SarN32x4: vex_printf("SarN32x4"); return;
=20
@@ -1586,9 +1589,9 @@
UNARY(Ity_V128, Ity_V128);
=20
case Iop_ShlV128: case Iop_ShrV128:
- case Iop_ShlN16x8: case Iop_ShlN32x4: case Iop_ShlN64x2:
- case Iop_ShrN16x8: case Iop_ShrN32x4: case Iop_ShrN64x2:
- case Iop_SarN16x8: case Iop_SarN32x4:
+ case Iop_ShlN8x16: case Iop_ShlN16x8: case Iop_ShlN32x4: case Iop_=
ShlN64x2:
+ case Iop_ShrN8x16: case Iop_ShrN16x8: case Iop_ShrN32x4: case Iop_=
ShrN64x2:
+ case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4:
BINARY(Ity_V128, Ity_V128, Ity_I8);
=20
default:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-09-15 16:00:58 UTC (rev 1397)
+++ trunk/pub/libvex_ir.h 2005-09-15 16:28:36 UTC (rev 1398)
@@ -570,9 +570,9 @@
Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4,
=20
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
- Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2,
- Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2,
- Iop_SarN16x8, Iop_SarN32x4,
+ Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2,
+ Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2,
+ Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4,
=20
/* VECTOR x VECTOR SHIFT / ROTATE */
Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4,
|
|
From: <sv...@va...> - 2005-09-15 16:01:04
|
Author: sewardj
Date: 2005-09-15 17:00:58 +0100 (Thu, 15 Sep 2005)
New Revision: 1397
Log:
Makefile fixes:
- Fix default compiler better
- Add dummy install target to help V's build system
- Don't hardwire 'ar' (fix for #112199).
Modified:
trunk/Makefile
Modified: trunk/Makefile
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/Makefile 2005-09-15 14:22:58 UTC (rev 1396)
+++ trunk/Makefile 2005-09-15 16:00:58 UTC (rev 1397)
@@ -63,9 +63,13 @@
PRIV_INCLUDES =3D -Ipriv
=20
=20
-ifeq ($(CC),)=20
+ifndef $(CC)
CC =3D gcc=20
endif=20
+ifndef $(AR)
+ AR =3D ar=20
+endif
+
CCFLAGS =3D -g -O -Wall -Wmissing-prototypes -Wshadow -Winline \
-Wpointer-arith -Wbad-function-cast -Wcast-qual \
-Wcast-align -Wmissing-declarations \
@@ -85,6 +89,9 @@
=20
all: vex
=20
+# Empty, needed for Valgrind
+install:
+
scratch: clean version all
=20
vex: libvex.a test_main.o
@@ -92,7 +99,7 @@
=20
libvex.a: $(LIB_OBJS)
rm -f libvex.a
- ar clq libvex.a $(LIB_OBJS)
+ $(AR) clq libvex.a $(LIB_OBJS)
=20
# This doesn't get rid of priv/main/vex_svnversion.h, because
# that can't be regenerated in the final Valgrind tarball, and
|
|
From: Tom H. <to...@co...> - 2005-09-15 15:09:48
|
In message <200...@gm...>
Josef Weidendorfer <Jos...@gm...> wrote:
> On Thursday 15 September 2005 06:52, Paul Mackerras wrote:
>> Valgrind sets LD_PRELOAD so that you get a simple Valgrind-supplied
>> set of string functions, including strlen, from vgpreload_memcheck.so
>> rather than the fancy glibc ones. However, that doesn't seem to catch
>> the calls to strlen from inside glibc - the call from vfprintf is a
>> direct branch rather than going through the PLT, for instance.
>
> Just curious: Why is it using LD_PRELOAD and not the VGs symbol redirection
> mechanism, which should catch strlen even if used inside of glibc?
We use both in combination - valgrind spots the special symbols in the
preload library and sets up redirections based on them.
Because we use redirection rather than relying on the LD_PRELOAD
acting as an overload it should catch internal calls as well as
ones which go through the PLT. What it won't catch is inlined
ones.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
|
|
From: Josef W. <Jos...@gm...> - 2005-09-15 14:50:20
|
On Thursday 15 September 2005 06:52, Paul Mackerras wrote: > Valgrind sets LD_PRELOAD so that you get a simple Valgrind-supplied > set of string functions, including strlen, from vgpreload_memcheck.so > rather than the fancy glibc ones. However, that doesn't seem to catch > the calls to strlen from inside glibc - the call from vfprintf is a > direct branch rather than going through the PLT, for instance. Just curious: Why is it using LD_PRELOAD and not the VGs symbol redirection mechanism, which should catch strlen even if used inside of glibc? Josef |
|
From: <sv...@va...> - 2005-09-15 14:23:01
|
Author: cerion
Date: 2005-09-15 15:22:58 +0100 (Thu, 15 Sep 2005)
New Revision: 1396
Log:
Added AltiVec integer compare insns.
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-15 12:42:16 UTC (rev 1395)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-15 14:22:58 UTC (rev 1396)
@@ -1154,6 +1154,50 @@
=20
=20
=20
+/* Set the CR6 flags following an AltiVec compare operation. */
+static void set_AV_CR6 ( IRExpr* result )
+{
+ vassert(typeOfIRExpr(irbb->tyenv,result) =3D=3D Ity_V128);
+
+ /* CR6[0:3] =3D {all_ones, 0, all_zeros, 0}
+ all_ones =3D (v[0] && v[1] && v[2] && v[3])
+ all_zeros =3D ~(v[0] || v[1] || v[2] || v[3])
+ */
+ IRTemp v0 =3D newTemp(Ity_V128);
+ IRTemp v1 =3D newTemp(Ity_V128);
+ IRTemp v2 =3D newTemp(Ity_V128);
+ IRTemp v3 =3D newTemp(Ity_V128);
+ IRTemp rOnes =3D newTemp(Ity_I8);
+ IRTemp rZeros =3D newTemp(Ity_I8);
+ assign( v0, result );
+ assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
+ assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
+ assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
+
+ assign( rOnes, unop(Iop_1Uto8,
+ binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
+ unop(Iop_V128to32,
+ binop(Iop_AndV128,
+ binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
+ binop(Iop_AndV128, mkexpr(v2), mkexpr(v3)))))) );
+
+ assign( rZeros, unop(Iop_1Uto8,
+ binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
+ unop(Iop_Not32,
+ unop(Iop_V128to32,
+ binop(Iop_OrV128,
+ binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)),
+ binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))))
+ ))) );
+
+ putCR321( 6, binop(Iop_Or8,
+ binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)),
+ binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) );
+ putCR0( 6, mkU8(0) );
+}=20
+
+
+
/*------------------------------------------------------------*/
/*--- Abstract register interface --- */
/*------------------------------------------------------------*/
@@ -5429,6 +5473,12 @@
UChar flag_Rc =3D toUChar((theInstr >> 10) & 0x1); /* theInstr[10] =
*/
UInt opc2 =3D (theInstr >> 0) & 0x3FF; /* theInstr[0:9]=
*/
=20
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ IRTemp vD =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_cmp(PPC32)(instr)\n");
return False;
@@ -5437,53 +5487,59 @@
switch (opc2) {
case 0x006: // vcmpequb (Compare Equal-to Unsigned B, AV p160)
DIP("vcmpequb%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpEQ8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161)
DIP("vcmpequh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpEQ16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162)
DIP("vcmpequw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpEQ32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x206: // vcmpgtub (Compare Greater-than Unsigned B, AV p168)
DIP("vcmpgtub%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT8Ux16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x246: // vcmpgtuh (Compare Greater-than Unsigned HW, AV p169)
DIP("vcmpgtuh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x286: // vcmpgtuw (Compare Greater-than Unsigned W, AV p170)
DIP("vcmpgtuw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x306: // vcmpgtsb (Compare Greater-than Signed B, AV p165)
DIP("vcmpgtsb%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT8Sx16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x346: // vcmpgtsh (Compare Greater-than Signed HW, AV p166)
DIP("vcmpgtsh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x386: // vcmpgtsw (Compare Greater-than Signed W, AV p167)
DIP("vcmpgtsw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
default:
vex_printf("dis_av_cmp(PPC32)(opc2)\n");
return False;
}
+
+ putVReg( vD_addr, mkexpr(vD) );
+
+ if (flag_Rc) {
+ set_AV_CR6( mkexpr(vD) );
+ }
return True;
}
=20
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-15 12:42:16 UTC (rev 1395)
+++ trunk/priv/host-ppc32/isel.c 2005-09-15 14:22:58 UTC (rev 1396)
@@ -3344,6 +3344,9 @@
case Iop_Max8Sx16: op =3D Pav_MAXS; goto do_AvBin8x16;
case Iop_Min8Ux16: op =3D Pav_MINU; goto do_AvBin8x16;
case Iop_Min8Sx16: op =3D Pav_MINS; goto do_AvBin8x16;
+ case Iop_CmpEQ8x16: op =3D Pav_CMPEQU; goto do_AvBin8x16;
+ case Iop_CmpGT8Ux16: op =3D Pav_CMPGTU; goto do_AvBin8x16;
+ case Iop_CmpGT8Sx16: op =3D Pav_CMPGTS; goto do_AvBin8x16;
do_AvBin8x16: {
HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
@@ -3368,6 +3371,9 @@
case Iop_MulLo16Sx8: op =3D Pav_OMULS; goto do_AvBin16x8;
case Iop_MulHi16Ux8: op =3D Pav_EMULU; goto do_AvBin16x8;
case Iop_MulHi16Sx8: op =3D Pav_EMULS; goto do_AvBin16x8;
+ case Iop_CmpEQ16x8: op =3D Pav_CMPEQU; goto do_AvBin16x8;
+ case Iop_CmpGT16Ux8: op =3D Pav_CMPGTU; goto do_AvBin16x8;
+ case Iop_CmpGT16Sx8: op =3D Pav_CMPGTS; goto do_AvBin16x8;
do_AvBin16x8: {
HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
@@ -3388,11 +3394,13 @@
case Iop_Max32Sx4: op =3D Pav_MAXS; goto do_AvBin32x4;
case Iop_Min32Ux4: op =3D Pav_MINU; goto do_AvBin32x4;
case Iop_Min32Sx4: op =3D Pav_MINS; goto do_AvBin32x4;
- case Iop_CmpGT32Ux4: op =3D Pav_CMPGTU; goto do_AvBin32x4;
case Iop_MulLo32Ux4: op =3D Pav_OMULU; goto do_AvBin32x4;
case Iop_MulLo32Sx4: op =3D Pav_OMULS; goto do_AvBin32x4;
case Iop_MulHi32Ux4: op =3D Pav_EMULU; goto do_AvBin32x4;
case Iop_MulHi32Sx4: op =3D Pav_EMULS; goto do_AvBin32x4;
+ case Iop_CmpEQ32x4: op =3D Pav_CMPEQU; goto do_AvBin32x4;
+ case Iop_CmpGT32Ux4: op =3D Pav_CMPGTU; goto do_AvBin32x4;
+ case Iop_CmpGT32Sx4: op =3D Pav_CMPGTS; goto do_AvBin32x4;
do_AvBin32x4: {
HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
|
|
From: <sv...@va...> - 2005-09-15 12:42:34
|
Author: cerion
Date: 2005-09-15 13:42:16 +0100 (Thu, 15 Sep 2005)
New Revision: 1395
Log:
Implemented simple AltiVec arithmetic insns:
- add, sub, max, min, avg, hi/lo mul
and all varieties thereof: (un)signed, (un)saturated, 8|16|32 lane siz=
e...
fixed backend hi/lo_mul: only valid for 16|32 bit lanes, not 8.
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-14 22:59:26 UTC (rev 1394)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-15 12:42:16 UTC (rev 1395)
@@ -5068,247 +5068,264 @@
/* Add */
case 0x180: { // vaddcuw (Add Carryout Unsigned Word, AV p136)
DIP("vaddcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- /* ov =3D x >u (x+y) */
- IRTemp sum =3D newTemp(Ity_V128);
- assign( sum, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) );
+ /* unsigned_ov(x+y) =3D (y >u not(x)) */
putVReg( vD_addr, binop(Iop_ShrN32x4,
- binop(Iop_CmpGT32Ux4, mkexpr(vA), mkexpr(s=
um)),
+ binop(Iop_CmpGT32Ux4, mkexpr(vB),
+ unop(Iop_NotV128, mkexpr(vA))),
mkU8(31)) );
break;
}
case 0x000: // vaddubm (Add Unsigned Byte Modulo, AV p141)
DIP("vaddubm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Add8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x040: // vadduhm (Add Unsigned Half Word Modulo, AV p143)
DIP("vadduhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Add16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x080: // vadduwm (Add Unsigned Word Modulo, AV p145)
DIP("vadduwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x200: // vaddubs (Add Unsigned Byte Saturate, AV p142)
DIP("vaddubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd8Ux16, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT], perhaps via new primop: Iop_SatOfQAdd8Ux16
+ break;
+
case 0x240: // vadduhs (Add Unsigned Half Word Saturate, AV p144)
DIP("vadduhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd16Ux8, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x280: // vadduws (Add Unsigned Word Saturate, AV p146)
DIP("vadduws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd32Ux4, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x300: // vaddsbs (Add Signed Byte Saturate, AV p138)
DIP("vaddsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd8Sx16, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x340: // vaddshs (Add Signed Half Word Saturate, AV p139)
DIP("vaddshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd16Sx8, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x380: // vaddsws (Add Signed Word Saturate, AV p140)
DIP("vaddsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QAdd32Sx4, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
+
/* Subtract */
- case 0x580: // vsubcuw (Subtract Carryout Unsigned Word, AV p260)
+ case 0x580: { // vsubcuw (Subtract Carryout Unsigned Word, AV p260)
DIP("vsubcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ /* unsigned_ov(x-y) =3D (y >u x) */
+ putVReg( vD_addr, binop(Iop_ShrN32x4,
+ unop(Iop_NotV128,
+ binop(Iop_CmpGT32Ux4, mkexpr(vB),
+ mkexpr(vA))),
+ mkU8(31)) );
+ break;
+ } =20
case 0x400: // vsububm (Subtract Unsigned Byte Modulo, AV p265)
DIP("vsububm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Sub8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x440: // vsubuhm (Subtract Unsigned Half Word Modulo, AV p267)
DIP("vsubuhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Sub16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x480: // vsubuwm (Subtract Unsigned Word Modulo, AV p269)
DIP("vsubuwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Sub32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
+
case 0x600: // vsububs (Subtract Unsigned Byte Saturate, AV p266)
DIP("vsububs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QSub8Ux16, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x640: // vsubuhs (Subtract Unsigned Half Word Saturate, AV p268=
)
DIP("vsubuhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QSub16Ux8, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x680: // vsubuws (Subtract Unsigned Word Saturate, AV p270)
DIP("vsubuws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QSub32Ux4, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x700: // vsubsbs (Subtract Signed Byte Saturate, AV p262)
DIP("vsubsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QSub8Sx16, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x740: // vsubshs (Subtract Signed Half Word Saturate, AV p263)
DIP("vsubshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_QSub16Sx8, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
+
case 0x780: // vsubsws (Subtract Signed Word Saturate, AV p264)
DIP("vsubsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_QSub32Sx4, mkexpr(vA), mkexpr(vB)) );
+ // TODO: set VSCR[SAT]
+ break;
=20
=20
/* Maximum */
case 0x002: // vmaxub (Maximum Unsigned Byte, AV p182)
DIP("vmaxub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max8Ux16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x042: // vmaxuh (Maximum Unsigned Half Word, AV p183)
DIP("vmaxuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x082: // vmaxuw (Maximum Unsigned Word, AV p184)
DIP("vmaxuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x102: // vmaxsb (Maximum Signed Byte, AV p179)
DIP("vmaxsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max8Sx16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x142: // vmaxsh (Maximum Signed Half Word, AV p180)
DIP("vmaxsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x182: // vmaxsw (Maximum Signed Word, AV p181)
DIP("vmaxsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
=20
/* Minimum */
case 0x202: // vminub (Minimum Unsigned Byte, AV p191)
DIP("vminub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min8Ux16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x242: // vminuh (Minimum Unsigned Half Word, AV p192)
DIP("vminuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x282: // vminuw (Minimum Unsigned Word, AV p193)
DIP("vminuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x302: // vminsb (Minimum Signed Byte, AV p188)
DIP("vminsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min8Sx16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x342: // vminsh (Minimum Signed Half Word, AV p189)
DIP("vminsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x382: // vminsw (Minimum Signed Word, AV p190)
DIP("vminsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ putVReg( vD_addr, binop(Iop_Min32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
+
/* Average */
case 0x402: // vavgub (Average Unsigned Byte, AV p152)
DIP("vavgub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg8Ux16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x442: // vavguh (Average Unsigned Half Word, AV p153)
DIP("vavguh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x482: // vavguw (Average Unsigned Word, AV p154)
DIP("vavguw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x502: // vavgsb (Average Signed Byte, AV p149)
DIP("vavgsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg8Sx16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x542: // vavgsh (Average Signed Half Word, AV p150)
DIP("vavgsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x582: // vavgsw (Average Signed Word, AV p151)
DIP("vavgsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Avg32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
=20
/* Multiply */
case 0x008: // vmuloub (Multiply Odd Unsigned Byte, AV p213)
DIP("vmuloub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulLo16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x048: // vmulouh (Multiply Odd Unsigned Half Word, AV p214)
DIP("vmulouh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulLo32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x108: // vmulosb (Multiply Odd Signed Byte, AV p211)
DIP("vmulosb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulLo16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x148: // vmulosh (Multiply Odd Signed Half Word, AV p212)
DIP("vmulosh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulLo32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x208: // vmuleub (Multiply Even Unsigned Byte, AV p209)
DIP("vmuleub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulHi16Ux8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x248: // vmuleuh (Multiply Even Unsigned Half Word, AV p210)
DIP("vmuleuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulHi32Ux4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x308: // vmulesb (Multiply Even Signed Byte, AV p207)
DIP("vmulesb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulHi16Sx8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x348: // vmulesh (Multiply Even Signed Half Word, AV p208)
DIP("vmulesh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_MulHi32Sx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
=20
/* Sum Across Partial */
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-14 22:59:26 UTC (rev 1394)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-15 12:42:16 UTC (rev 1395)
@@ -2902,11 +2902,6 @@
case Pav_SUBUS: opc2 =3D 1536; break; // vsububs
case Pav_SUBSS: opc2 =3D 1792; break; // vsubsbs
=20
- case Pav_OMULU: opc2 =3D 8; break; // vmuloub
- case Pav_OMULS: opc2 =3D 264; break; // vmulosb
- case Pav_EMULU: opc2 =3D 520; break; // vmuleub
- case Pav_EMULS: opc2 =3D 776; break; // vmulesb
-
case Pav_AVGU: opc2 =3D 1026; break; // vavgub
case Pav_AVGS: opc2 =3D 1282; break; // vavgsb
case Pav_MAXU: opc2 =3D 2; break; // vmaxub
@@ -2948,10 +2943,10 @@
case Pav_SUBUS: opc2 =3D 1600; break; // vsubuhs
case Pav_SUBSS: opc2 =3D 1856; break; // vsubshs
=20
- case Pav_OMULU: opc2 =3D 72; break; // vmulouh
- case Pav_OMULS: opc2 =3D 328; break; // vmulosh
- case Pav_EMULU: opc2 =3D 584; break; // vmuleuh
- case Pav_EMULS: opc2 =3D 840; break; // vmulesh
+ case Pav_OMULU: opc2 =3D 8; break; // vmuloub
+ case Pav_OMULS: opc2 =3D 264; break; // vmulosb
+ case Pav_EMULU: opc2 =3D 520; break; // vmuleub
+ case Pav_EMULS: opc2 =3D 776; break; // vmulesb
=20
case Pav_AVGU: opc2 =3D 1090; break; // vavguh
case Pav_AVGS: opc2 =3D 1346; break; // vavgsh
@@ -3000,6 +2995,11 @@
case Pav_SUBUS: opc2 =3D 1664; break; // vsubuws
case Pav_SUBSS: opc2 =3D 1920; break; // vsubsws
=20
+ case Pav_OMULU: opc2 =3D 72; break; // vmulouh
+ case Pav_OMULS: opc2 =3D 328; break; // vmulosh
+ case Pav_EMULU: opc2 =3D 584; break; // vmuleuh
+ case Pav_EMULS: opc2 =3D 840; break; // vmulesh
+
case Pav_AVGU: opc2 =3D 1154; break; // vavguw
case Pav_AVGS: opc2 =3D 1410; break; // vavgsw
=20
@@ -3069,17 +3069,17 @@
=20
// Finally, do the multiply:
p =3D mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46 );
- break;
+ break;
}
case Pav_CMPEQF:
p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198 ); // vcmp=
eqfp
- break;
+ break;
case Pav_CMPGTF:
p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 710 ); // vcmp=
gtfp
- break;
+ break;
case Pav_CMPGEF:
p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 454 ); // vcmp=
gefp
- break;
+ break;
=20
default:
goto bad;
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-14 22:59:26 UTC (rev 1394)
+++ trunk/priv/host-ppc32/isel.c 2005-09-15 12:42:16 UTC (rev 1395)
@@ -3217,7 +3217,7 @@
//.. addInstr(env, X86Instr_Sse32Fx4(op, argR, dst));
//.. return dst;
//.. }
-//..=20
+
//.. case Iop_CmpEQ64Fx2: op =3D Xsse_CMPEQF; goto do_64Fx2;
//.. case Iop_CmpLT64Fx2: op =3D Xsse_CMPLTF; goto do_64Fx2;
//.. case Iop_CmpLE64Fx2: op =3D Xsse_CMPLEF; goto do_64Fx2;
@@ -3237,7 +3237,7 @@
//.. addInstr(env, X86Instr_Sse64Fx2(op, argR, dst));
//.. return dst;
//.. }
-//..=20
+
//.. case Iop_CmpEQ32F0x4: op =3D Xsse_CMPEQF; goto do_32F0x4;
//.. case Iop_CmpLT32F0x4: op =3D Xsse_CMPLTF; goto do_32F0x4;
//.. case Iop_CmpLE32F0x4: op =3D Xsse_CMPLEF; goto do_32F0x4;
@@ -3255,7 +3255,7 @@
//.. addInstr(env, X86Instr_Sse32FLo(op, argR, dst));
//.. return dst;
//.. }
-//..=20
+
//.. case Iop_CmpEQ64F0x2: op =3D Xsse_CMPEQF; goto do_64F0x2;
//.. case Iop_CmpLT64F0x2: op =3D Xsse_CMPLTF; goto do_64F0x2;
//.. case Iop_CmpLE64F0x2: op =3D Xsse_CMPLEF; goto do_64F0x2;
@@ -3274,14 +3274,14 @@
//.. addInstr(env, X86Instr_Sse64FLo(op, argR, dst));
//.. return dst;
//.. }
-//..=20
+
//.. case Iop_QNarrow32Sx4:=20
//.. op =3D Xsse_PACKSSD; arg1isEReg =3D True; goto do_SseReRg;
//.. case Iop_QNarrow16Sx8:=20
//.. op =3D Xsse_PACKSSW; arg1isEReg =3D True; goto do_SseReRg;
//.. case Iop_QNarrow16Ux8:=20
//.. op =3D Xsse_PACKUSW; arg1isEReg =3D True; goto do_SseReRg;
-//..=20
+
//.. case Iop_InterleaveHI8x16:=20
//.. op =3D Xsse_UNPCKHB; arg1isEReg =3D True; goto do_SseReRg;
//.. case Iop_InterleaveHI16x8:=20
@@ -3290,7 +3290,7 @@
//.. op =3D Xsse_UNPCKHD; arg1isEReg =3D True; goto do_SseReRg;
//.. case Iop_InterleaveHI64x2:=20
//.. op =3D Xsse_UNPCKHQ; arg1isEReg =3D True; goto do_SseReRg;
-//..=20
+
//.. case Iop_InterleaveLO8x16:=20
//.. op =3D Xsse_UNPCKLB; arg1isEReg =3D True; goto do_SseReRg;
//.. case Iop_InterleaveLO16x8:=20
@@ -3303,9 +3303,15 @@
case Iop_AndV128: op =3D Pav_AND; goto do_AvBin;
case Iop_OrV128: op =3D Pav_OR; goto do_AvBin;
case Iop_XorV128: op =3D Pav_XOR; goto do_AvBin;
+ do_AvBin: {
+ HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBinary(op, dst, arg1, arg2));
+ return dst;
+ }
+
//.. case Iop_Add8x16: op =3D Xsse_ADD8; goto do_SseReRg;
-//.. case Iop_Add16x8: op =3D Xsse_ADD16; goto do_SseReRg;
-//.. case Iop_Add32x4: op =3D Xsse_ADD32; goto do_SseReRg;
//.. case Iop_Add64x2: op =3D Xsse_ADD64; goto do_SseReRg;
//.. case Iop_QAdd8Sx16: op =3D Xsse_QADD8S; goto do_SseReRg;
//.. case Iop_QAdd16Sx8: op =3D Xsse_QADD16S; goto do_SseReRg;
@@ -3319,31 +3325,74 @@
//.. case Iop_CmpGT8Sx16: op =3D Xsse_CMPGT8S; goto do_SseReRg;
//.. case Iop_CmpGT16Sx8: op =3D Xsse_CMPGT16S; goto do_SseReRg;
//.. case Iop_CmpGT32Sx4: op =3D Xsse_CMPGT32S; goto do_SseReRg;
-//.. case Iop_Max16Sx8: op =3D Xsse_MAX16S; goto do_SseReRg;
-//.. case Iop_Max8Ux16: op =3D Xsse_MAX8U; goto do_SseReRg;
-//.. case Iop_Min16Sx8: op =3D Xsse_MIN16S; goto do_SseReRg;
-//.. case Iop_Min8Ux16: op =3D Xsse_MIN8U; goto do_SseReRg;
-//.. case Iop_MulHi16Ux8: op =3D Xsse_MULHI16U; goto do_SseReRg;
-//.. case Iop_MulHi16Sx8: op =3D Xsse_MULHI16S; goto do_SseReRg;
//.. case Iop_Mul16x8: op =3D Xsse_MUL16; goto do_SseReRg;
-//.. case Iop_Sub8x16: op =3D Xsse_SUB8; goto do_SseReRg;
-//.. case Iop_Sub16x8: op =3D Xsse_SUB16; goto do_SseReRg;
-//.. case Iop_Sub32x4: op =3D Xsse_SUB32; goto do_SseReRg;
//.. case Iop_Sub64x2: op =3D Xsse_SUB64; goto do_SseReRg;
//.. case Iop_QSub8Sx16: op =3D Xsse_QSUB8S; goto do_SseReRg;
//.. case Iop_QSub16Sx8: op =3D Xsse_QSUB16S; goto do_SseReRg;
//.. case Iop_QSub8Ux16: op =3D Xsse_QSUB8U; goto do_SseReRg;
//.. case Iop_QSub16Ux8: op =3D Xsse_QSUB16U; goto do_SseReRg;
- do_AvBin: {
+
+ case Iop_Add8x16: op =3D Pav_ADDUM; goto do_AvBin8x16;
+ case Iop_QAdd8Ux16: op =3D Pav_ADDUS; goto do_AvBin8x16;
+ case Iop_QAdd8Sx16: op =3D Pav_ADDSS; goto do_AvBin8x16;
+ case Iop_Sub8x16: op =3D Pav_SUBUM; goto do_AvBin8x16;
+ case Iop_QSub8Ux16: op =3D Pav_SUBUS; goto do_AvBin8x16;
+ case Iop_QSub8Sx16: op =3D Pav_SUBSS; goto do_AvBin8x16;
+ case Iop_Avg8Ux16: op =3D Pav_AVGU; goto do_AvBin8x16;
+ case Iop_Avg8Sx16: op =3D Pav_AVGS; goto do_AvBin8x16;
+ case Iop_Max8Ux16: op =3D Pav_MAXU; goto do_AvBin8x16;
+ case Iop_Max8Sx16: op =3D Pav_MAXS; goto do_AvBin8x16;
+ case Iop_Min8Ux16: op =3D Pav_MINU; goto do_AvBin8x16;
+ case Iop_Min8Sx16: op =3D Pav_MINS; goto do_AvBin8x16;
+ do_AvBin8x16: {
HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
HReg dst =3D newVRegV(env);
- addInstr(env, PPC32Instr_AvBinary(op, dst, arg1, arg2));
+ addInstr(env, PPC32Instr_AvBin8x16(op, dst, arg1, arg2));
return dst;
}
=20
- case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
+ case Iop_Add16x8: op =3D Pav_ADDUM; goto do_AvBin16x8;
+ case Iop_QAdd16Ux8: op =3D Pav_ADDUS; goto do_AvBin16x8;
+ case Iop_QAdd16Sx8: op =3D Pav_ADDSS; goto do_AvBin16x8;
+ case Iop_Sub16x8: op =3D Pav_SUBUM; goto do_AvBin16x8;
+ case Iop_QSub16Ux8: op =3D Pav_SUBUS; goto do_AvBin16x8;
+ case Iop_QSub16Sx8: op =3D Pav_SUBSS; goto do_AvBin16x8;
+ case Iop_Avg16Ux8: op =3D Pav_AVGU; goto do_AvBin16x8;
+ case Iop_Avg16Sx8: op =3D Pav_AVGS; goto do_AvBin16x8;
+ case Iop_Max16Ux8: op =3D Pav_MAXU; goto do_AvBin16x8;
+ case Iop_Max16Sx8: op =3D Pav_MAXS; goto do_AvBin16x8;
+ case Iop_Min16Ux8: op =3D Pav_MINU; goto do_AvBin16x8;
+ case Iop_Min16Sx8: op =3D Pav_MINS; goto do_AvBin16x8;
+ case Iop_MulLo16Ux8: op =3D Pav_OMULU; goto do_AvBin16x8;
+ case Iop_MulLo16Sx8: op =3D Pav_OMULS; goto do_AvBin16x8;
+ case Iop_MulHi16Ux8: op =3D Pav_EMULU; goto do_AvBin16x8;
+ case Iop_MulHi16Sx8: op =3D Pav_EMULS; goto do_AvBin16x8;
+ do_AvBin16x8: {
+ HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBin16x8(op, dst, arg1, arg2));
+ return dst;
+ }
+
+ case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
+ case Iop_QAdd32Ux4: op =3D Pav_ADDUS; goto do_AvBin32x4;
+ case Iop_QAdd32Sx4: op =3D Pav_ADDSS; goto do_AvBin32x4;
+ case Iop_Sub32x4: op =3D Pav_SUBUM; goto do_AvBin32x4;
+ case Iop_QSub32Ux4: op =3D Pav_SUBUS; goto do_AvBin32x4;
+ case Iop_QSub32Sx4: op =3D Pav_SUBSS; goto do_AvBin32x4;
+ case Iop_Avg32Ux4: op =3D Pav_AVGU; goto do_AvBin32x4;
+ case Iop_Avg32Sx4: op =3D Pav_AVGS; goto do_AvBin32x4;
+ case Iop_Max32Ux4: op =3D Pav_MAXU; goto do_AvBin32x4;
+ case Iop_Max32Sx4: op =3D Pav_MAXS; goto do_AvBin32x4;
+ case Iop_Min32Ux4: op =3D Pav_MINU; goto do_AvBin32x4;
+ case Iop_Min32Sx4: op =3D Pav_MINS; goto do_AvBin32x4;
case Iop_CmpGT32Ux4: op =3D Pav_CMPGTU; goto do_AvBin32x4;
+ case Iop_MulLo32Ux4: op =3D Pav_OMULU; goto do_AvBin32x4;
+ case Iop_MulLo32Sx4: op =3D Pav_OMULS; goto do_AvBin32x4;
+ case Iop_MulHi32Ux4: op =3D Pav_EMULU; goto do_AvBin32x4;
+ case Iop_MulHi32Sx4: op =3D Pav_EMULS; goto do_AvBin32x4;
do_AvBin32x4: {
HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
@@ -3394,24 +3443,6 @@
return dst;
}
=20
-//.. do_SseShift: {
-//.. HReg greg =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2)=
;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. HReg ereg =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(rmi));
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, ereg, esp0));
-//.. addInstr(env, mk_vMOVsd_RR(greg, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, ereg, dst));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-
default:
break;
} /* switch (e->Iex.Binop.op) */
|
|
From: <sv...@va...> - 2005-09-15 09:31:49
|
Author: sewardj
Date: 2005-09-15 10:31:45 +0100 (Thu, 15 Sep 2005)
New Revision: 4667
Log:
Use the correct segment preening function.
Modified:
branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c
Modified: branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c 2005-09-15 09:14:1=
2 UTC (rev 4666)
+++ branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c 2005-09-15 09:31:4=
5 UTC (rev 4667)
@@ -499,6 +499,7 @@
{
Int i, j, rd, wr;
Segment *s, *s1;
+ aspacem_barf("preen_segments");
vg_assert(segments_used >=3D 0 && segments_used < VG_N_SEGMENTS);
vg_assert(segnames_used >=3D 0 && segnames_used < VG_N_SEGNAMES);
=20
@@ -1810,11 +1811,11 @@
=20
=20
/* Sanity-check and canonicalise the segment array (merge mergable
- segments). */
+ segments). Returns True if any segments were merged. */
=20
-static void preen_nsegments ( void )
+static Bool preen_nsegments ( void )
{
- Int i, r, w;
+ Int i, r, w, nsegments_used_old =3D nsegments_used;
=20
/* Pass 1: check the segment array covers the entire address space
exactly once, and also that each segment is sane. */
@@ -1843,6 +1844,8 @@
w++;
aspacem_assert(w > 0 && w <=3D nsegments_used);
nsegments_used =3D w;
+
+ return nsegments_used !=3D nsegments_used_old;
}
=20
=20
@@ -2116,7 +2119,7 @@
=20
nsegments[iLo] =3D *seg;
=20
- preen_nsegments();
+ (void)preen_nsegments();
if (0) VG_(am_show_nsegments)(0,"AFTER preen (add_segment)");
}
=20
@@ -2580,7 +2583,7 @@
=20
/* Changing permissions could have made previously un-mergable
segments mergeable. Therefore have to re-preen them. */
- preen_segments();
+ (void)preen_nsegments();
}
=20
=20
@@ -2606,8 +2609,7 @@
add_segment( &seg );
=20
/* Unmapping could create two adjacent free segments, so a preen is
- needed. */
- preen_segments();
+ needed. add_segment() will do that, so no need to here. */
}
=20
=20
|
|
From: <sv...@va...> - 2005-09-15 09:14:15
|
Author: sewardj
Date: 2005-09-15 10:14:12 +0100 (Thu, 15 Sep 2005)
New Revision: 4666
Log:
On x86 only, allow execution in segments with read permissions.
Modified:
branches/ASPACEM/coregrind/m_translate.c
Modified: branches/ASPACEM/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/m_translate.c 2005-09-15 08:58:53 UTC (rev=
4665)
+++ branches/ASPACEM/coregrind/m_translate.c 2005-09-15 09:14:12 UTC (rev=
4666)
@@ -440,7 +440,7 @@
{
Addr64 redir, orig_addr0 =3D orig_addr;
Int tmpbuf_used, verbosity;
- Bool notrace_until_done, do_self_check;
+ Bool notrace_until_done, do_self_check, allowR;
UInt notrace_until_limit =3D 0;
NSegment* seg;
VexGuestExtents vge;
@@ -531,9 +531,15 @@
=20
seg =3D VG_(am_find_nsegment)(orig_addr);
=20
+# if defined(VGA_x86)
+ allowR =3D True;
+# else
+ allowR =3D False;
+# endif
+
if (seg =3D=3D NULL=20
|| !(seg->kind =3D=3D SkAnonC || seg->kind =3D=3D SkFileC)
- || !seg->hasX) {
+ || !(seg->hasX || (seg->hasR && allowR)) ) {
=20
/* U R busted, sonny. Place your hands on your head and step
away from the orig_addr. */
|
|
From: <sv...@va...> - 2005-09-15 08:58:58
|
Author: sewardj
Date: 2005-09-15 09:58:53 +0100 (Thu, 15 Sep 2005)
New Revision: 4665
Log:
Make the meaning of ML_(valid_client_addr) more closely match what it
did before -- free space is allowable too.
Modified:
branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c
branches/ASPACEM/coregrind/m_syswrap/syswrap-generic.c
branches/ASPACEM/coregrind/pub_core_aspacemgr.h
Modified: branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c 2005-09-15 07:40:2=
0 UTC (rev 4664)
+++ branches/ASPACEM/coregrind/m_aspacemgr/aspacemgr.c 2005-09-15 08:58:5=
3 UTC (rev 4665)
@@ -1956,9 +1956,10 @@
=20
/* Test if a piece of memory is addressable by the client with at
least the "prot" protection permissions by examining the underlying
- segments.
+ segments. If freeOk is True then SkFree areas are also allowed.
*/
-Bool VG_(am_is_valid_for_client)( Addr start, SizeT len, UInt prot )
+static
+Bool is_valid_for_client( Addr start, SizeT len, UInt prot, Bool freeOk =
)
{
Int i, iLo, iHi;
Bool needR, needW, needX;
@@ -1975,10 +1976,13 @@
iLo =3D find_nsegment_idx(start);
iHi =3D find_nsegment_idx(start + len - 1);
for (i =3D iLo; i <=3D iHi; i++) {
- if ((nsegments[i].kind =3D=3D SkFileC || nsegments[i].kind =3D=3D =
SkAnonC)
- && (needR ? nsegments[i].hasR : True)
- && (needW ? nsegments[i].hasW : True)
- && (needX ? nsegments[i].hasX : True)) {
+ if ( (nsegments[i].kind =3D=3D SkFileC=20
+ || nsegments[i].kind =3D=3D SkAnonC
+ || (nsegments[i].kind =3D=3D SkFree && freeOk)
+ || (nsegments[i].kind =3D=3D SkResvn && freeOk))
+ && (needR ? nsegments[i].hasR : True)
+ && (needW ? nsegments[i].hasW : True)
+ && (needX ? nsegments[i].hasX : True) ) {
/* ok */
} else {
return False;
@@ -1987,7 +1991,25 @@
return True;
}
=20
+/* Test if a piece of memory is addressable by the client with at
+ least the "prot" protection permissions by examining the underlying
+ segments. */
+Bool VG_(am_is_valid_for_client)( Addr start, SizeT len,=20
+ UInt prot )
+{
+ return is_valid_for_client( start, len, prot, False/*free not OK*/ );
+}
=20
+/* Variant of VG_(am_is_valid_for_client) which allows free areas to
+ be consider part of the client's addressable space. It also
+ considers reservations to be allowable, since from the client's
+ point of view they don't exist. */
+Bool VG_(am_is_free_or_valid_for_client)( Addr start, SizeT len,=20
+ UInt prot )
+{
+ return is_valid_for_client( start, len, prot, True/*free is OK*/ );
+}
+
/*-----------------------------------------------------------------*/
/*--- ---*/
/*--- Modifying the segment array, and constructing segments. ---*/
Modified: branches/ASPACEM/coregrind/m_syswrap/syswrap-generic.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/m_syswrap/syswrap-generic.c 2005-09-15 07:=
40:20 UTC (rev 4664)
+++ branches/ASPACEM/coregrind/m_syswrap/syswrap-generic.c 2005-09-15 08:=
58:53 UTC (rev 4665)
@@ -57,32 +57,28 @@
#include "vki_unistd.h" /* for the __NR_* constants */
=20
=20
-/* return true if address range entirely contained within client
- address space */
+/* Returns True iff address range is something the client can
+ plausibly mess with: all of it is either already belongs to the
+ client or is free. */
+
Bool ML_(valid_client_addr)(Addr start, SizeT size, ThreadId tid,
const Char *syscallname)
{
- Addr end =3D start+size;
- Addr cl_base =3D VG_(client_base);
Bool ret;
=20
if (size =3D=3D 0)
return True;
=20
- if (0 && cl_base < 0x10000)
- cl_base =3D 0x10000;
+ ret =3D VG_(am_is_free_or_valid_for_client)(start,size,VKI_PROT_NONE)=
;
=20
- ret =3D VG_(am_is_valid_for_client)(start,size,VKI_PROT_NONE);
-
if (0)
- VG_(printf)("%s: test=3D%p-%p client=3D%p-%p ret=3D%d\n",
- syscallname, start, end, cl_base, VG_(client_end), (Int)ret);
+ VG_(printf)("%s: test=3D%p-%p ret=3D%d\n",
+ syscallname, start, start+size-1, (Int)ret);
=20
if (!ret && syscallname !=3D NULL) {
VG_(message)(Vg_UserMsg, "Warning: client syscall %s tried "
"to modify addresses %p-%p",
- syscallname, start, end);
-
+ syscallname, start, start+size-1);
if (VG_(clo_verbosity) > 1) {
VG_(get_and_pp_StackTrace)(tid, VG_(clo_backtrace_size));
}
Modified: branches/ASPACEM/coregrind/pub_core_aspacemgr.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/pub_core_aspacemgr.h 2005-09-15 07:40:20 U=
TC (rev 4664)
+++ branches/ASPACEM/coregrind/pub_core_aspacemgr.h 2005-09-15 08:58:53 U=
TC (rev 4665)
@@ -266,6 +266,13 @@
extern Bool VG_(am_is_valid_for_client)( Addr start, SizeT len,=20
UInt prot );
=20
+/* Variant of VG_(am_is_valid_for_client) which allows free areas to
+ be consider part of the client's addressable space. It also
+ considers reservations to be allowable, since from the client's
+ point of view they don't exist. */
+extern Bool VG_(am_is_free_or_valid_for_client)( Addr start, SizeT len,=20
+ UInt prot );
+
/* Trivial fn: return the total amount of space in anonymous mappings,
both for V and the client. Is used for printing stats in
out-of-memory messages. */
|
|
From: <sv...@va...> - 2005-09-15 07:40:27
|
Author: tom
Date: 2005-09-15 08:40:20 +0100 (Thu, 15 Sep 2005)
New Revision: 4664
Log:
Add ENOENT to the list of known errors.
Modified:
branches/ASPACEM/coregrind/m_syscall.c
branches/ASPACEM/include/vki-linux.h
Modified: branches/ASPACEM/coregrind/m_syscall.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/coregrind/m_syscall.c 2005-09-14 23:24:24 UTC (rev 4=
663)
+++ branches/ASPACEM/coregrind/m_syscall.c 2005-09-15 07:40:20 UTC (rev 4=
664)
@@ -228,6 +228,7 @@
{
switch (errnum) {
case VKI_EPERM: return "EPERM";
+ case VKI_ENOENT: return "ENOENT";
case VKI_ESRCH: return "ESRCH";
case VKI_EINTR: return "EINTR";
case VKI_EBADF: return "EBADF";
Modified: branches/ASPACEM/include/vki-linux.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/include/vki-linux.h 2005-09-14 23:24:24 UTC (rev 466=
3)
+++ branches/ASPACEM/include/vki-linux.h 2005-09-15 07:40:20 UTC (rev 466=
4)
@@ -1019,6 +1019,7 @@
//----------------------------------------------------------------------
=20
#define VKI_EPERM 1 /* Operation not permitted */
+#define VKI_ENOENT 2 /* No such file or directory */
#define VKI_ESRCH 3 /* No such process */
#define VKI_EINTR 4 /* Interrupted system call */
#define VKI_ENOEXEC 8 /* Exec format error */
|
|
From: <js...@ac...> - 2005-09-15 02:56:40
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-09-15 03:30:00 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 185 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <js...@ac...> - 2005-09-15 02:44:58
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2005-09-15 04:40:01 CEST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 158 tests, 17 stderr failures, 1 stdout failure ================= memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/fprw (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) cachegrind/tests/chdir (stderr) cachegrind/tests/dlclose (stdout) cachegrind/tests/dlclose (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/fdleak_ipv4 (stderr) |
|
From: Tom H. <to...@co...> - 2005-09-15 02:41:15
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2005-09-15 03:30:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 187 tests, 5 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-15 02:28:07
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-09-15 03:15:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 14 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-15 02:25:44
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-09-15 03:10:14 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-15 02:21:26
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2005-09-15 03:10:14 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-15 02:19:40
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2005-09-15 03:05:06 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-15 02:15:20
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-09-15 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) |