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From: <sv...@va...> - 2005-05-09 22:23:45
|
Author: sewardj
Date: 2005-05-09 23:23:38 +0100 (Mon, 09 May 2005)
New Revision: 1175
Modified:
trunk/priv/guest-amd64/toIR.c
Log:
Finish off amd64 MMX instructions before they finish me off (it's
either them or me). Honestly, the amd64 insn set has the most complex
encoding I have ever seen.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-09 18:15:21 UTC (rev 1174)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-09 22:23:38 UTC (rev 1175)
@@ -6085,62 +6085,62 @@
}
=20
=20
-//.. /* Vector by scalar shift of E by an immediate byte. This is a
-//.. straight copy of dis_SSE_shiftE_imm. */
-//..=20
-//.. static=20
-//.. UInt dis_MMX_shiftE_imm ( ULong delta, HChar* opname, IROp op )
-//.. {
-//.. Bool shl, shr, sar;
-//.. UChar rm =3D getUChar(delta);
-//.. IRTemp e0 =3D newTemp(Ity_I64);
-//.. IRTemp e1 =3D newTemp(Ity_I64);
-//.. UChar amt, size;
-//.. vassert(epartIsReg(rm));
-//.. vassert(gregOfRM(rm) =3D=3D 2=20
-//.. || gregOfRM(rm) =3D=3D 4 || gregOfRM(rm) =3D=3D 6);
-//.. amt =3D (Int)(getUChar(delta+1));
-//.. delta +=3D 2;
-//.. DIP("%s $%d,%s\n", opname,
-//.. (Int)amt,
-//.. nameMMXReg(eregOfRM(rm)) );
-//..=20
-//.. assign( e0, getMMXReg(eregOfRM(rm)) );
-//..=20
-//.. shl =3D shr =3D sar =3D False;
-//.. size =3D 0;
-//.. switch (op) {
-//.. case Iop_ShlN16x4: shl =3D True; size =3D 16; break;
-//.. case Iop_ShlN32x2: shl =3D True; size =3D 32; break;
-//.. case Iop_Shl64: shl =3D True; size =3D 64; break;
-//.. case Iop_SarN16x4: sar =3D True; size =3D 16; break;
-//.. case Iop_SarN32x2: sar =3D True; size =3D 32; break;
-//.. case Iop_ShrN16x4: shr =3D True; size =3D 16; break;
-//.. case Iop_ShrN32x2: shr =3D True; size =3D 32; break;
-//.. case Iop_Shr64: shr =3D True; size =3D 64; break;
-//.. default: vassert(0);
-//.. }
-//..=20
-//.. if (shl || shr) {
-//.. assign( e1, amt >=3D size=20
-//.. ? mkU64(0)
-//.. : binop(op, mkexpr(e0), mkU8(amt))
-//.. );
-//.. } else=20
-//.. if (sar) {
-//.. assign( e1, amt >=3D size=20
-//.. ? binop(op, mkexpr(e0), mkU8(size-1))
-//.. : binop(op, mkexpr(e0), mkU8(amt))
-//.. );
-//.. } else {
-//.. vassert(0);
-//.. }
-//..=20
-//.. putMMXReg( eregOfRM(rm), mkexpr(e1) );
-//.. return delta;
-//.. }
+/* Vector by scalar shift of E by an immediate byte. This is a
+ straight copy of dis_SSE_shiftE_imm. */
=20
+static=20
+ULong dis_MMX_shiftE_imm ( ULong delta, HChar* opname, IROp op )
+{
+ Bool shl, shr, sar;
+ UChar rm =3D getUChar(delta);
+ IRTemp e0 =3D newTemp(Ity_I64);
+ IRTemp e1 =3D newTemp(Ity_I64);
+ UChar amt, size;
+ vassert(epartIsReg(rm));
+ vassert(gregLO3ofRM(rm) =3D=3D 2=20
+ || gregLO3ofRM(rm) =3D=3D 4 || gregLO3ofRM(rm) =3D=3D 6);
+ amt =3D (Int)(getUChar(delta+1));
+ delta +=3D 2;
+ DIP("%s $%d,%s\n", opname,
+ (Int)amt,
+ nameMMXReg(eregLO3ofRM(rm)) );
=20
+ assign( e0, getMMXReg(eregLO3ofRM(rm)) );
+
+ shl =3D shr =3D sar =3D False;
+ size =3D 0;
+ switch (op) {
+ case Iop_ShlN16x4: shl =3D True; size =3D 16; break;
+ case Iop_ShlN32x2: shl =3D True; size =3D 32; break;
+ case Iop_Shl64: shl =3D True; size =3D 64; break;
+ case Iop_SarN16x4: sar =3D True; size =3D 16; break;
+ case Iop_SarN32x2: sar =3D True; size =3D 32; break;
+ case Iop_ShrN16x4: shr =3D True; size =3D 16; break;
+ case Iop_ShrN32x2: shr =3D True; size =3D 32; break;
+ case Iop_Shr64: shr =3D True; size =3D 64; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign( e1, amt >=3D size=20
+ ? mkU64(0)
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else=20
+ if (sar) {
+ assign( e1, amt >=3D size=20
+ ? binop(op, mkexpr(e0), mkU8(size-1))
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else {
+ vassert(0);
+ }
+
+ putMMXReg( eregLO3ofRM(rm), mkexpr(e1) );
+ return delta;
+}
+
+
/* Completely handle all MMX instructions except emms. */
=20
static
@@ -6157,51 +6157,97 @@
=20
switch (opc) {
=20
-//.. case 0x6E:=20
-//.. /* MOVD (src)ireg-or-mem (E), (dst)mmxreg (G)*/
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. modrm =3D getUChar(delta);
-//.. if (epartIsReg(modrm)) {
-//.. delta++;
-//.. putMMXReg(
-//.. gregOfRM(modrm),
-//.. binop( Iop_32HLto64,
-//.. mkU32(0),
-//.. getIReg(4, eregOfRM(modrm)) ) );
-//.. DIP("movd %s, %s\n",=20
-//.. nameIReg(4,eregOfRM(modrm)), nameMMXReg(gregOfRM(mo=
drm)));
-//.. } else {
-//.. IRTemp addr =3D disAMode( &len, sorb, delta, dis_buf );
-//.. delta +=3D len;
-//.. putMMXReg(
-//.. gregOfRM(modrm),
-//.. binop( Iop_32HLto64,
-//.. mkU32(0),
-//.. loadLE(Ity_I32, mkexpr(addr)) ) );
-//.. DIP("movd %s, %s\n", dis_buf, nameMMXReg(gregOfRM(modrm=
)));
-//.. }
-//.. break;
-//..=20
-//.. case 0x7E: /* MOVD (src)mmxreg (G), (dst)ireg-or-mem (E) */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. modrm =3D getUChar(delta);
-//.. if (epartIsReg(modrm)) {
-//.. delta++;
-//.. putIReg( 4, eregOfRM(modrm),
-//.. unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) =
);
-//.. DIP("movd %s, %s\n",=20
-//.. nameMMXReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(mo=
drm)));
-//.. } else {
-//.. IRTemp addr =3D disAMode( &len, sorb, delta, dis_buf );
-//.. delta +=3D len;
-//.. storeLE( mkexpr(addr),
-//.. unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) =
);
-//.. DIP("movd %s, %s\n", nameMMXReg(gregOfRM(modrm)), dis_b=
uf);
-//.. }
-//.. break;
+ case 0x6E:=20
+ if (sz =3D=3D 4) {
+ /* MOVD (src)ireg32-or-mem32 (E), (dst)mmxreg (G)*/
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ binop( Iop_32HLto64,
+ mkU32(0),
+ getIReg32(eregOfRexRM(pfx,modrm)) ) );
+ DIP("movd %s, %s\n",=20
+ nameIReg32(eregOfRexRM(pfx,modrm)),=20
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ binop( Iop_32HLto64,
+ mkU32(0),
+ loadLE(Ity_I32, mkexpr(addr)) ) );
+ DIP("movd %s, %s\n", dis_buf, nameMMXReg(gregLO3ofRM(modr=
m)));
+ }
+ }=20
+ else
+ if (sz =3D=3D 8) {
+ /* MOVD (src)ireg64-or-mem64 (E), (dst)mmxreg (G)*/
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putMMXReg( gregLO3ofRM(modrm),
+ getIReg64(eregOfRexRM(pfx,modrm)) );
+ DIP("movd %s, %s\n",=20
+ nameIReg64(eregOfRexRM(pfx,modrm)),=20
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ putMMXReg( gregLO3ofRM(modrm),
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movd{64} %s, %s\n", dis_buf, nameMMXReg(gregLO3ofRM(=
modrm)));
+ }
+ }
+ else {
+ goto mmx_decode_failure;
+ }
+ break;
=20
+ case 0x7E:
+ if (sz =3D=3D 4) {
+ /* MOVD (src)mmxreg (G), (dst)ireg32-or-mem32 (E) */
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putIReg32( eregOfRexRM(pfx,modrm),
+ unop(Iop_64to32, getMMXReg(gregLO3ofRM(modrm))=
) );
+ DIP("movd %s, %s\n",=20
+ nameMMXReg(gregLO3ofRM(modrm)),=20
+ nameIReg32(eregOfRexRM(pfx,modrm)));
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ storeLE( mkexpr(addr),
+ unop(Iop_64to32, getMMXReg(gregLO3ofRM(modrm)) )=
);
+ DIP("movd %s, %s\n", nameMMXReg(gregLO3ofRM(modrm)), dis_=
buf);
+ }
+ }
+ else
+ if (sz =3D=3D 8) {
+ /* MOVD (src)mmxreg (G), (dst)ireg64-or-mem64 (E) */
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putIReg64( eregOfRexRM(pfx,modrm),
+ getMMXReg(gregLO3ofRM(modrm)) );
+ DIP("movd %s, %s\n",=20
+ nameMMXReg(gregLO3ofRM(modrm)),=20
+ nameIReg64(eregOfRexRM(pfx,modrm)));
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ storeLE( mkexpr(addr),
+ getMMXReg(gregLO3ofRM(modrm)) );
+ DIP("movd{64} %s, %s\n", nameMMXReg(gregLO3ofRM(modrm)), =
dis_buf);
+ }
+ } else {
+ goto mmx_decode_failure;
+ }
+ break;
+
case 0x6F:
/* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
if (sz !=3D 4)=20
@@ -6394,54 +6440,47 @@
case 0xE2: SHIFT_BY_REG("psrad", Iop_SarN32x2);
=20
# undef SHIFT_BY_REG
-//..=20
-//.. case 0x71:=20
-//.. case 0x72:=20
-//.. case 0x73: {
-//.. /* (sz=3D=3D4): PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
-//.. UChar byte1, byte2, subopc;
-//.. void* hAddr;
-//.. Char* hName;
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. byte1 =3D opc; /* 0x71/72/73 */
-//.. byte2 =3D getUChar(delta); /* amode / sub-opcod=
e */
-//.. subopc =3D (byte2 >> 3) & 7;
-//..=20
-#if 0 /* stop gcc multi-line comment warning */
-/.. # define SHIFT_BY_IMM(_name,_op) \
-/.. do { delta =3D dis_MMX_shiftE_imm(delta,_name,_op); \
-/.. } while (0)
-#endif /* stop gcc multi-line comment warning */
-//..=20
-//.. hAddr =3D NULL;
-//.. hName =3D NULL;
-//..=20
-//.. if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x71)=20
-//.. SHIFT_BY_IMM("psrlw", Iop_ShrN16x4);
-//.. else if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x72)=20
-//.. SHIFT_BY_IMM("psrld", Iop_ShrN32x2);
-//.. else if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x73)=20
-//.. SHIFT_BY_IMM("psrlq", Iop_Shr64);
-//..=20
-//.. else if (subopc =3D=3D 4 /*SAR*/ && opc =3D=3D 0x71)=20
-//.. SHIFT_BY_IMM("psraw", Iop_SarN16x4);
-//.. else if (subopc =3D=3D 4 /*SAR*/ && opc =3D=3D 0x72)=20
-//.. SHIFT_BY_IMM("psrad", Iop_SarN32x2);
-//..=20
-//.. else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x71)=20
-//.. SHIFT_BY_IMM("psllw", Iop_ShlN16x4);
-//.. else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x72)=20
-//.. SHIFT_BY_IMM("pslld", Iop_ShlN32x2);
-//.. else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x73)=20
-//.. SHIFT_BY_IMM("psllq", Iop_Shl64);
-//..=20
-//.. else goto mmx_decode_failure;
-//..=20
-//.. # undef SHIFT_BY_IMM
-//.. break;
-//.. }
=20
+ case 0x71:=20
+ case 0x72:=20
+ case 0x73: {
+ /* (sz=3D=3D4): PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
+ UChar byte1, byte2, subopc;
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ byte1 =3D opc; /* 0x71/72/73 */
+ byte2 =3D getUChar(delta); /* amode / sub-opcode */
+ subopc =3D (byte2 >> 3) & 7;
+
+# define SHIFT_BY_IMM(_name,_op) \
+ do { delta =3D dis_MMX_shiftE_imm(delta,_name,_op); \
+ } while (0)
+
+ if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x71)=20
+ SHIFT_BY_IMM("psrlw", Iop_ShrN16x4);
+ else if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x72)=20
+ SHIFT_BY_IMM("psrld", Iop_ShrN32x2);
+ else if (subopc =3D=3D 2 /*SRL*/ && opc =3D=3D 0x73)=20
+ SHIFT_BY_IMM("psrlq", Iop_Shr64);
+
+ else if (subopc =3D=3D 4 /*SAR*/ && opc =3D=3D 0x71)=20
+ SHIFT_BY_IMM("psraw", Iop_SarN16x4);
+ else if (subopc =3D=3D 4 /*SAR*/ && opc =3D=3D 0x72)=20
+ SHIFT_BY_IMM("psrad", Iop_SarN32x2);
+
+ else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x71)=20
+ SHIFT_BY_IMM("psllw", Iop_ShlN16x4);
+ else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x72)=20
+ SHIFT_BY_IMM("pslld", Iop_ShlN32x2);
+ else if (subopc =3D=3D 6 /*SHL*/ && opc =3D=3D 0x73)=20
+ SHIFT_BY_IMM("psllq", Iop_Shl64);
+
+ else goto mmx_decode_failure;
+
+# undef SHIFT_BY_IMM
+ break;
+ }
+
/* --- MMX decode failure --- */
default:
mmx_decode_failure:
@@ -13277,12 +13316,12 @@
=20
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- MMXery =3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
=20
-//.. case 0x71:=20
-//.. case 0x72:=20
-//.. case 0x73: /* PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
-//..=20
-//.. case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */
-//.. case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */
+ case 0x71:=20
+ case 0x72:=20
+ case 0x73: /* PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
+
+ case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */
+ case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */
case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
=20
@@ -13352,7 +13391,7 @@
=20
/* If sz=3D=3D2 this is SSE, and we assume sse idec has
already spotted those cases by now. */
- if (sz !=3D 4)
+ if (sz !=3D 4 && sz !=3D 8)
goto decode_failure;
if (have66orF2orF3(pfx))
goto decode_failure;
|
|
From: Julian S. <js...@ac...> - 2005-05-09 22:10:13
|
That is to say, valgrind.org. J On Monday 09 May 2005 16:14, Donna Robinson wrote: > Hi All, > > Just to let you all know that our server > is scheduled for downtime re upgrades etc. > from 6am BST to 6.30am BST tomorrow, 10 May. > > Donna |
|
From: <sv...@va...> - 2005-05-09 22:01:45
|
Author: sewardj
Date: 2005-05-09 23:01:37 +0100 (Mon, 09 May 2005)
New Revision: 3647
Added:
trunk/none/tests/amd64/gen_insn_test.pl
trunk/none/tests/amd64/insn_mmx.def
Log:
Versions of Tom's excellent insn-set test programs modified for the
amd64 insn set.
Added: trunk/none/tests/amd64/gen_insn_test.pl
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/gen_insn_test.pl 2005-05-09 01:23:49 UTC (rev =
3646)
+++ trunk/none/tests/amd64/gen_insn_test.pl 2005-05-09 22:01:37 UTC (rev =
3647)
@@ -0,0 +1,984 @@
+#!/usr/bin/perl
+
+use 5.006;
+use strict;
+use warnings;
+
+our %ArgTypes =3D (
+ r8 =3D> "reg8_t",
+ r16 =3D> "reg16_t",
+ r32 =3D> "reg32_t",
+ r64 =3D> "reg64_t",
+ mm =3D> "reg64_t",
+ xmm =3D> "reg128_t",
+ m8 =3D> "reg8_t",
+ m16 =3D> "reg16_t",
+ m32 =3D> "reg32_t",
+ m64 =3D> "reg64_t",
+ m128 =3D> "reg128_t",
+ eflags =3D> "reg32_t",
+ st =3D> "reg64_t",
+ fpucw =3D> "reg16_t",
+ fpusw =3D> "reg16_t"
+ );
+
+our %SubTypeFormats =3D (
+ sb =3D> "%d",
+ ub =3D> "%u",
+ sw =3D> "%d",
+ uw =3D> "%u",
+ sd =3D> "%d",
+ ud =3D> "%u",
+ sq =3D> "%lld",
+ uq =3D> "%llu",
+ ps =3D> "%.16g",
+ pd =3D> "%.16g"
+ );
+
+our %SubTypeSuffixes =3D (
+ sb =3D> "",
+ ub =3D> "U",
+ sw =3D> "",
+ uw =3D> "",
+ sd =3D> "",
+ ud =3D> "",
+ sq =3D> "LL",
+ uq =3D> "ULL",
+ ps =3D> "F",
+ pd =3D> ""
+ );
+
+our %RegNums =3D (
+ al =3D> 0, ax =3D> 0, eax =3D> 0, rax =3D> 0,
+ bl =3D> 1, bx =3D> 1, ebx =3D> 1, rbx =3D> 1,
+ cl =3D> 2, cx =3D> 2, ecx =3D> 2, rcx =3D> 2,
+ dl =3D> 3, dx =3D> 3, edx =3D> 3, rdx =3D> 3,
+ ah =3D> 4,
+ bh =3D> 5,
+ ch =3D> 6,
+ dh =3D> 7,
+ st0 =3D> 0, st1 =3D> 1, st2 =3D> 2, st3 =3D> 3,
+ st4 =3D> 4, st5 =3D> 5, st6 =3D> 6, st7 =3D> 7
+ );
+
+our %RegTypes =3D (
+ al =3D> "r8", ah =3D> "r8", ax =3D> "r16", eax =3D> "r3=
2", rax =3D> "r64",
+ bl =3D> "r8", bh =3D> "r8", bx =3D> "r16", ebx =3D> "r3=
2", rbx =3D> "r64",
+ cl =3D> "r8", ch =3D> "r8", cx =3D> "r16", ecx =3D> "r3=
2", rcx =3D> "r64",
+ dl =3D> "r8", dh =3D> "r8", dx =3D> "r16", edx =3D> "r3=
2", rdx =3D> "r64"
+ );
+
+our @IntRegs =3D (
+ { r8 =3D> "al", r16 =3D> "ax", r32 =3D> "eax", r64 =3D> =
"rax" },
+ { r8 =3D> "bl", r16 =3D> "bx", r32 =3D> "ebx", r64 =3D> =
"rbx" },
+ { r8 =3D> "cl", r16 =3D> "cx", r32 =3D> "ecx", r64 =3D> =
"rcx" },
+ { r8 =3D> "dl", r16 =3D> "dx", r32 =3D> "edx", r64 =3D> =
"rdx" },
+ { r8 =3D> "ah" },
+ { r8 =3D> "bh" },
+ { r8 =3D> "ch" },
+ { r8 =3D> "dh" }
+ );
+
+print <<EOF;
+#include <math.h>
+#include <setjmp.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+typedef union {
+ char sb[1];
+ unsigned char ub[1];
+} reg8_t;
+
+typedef union {
+ char sb[2];
+ unsigned char ub[2];
+ short sw[1];
+ unsigned short uw[1];
+} reg16_t;
+
+typedef union {
+ char sb[4];
+ unsigned char ub[4];
+ short sw[2];
+ unsigned short uw[2];
+ int sd[1];
+ unsigned int ud[1];
+ float ps[1];
+} reg32_t;
+
+typedef union {
+ char sb[8];
+ unsigned char ub[8];
+ short sw[4];
+ unsigned short uw[4];
+ int sd[2];
+ unsigned int ud[2];
+ long long int sq[1];
+ unsigned long long int uq[1];
+ float ps[2];
+ double pd[1];
+} reg64_t __attribute__ ((aligned (8)));
+
+typedef union {
+ char sb[16];
+ unsigned char ub[16];
+ short sw[8];
+ unsigned short uw[8];
+ int sd[4];
+ unsigned int ud[4];
+ long long int sq[2];
+ unsigned long long int uq[2];
+ float ps[4];
+ double pd[2];
+} reg128_t __attribute__ ((aligned (16)));
+
+static sigjmp_buf catchpoint;
+
+static void handle_sigill(int signum)
+{
+ siglongjmp(catchpoint, 1);
+}
+
+__attribute__((unused))
+static int eq_float(float f1, float f2)
+{
+ return f1 =3D=3D f2 || fabsf(f1 - f2) < fabsf(f1) * 1.5 * pow(2,-12);
+}
+
+__attribute__((unused))
+static int eq_double(double d1, double d2)
+{
+ return d1 =3D=3D d2 || fabs(d1 - d2) < fabs(d1) * 1.5 * pow(2,-12);
+}
+
+EOF
+
+my %tests;
+my @tests;
+
+while (<>)
+{
+ next if /^#/;
+
+ my $insn;
+ my $presets;
+ my $args;
+ my $results;
+
+ if (/^(\S+)\s+(?:(\S+(?:\s+\S+)*)\s+:\s+)?((?:\S+\s+)*?)(?:=3D>\s+(\=
S+(?:\s+\S+)*))?$/)
+ {
+ $insn =3D $1;
+ $presets =3D $2 || "";
+ $args =3D $3 || "";
+ $results =3D $4 || "";
+
+# print STDERR "insn: $insn\n";
+# print STDERR "presets: $presets\n";
+# print STDERR "args: $args\n";
+# print STDERR "results: $results\n";
+ }
+ else
+ {
+ die "Can't parse test $_";
+ }
+ =20
+ $tests{$insn}++;
+ =20
+ my $test =3D "${insn}_$tests{$insn}";
+ =20
+ push @tests, $test;
+ =20
+ print qq|static void $test(void)\n|;
+ print qq|\{\n|;
+
+ my @intregs =3D @IntRegs;
+ my @mmregs =3D map { "mm$_" } (6,7,0,1,2,3,4,5);
+ my @xmmregs =3D map { "xmm$_" } (4,5,0,1,2,3,6,7);
+ my @fpregs =3D map { "st$_" } (0 .. 7);
+
+ my @presets;
+ my $presetc =3D 0;
+ my $eflagsmask;
+ my $eflagsset;
+ my $fpucwmask;
+ my $fpucwset;
+ my $fpuswmask;
+ my $fpuswset;
+
+ foreach my $preset (split(/\s+/, $presets))
+ {
+ if ($preset =3D~ /^([abcd][lh]|[abcd]x|e[abcd]x|r[abcd]x)\.(sb|u=
b|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]]+)\]$/)
+ {
+ my $name =3D "preset$presetc";
+ my $type =3D $RegTypes{$1};
+ my $regnum =3D $RegNums{$1};
+ my $register =3D $intregs[$regnum];
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ die "Register $1 already used" unless defined($register);
+
+ my $preset =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype,
+ register =3D> $register
+ };
+
+ delete($intregs[$regnum]);
+
+ push @presets, $preset;
+ =20
+ print qq| $ArgTypes{$type} $name =3D \{ .$subtype =3D \{|;
+ =20
+ my $valuec =3D 0;
+ =20
+ foreach my $value (@values)
+ {
+ print qq|,| if $valuec > 0;
+ print qq| $value$SubTypeSuffixes{$subtype}|;
+ $valuec++;
+ }
+ =20
+ print qq| \} \};\n|;
+
+ $presetc++;
+ }
+ elsif ($preset =3D~ /^st([0-9]+)\.(ps|pd)\[([^\]]+)\]$/)
+ {
+ my $name =3D "preset$presetc";
+ my $type =3D "st";
+ my $regnum =3D $1;
+ my $register =3D $fpregs[$regnum];
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+
+ die "Register st$1 already used" unless defined($register);
+
+ my $preset =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype,
+ register =3D> $register
+ };
+
+ delete($fpregs[$regnum]);
+
+ push @presets, $preset;
+ =20
+ print qq| $ArgTypes{$type} $name =3D \{ .$subtype =3D \{|;
+ =20
+ my $valuec =3D 0;
+ =20
+ foreach my $value (@values)
+ {
+ print qq|,| if $valuec > 0;
+ print qq| $value$SubTypeSuffixes{$subtype}|;
+ $valuec++;
+ }
+ =20
+ print qq| \} \};\n|;
+
+ $presetc++;
+ }
+ elsif ($preset =3D~ /^(eflags)\[([^\]]+)\]$/)
+ {
+ my $type =3D $1;
+ my @values =3D split(/,/, $2);
+
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+
+ $eflagsmask =3D sprintf "0x%08x", $values[0] ^ 0xffffffff;
+ $eflagsset =3D sprintf "0x%08x", $values[1];
+ }
+ elsif ($preset =3D~ /^(fpucw)\[([^\]]+)\]$/)
+ {
+ my $type =3D $1;
+ my @values =3D split(/,/, $2);
+
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+
+ $fpucwmask =3D sprintf "0x%04x", $values[0] ^ 0xffff;
+ $fpucwset =3D sprintf "0x%04x", $values[1];
+ }
+ elsif ($preset =3D~ /^(fpusw)\[([^\]]+)\]$/)
+ {
+ my $type =3D $1;
+ my @values =3D split(/,/, $2);
+
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+
+ $fpuswmask =3D sprintf "0x%04x", $values[0] ^ 0xffff;
+ $fpuswset =3D sprintf "0x%04x", $values[1];
+ }
+ else
+ {
+ die "Can't parse preset $preset";
+ }
+ }
+
+ my @args;
+ my $argc =3D 0;
+ =20
+ foreach my $arg (split(/\s+/, $args))
+ {
+ my $name =3D "arg$argc";
+
+ if ($arg =3D~ /^([abcd]l|[abcd]x|e[abcd]x|r[abcd]x|r8|r16|r32|r6=
4|mm|xmm|m8|m16|m32|m64|m128)\.(sb|ub|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]]+)\=
]$/)
+ {
+ my $type =3D $RegTypes{$1} || $1;
+ my $regnum =3D $RegNums{$1};
+ my $register =3D $intregs[$regnum] if defined($regnum);
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ die "Register $1 already used" if defined($regnum) && !defin=
ed($register);
+
+ my $arg =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype
+ };
+
+ if (defined($register))
+ {
+ $arg->{register} =3D $register;
+ delete($intregs[$regnum]);
+ }
+
+ push @args, $arg;
+ =20
+ print qq| $ArgTypes{$type} $name =3D \{ .$subtype =3D \{|;
+ =20
+ my $valuec =3D 0;
+ =20
+ foreach my $value (@values)
+ {
+ print qq|,| if $valuec > 0;
+ print qq| $value$SubTypeSuffixes{$subtype}|;
+ $valuec++;
+ }
+
+ print qq| \} \};\n|;
+ }
+ elsif ($arg =3D~ /^st([0-9]+)\.(ps|pd)\[([^\]]+)\]$/)
+ {
+ my $type =3D "st";
+ my $regnum =3D $1;
+ my $register =3D $fpregs[$regnum] if defined($regnum);
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ die "Register st$1 already used" if defined($regnum) && !def=
ined($register);
+
+ my $arg =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype
+ };
+
+ if (defined($register))
+ {
+ $arg->{register} =3D $register;
+ delete($fpregs[$regnum]);
+ }
+
+ push @args, $arg;
+ =20
+ print qq| $ArgTypes{$type} $name =3D \{ .$subtype =3D \{|;
+ =20
+ my $valuec =3D 0;
+ =20
+ foreach my $value (@values)
+ {
+ print qq|,| if $valuec > 0;
+ print qq| $value$SubTypeSuffixes{$subtype}|;
+ $valuec++;
+ }
+
+ print qq| \} \};\n|;
+ }
+ elsif ($arg =3D~ /^(imm8|imm16|imm32)\[([^\]]+)\]$/)
+ {
+ my $type =3D $1;
+ my $value =3D $2;
+ =20
+ my $arg =3D {
+ type =3D> $type,
+ value =3D> $value
+ };
+
+ push @args, $arg;
+ }
+ else
+ {
+ die "Can't parse argument $arg";
+ }
+
+ $argc++;
+ }
+ =20
+ foreach my $arg (@presets, @args)
+ {
+ if ($arg->{type} =3D~ /^(r8|r16|r32|r64|m8|m16|m32)$/)
+ {
+ while (!exists($arg->{register}) || !defined($arg->{register=
}))
+ {
+ $arg->{register} =3D shift @intregs;
+ }
+
+ $arg->{register} =3D $arg->{register}->{$arg->{type}};
+ }
+ elsif ($arg->{type} =3D~ /^(mm|m64)$/)
+ {
+ $arg->{register} =3D shift @mmregs;
+ }
+ elsif ($arg->{type} =3D~ /^(xmm|m128)$/)
+ {
+ $arg->{register} =3D shift @xmmregs;
+ }
+ elsif ($arg->{type} =3D~ /^st$/)
+ {
+ while (!exists($arg->{register}) || !defined($arg->{register=
}))
+ {
+ $arg->{register} =3D shift @fpregs;
+ }
+ }
+ }
+
+ my @results;
+ my $resultc =3D 0;
+ =20
+ foreach my $result (split(/\s+/, $results))
+ {
+ my $name =3D "result$resultc";
+ =20
+ if ($result =3D~ /^(\d+)\.(sb|ub|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]=
]+)\]$/)
+ {
+ my $index =3D $1;
+ my $type =3D $args[$index]->{type};
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ die "Argument $index not specified" unless exists($args[$ind=
ex]);
+
+ my $result =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype,
+ arg =3D> $args[$index],
+ register =3D> $args[$index]->{register},
+ values =3D> [ @values ]
+ };
+
+ push @results, $result;
+
+ print qq| $ArgTypes{$type} $name|;
+ print qq| =3D arg$index| if $type =3D~ /^m(8|16|32|64|128)$/=
;
+ print qq|;\n|;
+
+ $args[$index]->{result} =3D $result;
+ }
+ elsif ($result =3D~ /^([abcd][lh]|[abcd]x|e[abcd]x|r[abcd]x)\.(s=
b|ub|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]]+)\]$/)
+ {
+ my $register =3D $1;
+ my $type =3D $RegTypes{$register};
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ my $result =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype,
+ register =3D> $register,
+ values =3D> [ @values ]
+ };
+
+ push @results, $result;
+
+ print qq| $ArgTypes{$type} $name;\n|;
+ }
+ elsif ($result =3D~ /^(st[0-9]+)\.(ps|pd)\[([^\]]+)\]$/)
+ {
+ my $register =3D $1;
+ my $type =3D "st";
+ my $subtype =3D $2;
+ my @values =3D split(/,/, $3);
+ =20
+ my $result =3D {
+ name =3D> $name,
+ type =3D> $type,
+ subtype =3D> $subtype,
+ register =3D> $register,
+ values =3D> [ @values ]
+ };
+
+ push @results, $result;
+
+ print qq| $ArgTypes{$type} $name;\n|;
+ }
+ elsif ($result =3D~ /^eflags\[([^\]]+)\]$/)
+ {
+ my @values =3D split(/,/, $1);
+ =20
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+ =20
+ my $result =3D {
+ name =3D> $name,
+ type =3D> "eflags",
+ subtype =3D> "ud",
+ values =3D> [ map { sprintf "0x%08x", $_ } @values ]
+ };
+
+ push @results, $result;
+ =20
+ print qq| $ArgTypes{eflags} $name;\n|;
+
+ if (!defined($eflagsmask) && !defined($eflagsset))
+ {
+ $eflagsmask =3D sprintf "0x%08x", $values[0] ^ 0xfffffff=
f;
+ $eflagsset =3D sprintf "0x%08x", $values[0] & ~$values[1=
];
+ }
+ }
+ elsif ($result =3D~ /^fpucw\[([^\]]+)\]$/)
+ {
+ my @values =3D split(/,/, $1);
+ =20
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+ =20
+ my $result =3D {
+ name =3D> $name,
+ type =3D> "fpucw",
+ subtype =3D> "ud",
+ values =3D> [ map { sprintf "0x%04x", $_ } @values ]
+ };
+
+ push @results, $result;
+ =20
+ print qq| $ArgTypes{fpucw} $name;\n|;
+
+ if (!defined($fpucwmask) && !defined($fpucwset))
+ {
+ $fpucwmask =3D sprintf "0x%04x", $values[0] ^ 0xffff;
+ $fpucwset =3D sprintf "0x%04x", $values[0] & ~$values[1]=
;
+ }
+ }
+ elsif ($result =3D~ /^fpusw\[([^\]]+)\]$/)
+ {
+ my @values =3D split(/,/, $1);
+ =20
+ $values[0] =3D oct($values[0]) if $values[0] =3D~ /^0/;
+ $values[1] =3D oct($values[1]) if $values[1] =3D~ /^0/;
+ =20
+ my $result =3D {
+ name =3D> $name,
+ type =3D> "fpusw",
+ subtype =3D> "ud",
+ values =3D> [ map { sprintf "0x%04x", $_ } @values ]
+ };
+
+ push @results, $result;
+ =20
+ print qq| $ArgTypes{fpusw} $name;\n|;
+
+ if (!defined($fpuswmask) && !defined($fpuswset))
+ {
+ $fpuswmask =3D sprintf "0x%04x", $values[0] ^ 0xffff;
+ $fpuswset =3D sprintf "0x%04x", $values[0] & ~$values[1]=
;
+ }
+ }
+ else
+ {
+ die "Can't parse result $result";
+ }
+ =20
+ $resultc++;
+ }
+ =20
+ my $argnum =3D 0;
+
+ foreach my $result (@results)
+ {
+ if ($result->{type} =3D~ /^(m(8|16|32|64|128)|st|eflags|fpu[cs]w=
)$/)
+ {
+ $result->{argnum} =3D $argnum++;
+ }
+ }
+ =20
+ foreach my $arg (@presets, @args)
+ {
+ if (defined($arg->{name}))
+ {
+ $arg->{argnum} =3D $argnum++;
+ }
+ }
+ =20
+ foreach my $result (@results)
+ {
+ if ($result->{type} =3D~ /^(r(8|16|32|64)|mm|xmm)$/)
+ {
+ $result->{argnum} =3D $argnum++;
+ }
+ }
+
+ my $stateargnum =3D $argnum++;
+
+ print qq| char state\[108\];\n|;
+ print qq|\n|;
+ print qq| if (sigsetjmp(catchpoint, 1) =3D=3D 0)\n|;
+ print qq| \{\n|;
+ print qq| asm\(\n|;
+# print qq| \"fsave %$stateargnum\\n\"\n|;
+ =20
+ my @fpargs;
+
+ foreach my $arg (@presets, @args)
+ {
+ if ($arg->{type} eq "r8")
+ {
+ print qq| \"movb %$arg->{argnum}, %%$arg->{register}=
\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "r16")
+ {
+ print qq| \"movw %$arg->{argnum}, %%$arg->{register}=
\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "r32")
+ {
+ print qq| \"movl %$arg->{argnum}, %%$arg->{register}=
\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "r64")
+ {
+ print qq| \"movq %$arg->{argnum}, %%$arg->{register}=
\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "mm")
+ {
+ print qq| \"movq %$arg->{argnum}, %%$arg->{register}=
\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "xmm")
+ {
+ print qq| \"movlps 0%$arg->{argnum}, %%$arg->{regist=
er}\\n\"\n|;
+ print qq| \"movhps 8%$arg->{argnum}, %%$arg->{regist=
er}\\n\"\n|;
+ }
+ elsif ($arg->{type} eq "st")
+ {
+ $fpargs[$RegNums{$arg->{register}}] =3D $arg;
+ }
+ }
+ =20
+ foreach my $arg (reverse @fpargs)
+ {
+ if (defined($arg))
+ {
+ if ($arg->{subtype} eq "ps")
+ {
+ print qq| \"flds %$arg->{argnum}\\n\"\n|;
+ }
+ elsif ($arg->{subtype} eq "pd")
+ {
+ print qq| \"fldl %$arg->{argnum}\\n\"\n|;
+ }
+ }
+ else
+ {
+ print qq| \"fldz\\n\"\n|;
+ }
+ }
+
+ if (defined($eflagsmask) || defined($eflagsset))
+ {
+ print qq| \"pushfl\\n\"\n|;
+ print qq| \"andl \$$eflagsmask, (%%esp)\\n\"\n| if defin=
ed($eflagsmask);
+ print qq| \"orl \$$eflagsset, (%%esp)\\n\"\n| if defined=
($eflagsset);
+ print qq| \"popfl\\n\"\n|;
+ }
+
+ if (defined($fpucwmask) || defined($fpucwset))
+ {
+ print qq| \"subl \$2, %%esp\\n\"\n|;
+ print qq| \"fstcw (%%esp)\\n\"\n|;
+ print qq| \"andw \$$fpucwmask, (%%esp)\\n\"\n| if define=
d($fpucwmask);
+ print qq| \"orw \$$fpucwset, (%%esp)\\n\"\n| if defined(=
$fpucwset);
+ print qq| \"fldcw (%%esp)\\n\"\n|;
+ print qq| \"addl \$2, %%esp\\n\"\n|;
+ }
+
+ print qq| \"$insn|;
+ =20
+ my $prefix =3D " ";
+ =20
+ foreach my $arg (@args)
+ {
+ next if $arg->{type} eq "eflags";
+
+ if ($arg->{type} =3D~ /^(r8|r16|r32|r64|mm|xmm)$/)
+ {
+ print qq|$prefix%%$arg->{register}|;
+ }
+ elsif ($arg->{type} =3D~ /^st$/)
+ {
+ my $register =3D $arg->{register};
+
+ $register =3D~ s/st(\d+)/st\($1\)/;
+
+ print qq|$prefix%%$register|;
+ }
+ elsif ($arg->{type} =3D~ /^(m(8|16|32|64|128))$/)
+ {
+ if (exists($arg->{result}))
+ {
+ print qq|$prefix%$arg->{result}->{argnum}|;
+ }
+ else
+ {
+ print qq|$prefix%$arg->{argnum}|;
+ }
+ }
+ elsif ($arg->{type} =3D~ /^imm(8|16|32)$/)
+ {
+ print qq|$prefix\$$arg->{value}|;
+ }
+
+ $prefix =3D ", ";
+ }
+
+ print qq|\\n\"\n|;
+
+ my @fpresults;
+
+ foreach my $result (@results)
+ {
+ if ($result->{type} eq "r8")
+ {
+ print qq| \"movb %%$result->{register}, %$result->{a=
rgnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "r16")
+ {
+ print qq| \"movw %%$result->{register}, %$result->{a=
rgnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "r32")
+ {
+ print qq| \"movl %%$result->{register}, %$result->{a=
rgnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "r64")
+ {
+ print qq| \"movq %%$result->{register}, %$result->{a=
rgnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "mm")
+ {
+ print qq| \"movq %%$result->{register}, %$result->{a=
rgnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "xmm")
+ {
+ print qq| \"movlps %%$result->{register}, 0%$result-=
>{argnum}\\n\"\n|;
+ print qq| \"movhps %%$result->{register}, 8%$result-=
>{argnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "st")
+ {
+ $fpresults[$RegNums{$result->{register}}] =3D $result;
+ }
+ elsif ($result->{type} eq "eflags")
+ {
+ print qq| \"pushfl\\n\"\n|;
+ print qq| \"popl %$result->{argnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "fpucw")
+ {
+ print qq| \"fstcw %$result->{argnum}\\n\"\n|;
+ }
+ elsif ($result->{type} eq "fpusw")
+ {
+ print qq| \"fstsw %$result->{argnum}\\n\"\n|;
+ }
+ }
+ =20
+ foreach my $result (@fpresults)
+ {
+ if (defined($result))
+ {
+ if ($result->{subtype} eq "ps")
+ {
+ print qq| \"fstps %$result->{argnum}\\n\"\n|;
+ }
+ elsif ($result->{subtype} eq "pd")
+ {
+ print qq| \"fstpl %$result->{argnum}\\n\"\n|;
+ }
+ }
+ else
+ {
+ print qq| \"fincstp\\n\"\n|;
+ }
+ }
+
+# print qq| \"frstor %$stateargnum\\n\"\n|;
+
+ print qq| :|;
+
+ $prefix =3D " ";
+
+ foreach my $result (@results)
+ {
+ if ($result->{type} =3D~ /^(m(8|16|32|64|128)|st|eflags|fpu[cs]w=
)$/)
+ {
+ print qq|$prefix\"=3Dm\" \($result->{name}\)|;
+ $prefix =3D ", ";
+ }
+ }
+
+ print qq|\n|;
+ =20
+ $prefix =3D " : ";
+ =20
+ foreach my $arg (@presets, @args)
+ {
+ if (defined($arg->{name}))
+ {
+ print qq|$prefix\"m\" \($arg->{name}\)|;
+ $prefix =3D ", ";
+ }
+ }
+ =20
+ foreach my $result (@results)
+ {
+ if ($result->{type} =3D~ /^(r(8|16|32|64)|mm|xmm)$/)
+ {
+ print qq|$prefix\"m\" \($result->{name}\)|;
+ $prefix =3D ", ";
+ }
+ }
+
+ print qq|$prefix\"m\" \(state[0]\)\n|;
+
+ $prefix =3D " : ";
+
+ foreach my $arg (@presets, @args)
+ {
+ if ($arg->{register} && $arg->{type} ne "st")
+ {
+ print qq|$prefix\"$arg->{register}\"|;
+ $prefix =3D ", ";
+ }
+ }
+
+ print qq|\n|;
+ =20
+ print qq| \);\n|; =20
+ print qq|\n|;
+ =20
+ if (@results)
+ {
+ print qq| if \(|;
+ =20
+ $prefix =3D "";
+ =20
+ foreach my $result (@results)
+ {
+ my $type =3D $result->{type};
+ my $subtype =3D $result->{subtype};
+ my $suffix =3D $SubTypeSuffixes{$subtype};
+ my @values =3D @{$result->{values}};
+ =20
+ if ($type eq "eflags")
+ {
+ print qq|${prefix}\($result->{name}.ud[0] & $values[0]UL=
\) =3D=3D $values[1]UL|;
+ }
+ elsif ($type =3D~ /^fpu[cs]w$/)
+ {
+ print qq|${prefix}\($result->{name}.uw[0] & $values[0]\)=
=3D=3D $values[1]|;
+ }
+ else
+ {
+ foreach my $value (0 .. $#values)
+ {
+ if ($subtype eq "ps")
+ {
+ print qq|${prefix}eq_float($result->{name}.$subt=
ype\[$value\], $values[$value]$suffix)|;
+ }
+ elsif ($subtype eq "pd")
+ {
+ print qq|${prefix}eq_double($result->{name}.$sub=
type\[$value\], $values[$value]$suffix)|;
+ }
+ else
+ {
+ print qq|${prefix}$result->{name}.$subtype\[$val=
ue\] =3D=3D $values[$value]$suffix|;
+ }
+ =20
+ $prefix =3D " && ";
+ }
+ }
+ =20
+ $prefix =3D " &&\n ";
+ }
+ =20
+ print qq| \)\n|;
+ print qq| \{\n|;
+ print qq| printf("$test ... ok\\n");\n|;
+ print qq| \}\n|;
+ print qq| else\n|;
+ print qq| \{\n|;
+ print qq| printf("$test ... not ok\\n");\n|;
+ =20
+ foreach my $result (@results)
+ {
+ my $type =3D $result->{type};
+ my $subtype =3D $result->{subtype};
+ my $suffix =3D $SubTypeSuffixes{$subtype};
+ my @values =3D @{$result->{values}};
+ =20
+ if ($type eq "eflags")
+ {
+ print qq| printf(" eflags & 0x%lx =3D 0x%lx (ex=
pected 0x%lx)\\n", $values[0]UL, $result->{name}.ud\[0\] & $values[0]UL, =
$values[1]UL);\n|;
+ }
+ elsif ($type =3D~ /^fpu[cs]w$/)
+ {
+ print qq| printf(" $type & 0x%x =3D 0x%x (expec=
ted 0x%x)\\n", $values[0], $result->{name}.uw\[0\] & $values[0], $values[=
1]);\n|;
+ }
+ else
+ {
+ foreach my $value (0 .. $#values)
+ {
+ print qq| printf(" $result->{name}.$subtype=
\[$value\] =3D $SubTypeFormats{$subtype} (expected $SubTypeFormats{$subty=
pe})\\n", $result->{name}.$subtype\[$value\], $values[$value]$suffix);\n|=
;
+ }
+ }
+ }
+ =20
+ print qq| \}\n|;
+ }
+ else
+ {
+ print qq| printf("$test ... ok\\n");\n|;
+ }
+
+ print qq| \}\n|;
+ print qq| else\n|;
+ print qq| \{\n|;
+ print qq| printf("$test ... failed\\n");\n|;
+ print qq| \}\n|;
+ print qq|\n|;
+ print qq| return;\n|;
+ print qq|\}\n|;
+ print qq|\n|;
+}
+
+print qq|int main(int argc, char **argv)\n|;
+print qq|\{\n|;
+print qq| signal(SIGILL, handle_sigill);\n|;
+print qq|\n|;
+
+foreach my $test (@tests)
+{
+ print qq| $test();\n|;
+}
+
+print qq|\n|;
+print qq| exit(0);\n|;
+print qq|\}\n|;
+
+exit 0;
Added: trunk/none/tests/amd64/insn_mmx.def
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/insn_mmx.def 2005-05-09 01:23:49 UTC (rev 3646=
)
+++ trunk/none/tests/amd64/insn_mmx.def 2005-05-09 22:01:37 UTC (rev 3647=
)
@@ -0,0 +1,123 @@
+#
+# %mm <-> ireg64
+#
+movd mm.sd[1234,5678] r64.sd[1111,2222] =3D> 1.sd[1234,5678]
+movd r64.sd[1234,5678] mm.sd[1111,2222] =3D> 1.sd[1234,5678]
+#
+# %mm <-> ireg32
+#
+movd r32.sd[1234] mm.sd[1111,2222] =3D> 1.sd[1234,0]
+movd mm.sd[1234,2222] r32.sd[1111] =3D> 1.sd[1234]
+#
+# %mm <-> mem32
+#
+movd m32.sd[1234] mm.sd[1111,2222] =3D> 1.sd[1234,0]
+movd mm.sd[1234,2222] m32.sd[1111] =3D> 1.sd[1234]
+#
+# %mm <-> mem64
+#
+movq m64.uq[0x012345678abcdef] mm.uq[0x1212121234343434] =3D> 1.uq[0x012=
345678abcdef]
+movq mm.uq[0x012345678abcdef] m64.uq[0x1212121234343434] =3D> 1.uq[0x012=
345678abcdef]
+#
+# %mm -> %mm
+#
+movq mm.uq[0x012345678abcdef] mm.uq[0x1212121234343434] =3D> 1.uq[0x0123=
45678abcdef]
+#
+#
+#
+packssdw mm.sd[12345,123456] mm.sd[-12345,-123456] =3D> 1.sw[-12345,-327=
68,12345,32767]
+packssdw m64.sd[12345,123456] mm.sd[-12345,-123456] =3D> 1.sw[-12345,-32=
768,12345,32767]
+packsswb mm.sw[123,-123,1234,-1234] mm.sw[21,-21,321,-321] =3D> 1.sb[21,=
-21,127,-128,123,-123,127,-128]
+packsswb m64.sw[123,-123,1234,-1234] mm.sw[21,-21,321,-321] =3D> 1.sb[21=
,-21,127,-128,123,-123,127,-128]
+packuswb mm.sw[123,-123,1234,-1234] mm.sw[21,-21,321,-321] =3D> 1.ub[21,=
0,255,0,123,0,255,0]
+packuswb m64.sw[123,-123,1234,-1234] mm.sw[21,-21,321,-321] =3D> 1.ub[21=
,0,255,0,123,0,255,0]
+paddb mm.sb[12,34,56,78,21,43,65,87] mm.sb[8,7,6,5,4,3,2,1] =3D> 1.sb[20=
,41,62,83,25,46,67,88]
+paddb m64.sb[12,34,56,78,21,43,65,87] mm.sb[8,7,6,5,4,3,2,1] =3D> 1.sb[2=
0,41,62,83,25,46,67,88]
+paddd mm.sd[12345678,87654321] mm.sd[8765,4321] =3D> 1.sd[12354443,87658=
642]
+paddd m64.sd[12345678,87654321] mm.sd[8765,4321] =3D> 1.sd[12354443,8765=
8642]
+paddsb mm.sb[25,-25,50,-50,100,-100,125,-125] mm.sb[40,-40,30,-30,20,-20=
,10,-10] =3D> 1.sb[65,-65,80,-80,120,-120,127,-128]
+paddsb m64.sb[25,-25,50,-50,100,-100,125,-125] mm.sb[40,-40,30,-30,20,-2=
0,10,-10] =3D> 1.sb[65,-65,80,-80,120,-120,127,-128]
+paddsw mm.sw[12345,-12345,32145,-32145] mm.sw[32145,-32145,-12345,12345]=
=3D> 1.sw[32767,-32768,19800,-19800]
+paddsw m64.sw[12345,-12345,32145,-32145] mm.sw[32145,-32145,-12345,12345=
] =3D> 1.sw[32767,-32768,19800,-19800]
+paddusb mm.ub[25,50,75,100,125,150,175,200] mm.ub[10,20,30,40,50,60,70,8=
0] =3D> 1.ub[35,70,105,140,175,210,245,255]
+paddusb m64.ub[25,50,75,100,125,150,175,200] mm.ub[10,20,30,40,50,60,70,=
80] =3D> 1.ub[35,70,105,140,175,210,245,255]
+paddusw mm.uw[22222,33333,44444,55555] mm.uw[6666,7777,8888,9999] =3D> 1=
.uw[28888,41110,53332,65535]
+paddusw m64.uw[22222,33333,44444,55555] mm.uw[6666,7777,8888,9999] =3D> =
1.uw[28888,41110,53332,65535]
+paddw mm.sw[1234,5678,4321,8765] mm.sw[87,65,43,21] =3D> 1.sw[1321,5743,=
4364,8786]
+paddw m64.sw[1234,5678,4321,8765] mm.sw[87,65,43,21] =3D> 1.sw[1321,5743=
,4364,8786]
+pand mm.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x012=
1452188a84420]
+pand m64.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x01=
21452188a84420]
+pandn mm.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xfc=
98301064002000]
+pandn m64.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xf=
c98301064002000]
+pcmpeqb mm.ub[11,22,33,44,55,66,77,88] mm.ub[11,11,33,33,55,55,77,77] =3D=
> 1.ub[0xff,0x00,0xff,0x00,0xff,0x00,0xff,0x00]
+pcmpeqb m64.ub[11,22,33,44,55,66,77,88] mm.ub[11,11,33,33,55,55,77,77] =3D=
> 1.ub[0xff,0x00,0xff,0x00,0xff,0x00,0xff,0x00]
+pcmpeqd mm.ud[11223344,55667788] mm.ud[11223344,11223344] =3D> 1.ud[0xff=
ffffff,0x00000000]
+pcmpeqd m64.ud[11223344,55667788] mm.ud[11223344,11223344] =3D> 1.ud[0xf=
fffffff,0x00000000]
+pcmpeqw mm.uw[1122,3344,5566,7788] mm.uw[1122,1122,5566,5566] =3D> 1.uw[=
0xffff,0x0000,0xffff,0x0000]
+pcmpeqw m64.uw[1122,3344,5566,7788] mm.uw[1122,1122,5566,5566] =3D> 1.uw=
[0xffff,0x0000,0xffff,0x0000]
+pcmpgtb mm.sb[-77,-55,-33,-11,11,33,55,77] mm.sb[77,55,33,11,-11,-33,-55=
,-77] =3D> 1.ub[0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00]
+pcmpgtb m64.sb[-77,-55,-33,-11,11,33,55,77] mm.sb[77,55,33,11,-11,-33,-5=
5,-77] =3D> 1.ub[0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00]
+pcmpgtd mm.sd[-11111111,11111111] mm.sd[11111111,-11111111] =3D> 1.ud[0x=
ffffffff,0x00000000]
+pcmpgtd m64.sd[-11111111,11111111] mm.sd[11111111,-11111111] =3D> 1.ud[0=
xffffffff,0x00000000]
+pcmpgtw mm.sw[-3333,-1111,1111,3333] mm.sw[3333,1111,-1111,-3333] =3D> 1=
.uw[0xffff,0xffff,0x0000,0x0000]
+pcmpgtw m64.sw[-3333,-1111,1111,3333] mm.sw[3333,1111,-1111,-3333] =3D> =
1.uw[0xffff,0xffff,0x0000,0x0000]
+pmaddwd mm.sw[1234,5678,-4321,-8765] mm.sw[1111,-2222,3333,-4444] =3D> 1=
.sd[-11245542,24549767]
+pmaddwd m64.sw[1234,5678,-4321,-8765] mm.sw[1111,-2222,3333,-4444] =3D> =
1.sd[-11245542,24549767]
+pmulhw mm.sw[1111,2222,-1111,-2222] mm.sw[3333,-4444,3333,-4444] =3D> 1.=
uw[0x0038,0xff69,0xffc7,0x0096]
+pmulhw m64.sw[1111,2222,-1111,-2222] mm.sw[3333,-4444,3333,-4444] =3D> 1=
.uw[0x0038,0xff69,0xffc7,0x0096]
+pmullw mm.sw[1111,2222,-1111,-2222] mm.sw[3333,-4444,3333,-4444] =3D> 1.=
uw[0x80b3,0x5378,0x7f4d,0xac88]
+pmullw m64.sw[1111,2222,-1111,-2222] mm.sw[3333,-4444,3333,-4444] =3D> 1=
.uw[0x80b3,0x5378,0x7f4d,0xac88]
+por mm.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xfdbb=
7577edabedef]
+por m64.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xfdb=
b7577edabedef]
+pslld imm8[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x12345670,0x9abcde=
f0]
+pslld mm.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x12345670,0x9abcd=
ef0]
+pslld m64.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x12345670,0x9abc=
def0]
+psllq imm8[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x123456789abcdef0]
+psllq mm.uq[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x123456789abcdef0]
+psllq m64.uq[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x123456789abcdef0]
+psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x1230,0x5670=
,0x9ab0,0xdef0]
+psllw mm.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x1230,0x567=
0,0x9ab0,0xdef0]
+psllw m64.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x1230,0x56=
70,0x9ab0,0xdef0]
+psrad imm8[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0xf89abc=
de]
+psrad mm.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0xf89ab=
cde]
+psrad m64.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0xf89a=
bcde]
+psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x0456=
,0xf89a,0xfcde]
+psraw mm.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x045=
6,0xf89a,0xfcde]
+psraw m64.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x04=
56,0xf89a,0xfcde]
+psrld imm8[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0x089abc=
de]
+psrld mm.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0x089ab=
cde]
+psrld m64.uq[4] mm.ud[0x01234567,0x89abcdef] =3D> 1.ud[0x00123456,0x089a=
bcde]
+psrlq imm8[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x00123456789abcde]
+psrlq mm.uq[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x00123456789abcde]
+psrlq m64.uq[4] mm.uq[0x0123456789abcdef] =3D> 1.uq[0x00123456789abcde]
+psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x0456=
,0x089a,0x0cde]
+psrlw mm.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x045=
6,0x089a,0x0cde]
+psrlw m64.uq[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] =3D> 1.uw[0x0012,0x04=
56,0x089a,0x0cde]
+psubb mm.sb[8,7,6,5,4,3,2,1] mm.sb[12,34,56,78,21,43,65,87] =3D> 1.sb[4,=
27,50,73,17,40,63,86]
+psubb m64.sb[8,7,6,5,4,3,2,1] mm.sb[12,34,56,78,21,43,65,87] =3D> 1.sb[4=
,27,50,73,17,40,63,86]
+psubd mm.sd[8765,4321] mm.sd[12345678,87654321] =3D> 1.sd[12336913,87650=
000]
+psubd m64.sd[8765,4321] mm.sd[12345678,87654321] =3D> 1.sd[12336913,8765=
0000]
+psubsb mm.sb[-50,50,-40,40,-30,30,-20,20] mm.sb[25,-25,50,-50,100,-100,1=
25,-125] =3D> 1.sb[75,-75,90,-90,127,-128,127,-128]
+psubsb m64.sb[-50,50,-40,40,-30,30,-20,20] mm.sb[25,-25,50,-50,100,-100,=
125,-125] =3D> 1.sb[75,-75,90,-90,127,-128,127,-128]
+psubsw mm.sw[-32145,32145,12345,-12345] mm.sw[12345,-12345,32145,-32145]=
=3D> 1.sw[32767,-32768,19800,-19800]
+psubsw m64.sw[-32145,32145,12345,-12345] mm.sw[12345,-12345,32145,-32145=
] =3D> 1.sw[32767,-32768,19800,-19800]
+psubusb mm.ub[11,22,33,44,55,66,77,88] mm.ub[88,77,66,55,44,33,22,11] =3D=
> 1.ub[77,55,33,11,0,0,0,0]
+psubusb m64.ub[11,22,33,44,55,66,77,88] mm.ub[88,77,66,55,44,33,22,11] =3D=
> 1.ub[77,55,33,11,0,0,0,0]
+psubusw mm.uw[1122,3344,5566,7788] mm.uw[8877,6655,4433,2211] =3D> 1.uw[=
7755,3311,0,0]
+psubusw m64.uw[1122,3344,5566,7788] mm.uw[8877,6655,4433,2211] =3D> 1.uw=
[7755,3311,0,0]
+psubw mm.sw[87,65,43,21] mm.sw[1234,5678,4321,8765] =3D> 1.sw[1147,5613,=
4278,8744]
+psubw m64.sw[87,65,43,21] mm.sw[1234,5678,4321,8765] =3D> 1.sw[1147,5613=
,4278,8744]
+punpckhbw mm.ub[12,34,56,78,21,43,65,87] mm.ub[11,22,33,44,55,66,77,88] =
=3D> 1.ub[55,21,66,43,77,65,88,87]
+punpckhbw m64.ub[12,34,56,78,21,43,65,87] mm.ub[11,22,33,44,55,66,77,88]=
=3D> 1.ub[55,21,66,43,77,65,88,87]
+punpckhdq mm.ud[12345678,21436587] mm.ud[11223344,55667788] =3D> 1.ud[55=
667788,21436587]
+punpckhdq m64.ud[12345678,21436587] mm.ud[11223344,55667788] =3D> 1.ud[5=
5667788,21436587]
+punpckhwd mm.uw[1234,5678,2143,6587] mm.uw[1122,3344,5566,7788] =3D> 1.u=
w[5566,2143,7788,6587]
+punpckhwd m64.uw[1234,5678,2143,6587] mm.uw[1122,3344,5566,7788] =3D> 1.=
uw[5566,2143,7788,6587]
+punpcklbw mm.ub[12,34,56,78,21,43,65,87] mm.ub[11,22,33,44,55,66,77,88] =
=3D> 1.ub[11,12,22,34,33,56,44,78]
+punpcklbw m64.ub[12,34,56,78,21,43,65,87] mm.ub[11,22,33,44,55,66,77,88]=
=3D> 1.ub[11,12,22,34,33,56,44,78]
+punpckldq mm.ud[12345678,21436587] mm.ud[11223344,55667788] =3D> 1.ud[11=
223344,12345678]
+punpckldq m64.ud[12345678,21436587] mm.ud[11223344,55667788] =3D> 1.ud[1=
1223344,12345678]
+punpcklwd mm.uw[1234,5678,2143,6587] mm.uw[1122,3344,5566,7788] =3D> 1.u=
w[1122,1234,3344,5678]
+punpcklwd m64.uw[1234,5678,2143,6587] mm.uw[1122,3344,5566,7788] =3D> 1.=
uw[1122,1234,3344,5678]
+pxor mm.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xfc9=
a30566503a9cf]
+pxor m64.uq[0xfdb97531eca86420] mm.uq[0x0123456789abcdef] =3D> 1.uq[0xfc=
9a30566503a9cf]
|
|
From: Josef W. <Jos...@gm...> - 2005-05-09 21:26:05
|
On Monday 09 May 2005 14:46, Benoit Peccatte wrote: > > I think the tool should have control over whether it gets a file name > > with or without full directory. This really should be part of a debug > > info request API, part of the tool API. > > It's a matter of taste, but why should a tool control for the user how > filenames are handled ? Because the use of a long or an abbreviated file name without path depends on the context which only the tool knows about? E.g. for the output, it is clear that cachegrind/callgrind/cover always wants the full path, so that postprocessing tools can do annotation. If the postprocessing tool wants to show human readable output, it can strip the path itself. If the tool itself wants to produce human readable output, it could ask for the abbreviated version (API), or strip the path itself, too. In this case, I would simply remove the option, and even for the API, it is only convenience, but not really needed. I called it a "hack" because it looked like changing the semantic of an API from the outside ( e.g. VG_(get_filename_linenum)() ). > > Make UnitInfo as opaque data structure visible to the tool API (like > > SegInfo), and add a getDirectory(UnitInfo*). An iterator for debug line > > info would be getFirst/NextLine(UnitInfo*, int* line, Addr* addr) with > > (line,addr) as output. > > There are many UnitInfo, if you want to store ther you have to add a > table of UnitInfo and add a reference to them in the RiLoc structure. You need to have a way to iterate over the source files of a library, don't you? Josef > I intend to do such a thing soon since I've just adapted my tool to > valgrind3.0 |
|
From: Nicholas N. <nj...@cs...> - 2005-05-09 19:23:53
|
On Mon, 9 May 2005, Qin Zhao wrote: >> Sounds similar to CMU's TaintCheck >> (www.ece.cmu.edu/~jnewsome/docs/taintcheck.pdf) -- are there any major >> differences? > > Yes, actually it is inspired from that. I just wants to speed it up and make it > usable for application at realtime, and that's why I use DynamoRIO instead of > Valgrind. Right. I'd love to know how it goes, if you can do it. N |
|
From: Qin Z.
|
> Sounds similar to CMU's TaintCheck > (www.ece.cmu.edu/~jnewsome/docs/taintcheck.pdf) -- are there any major > differences? Yes, actually it is inspired from that. I just wants to speed it up and make it usable for application at realtime, and that's why I use DynamoRIO instead of Valgrind. |
|
From: Nicholas N. <nj...@cs...> - 2005-05-09 18:32:30
|
On Mon, 9 May 2005, Qin Zhao wrote: >>> I am developing a realtime information flow tracing tool using >>> DynamoRIO, which is similar to MemCheck, but more care about the speed. > > It is similar to MemCheck, each byte of memory and register has one byte shadow > memory, and intially set as clean. User can specify some part of data or data > reading from file or network as tainted, the corresponding shadow memory is > marked as tainted. Then during the execution, when the data is propagated > around, the instrumented code propagates data's taint status in shaodw memory. > We can perform some check at some point to see if the used data are tainted. > For example, we can check the data used for indirect branch's target address, > if it is tainted, it is very possible a buffer overflow attack happens. Sounds similar to CMU's TaintCheck (www.ece.cmu.edu/~jnewsome/docs/taintcheck.pdf) -- are there any major differences? > From my understanding, the basic tech is similar to MemCheck. Tracing and > checking. Yes. N |
|
From: <sv...@va...> - 2005-05-09 18:15:26
|
Author: sewardj
Date: 2005-05-09 19:15:21 +0100 (Mon, 09 May 2005)
New Revision: 1174
Modified:
trunk/priv/host-amd64/isel.c
Log:
Handle primops created by memchecking MMX code.
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-09 17:52:56 UTC (rev 1173)
+++ trunk/priv/host-amd64/isel.c 2005-05-09 18:15:21 UTC (rev 1174)
@@ -764,7 +764,10 @@
/* DO NOT CALL THIS DIRECTLY ! */
static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
+ /* Used for unary/binary SIMD64 ops. */
+ HWord fn =3D 0;
Bool second_is_UInt;
+
MatchInfo mi;
DECLARE_PATTERN(p_8Uto64);
DECLARE_PATTERN(p_1Uto8_64to1);
@@ -807,7 +810,6 @@
case Iex_Binop: {
AMD64AluOp aluOp;
AMD64ShiftOp shOp;
- HWord fn =3D 0; /* helper fn for most SIMD64 stuff */
=20
//..=20
//.. /* Pattern: Sub32(0,x) */
@@ -1484,6 +1486,32 @@
default:=20
break;
}
+
+ /* Deal with unary 64-bit SIMD ops. */
+ switch (e->Iex.Unop.op) {
+ case Iop_CmpNEZ32x2:
+ fn =3D (HWord)h_generic_calc_CmpNEZ32x2; break;
+ case Iop_CmpNEZ16x4:
+ fn =3D (HWord)h_generic_calc_CmpNEZ16x4; break;
+ case Iop_CmpNEZ8x8:
+ fn =3D (HWord)h_generic_calc_CmpNEZ8x8; break;
+ default:
+ fn =3D (HWord)0; break;
+ }
+ if (fn !=3D (HWord)0) {
+ /* Note: the following assumes all helpers are of
+ signature=20
+ ULong fn ( ULong ), and they are
+ not marked as regparm functions.=20
+ */
+ HReg dst =3D newVRegI(env);
+ HReg arg =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, mk_iMOVsd_RR(arg, hregAMD64_RDI()) );
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 1 ));
+ addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
+ return dst;
+ }
+
break;
}
=20
@@ -2522,33 +2550,6 @@
//.. return;
//.. }
//..=20
-//.. case Iop_CmpNEZ32x2:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ32x2; goto unish;
-//.. case Iop_CmpNEZ16x4:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ16x4; goto unish;
-//.. case Iop_CmpNEZ8x8:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ8x8; goto unish;
-//.. unish: {
-//.. /* Note: the following assumes all helpers are of
-//.. signature=20
-//.. ULong fn ( ULong ), and they are
-//.. not marked as regparm functions.=20
-//.. */
-//.. HReg xLo, xHi;
-//.. HReg tLo =3D newVRegI(env);
-//.. HReg tHi =3D newVRegI(env);
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xLo)));
-//.. addInstr(env, X86Instr_Call( Xcc_ALWAYS, (UInt)fn, 0 ))=
;
-//.. add_to_esp(env, 2*4);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
//.. default:=20
//.. break;
//.. }
|
|
From: <sv...@va...> - 2005-05-09 17:53:04
|
Author: sewardj
Date: 2005-05-09 18:52:56 +0100 (Mon, 09 May 2005)
New Revision: 1173
Modified:
trunk/priv/guest-amd64/ghelpers.c
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/isel.c
Log:
Make a whole bunch of mmx instructions work.
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2005-05-09 12:16:33 UTC (rev 1172)
+++ trunk/priv/guest-amd64/ghelpers.c 2005-05-09 17:52:56 UTC (rev 1173)
@@ -1383,7 +1383,44 @@
}
=20
=20
+/*---------------------------------------------------------------*/
+/*--- Helpers for MMX/SSE/SSE2. ---*/
+/*---------------------------------------------------------------*/
=20
+static inline ULong mk32x2 ( UInt w1, UInt w0 ) {
+ return (((ULong)w1) << 32) | ((ULong)w0);
+}
+
+static inline UShort sel16x4_3 ( ULong w64 ) {
+ UInt hi32 =3D toUInt(w64 >> 32);
+ return toUShort(hi32 >> 16);
+}
+static inline UShort sel16x4_2 ( ULong w64 ) {
+ UInt hi32 =3D toUInt(w64 >> 32);
+ return toUShort(hi32);
+}
+static inline UShort sel16x4_1 ( ULong w64 ) {
+ UInt lo32 =3D toUInt(w64);
+ return toUShort(lo32 >> 16);
+}
+static inline UShort sel16x4_0 ( ULong w64 ) {
+ UInt lo32 =3D toUInt(w64);
+ return toUShort(lo32);
+}
+
+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+ULong amd64g_calculate_mmx_pmaddwd ( ULong xx, ULong yy )
+{
+ return
+ mk32x2(
+ (((Int)(Short)sel16x4_3(xx)) * ((Int)(Short)sel16x4_3(yy)))
+ + (((Int)(Short)sel16x4_2(xx)) * ((Int)(Short)sel16x4_2(yy))=
),
+ (((Int)(Short)sel16x4_1(xx)) * ((Int)(Short)sel16x4_1(yy)))
+ + (((Int)(Short)sel16x4_0(xx)) * ((Int)(Short)sel16x4_0(yy))=
)
+ );
+}
+
+
/*---------------------------------------------------------------*/
/*--- Helpers for dealing with, and describing, ---*/
/*--- guest state as a whole. ---*/
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-09 12:16:33 UTC (rev 1172)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-09 17:52:56 UTC (rev 1173)
@@ -667,6 +667,13 @@
return (Int)( (mod_reg_rm >> 3) & 7 );
}
=20
+/* Ditto the 'e' field of a modRM byte. */
+inline
+static Int eregLO3ofRM ( UChar mod_reg_rm )
+{
+ return (Int)(mod_reg_rm & 0x7);
+}
+
/* Get a 8/16/32-bit unsigned value out of the insn stream. */
=20
static UChar getUChar ( ULong delta )
@@ -881,6 +888,12 @@
toBool((pfx & (PFX_66|PFX_F2|PFX_F3)) =3D=3D 0);
}
=20
+/* Return True iff pfx has any of 66, F2 and F3 set */
+static Bool have66orF2orF3 ( Prefix pfx )
+{
+ return ! haveNo66noF2noF3(pfx);
+}
+
/* Clear all the segment-override bits in a prefix. */
static Prefix clearSegBits ( Prefix p )
{
@@ -1968,15 +1981,15 @@
//.. default: vpanic("nameSReg(x86)");
//.. }
//.. }
-//..=20
-//.. static HChar* nameMMXReg ( Int mmxreg )
-//.. {
-//.. static HChar* mmx_names[8]=20
-//.. =3D { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", =
"%mm7" };
-//.. if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(x86,guest)");
-//.. return mmx_names[mmxreg];
-//.. }
=20
+static HChar* nameMMXReg ( Int mmxreg )
+{
+ static HChar* mmx_names[8]=20
+ =3D { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7=
" };
+ if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(amd64,guest)");
+ return mmx_names[mmxreg];
+}
+
static HChar* nameXMMReg ( Int xmmreg )
{
static HChar* xmm_names[16]=20
@@ -1988,16 +2001,16 @@
return xmm_names[xmmreg];
}
=20
-//.. static Char* nameMMXGran ( UChar gran )
-//.. {
-//.. switch (gran) {
-//.. case 0: return "b";
-//.. case 1: return "w";
-//.. case 2: return "d";
-//.. case 3: return "q";
-//.. default: vpanic("nameMMXGran(x86,guest)");
-//.. }
-//.. }
+static HChar* nameMMXGran ( UChar gran )
+{
+ switch (gran) {
+ case 0: return "b";
+ case 1: return "w";
+ case 2: return "d";
+ case 3: return "q";
+ default: vpanic("nameMMXGran(amd64,guest)");
+ }
+}
=20
static HChar nameISize ( Int size )
{
@@ -5790,288 +5803,288 @@
}
=20
=20
-//.. /*------------------------------------------------------------*/
-//.. /*--- ---*/
-//.. /*--- MMX INSTRUCTIONS ---*/
-//.. /*--- ---*/
-//.. /*------------------------------------------------------------*/
-//..=20
-//.. /* Effect of MMX insns on x87 FPU state (table 11-2 of=20
-//.. IA32 arch manual, volume 3):
-//..=20
-//.. Read from, or write to MMX register (viz, any insn except EMMS):
-//.. * All tags set to Valid (non-empty) -- FPTAGS[i] :=3D nonzero
-//.. * FP stack pointer set to zero
-//..=20
-//.. EMMS:
-//.. * All tags set to Invalid (empty) -- FPTAGS[i] :=3D zero
-//.. * FP stack pointer set to zero
-//.. */
-//..=20
-//.. static void do_MMX_preamble ( void )
-//.. {
-//.. Int i;
-//.. IRArray* descr =3D mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
-//.. IRExpr* zero =3D mkU32(0);
-//.. IRExpr* tag1 =3D mkU8(1);
-//.. put_ftop(zero);
-//.. for (i =3D 0; i < 8; i++)
-//.. stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
-//.. }
-//..=20
-//.. static void do_EMMS_preamble ( void )
-//.. {
-//.. Int i;
-//.. IRArray* descr =3D mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
-//.. IRExpr* zero =3D mkU32(0);
-//.. IRExpr* tag0 =3D mkU8(0);
-//.. put_ftop(zero);
-//.. for (i =3D 0; i < 8; i++)
-//.. stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
-//.. }
-//..=20
-//..=20
-//.. static IRExpr* getMMXReg ( UInt archreg )
-//.. {
-//.. vassert(archreg < 8);
-//.. return IRExpr_Get( OFFB_FPREGS + 8 * archreg, Ity_I64 );
-//.. }
-//..=20
-//..=20
-//.. static void putMMXReg ( UInt archreg, IRExpr* e )
-//.. {
-//.. vassert(archreg < 8);
-//.. vassert(typeOfIRExpr(irbb->tyenv,e) =3D=3D Ity_I64);
-//.. stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) );
-//.. }
-//..=20
-//..=20
-//.. /* Helper for non-shift MMX insns. Note this is incomplete in the
-//.. sense that it does not first call do_MMX_preamble() -- that is t=
he
-//.. responsibility of its caller. */
-//..=20
-//.. static=20
-//.. UInt dis_MMXop_regmem_to_reg ( UChar sorb,
-//.. UInt delta,
-//.. UChar opc,
-//.. Char* name,
-//.. Bool show_granularity )
-//.. {
-//.. HChar dis_buf[50];
-//.. UChar modrm =3D getUChar(delta);
-//.. Bool isReg =3D epartIsReg(modrm);
-//.. IRExpr* argL =3D NULL;
-//.. IRExpr* argR =3D NULL;
-//.. IRExpr* argG =3D NULL;
-//.. IRExpr* argE =3D NULL;
-//.. IRTemp res =3D newTemp(Ity_I64);
-//..=20
-//.. Bool invG =3D False;
-//.. IROp op =3D Iop_INVALID;
-//.. void* hAddr =3D NULL;
-//.. Char* hName =3D NULL;
-//.. Bool eLeft =3D False;
-//..=20
-//.. # define XXX(_name) do { hAddr =3D &_name; hName =3D #_name; } whi=
le (0)
-//..=20
-//.. switch (opc) {
-//.. /* Original MMX ones */
-//.. case 0xFC: op =3D Iop_Add8x8; break;
-//.. case 0xFD: op =3D Iop_Add16x4; break;
-//.. case 0xFE: op =3D Iop_Add32x2; break;
-//..=20
-//.. case 0xEC: op =3D Iop_QAdd8Sx8; break;
-//.. case 0xED: op =3D Iop_QAdd16Sx4; break;
-//..=20
-//.. case 0xDC: op =3D Iop_QAdd8Ux8; break;
-//.. case 0xDD: op =3D Iop_QAdd16Ux4; break;
-//..=20
-//.. case 0xF8: op =3D Iop_Sub8x8; break;
-//.. case 0xF9: op =3D Iop_Sub16x4; break;
-//.. case 0xFA: op =3D Iop_Sub32x2; break;
-//..=20
-//.. case 0xE8: op =3D Iop_QSub8Sx8; break;
-//.. case 0xE9: op =3D Iop_QSub16Sx4; break;
-//..=20
-//.. case 0xD8: op =3D Iop_QSub8Ux8; break;
-//.. case 0xD9: op =3D Iop_QSub16Ux4; break;
-//..=20
-//.. case 0xE5: op =3D Iop_MulHi16Sx4; break;
-//.. case 0xD5: op =3D Iop_Mul16x4; break;
-//.. case 0xF5: XXX(x86g_calculate_mmx_pmaddwd); break;
-//..=20
-//.. case 0x74: op =3D Iop_CmpEQ8x8; break;
-//.. case 0x75: op =3D Iop_CmpEQ16x4; break;
-//.. case 0x76: op =3D Iop_CmpEQ32x2; break;
-//..=20
-//.. case 0x64: op =3D Iop_CmpGT8Sx8; break;
-//.. case 0x65: op =3D Iop_CmpGT16Sx4; break;
-//.. case 0x66: op =3D Iop_CmpGT32Sx2; break;
-//..=20
-//.. case 0x6B: op =3D Iop_QNarrow32Sx2; eLeft =3D True; break;
-//.. case 0x63: op =3D Iop_QNarrow16Sx4; eLeft =3D True; break;
-//.. case 0x67: op =3D Iop_QNarrow16Ux4; eLeft =3D True; break;
-//..=20
-//.. case 0x68: op =3D Iop_InterleaveHI8x8; eLeft =3D True; break=
;
-//.. case 0x69: op =3D Iop_InterleaveHI16x4; eLeft =3D True; break=
;
-//.. case 0x6A: op =3D Iop_InterleaveHI32x2; eLeft =3D True; break=
;
-//..=20
-//.. case 0x60: op =3D Iop_InterleaveLO8x8; eLeft =3D True; break=
;
-//.. case 0x61: op =3D Iop_InterleaveLO16x4; eLeft =3D True; break=
;
-//.. case 0x62: op =3D Iop_InterleaveLO32x2; eLeft =3D True; break=
;
-//..=20
-//.. case 0xDB: op =3D Iop_And64; break;
-//.. case 0xDF: op =3D Iop_And64; invG =3D True; break;
-//.. case 0xEB: op =3D Iop_Or64; break;
-//.. case 0xEF: /* Possibly do better here if argL and argR are th=
e
-//.. same reg */
-//.. op =3D Iop_Xor64; break;
-//..=20
-//.. /* Introduced in SSE1 */
-//.. case 0xE0: op =3D Iop_Avg8Ux8; break;
-//.. case 0xE3: op =3D Iop_Avg16Ux4; break;
-//.. case 0xEE: op =3D Iop_Max16Sx4; break;
-//.. case 0xDE: op =3D Iop_Max8Ux8; break;
-//.. case 0xEA: op =3D Iop_Min16Sx4; break;
-//.. case 0xDA: op =3D Iop_Min8Ux8; break;
-//.. case 0xE4: op =3D Iop_MulHi16Ux4; break;
-//.. case 0xF6: XXX(x86g_calculate_mmx_psadbw); break;
-//..=20
-//.. /* Introduced in SSE2 */
-//.. case 0xD4: op =3D Iop_Add64; break;
-//.. case 0xFB: op =3D Iop_Sub64; break;
-//..=20
-//.. default:=20
-//.. vex_printf("\n0x%x\n", (Int)opc);
-//.. vpanic("dis_MMXop_regmem_to_reg");
-//.. }
-//..=20
-//.. # undef XXX
-//..=20
-//.. argG =3D getMMXReg(gregOfRM(modrm));
-//.. if (invG)
-//.. argG =3D unop(Iop_Not64, argG);
-//..=20
-//.. if (isReg) {
-//.. delta++;
-//.. argE =3D getMMXReg(eregOfRM(modrm));
-//.. } else {
-//.. Int len;
-//.. IRTemp addr =3D disAMode( &len, sorb, delta, dis_buf );
-//.. delta +=3D len;
-//.. argE =3D loadLE(Ity_I64, mkexpr(addr));
-//.. }
-//..=20
-//.. if (eLeft) {
-//.. argL =3D argE;
-//.. argR =3D argG;
-//.. } else {
-//.. argL =3D argG;
-//.. argR =3D argE;
-//.. }
-//..=20
-//.. if (op !=3D Iop_INVALID) {
-//.. vassert(hName =3D=3D NULL);
-//.. vassert(hAddr =3D=3D NULL);
-//.. assign(res, binop(op, argL, argR));
-//.. } else {
-//.. vassert(hName !=3D NULL);
-//.. vassert(hAddr !=3D NULL);
-//.. assign( res,=20
-//.. mkIRExprCCall(
-//.. Ity_I64,=20
-//.. 0/*regparms*/, hName, hAddr,
-//.. mkIRExprVec_2( argL, argR )
-//.. )=20
-//.. );
-//.. }
-//..=20
-//.. putMMXReg( gregOfRM(modrm), mkexpr(res) );
-//..=20
-//.. DIP("%s%s %s, %s\n",=20
-//.. name, show_granularity ? nameMMXGran(opc & 3) : (Char*)"",
-//.. ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
-//.. nameMMXReg(gregOfRM(modrm)) );
-//..=20
-//.. return delta;
-//.. }
-//..=20
-//..=20
-//.. /* Vector by scalar shift of G by the amount specified at the botto=
m
-//.. of E. This is a straight copy of dis_SSE_shiftG_byE. */
-//..=20
-//.. static UInt dis_MMX_shiftG_byE ( UChar sorb, ULong delta,=20
-//.. HChar* opname, IROp op )
-//.. {
-//.. HChar dis_buf[50];
-//.. Int alen, size;
-//.. IRTemp addr;
-//.. Bool shl, shr, sar;
-//.. UChar rm =3D getUChar(delta);
-//.. IRTemp g0 =3D newTemp(Ity_I64);
-//.. IRTemp g1 =3D newTemp(Ity_I64);
-//.. IRTemp amt =3D newTemp(Ity_I32);
-//.. IRTemp amt8 =3D newTemp(Ity_I8);
-//..=20
-//.. if (epartIsReg(rm)) {
-//.. assign( amt, unop(Iop_64to32, getMMXReg(eregOfRM(rm))) );
-//.. DIP("%s %s,%s\n", opname,
-//.. nameMMXReg(eregOfRM(rm)),
-//.. nameMMXReg(gregOfRM(rm)) );
-//.. delta++;
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. assign( amt, loadLE(Ity_I32, mkexpr(addr)) );
-//.. DIP("%s %s,%s\n", opname,
-//.. dis_buf,
-//.. nameMMXReg(gregOfRM(rm)) );
-//.. delta +=3D alen;
-//.. }
-//.. assign( g0, getMMXReg(gregOfRM(rm)) );
-//.. assign( amt8, unop(Iop_32to8, mkexpr(amt)) );
-//..=20
-//.. shl =3D shr =3D sar =3D False;
-//.. size =3D 0;
-//.. switch (op) {
-//.. case Iop_ShlN16x4: shl =3D True; size =3D 32; break;
-//.. case Iop_ShlN32x2: shl =3D True; size =3D 32; break;
-//.. case Iop_Shl64: shl =3D True; size =3D 64; break;
-//.. case Iop_ShrN16x4: shr =3D True; size =3D 16; break;
-//.. case Iop_ShrN32x2: shr =3D True; size =3D 32; break;
-//.. case Iop_Shr64: shr =3D True; size =3D 64; break;
-//.. case Iop_SarN16x4: sar =3D True; size =3D 16; break;
-//.. case Iop_SarN32x2: sar =3D True; size =3D 32; break;
-//.. default: vassert(0);
-//.. }
-//..=20
-//.. if (shl || shr) {
-//.. assign(=20
-//.. g1,
-//.. IRExpr_Mux0X(
-//.. unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size=
))),
-//.. mkU64(0),
-//.. binop(op, mkexpr(g0), mkexpr(amt8))
-//.. )
-//.. );
-//.. } else=20
-//.. if (sar) {
-//.. assign(=20
-//.. g1,
-//.. IRExpr_Mux0X(
-//.. unop(Iop_1Uto8,binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size=
))),
-//.. binop(op, mkexpr(g0), mkU8(size-1)),
-//.. binop(op, mkexpr(g0), mkexpr(amt8))
-//.. )
-//.. );
-//.. } else {
-//.. vassert(0);
-//.. }
-//..=20
-//.. putMMXReg( gregOfRM(rm), mkexpr(g1) );
-//.. return delta;
-//.. }
-//..=20
-//..=20
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- MMX INSTRUCTIONS ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/* Effect of MMX insns on x87 FPU state (table 11-2 of=20
+ IA32 arch manual, volume 3):
+
+ Read from, or write to MMX register (viz, any insn except EMMS):
+ * All tags set to Valid (non-empty) -- FPTAGS[i] :=3D nonzero
+ * FP stack pointer set to zero
+
+ EMMS:
+ * All tags set to Invalid (empty) -- FPTAGS[i] :=3D zero
+ * FP stack pointer set to zero
+*/
+
+static void do_MMX_preamble ( void )
+{
+ Int i;
+ IRArray* descr =3D mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero =3D mkU32(0);
+ IRExpr* tag1 =3D mkU8(1);
+ put_ftop(zero);
+ for (i =3D 0; i < 8; i++)
+ stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
+}
+
+static void do_EMMS_preamble ( void )
+{
+ Int i;
+ IRArray* descr =3D mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero =3D mkU32(0);
+ IRExpr* tag0 =3D mkU8(0);
+ put_ftop(zero);
+ for (i =3D 0; i < 8; i++)
+ stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
+}
+
+
+static IRExpr* getMMXReg ( UInt archreg )
+{
+ vassert(archreg < 8);
+ return IRExpr_Get( OFFB_FPREGS + 8 * archreg, Ity_I64 );
+}
+
+
+static void putMMXReg ( UInt archreg, IRExpr* e )
+{
+ vassert(archreg < 8);
+ vassert(typeOfIRExpr(irbb->tyenv,e) =3D=3D Ity_I64);
+ stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) );
+}
+
+
+/* Helper for non-shift MMX insns. Note this is incomplete in the
+ sense that it does not first call do_MMX_preamble() -- that is the
+ responsibility of its caller. */
+
+static=20
+ULong dis_MMXop_regmem_to_reg ( Prefix pfx,
+ ULong delta,
+ UChar opc,
+ Char* name,
+ Bool show_granularity )
+{
+ HChar dis_buf[50];
+ UChar modrm =3D getUChar(delta);
+ Bool isReg =3D epartIsReg(modrm);
+ IRExpr* argL =3D NULL;
+ IRExpr* argR =3D NULL;
+ IRExpr* argG =3D NULL;
+ IRExpr* argE =3D NULL;
+ IRTemp res =3D newTemp(Ity_I64);
+
+ Bool invG =3D False;
+ IROp op =3D Iop_INVALID;
+ void* hAddr =3D NULL;
+ Char* hName =3D NULL;
+ Bool eLeft =3D False;
+
+# define XXX(_name) do { hAddr =3D &_name; hName =3D #_name; } while (0=
)
+
+ switch (opc) {
+ /* Original MMX ones */
+ case 0xFC: op =3D Iop_Add8x8; break;
+ case 0xFD: op =3D Iop_Add16x4; break;
+ case 0xFE: op =3D Iop_Add32x2; break;
+
+ case 0xEC: op =3D Iop_QAdd8Sx8; break;
+ case 0xED: op =3D Iop_QAdd16Sx4; break;
+
+ case 0xDC: op =3D Iop_QAdd8Ux8; break;
+ case 0xDD: op =3D Iop_QAdd16Ux4; break;
+
+ case 0xF8: op =3D Iop_Sub8x8; break;
+ case 0xF9: op =3D Iop_Sub16x4; break;
+ case 0xFA: op =3D Iop_Sub32x2; break;
+
+ case 0xE8: op =3D Iop_QSub8Sx8; break;
+ case 0xE9: op =3D Iop_QSub16Sx4; break;
+
+ case 0xD8: op =3D Iop_QSub8Ux8; break;
+ case 0xD9: op =3D Iop_QSub16Ux4; break;
+
+ case 0xE5: op =3D Iop_MulHi16Sx4; break;
+ case 0xD5: op =3D Iop_Mul16x4; break;
+ case 0xF5: XXX(amd64g_calculate_mmx_pmaddwd); break;
+
+ case 0x74: op =3D Iop_CmpEQ8x8; break;
+ case 0x75: op =3D Iop_CmpEQ16x4; break;
+ case 0x76: op =3D Iop_CmpEQ32x2; break;
+
+ case 0x64: op =3D Iop_CmpGT8Sx8; break;
+ case 0x65: op =3D Iop_CmpGT16Sx4; break;
+ case 0x66: op =3D Iop_CmpGT32Sx2; break;
+
+ case 0x6B: op =3D Iop_QNarrow32Sx2; eLeft =3D True; break;
+ case 0x63: op =3D Iop_QNarrow16Sx4; eLeft =3D True; break;
+ case 0x67: op =3D Iop_QNarrow16Ux4; eLeft =3D True; break;
+
+ case 0x68: op =3D Iop_InterleaveHI8x8; eLeft =3D True; break;
+ case 0x69: op =3D Iop_InterleaveHI16x4; eLeft =3D True; break;
+ case 0x6A: op =3D Iop_InterleaveHI32x2; eLeft =3D True; break;
+
+ case 0x60: op =3D Iop_InterleaveLO8x8; eLeft =3D True; break;
+ case 0x61: op =3D Iop_InterleaveLO16x4; eLeft =3D True; break;
+ case 0x62: op =3D Iop_InterleaveLO32x2; eLeft =3D True; break;
+
+ case 0xDB: op =3D Iop_And64; break;
+ case 0xDF: op =3D Iop_And64; invG =3D True; break;
+ case 0xEB: op =3D Iop_Or64; break;
+ case 0xEF: /* Possibly do better here if argL and argR are the
+ same reg */
+ op =3D Iop_Xor64; break;
+
+ /* Introduced in SSE1 */
+ case 0xE0: op =3D Iop_Avg8Ux8; break;
+ case 0xE3: op =3D Iop_Avg16Ux4; break;
+ case 0xEE: op =3D Iop_Max16Sx4; break;
+ case 0xDE: op =3D Iop_Max8Ux8; break;
+ case 0xEA: op =3D Iop_Min16Sx4; break;
+ case 0xDA: op =3D Iop_Min8Ux8; break;
+ case 0xE4: op =3D Iop_MulHi16Ux4; break;
+ // case 0xF6: XXX(x86g_calculate_mmx_psadbw); break;
+
+ /* Introduced in SSE2 */
+ case 0xD4: op =3D Iop_Add64; break;
+ case 0xFB: op =3D Iop_Sub64; break;
+
+ default:=20
+ vex_printf("\n0x%x\n", (Int)opc);
+ vpanic("dis_MMXop_regmem_to_reg");
+ }
+
+# undef XXX
+
+ argG =3D getMMXReg(gregLO3ofRM(modrm));
+ if (invG)
+ argG =3D unop(Iop_Not64, argG);
+
+ if (isReg) {
+ delta++;
+ argE =3D getMMXReg(eregLO3ofRM(modrm));
+ } else {
+ Int len;
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ argE =3D loadLE(Ity_I64, mkexpr(addr));
+ }
+
+ if (eLeft) {
+ argL =3D argE;
+ argR =3D argG;
+ } else {
+ argL =3D argG;
+ argR =3D argE;
+ }
+
+ if (op !=3D Iop_INVALID) {
+ vassert(hName =3D=3D NULL);
+ vassert(hAddr =3D=3D NULL);
+ assign(res, binop(op, argL, argR));
+ } else {
+ vassert(hName !=3D NULL);
+ vassert(hAddr !=3D NULL);
+ assign( res,=20
+ mkIRExprCCall(
+ Ity_I64,=20
+ 0/*regparms*/, hName, hAddr,
+ mkIRExprVec_2( argL, argR )
+ )=20
+ );
+ }
+
+ putMMXReg( gregLO3ofRM(modrm), mkexpr(res) );
+
+ DIP("%s%s %s, %s\n",=20
+ name, show_granularity ? nameMMXGran(opc & 3) : "",
+ ( isReg ? nameMMXReg(eregLO3ofRM(modrm)) : dis_buf ),
+ nameMMXReg(gregLO3ofRM(modrm)) );
+
+ return delta;
+}
+
+
+/* Vector by scalar shift of G by the amount specified at the bottom
+ of E. This is a straight copy of dis_SSE_shiftG_byE. */
+
+static ULong dis_MMX_shiftG_byE ( Prefix pfx, ULong delta,=20
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen, size;
+ IRTemp addr;
+ Bool shl, shr, sar;
+ UChar rm =3D getUChar(delta);
+ IRTemp g0 =3D newTemp(Ity_I64);
+ IRTemp g1 =3D newTemp(Ity_I64);
+ IRTemp amt =3D newTemp(Ity_I64);
+ IRTemp amt8 =3D newTemp(Ity_I8);
+
+ if (epartIsReg(rm)) {
+ assign( amt, getMMXReg(eregLO3ofRM(rm)) );
+ DIP("%s %s,%s\n", opname,
+ nameMMXReg(eregLO3ofRM(rm)),
+ nameMMXReg(gregLO3ofRM(rm)) );
+ delta++;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta, dis_buf, 0 );
+ assign( amt, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("%s %s,%s\n", opname,
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(rm)) );
+ delta +=3D alen;
+ }
+ assign( g0, getMMXReg(gregLO3ofRM(rm)) );
+ assign( amt8, unop(Iop_64to8, mkexpr(amt)) );
+
+ shl =3D shr =3D sar =3D False;
+ size =3D 0;
+ switch (op) {
+ case Iop_ShlN16x4: shl =3D True; size =3D 32; break;
+ case Iop_ShlN32x2: shl =3D True; size =3D 32; break;
+ case Iop_Shl64: shl =3D True; size =3D 64; break;
+ case Iop_ShrN16x4: shr =3D True; size =3D 16; break;
+ case Iop_ShrN32x2: shr =3D True; size =3D 32; break;
+ case Iop_Shr64: shr =3D True; size =3D 64; break;
+ case Iop_SarN16x4: sar =3D True; size =3D 16; break;
+ case Iop_SarN32x2: sar =3D True; size =3D 32; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign(=20
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,binop(Iop_CmpLT64U,mkexpr(amt),mkU64(size))),
+ mkU64(0),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else=20
+ if (sar) {
+ assign(=20
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,binop(Iop_CmpLT64U,mkexpr(amt),mkU64(size))),
+ binop(op, mkexpr(g0), mkU8(size-1)),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else {
+ vassert(0);
+ }
+
+ putMMXReg( gregLO3ofRM(rm), mkexpr(g1) );
+ return delta;
+}
+
+
//.. /* Vector by scalar shift of E by an immediate byte. This is a
//.. straight copy of dis_SSE_shiftE_imm. */
//..=20
@@ -6126,24 +6139,24 @@
//.. putMMXReg( eregOfRM(rm), mkexpr(e1) );
//.. return delta;
//.. }
-//..=20
-//..=20
-//.. /* Completely handle all MMX instructions except emms. */
-//..=20
-//.. static
-//.. UInt dis_MMX ( Bool* decode_ok, UChar sorb, Int sz, ULong delta )
-//.. {
-//.. Int len;
-//.. UChar modrm;
-//.. HChar dis_buf[50];
-//.. UChar opc =3D getUChar(delta);
-//.. delta++;
-//..=20
-//.. /* dis_MMX handles all insns except emms. */
-//.. do_MMX_preamble();
-//..=20
-//.. switch (opc) {
-//..=20
+
+
+/* Completely handle all MMX instructions except emms. */
+
+static
+ULong dis_MMX ( Bool* decode_ok, Prefix pfx, Int sz, ULong delta )
+{
+ Int len;
+ UChar modrm;
+ HChar dis_buf[50];
+ UChar opc =3D getUChar(delta);
+ delta++;
+
+ /* dis_MMX handles all insns except emms. */
+ do_MMX_preamble();
+
+ switch (opc) {
+
//.. case 0x6E:=20
//.. /* MOVD (src)ireg-or-mem (E), (dst)mmxreg (G)*/
//.. if (sz !=3D 4)=20
@@ -6188,201 +6201,200 @@
//.. DIP("movd %s, %s\n", nameMMXReg(gregOfRM(modrm)), dis_b=
uf);
//.. }
//.. break;
+
+ case 0x6F:
+ /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putMMXReg( gregLO3ofRM(modrm), getMMXReg(eregLO3ofRM(modrm))=
);
+ DIP("movq %s, %s\n",=20
+ nameMMXReg(eregLO3ofRM(modrm)),=20
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ putMMXReg( gregLO3ofRM(modrm), loadLE(Ity_I64, mkexpr(addr))=
);
+ DIP("movq %s, %s\n",=20
+ dis_buf, nameMMXReg(gregLO3ofRM(modrm)));
+ }
+ break;
+
+ case 0x7F:
+ /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ modrm =3D getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* Fall through. The assembler doesn't appear to generate
+ these. */
+ goto mmx_decode_failure;
+ } else {
+ IRTemp addr =3D disAMode( &len, pfx, delta, dis_buf, 0 );
+ delta +=3D len;
+ storeLE( mkexpr(addr), getMMXReg(gregLO3ofRM(modrm)) );
+ DIP("mov(nt)q %s, %s\n",=20
+ nameMMXReg(gregLO3ofRM(modrm)), dis_buf);
+ }
+ break;
+
+ case 0xFC:=20
+ case 0xFD:=20
+ case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "padd", Tr=
ue );
+ break;
+
+ case 0xEC:=20
+ case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "padds", T=
rue );
+ break;
+
+ case 0xDC:=20
+ case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "paddus", =
True );
+ break;
+
+ case 0xF8:=20
+ case 0xF9:=20
+ case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "psub", Tr=
ue );
+ break;
+
+ case 0xE8:=20
+ case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "psubs", T=
rue );
+ break;
+
+ case 0xD8:=20
+ case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "psubus", =
True );
+ break;
+
+ case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pmulhw", =
False );
+ break;
+
+ case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pmullw", =
False );
+ break;
+
+ case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */
+ vassert(sz =3D=3D 4);
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pmaddwd",=
False );
+ break;
+
+ case 0x74:=20
+ case 0x75:=20
+ case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pcmpeq", =
True );
+ break;
+
+ case 0x64:=20
+ case 0x65:=20
+ case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pcmpgt", =
True );
+ break;
+
+ case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "packssdw"=
, False );
+ break;
+
+ case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "packsswb"=
, False );
+ break;
+
+ case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "packuswb"=
, False );
+ break;
+
+ case 0x68:=20
+ case 0x69:=20
+ case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "punpckh",=
True );
+ break;
+
+ case 0x60:=20
+ case 0x61:=20
+ case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "punpckl",=
True );
+ break;
+
+ case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pand", Fa=
lse );
+ break;
+
+ case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pandn", F=
alse );
+ break;
+
+ case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "por", Fal=
se );
+ break;
+
+ case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */
+ if (sz !=3D 4)=20
+ goto mmx_decode_failure;
+ delta =3D dis_MMXop_regmem_to_reg ( pfx, delta, opc, "pxor", Fa=
lse );
+ break;=20
+
+# define SHIFT_BY_REG(_name,_op) \
+ delta =3D dis_MMX_shiftG_byE(pfx, delta, _name, _op); \
+ break;
+
+ /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xF1: SHIFT_BY_REG("psllw", Iop_ShlN16x4);
+ case 0xF2: SHIFT_BY_REG("pslld", Iop_ShlN32x2);
+ case 0xF3: SHIFT_BY_REG("psllq", Iop_Shl64);
+
+ /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xD1: SHIFT_BY_REG("psrlw", Iop_ShrN16x4);
+ case 0xD2: SHIFT_BY_REG("psrld", Iop_ShrN32x2);
+ case 0xD3: SHIFT_BY_REG("psrlq", Iop_Shr64);
+
+ /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xE1: SHIFT_BY_REG("psraw", Iop_SarN16x4);
+ case 0xE2: SHIFT_BY_REG("psrad", Iop_SarN32x2);
+
+# undef SHIFT_BY_REG
//..=20
-//.. case 0x6F:
-//.. /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. modrm =3D getUChar(delta);
-//.. if (epartIsReg(modrm)) {
-//.. delta++;
-//.. putMMXReg( gregOfRM(modrm), getMMXReg(eregOfRM(modrm)) =
);
-//.. DIP("movq %s, %s\n",=20
-//.. nameMMXReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(mo=
drm)));
-//.. } else {
-//.. IRTemp addr =3D disAMode( &len, sorb, delta, dis_buf );
-//.. delta +=3D len;
-//.. putMMXReg( gregOfRM(modrm), loadLE(Ity_I64, mkexpr(addr=
)) );
-//.. DIP("movq %s, %s\n",=20
-//.. dis_buf, nameMMXReg(gregOfRM(modrm)));
-//.. }
-//.. break;
-//..=20
-//.. case 0x7F:
-//.. /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. modrm =3D getUChar(delta);
-//.. if (epartIsReg(modrm)) {
-//.. /* Fall through. The assembler doesn't appear to gener=
ate
-//.. these. */
-//.. goto mmx_decode_failure;
-//.. } else {
-//.. IRTemp addr =3D disAMode( &len, sorb, delta, dis_buf );
-//.. delta +=3D len;
-//.. storeLE( mkexpr(addr), getMMXReg(gregOfRM(modrm)) );
-//.. DIP("mov(nt)q %s, %s\n",=20
-//.. nameMMXReg(gregOfRM(modrm)), dis_buf);
-//.. }
-//.. break;
-//..=20
-//.. case 0xFC:=20
-//.. case 0xFD:=20
-//.. case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pad=
d", True );
-//.. break;
-//..=20
-//.. case 0xEC:=20
-//.. case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pad=
ds", True );
-//.. break;
-//..=20
-//.. case 0xDC:=20
-//.. case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pad=
dus", True );
-//.. break;
-//..=20
-//.. case 0xF8:=20
-//.. case 0xF9:=20
-//.. case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psu=
b", True );
-//.. break;
-//..=20
-//.. case 0xE8:=20
-//.. case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psu=
bs", True );
-//.. break;
-//..=20
-//.. case 0xD8:=20
-//.. case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psu=
bus", True );
-//.. break;
-//..=20
-//.. case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmu=
lhw", False );
-//.. break;
-//..=20
-//.. case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmu=
llw", False );
-//.. break;
-//..=20
-//.. case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */
-//.. vassert(sz =3D=3D 4);
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pma=
ddwd", False );
-//.. break;
-//..=20
-//.. case 0x74:=20
-//.. case 0x75:=20
-//.. case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcm=
peq", True );
-//.. break;
-//..=20
-//.. case 0x64:=20
-//.. case 0x65:=20
-//.. case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcm=
pgt", True );
-//.. break;
-//..=20
-//.. case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pac=
kssdw", False );
-//.. break;
-//..=20
-//.. case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pac=
ksswb", False );
-//.. break;
-//..=20
-//.. case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pac=
kuswb", False );
-//.. break;
-//..=20
-//.. case 0x68:=20
-//.. case 0x69:=20
-//.. case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pun=
pckh", True );
-//.. break;
-//..=20
-//.. case 0x60:=20
-//.. case 0x61:=20
-//.. case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pun=
pckl", True );
-//.. break;
-//..=20
-//.. case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pan=
d", False );
-//.. break;
-//..=20
-//.. case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pan=
dn", False );
-//.. break;
-//..=20
-//.. case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "por=
", False );
-//.. break;
-//..=20
-//.. case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */
-//.. if (sz !=3D 4)=20
-//.. goto mmx_decode_failure;
-//.. delta =3D dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pxo=
r", False );
-//.. break;=20
-//..=20
-#if 0 /* stop gcc multi-line comment warning */
-/.. # define SHIFT_BY_REG(_name,_op) =
\
-/.. delta =3D dis_MMX_shiftG_byE(sorb, delta, _name, _op=
); \
-/.. break;
-#endif /* stop gcc multi-line comment warning */
-//..=20
-//.. /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xF1: SHIFT_BY_REG("psllw", Iop_ShlN16x4);
-//.. case 0xF2: SHIFT_BY_REG("pslld", Iop_ShlN32x2);
-//.. case 0xF3: SHIFT_BY_REG("psllq", Iop_Shl64);
-//..=20
-//.. /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xD1: SHIFT_BY_REG("psrlw", Iop_ShrN16x4);
-//.. case 0xD2: SHIFT_BY_REG("psrld", Iop_ShrN32x2);
-//.. case 0xD3: SHIFT_BY_REG("psrlq", Iop_Shr64);
-//..=20
-//.. /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xE1: SHIFT_BY_REG("psraw", Iop_SarN16x4);
-//.. case 0xE2: SHIFT_BY_REG("psrad", Iop_SarN32x2);
-//..=20
-//.. # undef SHIFT_BY_REG
-//..=20
//.. case 0x71:=20
//.. case 0x72:=20
//.. case 0x73: {
@@ -6429,20 +6441,20 @@
//.. # undef SHIFT_BY_IMM
//.. break;
//.. }
-//..=20
-//.. /* --- MMX decode failure --- */
-//.. default:
-//.. mmx_decode_failure:
-//.. *decode_ok =3D False;
-//.. return delta; /* ignored */
-//..=20
-//.. }
-//..=20
-//.. *decode_ok =3D True;
-//.. return delta;
-//.. }
-//..=20
-//..=20
+
+ /* --- MMX decode failure --- */
+ default:
+ mmx_decode_failure:
+ *decode_ok =3D False;
+ return delta; /* ignored */
+
+ }
+
+ *decode_ok =3D True;
+ return delta;
+}
+
+
//.. /*------------------------------------------------------------*/
//.. /*--- More misc arithmetic and other obscure insns. ---*/
//.. /*------------------------------------------------------------*/
@@ -10499,16 +10511,17 @@
//.. "paddd", Iop_Add32x4, False );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
-//.. /* 0F D4 =3D PADDQ -- add 64x1 */
-//.. if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD4) {
-//.. do_MMX_preamble();
-//.. delta =3D dis_MMXop_regmem_to_reg (=20
-//.. sorb, delta+2, insn[1], "paddq", False );
-//.. goto decode_success;
-//.. }
=20
+ /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
+ /* 0F D4 =3D PADDQ -- add 64x1 */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD4) {
+ do_MMX_preamble();
+ delta =3D dis_MMXop_regmem_to_reg (=20
+ pfx, delta+2, insn[1], "paddq", False );
+ goto decode_success;
+ }
+
/* 66 0F D4 =3D PADDQ */
if (have66noF2noF3(pfx) && sz =3D=3D 2=20
&& insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD4) {
@@ -11201,16 +11214,17 @@
//.. "psubd", Iop_Sub32x4, False );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
-//.. /* 0F FB =3D PSUBQ -- sub 64x1 */
-//.. if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFB) {
-//.. do_MMX_preamble();
-//.. delta =3D dis_MMXop_regmem_to_reg (=20
-//.. sorb, delta+2, insn[1], "psubq", False );
-//.. goto decode_success;
-//.. }
=20
+ /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
+ /* 0F FB =3D PSUBQ -- sub 64x1 */
+ if (haveNo66noF2noF3(pfx) && sz =3D=3D 4=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFB) {
+ do_MMX_preamble();
+ delta =3D dis_MMXop_regmem_to_reg (=20
+ pfx, delta+2, insn[1], "psubq", False );
+ goto decode_success;
+ }
+
/* 66 0F FB =3D PSUBQ */
if (have66noF2noF3(pfx) && sz =3D=3D 2=20
&& insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFB) {
@@ -11583,46 +11597,6 @@
goto decode_failure;
}
=20
-//.. /* ------------------------ INC & DEC ------------------ */
-//..=20
-//.. case 0x40: /* INC eAX */
-//.. case 0x41: /* INC eCX */
-//.. case 0x42: /* INC eDX */
-//.. case 0x43: /* INC eBX */
-//.. case 0x44: /* INC eSP */
-//.. case 0x45: /* INC eBP */
-//.. case 0x46: /* INC eSI */
-//.. case 0x47: /* INC eDI */
-//.. vassert(sz =3D=3D 2 || sz =3D=3D 4);
-//.. ty =3D szToITy(sz);
-//.. t1 =3D newTemp(ty);
-//.. assign( t1, binop(mkSizedOp(ty,Iop_Add8),
-//.. getIReg(sz, (UInt)(opc - 0x40)),
-//.. mkU(ty,1)) );
-//.. setFlags_INC_DEC( True, t1, ty );
-//.. putIReg(sz, (UInt)(opc - 0x40), mkexpr(t1));
-//.. DIP("inc%c %s\n", nameISize(sz), nameIReg(sz,opc-0x40));
-//.. break;
-//..=20
-//.. case 0x48: /* DEC eAX */
-//.. case 0x49: /* DEC eCX */
-//.. case 0x4A: /* DEC eDX */
-//.. case 0x4B: /* DEC eBX */
-//.. case 0x4C: /* DEC eSP */
-//.. case 0x4D: /* DEC eBP */
-//.. case 0x4E: /* DEC eSI */
-//.. case 0x4F: /* DEC eDI */
-//.. vassert(sz =3D=3D 2 || sz =3D=3D 4);
-//.. ty =3D szToITy(sz);
-//.. t1 =3D newTemp(ty);
-//.. assign( t1, binop(mkSizedOp(ty,Iop_Sub8),
-//.. getIReg(sz, (UInt)(opc - 0x48)),
-//.. mkU(ty,1)) );
-//.. setFlags_INC_DEC( False, t1, ty );
-//.. putIReg(sz, (UInt)(opc - 0x48), mkexpr(t1));
-//.. DIP("dec%c %s\n", nameISize(sz), nameIReg(sz,opc-0x48));
-//.. break;
-
/* ------------------------ Jcond, byte offset --------- */
=20
case 0xEB: /* Jb (jump, byte offset) */
@@ -11813,7 +11787,7 @@
//.. sorbTxt(sorb), d32);
//.. break;
=20
-/* XXXX be careful here with moves to AH/BH/CH/DH */
+ /* XXXX be careful here with moves to AH/BH/CH/DH */
case 0xB0: /* MOV imm,AL */
case 0xB1: /* MOV imm,CL */
case 0xB2: /* MOV imm,DL */
@@ -13301,101 +13275,103 @@
break;
}
=20
-//.. /* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- MMXery =3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D-=3D */
-//..=20
+ /* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- MMXery =3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
+
//.. case 0x71:=20
//.. case 0x72:=20
//.. case 0x73: /* PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
//..=20
//.. case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */
//.. case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */
-//.. case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
-//.. case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xFC:=20
-//.. case 0xFD:=20
-//.. case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xEC:=20
-//.. case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xDC:
-//.. case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xF8:=20
-//.. case 0xF9:=20
-//.. case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xE8:=20
-//.. case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xD8:=20
-//.. case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0x74:=20
-//.. case 0x75:=20
-//.. case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0x64:=20
-//.. case 0x65:=20
-//.. case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0x68:=20
-//.. case 0x69:=20
-//.. case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0x60:=20
-//.. case 0x61:=20
-//.. case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */
-//..=20
-//.. case 0xF1: /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xF2:=20
-//.. case 0xF3:=20
-//..=20
-//.. case 0xD1: /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xD2:=20
-//.. case 0xD3:=20
-//..=20
-//.. case 0xE1: /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
-//.. case 0xE2:=20
-//.. {
-//.. ULong delta0 =3D delta-1;
-//.. Bool decode_OK =3D False;
-//..=20
-//.. /* If sz=3D=3D2 this is SSE, and we assume sse idec has
-//.. already spotted those cases by now. */
-//.. if (sz !=3D 4)
-//.. goto decode_failure;
-//..=20
-//.. delta =3D dis_MMX ( &decode_OK, sorb, sz, delta-1 );
-//.. if (!decode_OK) {
-//.. delta =3D delta0;
-//.. goto decode_failure;
-//.. }
-//.. break;
-//.. }
-//..=20
-//.. case 0x77: /* EMMS */
-//.. if (sz !=3D 4)
-//.. goto decode_failure;
-//.. do_EMMS_preamble();
-//.. DIP("emms\n");
-//.. break;
+ case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
+ case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
=20
+ case 0xFC:=20
+ case 0xFD:=20
+ case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xEC:=20
+ case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xDC:
+ case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xF8:=20
+ case 0xF9:=20
+ case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xE8:=20
+ case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xD8:=20
+ case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0x74:=20
+ case 0x75:=20
+ case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0x64:=20
+ case 0x65:=20
+ case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0x68:=20
+ case 0x69:=20
+ case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0x60:=20
+ case 0x61:=20
+ case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */
+
+ case 0xF1: /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xF2:=20
+ case 0xF3:=20
+
+ case 0xD1: /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xD2:=20
+ case 0xD3:=20
+
+ case 0xE1: /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
+ case 0xE2:=20
+ {
+ ULong delta0 =3D delta-1;
+ Bool decode_OK =3D False;
+
+ /* If sz=3D=3D2 this is SSE, and we assume sse idec has
+ already spotted those cases by now. */
+ if (sz !=3D 4)
+ goto decode_failure;
+ if (have66orF2orF3(pfx))
+ goto decode_failure;
+
+ delta =3D dis_MMX ( &decode_OK, pfx, sz, delta-1 );
+ if (!decode_OK) {
+ delta =3D delta0;
+ goto decode_failure;
+ }
+ break;
+ }
+
+ case 0x77: /* EMMS */
+ if (sz !=3D 4)
+ goto decode_failure;
+ do_EMMS_preamble();
+ DIP("emms\n");
+ break;
+
/* =3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- unimp2 =3D-=3D-=3D-=3D-=3D=
-=3D-=3D-=3D-=3D-=3D-=3D */
=20
default:
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-09 12:16:33 UTC (rev 1172)
+++ trunk/priv/host-amd64/isel.c 2005-05-09 17:52:56 UTC (rev 1173)
@@ -41,7 +41,7 @@
#include "main/vex_util.h"
#include "main/vex_globals.h"
#include "host-generic/h_generic_regs.h"
-//.. #include "host-generic/h_generic_simd64.h"
+#include "host-generic/h_generic_simd64.h"
#include "host-amd64/hdefs.h"
=20
=20
@@ -764,6 +764,7 @@
/* DO NOT CALL THIS DIRECTLY ! */
static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
+ Bool second_is_UInt;
MatchInfo mi;
DECLARE_PATTERN(p_8Uto64);
DECLARE_PATTERN(p_1Uto8_64to1);
@@ -806,6 +807,8 @@
case Iex_Binop: {
AMD64AluOp aluOp;
AMD64ShiftOp shOp;
+ HWord fn =3D 0; /* helper fn for most SIMD64 stuff */
+
//..=20
//.. /* Pattern: Sub32(0,x) */
//.. if (e->Iex.Binop.op =3D=3D Iop_Sub32 && isZero32(e->Iex.Binop=
.arg1)) {
@@ -919,6 +922,141 @@
return dst;
}
=20
+ /* Deal with 64-bit SIMD binary ops */
+ second_is_UInt =3D False;
+ switch (e->Iex.Binop.op) {
+ case Iop_Add8x8:
+ fn =3D (HWord)h_generic_calc_Add8x8; break;
+ case Iop_Add16x4:
+ fn =3D (HWord)h_generic_calc_Add16x4; break;
+ case Iop_Add32x2:
+ fn =3D (HWord)h_generic_calc_Add32x2; break;
+//..=20
+//.. case Iop_Avg8Ux8:
+//.. fn =3D (HWord)h_generic_calc_Avg8Ux8; break;
+//.. case Iop_Avg16Ux4:
+//.. fn =3D (HWord)h_generic_calc_Avg16Ux4; break;
+
+ case Iop_CmpEQ8x8:
+ fn =3D (HWord)h_generic_calc_CmpEQ8x8; break;
+ case Iop_CmpEQ16x4:
+ fn =3D (HWord)h_generic_calc_CmpEQ16x4; break;
+ case Iop_CmpEQ32x2:
+ fn =3D (HWord)h_generic_calc_CmpEQ32x2; break;
+
+ case Iop_CmpGT8Sx8:
+ fn =3D (HWord)h_generic_calc_CmpGT8Sx8; break;
+ case Iop_CmpGT16Sx4:
+ fn =3D (HWord)h_generic_calc_CmpGT16Sx4; break;
+ case Iop_CmpGT32Sx2:
+ fn =3D (HWord)h_generic_calc_CmpGT32Sx2; break;
+
+ case Iop_InterleaveHI8x8:
+ fn =3D (HWord)h_generic_calc_InterleaveHI8x8; break;
+ case Iop_InterleaveLO8x8:
+ fn =3D (HWord)h_generic_calc_InterleaveLO8x8; break;
+ case Iop_InterleaveHI16x4:
+ fn =3D (HWord)h_generic_calc_InterleaveHI16x4; break;
+ case Iop_InterleaveLO16x4:
+ fn =3D (HWord)h_generic_calc_InterleaveLO16x4; break;
+ case Iop_InterleaveHI32x2:
+ fn =3D (HWord)h_generic_calc_InterleaveHI32x2; break;
+ case Iop_InterleaveLO32x2:
+ fn =3D (HWord)h_generic_calc_InterleaveLO32x2; break;
+
+//.. case Iop_Max8Ux8:
+//.. fn =3D (HWord)h_generic_calc_Max8Ux8; break;
+//.. case Iop_Max16Sx4:
+//.. fn =3D (HWord)h_generic_calc_Max16Sx4; break;
+//.. case Iop_Min8Ux8:
+//.. fn =3D (HWord)h_generic_calc_Min8Ux8; break;
+//.. case Iop_Min16Sx4:
+//.. fn =3D (HWord)h_generic_calc_Min16Sx4; break;
+
+ case Iop_Mul16x4:
+ fn =3D (HWord)h_generic_calc_Mul16x4; break;
+ case Iop_MulHi16Sx4:
+ fn =3D (HWord)h_generic_calc_MulHi16Sx4; break;
+//.. case Iop_MulHi16Ux4:
+//.. fn =3D (HWord)h_generic_calc_MulHi16Ux4; break;
+//..=20
+ case Iop_QAdd8Sx8:
+ fn =3D (HWord)h_generic_calc_QAdd8Sx8; break;
+ case Iop_QAdd16Sx4:
+ fn =3D (HWord)h_generic_calc_QAdd16Sx4; break;
+ case Iop_QAdd8Ux8:
+ fn =3D (HWord)h_generic_calc_QAdd8Ux8; break;
+ case Iop_QAdd16Ux4:
+ fn =3D (HWord)h_generic_calc_QAdd16Ux4; break;
+
+ case Iop_QNarrow32Sx2:
+ fn =3D (HWord)h_generic_calc_QNarrow32Sx2; break;
+ case Iop_QNarrow16Sx4:
+ fn =3D (HWord)h_generic_calc_QNarrow16Sx4; break;
+ case Iop_QNarrow16Ux4:
+ fn =3D (HWord)h_generic_calc_QNarrow16Ux4; break;
+
+ case Iop_QSub8Sx8:
+ fn =3D (HWord)h_generic_calc_QSub8Sx8; break;
+ case Iop_QSub16Sx4:
+ fn =3D (HWord)h_generic_calc_QSub16Sx4; break;
+ case Iop_QSub8Ux8:
+ fn =3D (HWord)h_generic_calc_QSub8Ux8; break;
+ case Iop_QSub16Ux4:
+ fn =3D (HWord)h_generic_calc_QSub16Ux4; break;
+
+ case Iop_Sub8x8:
+ fn =3D (HWord)h_generic_calc_Sub8x8; break;
+ case Iop_Sub16x4:
+ fn =3D (HWord)h_generic_calc_Sub16x4; break;
+ case Iop_Sub32x2:
+ fn =3D (HWord)h_generic_calc_Sub32x2; break;
+
+ case Iop_ShlN32x2:
+ fn =3D (HWord)h_generic_calc_ShlN32x2;=20
+ second_is_UInt =3D True;
+ break;
+ case Iop_ShlN16x4:
+ fn =3D (HWord)h_generic_calc_ShlN16x4;
+ second_is_UInt =3D True;
+ break;
+ case Iop_ShrN32x2:
+ fn =3D (HWord)h_generic_calc_ShrN32x2;=20
+ second_is_UInt =3D True;=20
+ break;
+ case Iop_ShrN16x4:
+ fn =3D (HWord)h_generic_calc_ShrN16x4;
+ second_is_UInt =3D True;=20
+ break;
+ case Iop_SarN32x2:
+ fn =3D (HWord)h_generic_calc_SarN32x2;
+ second_is_UInt =3D True;=20
+ break;
+ case Iop_SarN16x4:
+ fn =3D (HWord)h_generic_calc_SarN16x4;
+ second_is_UInt =3D True;=20
+ break;
+
+ default:
+ fn =3D (HWord)0; break;
+ }
+ if (fn !=3D (HWord)0) {
+ /* Note: the following assumes all helpers are of signature=20
+ ULong fn ( ULong, ULong ), and they are
+ not marked as regparm functions.=20
+ */
+ HReg dst =3D newVRegI(env);
+ HReg argL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg argR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ if (second_is_UInt)
+ addInstr(env, AMD64Instr_MovZLQ(argR, argR));
+ addInstr(env, mk_iMOVsd_RR(argL, hregAMD64_RDI()) );
+ addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
+ addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 2 ));
+ addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
+ return dst;
+ }
+
/* Handle misc other ops. */
=20
if (e->Iex.Binop.op =3D=3D Iop_DivModS64to32
@@ -2320,152 +2458,6 @@
//.. return;
//.. }
//..=20
-//.. case Iop_Add8x8:
-//.. fn =3D (HWord)h_generic_calc_Add8x8; goto binnish;
-//.. case Iop_Add16x4:
-//.. fn =3D (HWord)h_generic_calc_Add16x4; goto binnish;
-//.. case Iop_Add32x2:
-//.. fn =3D (HWord)h_generic_calc_Add32x2; goto binnish;
-//..=20
-//.. case Iop_Avg8Ux8:
-//.. fn =3D (HWord)h_generic_calc_Avg8Ux8; goto binnish;
-//.. case Iop_Avg16Ux4:
-//.. fn =3D (HWord)h_generic_calc_Avg16Ux4; goto binnish;
-//..=20
-//.. case Iop_CmpEQ8x8:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ8x8; goto binnish;
-//.. case Iop_CmpEQ16x4:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ16x4; goto binnish;
-//.. case Iop_CmpEQ32x2:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ32x2; goto binnish;
-//..=20
-//.. case Iop_CmpGT8Sx8:
-//.. fn =3D (HWord)h_generic_calc_CmpGT8Sx8; goto binnish;
-//.. case Iop_CmpGT16Sx4:
-//.. fn =3D (HWord)h_generic_calc_CmpGT16Sx4; goto binnish;
-//.. case Iop_CmpGT32Sx2:
-//.. fn =3D (HWord)h_generic_calc_CmpGT32Sx2; goto binnish;
-//..=20
-//.. case Iop_InterleaveHI8x8:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI8x8; goto binn=
ish;
-//.. case Iop_InterleaveLO8x8:
-//.. fn =3D (HWord)h_generic_calc_InterleaveLO8x8; goto binn=
ish;
-//.. case Iop_InterleaveHI16x4:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI16x4; goto bin=
nish;
-//.. case Iop_InterleaveLO16x4:
-//.. fn =3D (HWord)h_generic_calc_InterleaveLO16x4; goto bin=
nish;
-//.. case Iop_InterleaveHI32x2:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI32x2; goto bin=
nish;
-//.. case Iop_InterleaveLO32x2:
-//.. fn =3D (HWord)h_generi...
[truncated message content] |
|
From: Qin Z.
|
Quoting Nicholas Nethercote <nj...@cs...>: > On Mon, 9 May 2005, Qin Zhao wrote: > > > I am developing a realtime information flow tracing tool using > > DynamoRIO, which is similar to MemCheck, but more care about the speed. > > Can you give any more detail about how it will work, what it will do? > Will every value (in registers and memory) be shadowed by some kind of > metavalue? > > I'd be really interested to hear if you can get a Memcheck-like tool > working well in DynamoRIO. > > N > It is similar to MemCheck, each byte of memory and register has one byte shadow memory, and intially set as clean. User can specify some part of data or data reading from file or network as tainted, the corresponding shadow memory is marked as tainted. Then during the execution, when the data is propagated around, the instrumented code propagates data's taint status in shaodw memory. We can perform some check at some point to see if the used data are tainted. For example, we can check the data used for indirect branch's target address, if it is tainted, it is very possible a buffer overflow attack happens. From my understanding, the basic tech is similar to MemCheck. Tracing and checking. |
|
From: Nicholas N. <nj...@cs...> - 2005-05-09 16:32:52
|
On Mon, 9 May 2005, Qin Zhao wrote: > I am developing a realtime information flow tracing tool using > DynamoRIO, which is similar to MemCheck, but more care about the speed. Can you give any more detail about how it will work, what it will do? Will every value (in registers and memory) be shadowed by some kind of metavalue? I'd be really interested to hear if you can get a Memcheck-like tool working well in DynamoRIO. N |
|
From: Bryan O'S. <bo...@se...> - 2005-05-09 15:51:59
|
On Mon, 2005-05-09 at 11:38 -0400, Qin Zhao wrote: > One weak point is that DynamoRIO source code is not public available, This would be the reason: http://www.determina.com/ <b |
|
From: Qin Z.
|
I have worked on DynamoRIO for a while. I thinks it is really fast, and more suitable for realtime application. Different from valgrind and PIN, it provides an IR which is very close to x86 instruction set, complex but fast. I am developing a realtime information flow tracing tool using DynamoRIO, which is similar to MemCheck, but more care about the speed. One weak point is that DynamoRIO source code is not public available, Quoting Nicholas Nethercote <nj...@cs...>: > Hi, > > I don't think I've mentioned this before: > > www.burningcutlery.com/derek/phd.html > > has Derek Bruening's PhD dissertation about DynamoRIO, which is a > Valgrind-like system for dynamic binary instrumentation. What's notable > is that it is really fast, ie. typical slowdowns are in the 0--50% range. > I believe it's less suitable for doing heavyweight instrumentation than > Valgrind; eg. I don't think you could write Memcheck easily in it. It's > also x86-specific, but it impressively supports both Windows and Linux. > The dissertation has lots of good stuff about getting good performance. > > Also, there's a recent paper about another tool called Pin > > http://rogue.colorado.edu/Pin/docs/papers/pin-pldi05.pdf > > Pin works on multiple platforms, is again pretty fast, but again doesn't > seem suitable for heavyweight instrumentation. They give some performance > comparisons against Valgrind and DynamoRIO which are interesting. > Valgrind doesn't fare very well, but it's really an apples-to-oranges > comparison since the two comparisons involve no instrumentation and > minimal instrumentation. > > Both are good reading, I believe these two systems are the strongest > competitors Valgrind has of various dynamic binary instrumentation systems > out there. > > N > > > ------------------------------------------------------- > This SF.Net email is sponsored by: NEC IT Guy Games. > Get your fingers limbered up and give it your best shot. 4 great events, 4 > opportunities to win big! Highest score wins.NEC IT Guy Games. Play to > win an NEC 61 plasma display. Visit http://www.necitguy.com/?r=20 > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |
|
From: Donna R. <do...@te...> - 2005-05-09 15:14:20
|
Hi All, Just to let you all know that our server is scheduled for downtime re upgrades etc. from 6am BST to 6.30am BST tomorrow, 10 May. Donna |
|
From: Nicholas N. <nj...@cs...> - 2005-05-09 14:45:05
|
Hi, I don't think I've mentioned this before: www.burningcutlery.com/derek/phd.html has Derek Bruening's PhD dissertation about DynamoRIO, which is a Valgrind-like system for dynamic binary instrumentation. What's notable is that it is really fast, ie. typical slowdowns are in the 0--50% range. I believe it's less suitable for doing heavyweight instrumentation than Valgrind; eg. I don't think you could write Memcheck easily in it. It's also x86-specific, but it impressively supports both Windows and Linux. The dissertation has lots of good stuff about getting good performance. Also, there's a recent paper about another tool called Pin http://rogue.colorado.edu/Pin/docs/papers/pin-pldi05.pdf Pin works on multiple platforms, is again pretty fast, but again doesn't seem suitable for heavyweight instrumentation. They give some performance comparisons against Valgrind and DynamoRIO which are interesting. Valgrind doesn't fare very well, but it's really an apples-to-oranges comparison since the two comparisons involve no instrumentation and minimal instrumentation. Both are good reading, I believe these two systems are the strongest competitors Valgrind has of various dynamic binary instrumentation systems out there. N |
|
From: Benoit P. <ben...@en...> - 2005-05-09 12:46:55
|
Le lun 09/05/2005 =E0 11:59, Josef Weidendorfer a =E9crit : > On Sunday 08 May 2005 23:27, Benoit Peccatte wrote: > > I have taken this patch and modified it a bit so that it be more generi= c. > > Which means it now uses an option named --long-filenames to enable the > > display of full path for source files. > > > > This patch is made for valgrind 3.0 from subversion. > > > > This can be usefull not only for cover but for cachegrind too. > > So I'm wondering if such a patch could be included in valgrind. >=20 > Cool. Of course, it is interesting for callgrind likewise. >=20 > But why a global command line option for all tools? This looks like a=20 > temporary hack to me. >=20 > I think the tool should have control over whether it gets a file name wit= h or=20 > without full directory. This really should be part of a debug info reques= t=20 > API, part of the tool API. It's a matter of taste, but why should a tool control for the user how filenames are handled ? > Make UnitInfo as opaque data structure visible to the tool API (like SegI= nfo),=20 > and add a getDirectory(UnitInfo*). An iterator for debug line info would = be > getFirst/NextLine(UnitInfo*, int* line, Addr* addr) with (line,addr) as=20 > output. There are many UnitInfo, if you want to store ther you have to add a table of UnitInfo and add a reference to them in the RiLoc structure. > The next step would be to make your tool independent from the internal VG= =20 > structures by using this debug line iterator. This way, the debug info=20 > request API is used and can be improved for the needed szenarios of tools > (Perhaps the suggested API functions are totally bogus for your needs). I intend to do such a thing soon since I've just adapted my tool to valgrind3.0 |
|
From: <sv...@va...> - 2005-05-09 12:16:49
|
Author: sewardj
Date: 2005-05-09 13:16:33 +0100 (Mon, 09 May 2005)
New Revision: 1172
Modified:
trunk/priv/host-x86/isel.c
Log:
Support GetI/PutI of 32-bit integer arrays.
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2005-05-09 02:57:08 UTC (rev 1171)
+++ trunk/priv/host-x86/isel.c 2005-05-09 12:16:33 UTC (rev 1172)
@@ -560,14 +560,22 @@
HReg tmp, roff;
Int elemSz =3D sizeofIRType(descr->elemTy);
Int nElems =3D descr->nElems;
+ Int shift =3D 0;
=20
/* throw out any cases not generated by an x86 front end. In
theory there might be a day where we need to handle them -- if
we ever run non-x86-guest on x86 host. */
=20
- if (nElems !=3D 8 || (elemSz !=3D 1 && elemSz !=3D 8))
- vpanic("genGuestArrayOffset(x86 host)");
+ if (nElems !=3D 8)=20
+ vpanic("genGuestArrayOffset(x86 host)(1)");
=20
+ switch (elemSz) {
+ case 1: shift =3D 0; break;
+ case 4: shift =3D 2; vassert(0); /* awaiting test case */ break;
+ case 8: shift =3D 3; break;
+ default: vpanic("genGuestArrayOffset(x86 host)(2)");
+ }
+
/* Compute off into a reg, %off. Then return:
=20
movl %off, %tmp
@@ -584,10 +592,8 @@
}
addInstr(env,=20
X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(7), tmp));
- vassert(elemSz =3D=3D 1 || elemSz =3D=3D 8);
return
- X86AMode_IRRS( descr->base, hregX86_EBP(), tmp,
- elemSz=3D=3D8 ? 3 : 0);
+ X86AMode_IRRS( descr->base, hregX86_EBP(), tmp, shift );
}
=20
=20
@@ -1159,6 +1165,11 @@
addInstr(env, X86Instr_LoadEX( 1, False, am, dst ));
return dst;
}
+ if (ty =3D=3D Ity_I32) {
+ vassert(0); /* awaiting test case */
+ addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), dst));
+ return dst;
+ }
break;
}
=20
@@ -3363,6 +3374,12 @@
addInstr(env, X86Instr_Store( 1, r, am ));
return;
}
+ if (ty =3D=3D Ity_I32) {
+ HReg r =3D iselIntExpr_R(env, stmt->Ist.PutI.data);
+ vassert(0); /* awaiting test case */
+ addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(r), am ));
+ return;
+ }
if (ty =3D=3D Ity_I64) {
HReg rHi, rLo;
X86AMode* am4 =3D advance4(am);
|
|
From: Josef W. <Jos...@gm...> - 2005-05-09 10:03:12
|
On Sunday 08 May 2005 23:27, Benoit Peccatte wrote: > I have taken this patch and modified it a bit so that it be more generic. > Which means it now uses an option named --long-filenames to enable the > display of full path for source files. > > This patch is made for valgrind 3.0 from subversion. > > This can be usefull not only for cover but for cachegrind too. > So I'm wondering if such a patch could be included in valgrind. Cool. Of course, it is interesting for callgrind likewise. But why a global command line option for all tools? This looks like a temporary hack to me. I think the tool should have control over whether it gets a file name with or without full directory. This really should be part of a debug info request API, part of the tool API. Make UnitInfo as opaque data structure visible to the tool API (like SegInfo), and add a getDirectory(UnitInfo*). An iterator for debug line info would be getFirst/NextLine(UnitInfo*, int* line, Addr* addr) with (line,addr) as output. The next step would be to make your tool independent from the internal VG structures by using this debug line iterator. This way, the debug info request API is used and can be improved for the needed szenarios of tools (Perhaps the suggested API functions are totally bogus for your needs). Josef |
|
From: <js...@ac...> - 2005-05-09 03:03:19
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-05-09 03:50:00 BST Checking out source tree ... done Configuring ... done Building ... done Running regression tests ... done Last 20 lines of log.verbose follow insn_mmx: valgrind ./insn_mmx insn_mmxext: (skipping, prereq failed: ../../../tests/cputest x86-mmxext) insn_sse: valgrind ./insn_sse insn_sse2: (skipping, prereq failed: ../../../tests/cputest x86-sse2) int: valgrind ./int pushpopseg: valgrind ./pushpopseg rcl_assert: valgrind ./rcl_assert seg_override: valgrind ./seg_override -- Finished tests in none/tests/x86 ------------------------------------ yield: valgrind ./yield -- Finished tests in none/tests ---------------------------------------- == 201 tests, 5 stderr failures, 0 stdout failures ================= memcheck/tests/pth_once (stderr) memcheck/tests/scalar (stderr) memcheck/tests/threadederrno (stderr) memcheck/tests/writev (stderr) corecheck/tests/fdleak_fcntl (stderr) make: *** [regtest] Error 1 |
|
From: <sv...@va...> - 2005-05-09 02:57:13
|
Author: sewardj
Date: 2005-05-09 03:57:08 +0100 (Mon, 09 May 2005)
New Revision: 1171
Modified:
trunk/priv/guest-amd64/gdefs.h
trunk/priv/guest-amd64/ghelpers.c
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
Log:
Even more x87 instructions.
Modified: trunk/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/gdefs.h 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/guest-amd64/gdefs.h 2005-05-09 02:57:08 UTC (rev 1171)
@@ -97,9 +97,9 @@
// UInt arg, UInt rot_amt, UInt eflags_in, UInt sz=20
// );
=20
-//extern ULong amd64g_check_fldcw ( ULong fpucw );
+extern ULong amd64g_check_fldcw ( ULong fpucw );
=20
-//extern ULong amd64g_create_fpucw ( ULong fpround );
+extern ULong amd64g_create_fpucw ( ULong fpround );
=20
extern ULong amd64g_check_ldmxcsr ( ULong mxcsr );
=20
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/guest-amd64/ghelpers.c 2005-05-09 02:57:08 UTC (rev 1171)
@@ -1268,7 +1268,44 @@
}
=20
=20
+/* CLEAN HELPER */
+/* fpucw[15:0] contains a x87 native format FPU control word.
+ Extract from it the required FPROUND value and any resulting
+ emulation warning, and return (warn << 32) | fpround value.
+*/
+ULong amd64g_check_fldcw ( ULong fpucw )
+{
+ /* Decide on a rounding mode. fpucw[11:10] holds it. */
+ /* NOTE, encoded exactly as per enum IRRoundingMode. */
+ ULong rmode =3D (fpucw >> 10) & 3;
=20
+ /* Detect any required emulation warnings. */
+ VexEmWarn ew =3D EmWarn_NONE;
+
+ if ((fpucw & 0x3F) !=3D 0x3F) {
+ /* unmasked exceptions! */
+ ew =3D EmWarn_X86_x87exns;
+ }
+ else
+ if (((fpucw >> 8) & 3) !=3D 3) {
+ /* unsupported precision */
+ ew =3D EmWarn_X86_x87precision;
+ }
+
+ return (((ULong)ew) << 32) | ((ULong)rmode);
+}
+
+
+/* CLEAN HELPER */
+/* Given fpround as an IRRoundingMode value, create a suitable x87
+ native format FPU control word. */
+ULong amd64g_create_fpucw ( ULong fpround )
+{
+ fpround &=3D 3;
+ return 0x037F | (fpround << 10);
+}
+
+
/*---------------------------------------------------------------*/
/*--- Misc integer helpers, including rotates and CPUID. ---*/
/*---------------------------------------------------------------*/
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-09 02:57:08 UTC (rev 1171)
@@ -4143,11 +4143,11 @@
return unop(Iop_64to32, IRExpr_Get( OFFB_FPROUND, Ity_I64 ));
}
=20
-//.. static void put_fpround ( IRExpr* /* :: Ity_I32 */ e )
-//.. {
-//.. vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I32);
-//.. stmt( IRStmt_Put( OFFB_FPROUND, unop(Iop_32Uto64,e) ) );
-//.. }
+static void put_fpround ( IRExpr* /* :: Ity_I32 */ e )
+{
+ vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I32);
+ stmt( IRStmt_Put( OFFB_FPROUND, unop(Iop_32Uto64,e) ) );
+}
=20
=20
/* --------- Synthesise a 2-bit FPU rounding mode. --------- */
@@ -4617,47 +4617,47 @@
//.. DIP("fldenv %s\n", dis_buf);
//.. break;
//.. }
-//..=20
-//.. case 5: {/* FLDCW */
-//.. /* The only thing we observe in the control word is =
the
-//.. rounding mode. Therefore, pass the 16-bit value
-//.. (x87 native-format control word) to a clean helpe=
r,
-//.. getting back a 64-bit value, the lower half of wh=
ich
-//.. is the FPROUND value to store, and the upper half=
of
-//.. which is the emulation-warning token which may be
-//.. generated.
-//.. */
-//.. /* ULong x86h_check_fldcw ( UInt ); */
-//.. IRTemp t64 =3D newTemp(Ity_I64);
-//.. IRTemp ew =3D newTemp(Ity_I32);
-//.. DIP("fldcw %s\n", dis_buf);
-//.. assign( t64, mkIRExprCCall(
-//.. Ity_I64, 0/*regparms*/,=20
-//.. "x86g_check_fldcw",
-//.. &x86g_check_fldcw,=20
-//.. mkIRExprVec_1(=20
-//.. unop( Iop_16Uto32,=20
-//.. loadLE(Ity_I16, mkexpr(addr=
)))
-//.. )
-//.. )
-//.. );
-//..=20
-//.. put_fpround( unop(Iop_64to32, mkexpr(t64)) );
-//.. assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) );
-//.. put_emwarn( mkexpr(ew) );
-//.. /* Finally, if an emulation warning was reported,
-//.. side-exit to the next insn, reporting the warning=
,
-//.. so that Valgrind's dispatcher sees the warning. *=
/
-//.. stmt(=20
-//.. IRStmt_Exit(
-//.. binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
-//.. Ijk_EmWarn,
-//.. IRConst_U32( ((Addr32)guest_eip_bbstart)+delta=
)
-//.. )
-//.. );
-//.. break;
-//.. }
-//..=20
+
+ case 5: {/* FLDCW */
+ /* The only thing we observe in the control word is the
+ rounding mode. Therefore, pass the 16-bit value
+ (x87 native-format control word) to a clean helper,
+ getting back a 64-bit value, the lower half of which
+ is the FPROUND value to store, and the upper half of
+ which is the emulation-warning token which may be
+ generated.
+ */
+ /* ULong amd64h_check_fldcw ( ULong ); */
+ IRTemp t64 =3D newTemp(Ity_I64);
+ IRTemp ew =3D newTemp(Ity_I32);
+ DIP("fldcw %s\n", dis_buf);
+ assign( t64, mkIRExprCCall(
+ Ity_I64, 0/*regparms*/,=20
+ "amd64g_check_fldcw",
+ &amd64g_check_fldcw,=20
+ mkIRExprVec_1(=20
+ unop( Iop_16Uto64,=20
+ loadLE(Ity_I16, mkexpr(addr)))
+ )
+ )
+ );
+
+ put_fpround( unop(Iop_64to32, mkexpr(t64)) );
+ assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) );
+ put_emwarn( mkexpr(ew) );
+ /* Finally, if an emulation warning was reported,
+ side-exit to the next insn, reporting the warning,
+ so that Valgrind's dispatcher sees the warning. */
+ stmt(=20
+ IRStmt_Exit(
+ binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
+ Ijk_EmWarn,
+ IRConst_U64( guest_rip_bbstart+delta )
+ )
+ );
+ break;
+ }
+
//.. case 6: { /* FNSTENV m28 */
//.. /* Uses dirty helper:=20
//.. void x86g_do_FSTENV ( VexGuestX86State*, UInt =
) */
@@ -4697,25 +4697,25 @@
//.. DIP("fnstenv %s\n", dis_buf);
//.. break;
//.. }
-//..=20
-//.. case 7: /* FNSTCW */
-//.. /* Fake up a native x87 FPU control word. The only
-//.. thing it depends on is FPROUND[1:0], so call a cle=
an
-//.. helper to cook it up. */
-//.. /* UInt x86h_create_fpucw ( UInt fpround ) */
-//.. DIP("fnstcw %s\n", dis_buf);
-//.. storeLE(
-//.. mkexpr(addr),=20
-//.. unop( Iop_32to16,=20
-//.. mkIRExprCCall(
-//.. Ity_I32, 0/*regp*/,
-//.. "x86g_create_fpucw", &x86g_create_fpucw,=
=20
-//.. mkIRExprVec_1( get_fpround() )=20
-//.. )=20
-//.. )=20
-//.. );
-//.. break;
=20
+ case 7: /* FNSTCW */
+ /* Fake up a native x87 FPU control word. The only
+ thing it depends on is FPROUND[1:0], so call a clean
+ helper to cook it up. */
+ /* ULong x86h_create_fpucw ( ULong fpround ) */
+ DIP("fnstcw %s\n", dis_buf);
+ storeLE(
+ mkexpr(addr),=20
+ unop( Iop_64to16,=20
+ mkIRExprCCall(
+ Ity_I64, 0/*regp*/,
+ "amd64g_create_fpucw", &amd64g_create_fpucw,=20
+ mkIRExprVec_1( unop(Iop_32Uto64, get_fpround(=
)) )=20
+ )=20
+ )=20
+ );
+ break;
+
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
vex_printf("first_opcode =3D=3D 0xD9\n");
@@ -4837,13 +4837,13 @@
fp_pop();
break;
=20
-//.. case 0xF2: /* FPTAN */
-//.. DIP("ftan\n");
-//.. put_ST_UNCHECKED(0, unop(Iop_TanF64, get_ST(0)));
-//.. fp_push();
-//.. put_ST(0, IRExpr_Const(IRConst_F64(1.0)));
-//.. clear_C2(); /* HACK */
-//.. break;
+ case 0xF2: /* FPTAN */
+ DIP("ftan\n");
+ put_ST_UNCHECKED(0, unop(Iop_TanF64, get_ST(0)));
+ fp_push();
+ put_ST(0, IRExpr_Const(IRConst_F64(1.0)));
+ clear_C2(); /* HACK */
+ break;
=20
case 0xF3: /* FPATAN */
DIP("fpatan\n");
@@ -4885,12 +4885,12 @@
//.. break;
//.. }
//..=20
-//.. case 0xF9: /* FYL2XP1 */
-//.. DIP("fyl2xp1\n");
-//.. put_ST_UNCHECKED(1, binop(Iop_Yl2xp1F64,
-//.. get_ST(1), get_ST(0)));
-//.. fp_pop();
-//.. break;
+ case 0xF9: /* FYL2XP1 */
+ DIP("fyl2xp1\n");
+ put_ST_UNCHECKED(1, binop(Iop_Yl2xp1F64,
+ get_ST(1), get_ST(0)));
+ fp_pop();
+ break;
=20
case 0xFA: /* FSQRT */
DIP("fsqrt\n");
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-09 02:57:08 UTC (rev 1171)
@@ -567,7 +567,7 @@
case Afp_SCALE: return "scale";
case Afp_ATAN: return "atan";
case Afp_YL2X: return "yl2x";
-//.. case Xfp_YL2XP1: return "yl2xp1";
+ case Afp_YL2XP1: return "yl2xp1";
//.. case Xfp_PREM: return "prem";
//.. case Xfp_PREM1: return "prem1";
case Afp_SQRT: return "sqrt";
@@ -576,7 +576,7 @@
//.. case Xfp_MOV: return "mov";
case Afp_SIN: return "sin";
case Afp_COS: return "cos";
-//.. case Xfp_TAN: return "tan";
+ case Afp_TAN: return "tan";
case Afp_ROUND: return "round";
case Afp_2XM1: return "2xm1";
default: vpanic("showA87FpOp");
@@ -2836,14 +2836,16 @@
=20
case Ain_A87FpOp:
switch (i->Ain.A87FpOp.op) {
- case Afp_SQRT: *p++ =3D 0xD9; *p++ =3D 0xFA; break;
- case Afp_SIN: *p++ =3D 0xD9; *p++ =3D 0xFE; break;
- case Afp_COS: *p++ =3D 0xD9; *p++ =3D 0xFF; break;
- case Afp_ROUND: *p++ =3D 0xD9; *p++ =3D 0xFC; break;
- case Afp_2XM1: *p++ =3D 0xD9; *p++ =3D 0xF0; break;
- case Afp_SCALE: *p++ =3D 0xD9; *p++ =3D 0xFD; break;
- case Afp_ATAN: *p++ =3D 0xD9; *p++ =3D 0xF3; break;
- case Afp_YL2X: *p++ =3D 0xD9; *p++ =3D 0xF1; break;
+ case Afp_SQRT: *p++ =3D 0xD9; *p++ =3D 0xFA; break;
+ case Afp_SIN: *p++ =3D 0xD9; *p++ =3D 0xFE; break;
+ case Afp_COS: *p++ =3D 0xD9; *p++ =3D 0xFF; break;
+ case Afp_TAN: *p++ =3D 0xD9; *p++ =3D 0xF2; break;
+ case Afp_ROUND: *p++ =3D 0xD9; *p++ =3D 0xFC; break;
+ case Afp_2XM1: *p++ =3D 0xD9; *p++ =3D 0xF0; break;
+ case Afp_SCALE: *p++ =3D 0xD9; *p++ =3D 0xFD; break;
+ case Afp_ATAN: *p++ =3D 0xD9; *p++ =3D 0xF3; break;
+ case Afp_YL2X: *p++ =3D 0xD9; *p++ =3D 0xF1; break;
+ case Afp_YL2XP1: *p++ =3D 0xD9; *p++ =3D 0xF9; break;
default: goto bad;
}
goto done;
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/host-amd64/hdefs.h 2005-05-09 02:57:08 UTC (rev 1171)
@@ -297,10 +297,10 @@
Afp_INVALID,
/* Binary */
//.. Xfp_ADD, Xfp_SUB, Xfp_MUL, Xfp_DIV,=20
- Afp_SCALE, Afp_ATAN, Afp_YL2X, //Xfp_YL2XP1, Xfp_PREM, Xfp_PREM1,
+ Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, //Xfp_PREM, Xfp_PREM1,
/* Unary */
Afp_SQRT, //Xfp_ABS, Xfp_NEG, Xfp_MOV,=20
- Afp_SIN, Afp_COS, //Xfp_TAN,
+ Afp_SIN, Afp_COS, Afp_TAN,
Afp_ROUND, Afp_2XM1
}
A87FpOp;
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-08 23:03:48 UTC (rev 1170)
+++ trunk/priv/host-amd64/isel.c 2005-05-09 02:57:08 UTC (rev 1171)
@@ -2838,7 +2838,8 @@
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_ScaleF64
|| e->Iex.Binop.op =3D=3D Iop_AtanF64
- || e->Iex.Binop.op =3D=3D Iop_Yl2xF64)
+ || e->Iex.Binop.op =3D=3D Iop_Yl2xF64
+ || e->Iex.Binop.op =3D=3D Iop_Yl2xp1F64)
) {
AMD64AMode* m8_rsp =3D AMD64AMode_IR(-8, hregAMD64_RSP());
HReg arg1 =3D iselDblExpr(env, e->Iex.Binop.arg1);
@@ -2868,6 +2869,9 @@
case Iop_Yl2xF64:=20
addInstr(env, AMD64Instr_A87FpOp(Afp_YL2X));
break;
+ case Iop_Yl2xp1F64:=20
+ addInstr(env, AMD64Instr_A87FpOp(Afp_YL2XP1));
+ break;
default:=20
vassert(0);
}
@@ -2927,9 +2931,9 @@
//.. case Iop_NegF64: fpop =3D Xfp_NEG; break;
//.. case Iop_AbsF64: fpop =3D Xfp_ABS; break;
case Iop_SqrtF64: fpop =3D Afp_SQRT; break;
- case Iop_SinF64: fpop =3D Afp_SIN; break;
- case Iop_CosF64: fpop =3D Afp_COS; break;
-//.. case Iop_TanF64: fpop =3D Xfp_TAN; break;
+ case Iop_SinF64: fpop =3D Afp_SIN; break;
+ case Iop_CosF64: fpop =3D Afp_COS; break;
+ case Iop_TanF64: fpop =3D Afp_TAN; break;
case Iop_2xm1F64: fpop =3D Afp_2XM1; break;
default: break;
}
@@ -2937,10 +2941,15 @@
AMD64AMode* m8_rsp =3D AMD64AMode_IR(-8, hregAMD64_RSP());
HReg arg =3D iselDblExpr(env, e->Iex.Unop.arg);
HReg dst =3D newVRegV(env);
+ Int nNeeded =3D e->Iex.Unop.op=3D=3DIop_TanF64 ? 2 : 1;
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp=
));
- addInstr(env, AMD64Instr_A87Free(1));
+ addInstr(env, AMD64Instr_A87Free(nNeeded));
addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
addInstr(env, AMD64Instr_A87FpOp(fpop));
+ if (e->Iex.Unop.op=3D=3DIop_TanF64) {
+ /* get rid of the extra 1.0 that fptan pushes */
+ addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
+ }
addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp))=
;
return dst;
|
|
From: Tom H. <to...@co...> - 2005-05-09 02:36:04
|
Nightly build on dunsmere ( athlon, Fedora Core 3 ) started at 2005-05-09 03:30:04 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 175 tests, 167 stderr failures, 1 stdout failure ================= memcheck/tests/addressable (stderr) memcheck/tests/badaddrvalue (stderr) memcheck/tests/badfree-2trace (stderr) memcheck/tests/badfree (stderr) memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/badloop (stderr) memcheck/tests/badpoll (stderr) memcheck/tests/badrw (stderr) memcheck/tests/brk (stderr) memcheck/tests/brk2 (stderr) memcheck/tests/buflen_check (stderr) memcheck/tests/clientperm (stderr) memcheck/tests/custom_alloc (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/doublefree (stderr) memcheck/tests/errs1 (stderr) memcheck/tests/execve (stderr) memcheck/tests/execve2 (stderr) memcheck/tests/exitprog (stderr) memcheck/tests/fprw (stderr) memcheck/tests/fwrite (stderr) memcheck/tests/inits (stderr) memcheck/tests/inline (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/malloc1 (stderr) memcheck/tests/malloc2 (stderr) memcheck/tests/malloc3 (stderr) memcheck/tests/manuel1 (stderr) memcheck/tests/manuel2 (stderr) memcheck/tests/manuel3 (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/memalign2 (stderr) memcheck/tests/memalign_test (stderr) memcheck/tests/memcmptest (stderr) memcheck/tests/mempool (stderr) memcheck/tests/mismatches (stderr) memcheck/tests/mmaptest (stderr) memcheck/tests/nanoleak (stderr) memcheck/tests/nanoleak_supp (stderr) memcheck/tests/new_nothrow (stderr) memcheck/tests/new_override (stderr) memcheck/tests/null_socket (stderr) memcheck/tests/overlap (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/post-syscall (stderr) memcheck/tests/realloc1 (stderr) memcheck/tests/realloc2 (stderr) memcheck/tests/realloc3 (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/signal2 (stderr) memcheck/tests/sigprocmask (stderr) memcheck/tests/str_tester (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp2 (stderr) memcheck/tests/suppfree (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/trivialleak (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/writev (stderr) memcheck/tests/x86/fpeflags (stderr) memcheck/tests/x86/pushfpopf (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_exit_group (stderr) memcheck/tests/x86/scalar_fork (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/scalar_vfork (stderr) memcheck/tests/x86/tronical (stderr) memcheck/tests/zeropage (stderr) cachegrind/tests/chdir (stderr) cachegrind/tests/dlclose (stderr) cachegrind/tests/x86/fpu-28-108 (stderr) corecheck/tests/as_mmap (stderr) corecheck/tests/as_shm (stderr) corecheck/tests/erringfds (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/fdleak_creat (stderr) corecheck/tests/fdleak_dup (stderr) corecheck/tests/fdleak_dup2 (stderr) corecheck/tests/fdleak_fcntl (stderr) corecheck/tests/fdleak_ipv4 (stderr) corecheck/tests/fdleak_open (stderr) corecheck/tests/fdleak_pipe (stderr) corecheck/tests/fdleak_socketpair (stderr) corecheck/tests/pth_atfork1 (stderr) corecheck/tests/pth_cancel1 (stderr) corecheck/tests/pth_cancel2 (stderr) corecheck/tests/pth_cvsimple (stderr) corecheck/tests/pth_empty (stderr) corecheck/tests/pth_exit (stderr) corecheck/tests/pth_exit2 (stderr) corecheck/tests/pth_mutexspeed (stderr) corecheck/tests/pth_once (stderr) corecheck/tests/pth_rwlock (stderr) corecheck/tests/res_search (stderr) corecheck/tests/sigkill (stderr) corecheck/tests/threadederrno (stderr) corecheck/tests/vgprintf (stderr) massif/tests/toobig-allocs (stderr) massif/tests/true_html (stderr) massif/tests/true_text (stderr) lackey/tests/true (stderr) none/tests/args (stderr) none/tests/async-sigs (stderr) none/tests/bitfield1 (stderr) none/tests/blockfault (stderr) none/tests/closeall (stderr) none/tests/coolo_sigaction (stderr) none/tests/coolo_strlen (stderr) none/tests/discard (stderr) none/tests/exec-sigmask (stderr) none/tests/execve (stderr) none/tests/faultstatus (stderr) none/tests/fcntl_setown (stderr) none/tests/floored (stderr) none/tests/fork (stderr) none/tests/fucomip (stderr) none/tests/gxx304 (stderr) none/tests/manythreads (stderr) none/tests/map_unaligned (stderr) none/tests/map_unmap (stderr) none/tests/mq (stderr) none/tests/mremap (stderr) none/tests/munmap_exe (stderr) none/tests/pending (stderr) none/tests/pth_blockedsig (stderr) none/tests/pth_stackalign (stderr) none/tests/rcrl (stderr) none/tests/readline1 (stderr) none/tests/resolv (stderr) none/tests/rlimit_nofile (stderr) none/tests/selfrun (stdout) none/tests/selfrun (stderr) none/tests/sem (stderr) none/tests/semlimit (stderr) none/tests/sha1_test (stderr) none/tests/shortpush (stderr) none/tests/shorts (stderr) none/tests/sigstackgrowth (stderr) none/tests/smc1 (stderr) none/tests/stackgrowth (stderr) none/tests/syscall-restart1 (stderr) none/tests/syscall-restart2 (stderr) none/tests/system (stderr) none/tests/thread-exits (stderr) none/tests/threaded-fork (stderr) none/tests/tls (stderr) none/tests/x86/badseg (stderr) none/tests/x86/bt_everything (stderr) none/tests/x86/bt_literal (stderr) none/tests/x86/cpuid (stderr) none/tests/x86/fpu_lazy_eflags (stderr) none/tests/x86/getseg (stderr) none/tests/x86/insn_basic (stderr) none/tests/x86/insn_cmov (stderr) none/tests/x86/insn_fpu (stderr) none/tests/x86/insn_mmx (stderr) none/tests/x86/insn_mmxext (stderr) none/tests/x86/insn_sse (stderr) none/tests/x86/int (stderr) none/tests/x86/pushpopseg (stderr) none/tests/x86/seg_override (stderr) none/tests/x86/sigcontext (stderr) none/tests/yield (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-09 02:31:20
|
Nightly build on audi ( i686, Red Hat 9 ) started at 2005-05-09 03:25:02 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 174 tests, 3 stderr failures, 0 stdout failures ================= corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <to...@co...> - 2005-05-09 02:26:30
|
Nightly build on dunsmere ( Fedora Core 3 ) started at 2005-05-09 03:20:03 BST Checking out source tree ... done Configuring ... done Building ... done Running regression tests ... done Last 20 lines of log.verbose follow insn_mmx: valgrind ./insn_mmx insn_mmxext: valgrind ./insn_mmxext insn_sse: valgrind ./insn_sse insn_sse2: (skipping, prereq failed: ../../../tests/cputest x86-sse2) int: valgrind ./int sh: line 1: 16619 Segmentation fault VALGRINDLIB=/tmp/valgrind.23307/valgrind/.in_place /tmp/valgrind.23307/valgrind/./coregrind/valgrind --command-line-only=yes --memcheck:leak-check=no --addrcheck:leak-check=no --tool=none ./int >int.stdout.out 2>int.stderr.out pushpopseg: valgrind ./pushpopseg rcl_assert: valgrind ./rcl_assert seg_override: valgrind ./seg_override -- Finished tests in none/tests/x86 ------------------------------------ yield: valgrind ./yield -- Finished tests in none/tests ---------------------------------------- == 207 tests, 4 stderr failures, 0 stdout failures ================= memcheck/tests/execve (stderr) memcheck/tests/execve2 (stderr) memcheck/tests/scalar (stderr) memcheck/tests/scalar_supp (stderr) make: *** [regtest] Error 1 |
|
From: Julian S. <js...@ac...> - 2005-05-09 02:26:18
|
Author: njn Date: 2005-05-09 02:02:08 +0100 (Mon, 09 May 2005) New Revision: 3644 Added: trunk/include/tool.h Removed: trunk/coregrind/gen_toolint.pl trunk/coregrind/toolfuncs.def trunk/include/tool.h.base Modified: trunk/addrcheck/ac_main.c trunk/cachegrind/cg_main.c trunk/corecheck/cc_main.c trunk/coregrind/Makefile.am trunk/coregrind/core.h trunk/coregrind/m_aspacemgr/aspacemgr.c trunk/coregrind/m_errormgr.c trunk/coregrind/m_syscalls/priv_syscalls.h trunk/coregrind/m_syscalls/syscalls.c trunk/coregrind/vg_main.c trunk/coregrind/vg_needs.c trunk/coregrind/vg_replace_malloc.c trunk/coregrind/vg_scheduler.c trunk/coregrind/vg_translate.c trunk/docs/xml/writing-tools.xml trunk/helgrind/hg_main.c trunk/include/Makefile.am trunk/include/pub_tool_errormgr.h trunk/include/tool_asm.h trunk/lackey/lk_main.c trunk/massif/ms_main.c trunk/memcheck/mac_malloc_wrappers.c trunk/memcheck/mac_needs.c trunk/memcheck/mac_shared.h trunk/memcheck/mc_include.h trunk/memcheck/mc_main.c trunk/memcheck/mc_translate.c trunk/none/nl_main.c Log: Big clean-up: changed the core/tool interface to be mediated entirely through the VG_(tdict) function dictionary, rather than using TL_(foo) functions. This facilitated the following changes: - Removed the "TL_" prefix, which is no longer needed. - Removed the auto-generated files vg_toolint.[ch], which were no longer needed, which simplifies the build a great deal. Their (greatly streamlined) contents went into core.h and vg_needs.h (and will soon go into a new module defining the core/tool interface). =20 =20 This also meant that tool.h.base reverted to tool.h (so no more accidentally editing tool.h and not having the changes go into the repo, hooray!) And gen_toolint.pl was removed. And toolfuncs.def was removed. - Removed VG_(missing_tool_func)(), no longer used. - Bumped the core/tool interface major version number to 8. And I killed the minor version number, which was never used. The layout of the ToolInfo struct is such that this should not cause problems. [changes are huge and therefore deleted -- J] |
|
From: Tom H. <th...@cy...> - 2005-05-09 02:25:44
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-05-09 03:20:02 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 173 tests, 3 stderr failures, 0 stdout failures ================= corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |