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From: <sv...@va...> - 2005-05-05 21:48:01
|
Author: sewardj
Date: 2005-05-05 22:46:50 +0100 (Thu, 05 May 2005)
New Revision: 1164
Modified:
trunk/priv/guest-amd64/ghelpers.c
trunk/priv/guest-amd64/toIR.c
Log:
Fix up %rflags handling after 64-bit multiplies.
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2005-05-05 21:34:02 UTC (rev 1163)
+++ trunk/priv/guest-amd64/ghelpers.c 2005-05-05 21:46:50 UTC (rev 1164)
@@ -92,7 +92,6 @@
*rLo =3D u * v;
}
=20
-#if 0 /* UNUSED */
static void mullU64 ( ULong u, ULong v, ULong* rHi, ULong* rLo )
{
ULong u0, v0, w0;
@@ -109,7 +108,6 @@
*rHi =3D u1 * v1 + w2 + (w1 >> 32);
*rLo =3D u * v;
}
-#endif /* UNUSED */
=20
=20
static const UChar parity_table[256] =3D {
@@ -644,6 +642,8 @@
case AMD64G_CC_OP_UMULL: ACTIONS_UMUL( 32, UInt, toUInt,
ULong, idULong );
=20
+ case AMD64G_CC_OP_UMULQ: ACTIONS_UMULQ;
+
case AMD64G_CC_OP_SMULB: ACTIONS_SMUL( 8, Char, toUChar,
Short, toUShort );
case AMD64G_CC_OP_SMULW: ACTIONS_SMUL( 16, Short, toUShort,=20
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-05 21:34:02 UTC (rev 1163)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-05 21:46:50 UTC (rev 1164)
@@ -3425,7 +3425,7 @@
IRTemp resHi =3D newTemp(Ity_I64);
IRTemp resLo =3D newTemp(Ity_I64);
IROp mulOp =3D syned ? Iop_MullS64 : Iop_MullU64;
- UInt tBaseOp =3D syned ? AMD64G_CC_OP_SMULQ : AMD64G_CC_OP_UM=
ULQ;
+ UInt tBaseOp =3D syned ? AMD64G_CC_OP_SMULB : AMD64G_CC_OP_UM=
ULB;
setFlags_MUL ( Ity_I64, t1, tmp, tBaseOp );
assign( res128, binop(mulOp, mkexpr(t1), mkexpr(tmp)) );
assign( resHi, unop(Iop_128HIto64,mkexpr(res128)));
|
|
From: <sv...@va...> - 2005-05-05 21:34:08
|
Author: sewardj
Date: 2005-05-05 22:34:02 +0100 (Thu, 05 May 2005)
New Revision: 1163
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
Log:
Implement a whole bunch more SSE instructions on amd64.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-05 12:05:54 UTC (rev 1162)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-05 21:34:02 UTC (rev 1163)
@@ -2163,7 +2163,7 @@
by the caller. This is needed to make sense of %rip-relative
addresses. Note that the value that *len is set to is only the
length of the amode itself and does not include the value supplied
- in xtra_bytes.
+ in extra_bytes.
*/
=20
static IRTemp disAMode_copy2tmp ( IRExpr* addr64 )
@@ -7443,41 +7443,41 @@
}
=20
=20
-//.. /* SSE integer binary operation:
-//.. G =3D G `op` E (eLeft =3D=3D False)
-//.. G =3D E `op` G (eLeft =3D=3D True)
-//.. */
-//.. static UInt dis_SSEint_E_to_G(=20
-//.. UChar sorb, ULong delta,=20
-//.. HChar* opname, IROp op,
-//.. Bool eLeft
-//.. )
-//.. {
-//.. HChar dis_buf[50];
-//.. Int alen;
-//.. IRTemp addr;
-//.. UChar rm =3D getUChar(delta);
-//.. IRExpr* gpart =3D getXMMReg(gregOfRM(rm));
-//.. IRExpr* epart =3D NULL;
-//.. if (epartIsReg(rm)) {
-//.. epart =3D getXMMReg(eregOfRM(rm));
-//.. DIP("%s %s,%s\n", opname,
-//.. nameXMMReg(eregOfRM(rm)),
-//.. nameXMMReg(gregOfRM(rm)) );
-//.. delta +=3D 1;
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. epart =3D loadLE(Ity_V128, mkexpr(addr));
-//.. DIP("%s %s,%s\n", opname,
-//.. dis_buf,
-//.. nameXMMReg(gregOfRM(rm)) );
-//.. delta +=3D alen;
-//.. }
-//.. putXMMReg( gregOfRM(rm),=20
-//.. eLeft ? binop(op, epart, gpart)
-//.. : binop(op, gpart, epart) );
-//.. return delta;
-//.. }
+/* SSE integer binary operation:
+ G =3D G `op` E (eLeft =3D=3D False)
+ G =3D E `op` G (eLeft =3D=3D True)
+*/
+static ULong dis_SSEint_E_to_G(=20
+ Prefix pfx, ULong delta,=20
+ HChar* opname, IROp op,
+ Bool eLeft
+ )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ UChar rm =3D getUChar(delta);
+ IRExpr* gpart =3D getXMMReg(gregOfRexRM(pfx,rm));
+ IRExpr* epart =3D NULL;
+ if (epartIsReg(rm)) {
+ epart =3D getXMMReg(eregOfRexRM(pfx,rm));
+ DIP("%s %s,%s\n", opname,
+ nameXMMReg(eregOfRexRM(pfx,rm)),
+ nameXMMReg(gregOfRexRM(pfx,rm)) );
+ delta +=3D 1;
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta, dis_buf, 0 );
+ epart =3D loadLE(Ity_V128, mkexpr(addr));
+ DIP("%s %s,%s\n", opname,
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,rm)) );
+ delta +=3D alen;
+ }
+ putXMMReg( gregOfRexRM(pfx,rm),=20
+ eLeft ? binop(op, epart, gpart)
+ : binop(op, gpart, epart) );
+ return delta;
+}
=20
=20
/* Helper for doing SSE FP comparisons. */
@@ -7659,62 +7659,63 @@
//.. putXMMReg( gregOfRM(rm), mkexpr(g1) );
//.. return delta;
//.. }
-//..=20
-//..=20
-//.. /* Vector by scalar shift of E by an immediate byte. */
-//..=20
-//.. static=20
-//.. UInt dis_SSE_shiftE_imm ( ULong delta, HChar* opname, IROp op )
-//.. {
-//.. Bool shl, shr, sar;
-//.. UChar rm =3D getUChar(delta);
-//.. IRTemp e0 =3D newTemp(Ity_V128);
-//.. IRTemp e1 =3D newTemp(Ity_V128);
-//.. UChar amt, size;
-//.. vassert(epartIsReg(rm));
-//.. vassert(gregOfRM(rm) =3D=3D 2=20
-//.. || gregOfRM(rm) =3D=3D 4 || gregOfRM(rm) =3D=3D 6);
-//.. amt =3D (Int)(getUChar(delta+1));
-//.. delta +=3D 2;
-//.. DIP("%s $%d,%s\n", opname,
-//.. (Int)amt,
-//.. nameXMMReg(eregOfRM(rm)) );
-//.. assign( e0, getXMMReg(eregOfRM(rm)) );
-//..=20
-//.. shl =3D shr =3D sar =3D False;
-//.. size =3D 0;
-//.. switch (op) {
-//.. case Iop_ShlN16x8: shl =3D True; size =3D 16; break;
-//.. case Iop_ShlN32x4: shl =3D True; size =3D 32; break;
-//.. case Iop_ShlN64x2: shl =3D True; size =3D 64; break;
-//.. case Iop_SarN16x8: sar =3D True; size =3D 16; break;
-//.. case Iop_SarN32x4: sar =3D True; size =3D 32; break;
-//.. case Iop_ShrN16x8: shr =3D True; size =3D 16; break;
-//.. case Iop_ShrN32x4: shr =3D True; size =3D 32; break;
-//.. case Iop_ShrN64x2: shr =3D True; size =3D 64; break;
-//.. default: vassert(0);
-//.. }
-//..=20
-//.. if (shl || shr) {
-//.. assign( e1, amt >=3D size=20
-//.. ? mkV128(0x0000)
-//.. : binop(op, mkexpr(e0), mkU8(amt))
-//.. );
-//.. } else=20
-//.. if (sar) {
-//.. assign( e1, amt >=3D size=20
-//.. ? binop(op, mkexpr(e0), mkU8(size-1))
-//.. : binop(op, mkexpr(e0), mkU8(amt))
-//.. );
-//.. } else {
-//.. vassert(0);
-//.. }
-//..=20
-//.. putXMMReg( eregOfRM(rm), mkexpr(e1) );
-//.. return delta;
-//.. }
=20
=20
+/* Vector by scalar shift of E by an immediate byte. */
+
+static=20
+ULong dis_SSE_shiftE_imm ( Prefix pfx,=20
+ ULong delta, HChar* opname, IROp op )
+{
+ Bool shl, shr, sar;
+ UChar rm =3D getUChar(delta);
+ IRTemp e0 =3D newTemp(Ity_V128);
+ IRTemp e1 =3D newTemp(Ity_V128);
+ UChar amt, size;
+ vassert(epartIsReg(rm));
+ vassert(gregLO3ofRM(rm) =3D=3D 2=20
+ || gregLO3ofRM(rm) =3D=3D 4 || gregLO3ofRM(rm) =3D=3D 6);
+ amt =3D (Int)(getUChar(delta+1));
+ delta +=3D 2;
+ DIP("%s $%d,%s\n", opname,
+ (Int)amt,
+ nameXMMReg(eregOfRexRM(pfx,rm)) );
+ assign( e0, getXMMReg(eregOfRexRM(pfx,rm)) );
+
+ shl =3D shr =3D sar =3D False;
+ size =3D 0;
+ switch (op) {
+ case Iop_ShlN16x8: shl =3D True; size =3D 16; break;
+ case Iop_ShlN32x4: shl =3D True; size =3D 32; break;
+ case Iop_ShlN64x2: shl =3D True; size =3D 64; break;
+ case Iop_SarN16x8: sar =3D True; size =3D 16; break;
+ case Iop_SarN32x4: sar =3D True; size =3D 32; break;
+ case Iop_ShrN16x8: shr =3D True; size =3D 16; break;
+ case Iop_ShrN32x4: shr =3D True; size =3D 32; break;
+ case Iop_ShrN64x2: shr =3D True; size =3D 64; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign( e1, amt >=3D size=20
+ ? mkV128(0x0000)
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else=20
+ if (sar) {
+ assign( e1, amt >=3D size=20
+ ? binop(op, mkexpr(e0), mkU8(size-1))
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else {
+ vassert(0);
+ }
+
+ putXMMReg( eregOfRexRM(pfx,rm), mkexpr(e1) );
+ return delta;
+}
+
+
/* Get the current SSE rounding mode. */
=20
static IRExpr* /* :: Ity_I32 */ get_sse_roundingmode ( void )
@@ -7832,7 +7833,7 @@
/*OUT*/ Addr64* whereNext )
{
IRType ty;
- IRTemp addr, /* t0, */ t1, t2, t3, t4 /*, t5, t6 */;
+ IRTemp addr, t0, t1, t2, t3, t4 /*, t5, t6 */;
Int alen;
UChar opc, modrm, /*abyte,*/ pre;
Long d64;
@@ -7860,7 +7861,7 @@
vassert(guest_rip_next_assumed =3D=3D 0);
vassert(guest_rip_next_mustcheck =3D=3D False);
=20
- addr =3D /* t0 =3D */ t1 =3D t2 =3D t3 =3D t4 =3D /* t5 =3D t6 =3D */=
IRTemp_INVALID;=20
+ addr =3D t0 =3D t1 =3D t2 =3D t3 =3D t4 =3D /* t5 =3D t6 =3D */ IRTem=
p_INVALID;=20
=20
DIP("\t0x%llx: ", guest_rip_bbstart+delta);
=20
@@ -7966,15 +7967,49 @@
=20
=20
/* ---------------------------------------------------- */
- /* --- The SSE decoder. --- */
+ /* --- The SSE/SSE2 decoder. --- */
/* ---------------------------------------------------- */
=20
/* What did I do to deserve SSE ? Perhaps I was really bad in a
previous life? */
=20
- /* Note, this doesn't handle SSE2 or SSE3. That is handled in a
- later section, further on. */
+ /* Note, this doesn't handle SSE3 right now. All amd64s support
+ SSE2 as a minimum so there is no point distinguishing SSE1 vs
+ SSE2. */
=20
+ /* There are just so many damn SSE insns, and amongst them are a
+ large number of data-move insns, many of which seem almost
+ identical. Here's a statement of the behaviour of MOVQ, MOVSD,
+ MOVD, MOVSS. It doesn't help that the Intel manuals are less
+ than accurate about these. The AMD docs seem OK tho.=20
+
+ The following is true for both x86 and amd64. MOVQ and MOVSD
+ shunt 64-bit things around. r is an xmm register and m is
+ memory.
+
+ MOVQ r <- r lo64 moved; hi64 set to zero
+ MOVQ m <- r lo64 moved
+ MOVQ r <- m lo64 moved; hi64 set to zero
+
+ MOVSD r <- r lo64 moved; hi64 unchanged
+ MOVSD m <- r lo64 moved
+ MOVSD r <- m lo64 moved; hi64 set to zero
+
+ MOVD and MOVSS shunt 32-bit things around, and are exactly
+ analogous:
+
+ MOVD r <- r lo32 moved; hi96 set to zero
+ MOVD m <- r lo32 moved
+ MOVD r <- m lo32 moved; hi96 set to zero
+
+ MOVSS r <- r lo32 moved; hi96 unchanged
+ MOVSS m <- r lo32 moved
+ MOVSS r <- m lo32 moved; hi96 set to zero
+
+ For MOVQ and MOVD, the r <- r rules apply even if the source r
+ is instead an integer register.
+ */
+
insn =3D (UChar*)&guest_code[delta];
=20
//.. /* Treat fxsave specially. It should be doable even on an SSE0
@@ -9244,39 +9279,39 @@
goto decode_success;
}
=20
-//.. /* F3 0F E6 =3D CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm t=
o 2 x
-//.. F64 in xmm(G) */
-//.. if (insn[0] =3D=3D 0xF3 && insn[1] =3D=3D 0x0F && insn[2] =3D=3D=
0xE6) {
-//.. IRTemp arg64 =3D newTemp(Ity_I64);
-//.. vassert(sz =3D=3D 4);
-//..=20
-//.. modrm =3D getUChar(delta+3);
-//.. if (epartIsReg(modrm)) {
-//.. assign( arg64, getXMMRegLane64(eregOfRM(modrm), 0) );
-//.. delta +=3D 3+1;
-//.. DIP("cvtdq2pd %s,%s\n", nameXMMReg(eregOfRM(modrm)),
-//.. nameXMMReg(gregOfRM(modrm)));
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+3, dis_buf );
-//.. assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
-//.. delta +=3D 3+alen;
-//.. DIP("cvtdq2pd %s,%s\n", dis_buf,
-//.. nameXMMReg(gregOfRM(modrm)) );
-//.. }
-//..=20
-//.. putXMMRegLane64F(=20
-//.. gregOfRM(modrm), 0,
-//.. unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64)))
-//.. );
-//..=20
-//.. putXMMRegLane64F(
-//.. gregOfRM(modrm), 1,=20
-//.. unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64)))
-//.. );
-//..=20
-//.. goto decode_success;
-//.. }
-//..=20
+ /* F3 0F E6 =3D CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x
+ F64 in xmm(G) */
+ if (haveF3no66noF2(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xE6=
) {
+ IRTemp arg64 =3D newTemp(Ity_I64);
+ if (sz !=3D 4) goto decode_failure;
+
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ assign( arg64, getXMMRegLane64(eregOfRexRM(pfx,modrm), 0) );
+ delta +=3D 2+1;
+ DIP("cvtdq2pd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta +=3D 2+alen;
+ DIP("cvtdq2pd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+
+ putXMMRegLane64F(=20
+ gregOfRexRM(pfx,modrm), 0,
+ unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64)))
+ );
+
+ putXMMRegLane64F(
+ gregOfRexRM(pfx,modrm), 1,=20
+ unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64)))
+ );
+
+ goto decode_success;
+ }
+
//.. /* 0F 5B =3D CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 i=
n
//.. xmm(G) */
//.. if (sz =3D=3D 4 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5B) {
@@ -9315,52 +9350,50 @@
//..=20
//.. goto decode_success;
//.. }
-//..=20
-//.. /* F2 0F E6 =3D CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I3=
2 in
-//.. lo half xmm(G), and zero upper half */
-//.. if (insn[0] =3D=3D 0xF2 && insn[1] =3D=3D 0x0F && insn[2] =3D=3D=
0xE6) {
-//.. IRTemp argV =3D newTemp(Ity_V128);
-//.. IRTemp rmode =3D newTemp(Ity_I32);
-//.. vassert(sz =3D=3D 4);
-//..=20
-//.. modrm =3D getUChar(delta+3);
-//.. if (epartIsReg(modrm)) {
-//.. assign( argV, getXMMReg(eregOfRM(modrm)) );
-//.. delta +=3D 3+1;
-//.. DIP("cvtpd2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)),
-//.. nameXMMReg(gregOfRM(modrm)));
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+3, dis_buf );
-//.. assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
-//.. delta +=3D 3+alen;
-//.. DIP("cvtpd2dq %s,%s\n", dis_buf,
-//.. nameXMMReg(gregOfRM(modrm)) );
-//.. }
-//.. =20
-//.. assign( rmode, get_sse_roundingmode() );
-//.. t0 =3D newTemp(Ity_F64);
-//.. t1 =3D newTemp(Ity_F64);
-//.. assign( t0, unop(Iop_ReinterpI64asF64,=20
-//.. unop(Iop_128to64, mkexpr(argV))) );
-//.. assign( t1, unop(Iop_ReinterpI64asF64,=20
-//.. unop(Iop_128HIto64, mkexpr(argV))) );
-//.. =20
-#if 0 /* stop gcc multi-line comment warning */
-/.. # define CVT(_t) binop( Iop_F64toI32, \
-/.. mkexpr(rmode), \
-/.. mkexpr(_t) )
-#endif /* stop gcc multi-line comment warning */
-//.. =20
-//.. putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) );
-//.. putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) );
-//.. putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) );
-//.. putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) );
-//..=20
-//.. # undef CVT
-//..=20
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* F2 0F E6 =3D CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in
+ lo half xmm(G), and zero upper half */
+ if (haveF2no66noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xE6=
) {
+ IRTemp argV =3D newTemp(Ity_V128);
+ IRTemp rmode =3D newTemp(Ity_I32);
+ if (sz !=3D 4) goto decode_failure;
+
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ assign( argV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ delta +=3D 2+1;
+ DIP("cvtpd2dq %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta +=3D 2+alen;
+ DIP("cvtpd2dq %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+ =20
+ assign( rmode, get_sse_roundingmode() );
+ t0 =3D newTemp(Ity_F64);
+ t1 =3D newTemp(Ity_F64);
+ assign( t0, unop(Iop_ReinterpI64asF64,=20
+ unop(Iop_V128to64, mkexpr(argV))) );
+ assign( t1, unop(Iop_ReinterpI64asF64,=20
+ unop(Iop_V128HIto64, mkexpr(argV))) );
+ =20
+# define CVT(_t) binop( Iop_F64toI32, \
+ mkexpr(rmode), \
+ mkexpr(_t) )
+ =20
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 3, mkU32(0) );
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 2, mkU32(0) );
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 1, CVT(t1) );
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 0, CVT(t0) );
+
+# undef CVT
+
+ goto decode_success;
+ }
+
//.. /* 66 0F 2D =3D CVTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
//.. I32 in mmx, according to prevailing SSE rounding mode */
//.. /* 66 0F 2C =3D CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
@@ -9909,66 +9942,95 @@
}
}
=20
-//.. /* 66 0F 6E =3D MOVD from r/m32 to xmm, zeroing high 3/4 of xmm.=
*/
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x6E) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. delta +=3D 2+1;
-//.. putXMMReg(
-//.. gregOfRM(modrm),
-//.. unop( Iop_32Uto128, getIReg(4, eregOfRM(modrm)) )=20
-//.. );
-//.. DIP("movd %s, %s\n",=20
-//.. nameIReg(4,eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm=
)));
-//.. } else {
-//.. addr =3D disAMode( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//.. putXMMReg(
-//.. gregOfRM(modrm),
-//.. unop( Iop_32Uto128,loadLE(Ity_I32, mkexpr(addr)) )=20
-//.. );
-//.. DIP("movd %s, %s\n", dis_buf, nameXMMReg(gregOfRM(modrm)))=
;
-//.. }
-//.. goto decode_success;
-//.. }
-//..=20
-//.. /* 66 0F 7E =3D MOVD from xmm low 1/4 to r/m32. */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x7E) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. delta +=3D 2+1;
-//.. putIReg( 4, eregOfRM(modrm),
-//.. getXMMRegLane32(gregOfRM(modrm), 0) );
-//.. DIP("movd %s, %s\n",=20
-//.. nameXMMReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm=
)));
-//.. } else {
-//.. addr =3D disAMode( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//.. storeLE( mkexpr(addr),
-//.. getXMMRegLane32(gregOfRM(modrm), 0) );
-//.. DIP("movd %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf)=
;
-//.. }
-//.. goto decode_success;
-//.. }
-//..=20
-//.. /* 66 0F 7F =3D MOVDQA -- move from G (xmm) to E (mem or xmm). *=
/
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x7F) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. delta +=3D 2+1;
-//.. putXMMReg( eregOfRM(modrm),
-//.. getXMMReg(gregOfRM(modrm)) );
-//.. DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)),=20
-//.. nameXMMReg(eregOfRM(modrm)));
-//.. } else {
-//.. addr =3D disAMode( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//.. storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) );
-//.. DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_bu=
f);
-//.. }
-//.. goto decode_success;
-//.. }
-//..=20
+ /* 66 0F 6E =3D MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 =
of xmm. */
+ /* or from ireg64/m64 to xmm lo 1/2, zeroing high 1/2 of=
xmm. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x6E=
) {
+ vassert(sz =3D=3D 4 || sz =3D=3D 8);
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ delta +=3D 2+1;
+ if (sz =3D=3D 4) {
+ goto decode_failure; /* awaiting test case */
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_32UtoV128, getIReg32(eregOfRexRM(pfx,modrm)) )=20
+ );
+ DIP("movd %s, %s\n", nameIReg32(eregOfRexRM(pfx,modrm)),=20
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_64UtoV128, getIReg64(eregOfRexRM(pfx,modrm)) )=20
+ );
+ DIP("movq %s, %s\n", nameIReg64(eregOfRexRM(pfx,modrm)),=20
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ } else {
+ addr =3D disAMode( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ sz =3D=3D 4=20
+ ? unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)) )=20
+ : unop( Iop_64UtoV128,loadLE(Ity_I64, mkexpr(addr)) )
+ );
+ DIP("mov%c %s, %s\n", sz =3D=3D 4 ? 'd' : 'q', dis_buf,=20
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ goto decode_success;
+ }
+
+ /* 66 0F 7E =3D MOVD from xmm low 1/4 to ireg32 or m32. */
+ /* or from xmm low 1/2 to ireg64 or m64. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x7E=
) {
+ if (sz =3D=3D 2) sz =3D 4;
+ vassert(sz =3D=3D 4 || sz =3D=3D 8);
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ delta +=3D 2+1;
+ if (sz =3D=3D 4) {
+ putIReg32( eregOfRexRM(pfx,modrm),
+ getXMMRegLane32(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movd %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),=20
+ nameIReg32(eregOfRexRM(pfx,modrm)));
+ } else {
+ putIReg64( eregOfRexRM(pfx,modrm),
+ getXMMRegLane64(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movq %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),=20
+ nameIReg64(eregOfRexRM(pfx,modrm)));
+ }
+ } else {
+ addr =3D disAMode( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ storeLE( mkexpr(addr),
+ sz =3D=3D 4
+ ? getXMMRegLane32(gregOfRexRM(pfx,modrm),0)
+ : getXMMRegLane64(gregOfRexRM(pfx,modrm),0) );
+ DIP("mov%c %s, %s\n", sz =3D=3D 4 ? 'd' : 'q',
+ nameXMMReg(gregOfRexRM(pfx,modrm)), dis_b=
uf);
+ }
+ goto decode_success;
+ }
+
+ /* 66 0F 7F =3D MOVDQA -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x7F) {
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ delta +=3D 2+1;
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),=20
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ } else {
+ addr =3D disAMode( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_=
buf);
+ }
+ goto decode_success;
+ }
+
//.. /* F3 0F 6F =3D MOVDQU -- move from E (mem or xmm) to G (xmm). *=
/
//.. /* Unfortunately can't simply use the MOVDQA case since the
//.. prefix lengths are different (66 vs F3) */
@@ -10259,55 +10321,56 @@
goto decode_success;
}
=20
-//.. /* 66 0F C6 /r ib =3D SHUFPD -- shuffle packed F64s */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xC6) {
-//.. Int select;
-//.. IRTemp sV =3D newTemp(Ity_V128);
-//.. IRTemp dV =3D newTemp(Ity_V128);
-//.. IRTemp s1 =3D newTemp(Ity_I64);
-//.. IRTemp s0 =3D newTemp(Ity_I64);
-//.. IRTemp d1 =3D newTemp(Ity_I64);
-//.. IRTemp d0 =3D newTemp(Ity_I64);
-//..=20
-//.. modrm =3D insn[2];
-//.. assign( dV, getXMMReg(gregOfRM(modrm)) );
-//..=20
-//.. if (epartIsReg(modrm)) {
-//.. assign( sV, getXMMReg(eregOfRM(modrm)) );
-//.. select =3D (Int)insn[3];
-//.. delta +=3D 2+2;
-//.. DIP("shufpd $%d,%s,%s\n", select,=20
-//.. nameXMMReg(eregOfRM(modrm)),
-//.. nameXMMReg(gregOfRM(modrm)));
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
-//.. select =3D (Int)insn[2+alen];
-//.. delta +=3D 3+alen;
-//.. DIP("shufpd $%d,%s,%s\n", select,=20
-//.. dis_buf,
-//.. nameXMMReg(gregOfRM(modrm)));
-//.. }
-//..=20
-//.. assign( d1, unop(Iop_128HIto64, mkexpr(dV)) );
-//.. assign( d0, unop(Iop_128to64, mkexpr(dV)) );
-//.. assign( s1, unop(Iop_128HIto64, mkexpr(sV)) );
-//.. assign( s0, unop(Iop_128to64, mkexpr(sV)) );
-//..=20
-//.. # define SELD(n) mkexpr((n)=3D=3D0 ? d0 : d1)
-//.. # define SELS(n) mkexpr((n)=3D=3D0 ? s0 : s1)
-//..=20
-//.. putXMMReg(
-//.. gregOfRM(modrm),=20
-//.. binop(Iop_64HLto128, SELS((select>>1)&1), SELD((select>>0)=
&1) )
-//.. );
-//..=20
-//.. # undef SELD
-//.. # undef SELS
-//..=20
-//.. goto decode_success;
-//.. }
-//..=20
+ /* 66 0F C6 /r ib =3D SHUFPD -- shuffle packed F64s */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xC6) {
+ Int select;
+ IRTemp sV =3D newTemp(Ity_V128);
+ IRTemp dV =3D newTemp(Ity_V128);
+ IRTemp s1 =3D newTemp(Ity_I64);
+ IRTemp s0 =3D newTemp(Ity_I64);
+ IRTemp d1 =3D newTemp(Ity_I64);
+ IRTemp d0 =3D newTemp(Ity_I64);
+
+ modrm =3D insn[2];
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ select =3D (Int)insn[3];
+ delta +=3D 2+2;
+ DIP("shufpd $%d,%s,%s\n", select,=20
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ select =3D (Int)insn[2+alen];
+ delta +=3D 3+alen;
+ DIP("shufpd $%d,%s,%s\n", select,=20
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( d0, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( s0, unop(Iop_V128to64, mkexpr(sV)) );
+
+# define SELD(n) mkexpr((n)=3D=3D0 ? d0 : d1)
+# define SELS(n) mkexpr((n)=3D=3D0 ? s0 : s1)
+
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),=20
+ binop(Iop_64HLtoV128, SELS((select>>1)&1), SELD((select>>0)&1) =
)
+ );
+
+# undef SELD
+# undef SELS
+
+ goto decode_success;
+ }
+
//.. /* 66 0F 51 =3D SQRTPD -- approx sqrt 64Fx2 from R/M to R */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x51) {
//.. delta =3D dis_SSE_E_to_G_unary_all( sorb, delta+2,=20
@@ -10434,14 +10497,15 @@
//.. sorb, delta+2, insn[1], "paddq", False );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F D4 =3D PADDQ */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD4) {
-//.. delta =3D dis_SSEint_E_to_G( sorb, delta+2,=20
-//.. "paddq", Iop_Add64x2, False );
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* 66 0F D4 =3D PADDQ */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD4) {
+ delta =3D dis_SSEint_E_to_G( pfx, delta+2,=20
+ "paddq", Iop_Add64x2, False );
+ goto decode_success;
+ }
+
//.. /* 66 0F FD =3D PADDW */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFD) {
//.. delta =3D dis_SSEint_E_to_G( sorb, delta+2,=20
@@ -10476,13 +10540,14 @@
//.. "paddusw", Iop_QAdd16Ux8, False );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F DB =3D PAND */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xDB) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "pand", Iop_And1=
28 );
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* 66 0F DB =3D PAND */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xDB) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "pand", Iop_AndV128 );
+ goto decode_success;
+ }
+
//.. /* 66 0F DF =3D PANDN */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xDF) {
//.. delta =3D dis_SSE_E_to_G_all_invG( sorb, delta+2, "pandn", Io=
p_And128 );
@@ -10745,13 +10810,14 @@
//.. putXMMRegLane64( gregOfRM(modrm), 1, mkexpr(t1) );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F EB =3D POR */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xEB) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "por", Iop_Or128=
);
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* 66 0F EB =3D POR */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xEB) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "por", Iop_OrV128 );
+ goto decode_success;
+ }
+
//.. /* 66 0F 70 =3D PSHUFD -- rearrange 4x32 from E(xmm or mem) to G=
(xmm) */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x70) {
//.. Int order;
@@ -11081,15 +11147,16 @@
//.. putXMMReg(reg, mkexpr(dV));
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F 73 /2 ib =3D PSRLQ by immediate */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x73
-//.. && epartIsReg(insn[2])
-//.. && gregOfRM(insn[2]) =3D=3D 2) {
-//.. delta =3D dis_SSE_shiftE_imm( delta+2, "psrlq", Iop_ShrN64x2 =
);
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* 66 0F 73 /2 ib =3D PSRLQ by immediate */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x73
+ && epartIsReg(insn[2])
+ && gregLO3ofRM(insn[2]) =3D=3D 2) {
+ delta =3D dis_SSE_shiftE_imm( pfx, delta+2, "psrlq", Iop_ShrN64x2 =
);
+ goto decode_success;
+ }
+
//.. /* 66 0F D3 =3D PSRLQ by E */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xD3) {
//.. delta =3D dis_SSE_shiftG_byE( sorb, delta+2, "psrlq", Iop_Shr=
N64x2 );
@@ -11132,14 +11199,15 @@
//.. sorb, delta+2, insn[1], "psubq", False );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F FB =3D PSUBQ */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFB) {
-//.. delta =3D dis_SSEint_E_to_G( sorb, delta+2,=20
-//.. "psubq", Iop_Sub64x2, False );
-//.. goto decode_success;
-//.. }
-//..=20
+
+ /* 66 0F FB =3D PSUBQ */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xFB) {
+ delta =3D dis_SSEint_E_to_G( pfx, delta+2,=20
+ "psubq", Iop_Sub64x2, False );
+ goto decode_success;
+ }
+
//.. /* 66 0F F9 =3D PSUBW */
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xF9) {
//.. delta =3D dis_SSEint_E_to_G( sorb, delta+2,=20
@@ -11238,14 +11306,14 @@
//.. Iop_InterleaveLO16x8, True );
//.. goto decode_success;
//.. }
-//..=20
-//.. /* 66 0F EF =3D PXOR */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xEF) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "pxor", Iop_Xor1=
28 );
-//.. goto decode_success;
-//.. }
-//..=20
-//..=20
+
+ /* 66 0F EF =3D PXOR */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xEF) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "pxor", Iop_XorV128 );
+ goto decode_success;
+ }
+
//.. //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. =
*/
//.. //-- if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xAE=20
//.. //-- && (!epartIsReg(insn[2]))
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-05 12:05:54 UTC (rev 1162)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-05 21:34:02 UTC (rev 1163)
@@ -606,7 +606,7 @@
//.. case Xsse_ADD8: return "paddb";
//.. case Xsse_ADD16: return "paddw";
//.. case Xsse_ADD32: return "paddd";
-//.. case Xsse_ADD64: return "paddq";
+ case Asse_ADD64: return "paddq";
//.. case Xsse_QADD8U: return "paddusb";
//.. case Xsse_QADD16U: return "paddusw";
//.. case Xsse_QADD8S: return "paddsb";
@@ -614,7 +614,7 @@
//.. case Xsse_SUB8: return "psubb";
//.. case Xsse_SUB16: return "psubw";
//.. case Xsse_SUB32: return "psubd";
-//.. case Xsse_SUB64: return "psubq";
+ case Asse_SUB64: return "psubq";
//.. case Xsse_QSUB8U: return "psubusb";
//.. case Xsse_QSUB16U: return "psubusw";
//.. case Xsse_QSUB8S: return "psubsb";
@@ -630,7 +630,7 @@
//.. case Xsse_MIN8U: return "pminub";
//.. case Xsse_CMPEQ8: return "pcmpeqb";
//.. case Xsse_CMPEQ16: return "pcmpeqw";
-//.. case Xsse_CMPEQ32: return "pcmpeqd";
+ case Asse_CMPEQ32: return "pcmpeqd";
//.. case Xsse_CMPGT8S: return "pcmpgtb";
//.. case Xsse_CMPGT16S: return "pcmpgtw";
//.. case Xsse_CMPGT32S: return "pcmpgtd";
@@ -639,7 +639,7 @@
//.. case Xsse_SHL64: return "psllq";
//.. case Xsse_SHR16: return "psrlw";
//.. case Xsse_SHR32: return "psrld";
-//.. case Xsse_SHR64: return "psrlq";
+ case Asse_SHR64: return "psrlq";
//.. case Xsse_SAR16: return "psraw";
//.. case Xsse_SAR32: return "psrad";
//.. case Xsse_PACKSSD: return "packssdw";
@@ -1001,15 +1001,15 @@
vassert(cond !=3D Acc_ALWAYS);
return i;
}
-//.. AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ) {
-//.. AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag =3D Xin_SseShuf;
-//.. i->Xin.SseShuf.order =3D order;
-//.. i->Xin.SseShuf.src =3D src;
-//.. i->Xin.SseShuf.dst =3D dst;
-//.. vassert(order >=3D 0 && order <=3D 0xFF);
-//.. return i;
-//.. }
+AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ) {
+ AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag =3D Ain_SseShuf;
+ i->Ain.SseShuf.order =3D order;
+ i->Ain.SseShuf.src =3D src;
+ i->Ain.SseShuf.dst =3D dst;
+ vassert(order >=3D 0 && order <=3D 0xFF);
+ return i;
+}
=20
void ppAMD64Instr ( AMD64Instr* i )=20
{
@@ -1303,12 +1303,12 @@
vex_printf(",");
ppHRegAMD64(i->Ain.SseCMov.dst);
return;
-//.. case Xin_SseShuf:
-//.. vex_printf("pshufd $0x%x,", i->Xin.SseShuf.order);
-//.. ppHRegAMD64(i->Xin.SseShuf.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.SseShuf.dst);
-//.. return;
+ case Ain_SseShuf:
+ vex_printf("pshufd $0x%x,", i->Ain.SseShuf.order);
+ ppHRegAMD64(i->Ain.SseShuf.src);
+ vex_printf(",");
+ ppHRegAMD64(i->Ain.SseShuf.dst);
+ return;
=20
default:
vpanic("ppAMD64Instr");
@@ -1572,10 +1572,10 @@
addHRegUse(u, HRmRead, i->Ain.SseCMov.src);
addHRegUse(u, HRmModify, i->Ain.SseCMov.dst);
return;
-//.. case Xin_SseShuf:
-//.. addHRegUse(u, HRmRead, i->Xin.SseShuf.src);
-//.. addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst);
-//.. return;
+ case Ain_SseShuf:
+ addHRegUse(u, HRmRead, i->Ain.SseShuf.src);
+ addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
+ return;
default:
ppAMD64Instr(i);
vpanic("getRegUsage_AMD64Instr");
@@ -1737,10 +1737,10 @@
mapReg(m, &i->Ain.SseCMov.src);
mapReg(m, &i->Ain.SseCMov.dst);
return;
-//.. case Xin_SseShuf:
-//.. mapReg(m, &i->Xin.SseShuf.src);
-//.. mapReg(m, &i->Xin.SseShuf.dst);
-//.. return;
+ case Ain_SseShuf:
+ mapReg(m, &i->Ain.SseShuf.src);
+ mapReg(m, &i->Ain.SseShuf.dst);
+ return;
default:
ppAMD64Instr(i);
vpanic("mapRegs_AMD64Instr");
@@ -3203,7 +3203,7 @@
//.. case Xsse_ADD8: XX(0x66); XX(rex); XX(0x0F); XX(0xFC);=
break;
//.. case Xsse_ADD16: XX(0x66); XX(rex); XX(0x0F); XX(0xFD);=
break;
//.. case Xsse_ADD32: XX(0x66); XX(rex); XX(0x0F); XX(0xFE);=
break;
-//.. case Xsse_ADD64: XX(0x66); XX(rex); XX(0x0F); XX(0xD4);=
break;
+ case Asse_ADD64: XX(0x66); XX(rex); XX(0x0F); XX(0xD4); brea=
k;
//.. case Xsse_QADD8S: XX(0x66); XX(rex); XX(0x0F); XX(0xEC);=
break;
//.. case Xsse_QADD16S: XX(0x66); XX(rex); XX(0x0F); XX(0xED);=
break;
//.. case Xsse_QADD8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDC);=
break;
@@ -3212,7 +3212,7 @@
//.. case Xsse_AVG16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE3);=
break;
//.. case Xsse_CMPEQ8: XX(0x66); XX(rex); XX(0x0F); XX(0x74);=
break;
//.. case Xsse_CMPEQ16: XX(0x66); XX(rex); XX(0x0F); XX(0x75);=
break;
-//.. case Xsse_CMPEQ32: XX(0x66); XX(rex); XX(0x0F); XX(0x76);=
break;
+ case Asse_CMPEQ32: XX(0x66); XX(rex); XX(0x0F); XX(0x76); brea=
k;
//.. case Xsse_CMPGT8S: XX(0x66); XX(rex); XX(0x0F); XX(0x64);=
break;
//.. case Xsse_CMPGT16S: XX(0x66); XX(rex); XX(0x0F); XX(0x65);=
break;
//.. case Xsse_CMPGT32S: XX(0x66); XX(rex); XX(0x0F); XX(0x66);=
break;
@@ -3230,11 +3230,11 @@
//.. case Xsse_SAR32: XX(0x66); XX(rex); XX(0x0F); XX(0xE2);=
break;
//.. case Xsse_SHR16: XX(0x66); XX(rex); XX(0x0F); XX(0xD1);=
break;
//.. case Xsse_SHR32: XX(0x66); XX(rex); XX(0x0F); XX(0xD2);=
break;
-//.. case Xsse_SHR64: XX(0x66); XX(rex); XX(0x0F); XX(0xD3);=
break;
+ case Asse_SHR64: XX(0x66); XX(rex); XX(0x0F); XX(0xD3); brea=
k;
//.. case Xsse_SUB8: XX(0x66); XX(rex); XX(0x0F); XX(0xF8);=
break;
//.. case Xsse_SUB16: XX(0x66); XX(rex); XX(0x0F); XX(0xF9);=
break;
//.. case Xsse_SUB32: XX(0x66); XX(rex); XX(0x0F); XX(0xFA);=
break;
-//.. case Xsse_SUB64: XX(0x66); XX(rex); XX(0x0F); XX(0xFB);=
break;
+ case Asse_SUB64: XX(0x66); XX(rex); XX(0x0F); XX(0xFB); brea=
k;
//.. case Xsse_QSUB8S: XX(0x66); XX(rex); XX(0x0F); XX(0xE8);=
break;
//.. case Xsse_QSUB16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE9);=
break;
//.. case Xsse_QSUB8U: XX(0x66); XX(rex); XX(0x0F); XX(0xD8);=
break;
@@ -3273,15 +3273,18 @@
*(ptmp-1) =3D toUChar(p - ptmp);
goto done;
=20
-//.. case Xin_SseShuf:
-//.. *p++ =3D 0x66;=20
-//.. *p++ =3D 0x0F;=20
-//.. *p++ =3D 0x70;=20
-//.. p =3D doAMode_R(p, fake(vregNo(i->Xin.SseShuf.dst)),
-//.. fake(vregNo(i->Xin.SseShuf.src)) );
-//.. *p++ =3D (UChar)(i->Xin.SseShuf.order);
-//.. goto done;
-//..=20
+ case Ain_SseShuf:
+ *p++ =3D 0x66;=20
+ *p++ =3D clearWBit(
+ rexAMode_R( vreg2ireg(i->Ain.SseShuf.dst),
+ vreg2ireg(i->Ain.SseShuf.src) ));
+ *p++ =3D 0x0F;=20
+ *p++ =3D 0x70;=20
+ p =3D doAMode_R(p, vreg2ireg(i->Ain.SseShuf.dst),
+ vreg2ireg(i->Ain.SseShuf.src) );
+ *p++ =3D (UChar)(i->Ain.SseShuf.order);
+ goto done;
+
default:=20
goto bad;
}
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-05-05 12:05:54 UTC (rev 1162)
+++ trunk/priv/host-amd64/hdefs.h 2005-05-05 21:34:02 UTC (rev 1163)
@@ -322,10 +322,12 @@
/* Bitwise */
Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN,
//.. /* Integer binary */
-//.. Xsse_ADD8, Xsse_ADD16, Xsse_ADD32, Xsse_ADD64,
+//.. Xsse_ADD8, Xsse_ADD16, Xsse_ADD32,
+ Asse_ADD64,
//.. Xsse_QADD8U, Xsse_QADD16U,
//.. Xsse_QADD8S, Xsse_QADD16S,
-//.. Xsse_SUB8, Xsse_SUB16, Xsse_SUB32, Xsse_SUB64,
+//.. Xsse_SUB8, Xsse_SUB16, Xsse_SUB32,
+ Asse_SUB64,
//.. Xsse_QSUB8U, Xsse_QSUB16U,
//.. Xsse_QSUB8S, Xsse_QSUB16S,
//.. Xsse_MUL16,
@@ -336,10 +338,12 @@
//.. Xsse_MAX8U,
//.. Xsse_MIN16S,
//.. Xsse_MIN8U,
-//.. Xsse_CMPEQ8, Xsse_CMPEQ16, Xsse_CMPEQ32,
+//.. Xsse_CMPEQ8, Xsse_CMPEQ16, =20
+ Asse_CMPEQ32,
//.. Xsse_CMPGT8S, Xsse_CMPGT16S, Xsse_CMPGT32S,
//.. Xsse_SHL16, Xsse_SHL32, Xsse_SHL64,
-//.. Xsse_SHR16, Xsse_SHR32, Xsse_SHR64,
+//.. Xsse_SHR16, Xsse_SHR32,=20
+ Asse_SHR64,
//.. Xsse_SAR16, Xsse_SAR32,=20
//.. Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW,
//.. Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ,
@@ -397,7 +401,7 @@
Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */
Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */
Ain_SseCMov, /* SSE conditional move */
-//.. Xin_SseShuf /* SSE2 shuffle (pshufd) */
+ Ain_SseShuf /* SSE2 shuffle (pshufd) */
}
AMD64InstrTag;
=20
@@ -642,11 +646,11 @@
HReg src;
HReg dst;
} SseCMov;
-//.. struct {
-//.. Int order; /* 0 <=3D order <=3D 0xFF */
-//.. HReg src;
-//.. HReg dst;
-//.. } SseShuf;
+ struct {
+ Int order; /* 0 <=3D order <=3D 0xFF */
+ HReg src;
+ HReg dst;
+ } SseShuf;
=20
} Ain;
}
@@ -695,7 +699,7 @@
extern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg =
dst );
-//.. extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg=
dst );
+extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst =
);
=20
=20
extern void ppAMD64Instr ( AMD64Instr* );
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-05 12:05:54 UTC (rev 1162)
+++ trunk/priv/host-amd64/isel.c 2005-05-05 21:34:02 UTC (rev 1163)
@@ -699,19 +699,16 @@
//.. }
=20
=20
-/* Generate !src into a new vector register, and be sure that the code
- is SSE1 compatible. Amazing that Intel doesn't offer a less crappy
- way to do this.=20
+/* Generate !src into a new vector register. Amazing that there isn't
+ a less crappy way to do this.
*/
static HReg do_sse_NotV128 ( ISelEnv* env, HReg src )
{
HReg dst =3D newVRegV(env);
- /* Set dst to zero. Not strictly necessary, but the idea of doing
- a FP comparison on whatever junk happens to be floating around
- in it is just too scary. */
+ /* Set dst to zero. Not strictly necessary. */
addInstr(env, AMD64Instr_SseReRg(Asse_XOR, dst, dst));
/* And now make it all 1s ... */
- addInstr(env, AMD64Instr_Sse32Fx4(Asse_CMPEQF, dst, dst));
+ addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, dst, dst));
/* Finally, xor 'src' into it. */
addInstr(env, AMD64Instr_SseReRg(Asse_XOR, src, dst));
return dst;
@@ -3049,34 +3046,33 @@
return do_sse_NotV128(env, arg);
}
=20
-//.. case Iop_CmpNEZ64x2: {
-//.. /* We can use SSE2 instructions for this. */
-//.. /* Ideally, we want to do a 64Ix2 comparison against zero =
of
-//.. the operand. Problem is no such insn exists. Solution
-//.. therefore is to do a 32Ix4 comparison instead, and bitw=
ise-
-//.. negate (NOT) the result. Let a,b,c,d be 32-bit lanes, =
and=20
-//.. let the not'd result of this initial comparison be a:b:=
c:d.
-//.. What we need to compute is (a|b):(a|b):(c|d):(c|d). So=
, use
-//.. pshufd to create a value b:a:d:c, and OR that with a:b:=
c:d,
-//.. giving the required result.
-//..=20
-//.. The required selection sequence is 2,3,0,1, which
-//.. according to Intel's documentation means the pshufd
-//.. literal value is 0xB1, that is,=20
-//.. (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)=20
-//.. */
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg tmp =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, tmp, tmp));
-//.. addInstr(env, X86Instr_SseReRg(Xsse_CMPEQ32, arg, tmp));
-//.. tmp =3D do_sse_Not128(env, tmp);
-//.. addInstr(env, X86Instr_SseShuf(0xB1, tmp, dst));
-//.. addInstr(env, X86Instr_SseReRg(Xsse_OR, tmp, dst));
-//.. return dst;
-//.. }
-//..=20
+ case Iop_CmpNEZ64x2: {
+ /* We can use SSE2 instructions for this. */
+ /* Ideally, we want to do a 64Ix2 comparison against zero of
+ the operand. Problem is no such insn exists. Solution
+ therefore is to do a 32Ix4 comparison instead, and bitwise-
+ negate (NOT) the result. Let a,b,c,d be 32-bit lanes, and=20
+ let the not'd result of this initial comparison be a:b:c:d.
+ What we need to compute is (a|b):(a|b):(c|d):(c|d). So, use
+ pshufd to create a value b:a:d:c, and OR that with a:b:c:d,
+ giving the required result.
+
+ The required selection sequence is 2,3,0,1, which
+ according to Intel's documentation means the pshufd
+ literal value is 0xB1, that is,=20
+ (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)=20
+ */
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg tmp =3D newVRegV(env);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, AMD64Instr_SseReRg(Asse_XOR, tmp, tmp));
+ addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, arg, tmp));
+ tmp =3D do_sse_NotV128(env, tmp);
+ addInstr(env, AMD64Instr_SseShuf(0xB1, tmp, dst));
+ addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmp, dst));
+ return dst;
+ }
+
//.. case Iop_CmpNEZ32x4: {
//.. /* Sigh, we have to generate lousy code since this has to
//.. work on SSE1 hosts */
@@ -3355,7 +3351,7 @@
//.. case Iop_Add8x16: op =3D Xsse_ADD8; goto do_SseReRg;
//.. case Iop_Add16x8: op =3D Xsse_ADD16; goto do_SseReRg;
//.. case Iop_Add32x4: op =3D Xsse_ADD32; goto do_SseReRg;
-//.. case Iop_Add64x2: op =3D Xsse_ADD64; goto do_SseReRg;
+ case Iop_Add64x2: op =3D Asse_ADD64; goto do_SseReRg;
//.. case Iop_QAdd8Sx16: op =3D Xsse_QADD8S; goto do_SseReRg;
//.. case Iop_QAdd16Sx8: op =3D Xsse_QADD16S; goto do_SseReRg;
//.. case Iop_QAdd8Ux16: op =3D Xsse_QADD8U; goto do_SseReRg;
@@ -3378,7 +3374,7 @@
//.. case Iop_Sub8x16: op =3D Xsse_SUB8; goto do_SseReRg;
//.. case Iop_Sub16x8: op =3D Xsse_SUB16; goto do_SseReRg;
//.. case Iop_Sub32x4: op =3D Xsse_SUB32; goto do_SseReRg;
-//.. case Iop_Sub64x2: op =3D Xsse_SUB64; goto do_SseReRg;
+ case Iop_Sub64x2: op =3D Asse_SUB64; goto do_SseReRg;
//.. case Iop_QSub8Sx16: op =3D Xsse_QSUB8S; goto do_SseReRg;
//.. case Iop_QSub16Sx8: op =3D Xsse_QSUB16S; goto do_SseReRg;
//.. case Iop_QSub8Ux16: op =3D Xsse_QSUB8U; goto do_SseReRg;
@@ -3405,24 +3401,21 @@
//.. case Iop_SarN32x4: op =3D Xsse_SAR32; goto do_SseShift;
//.. case Iop_ShrN16x8: op =3D Xsse_SHR16; goto do_SseShift;
//.. case Iop_ShrN32x4: op =3D Xsse_SHR32; goto do_SseShift;
-//.. case Iop_ShrN64x2: op =3D Xsse_SHR64; goto do_SseShift;
-//.. do_SseShift: {
-//.. HReg greg =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2)=
;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. HReg ereg =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Imm(0)));
-//.. addInstr(env, X86Instr_Push(rmi));
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, ereg, esp0));
-//.. addInstr(env, mk_vMOVsd_RR(greg, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, ereg, dst));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
+ case Iop_ShrN64x2: op =3D Asse_SHR64; goto do_SseShift;
+ do_SseShift: {
+ HReg greg =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ AMD64RMI* rmi =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+ AMD64AMode* rsp0 =3D AMD64AMode_IR(0, hregAMD64_RSP());
+ HReg ereg =3D newVRegV(env);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
+ addInstr(env, AMD64Instr_Push(rmi));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, ereg, rsp0))=
;
+ addInstr(env, mk_vMOVsd_RR(greg, dst));
+ addInstr(env, AMD64Instr_SseReRg(op, ereg, dst));
+ add_to_rsp(env, 16);
+ return dst;
+ }
=20
default:
break;
|
|
From: <sv...@va...> - 2005-05-05 14:52:57
|
Author: njn
Date: 2005-05-05 15:43:31 +0100 (Thu, 05 May 2005)
New Revision: 113
Modified:
trunk/docs/pubs.html
Log:
Spell Anaheim correctly.
Modified: trunk/docs/pubs.html
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/docs/pubs.html 2005-05-02 23:33:34 UTC (rev 112)
+++ trunk/docs/pubs.html 2005-05-05 14:43:31 UTC (rev 113)
@@ -9,7 +9,7 @@
<a href=3D"/docs/memcheck2005.pdf">Using Valgrind to detect undefined v=
alue
errors with bit-precision.</a><br>
Julian Seward and Nicholas Nethercote.<br>
- Proceedings of the USENIX'05 Annual Technical Conference, Annaheim,
+ Proceedings of the USENIX'05 Annual Technical Conference, Anaheim,
California, USA, April 2005.
</p></li>
=20
|
|
From: <sv...@va...> - 2005-05-05 14:52:36
|
Author: njn Date: 2005-05-05 15:44:58 +0100 (Thu, 05 May 2005) New Revision: 114 Modified: trunk/devel/cvs_svn.html trunk/php/menu.php Log: Update for the KDE CVS->SVN switchover. Modified: trunk/devel/cvs_svn.html =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/devel/cvs_svn.html 2005-05-05 14:43:31 UTC (rev 113) +++ trunk/devel/cvs_svn.html 2005-05-05 14:44:58 UTC (rev 114) @@ -12,30 +12,36 @@ =20 The development valgrind-3.0 line is now in SVN at valgrind.org.<br /> =20 -The stable valgrind-2.4 line continues to be in CVS at kde.org, -at least for now.</p> +The stable valgrind-2.4 line continues to be kde.org, now also in SVN, a= t +least for now.</p> =20 <p>If you are doing any development work other than bug fixes for 2.4, p= lease -do them on the 3.0 line against the Subversion repository!</p> +do them on the 3.0 line against the valgrind.org repository!</p> =20 =20 <div class=3D"hr_brown"><hr/></div> <h2>The stable valgrind-2.4 line</h2> =20 <p>If you want to browse the 2.4 repository you can use the=20 -web based interface=20 -<a href=3D"http://webcvs.kde.org/cgi-bin/cvsweb.cgi/valgrind/">ViewCVS</= a>.</p> +<a href=3D"http://websvn.kde.org/trunk/valgrind/">web based interface</a= >.</p> =20 -<p>To check out code on the 2.4 line (anonymous, read-only CVS +<p>To check out code on the 2.4 line (anonymous, read-only Subversion access), follow these=20 -<a href=3D"http://developer.kde.org/source/anoncvs.html">anonymous -cvs</a> instructions. To build the result, follow the -instructions in the <code>README</code> file that the checkout -should give you.</p> +<a href=3D"http://developer.kde.org/source/anonsvn.html">anonymous +SVN</a> instructions. <br /> =20 +Or, if you want the short version, to check out the SVN trunk, run:</p> =20 +<pre> +svn co svn://anonsvn.kde.org/home/kde/trunk/valgrind/ +</pre> =20 +<p> +To build the checked out code, follow the instructions in the +<code>README</code> file that the checkout should give you.</p> =20 + + <div class=3D"hr_brown"><hr/></div> <h2>The unstable valgrind-3.0 development line</h2> =20 Modified: trunk/php/menu.php =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/php/menu.php 2005-05-05 14:43:31 UTC (rev 113) +++ trunk/php/menu.php 2005-05-05 14:44:58 UTC (rev 114) @@ -34,7 +34,7 @@ =20 $devel =3D array( array( 'url'=3D>'platforms.html', 'tag'=3D>'Supported Platforms' ), - array( 'url'=3D>'cvs_svn.html', 'tag'=3D>'CVS / SVN Repos' ), + array( 'url'=3D>'cvs_svn.html', 'tag'=3D>'SVN Repos' ), array( 'url'=3D>'guis.html', 'tag'=3D>'Front Ends / GUIs' ) /*array( 'url'=3D>'consultants.html', 'tag'=3D>'Commercial Support' )= */ ); |
|
From: <sv...@va...> - 2005-05-05 14:52:10
|
Author: njn Date: 2005-05-05 15:49:48 +0100 (Thu, 05 May 2005) New Revision: 115 Modified: trunk/devel/cvs_svn.html Log: Re-express slightly Modified: trunk/devel/cvs_svn.html =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/devel/cvs_svn.html 2005-05-05 14:44:58 UTC (rev 114) +++ trunk/devel/cvs_svn.html 2005-05-05 14:49:48 UTC (rev 115) @@ -13,7 +13,7 @@ The development valgrind-3.0 line is now in SVN at valgrind.org.<br /> =20 The stable valgrind-2.4 line continues to be kde.org, now also in SVN, a= t -least for now.</p> +least for the moment.</p> =20 <p>If you are doing any development work other than bug fixes for 2.4, p= lease do them on the 3.0 line against the valgrind.org repository!</p> |
|
From: <sv...@va...> - 2005-05-05 12:06:01
|
Author: sewardj
Date: 2005-05-05 13:05:54 +0100 (Thu, 05 May 2005)
New Revision: 1162
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
Log:
Play a few more rounds of the SSE game on amd64.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -9164,12 +9164,13 @@
//.. goto after_sse_decoders;
//..=20
//.. insn =3D (UChar*)&guest_code[delta];
-//..=20
-//.. /* 66 0F 58 =3D ADDPD -- add 32Fx4 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "addpd", Iop_Add=
64Fx2 );
-//.. goto decode_success;
-//.. }
+
+ /* 66 0F 58 =3D ADDPD -- add 32Fx4 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "addpd", Iop_Add64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 58 =3D ADDSD -- add 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58=
) {
@@ -9893,21 +9894,21 @@
goto decode_success;
}
=20
-//.. /* 66 0F 29 =3D MOVAPD -- move from G (xmm) to E (mem or xmm). *=
/
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x29) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. /* fall through; awaiting test case */
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) );
-//.. DIP("movapd %s,%s\n", nameXMMReg(gregOfRM(modrm)),
-//.. dis_buf );
-//.. delta +=3D 2+alen;
-//.. goto decode_success;
-//.. }
-//.. }
-//..=20
+ /* 66 0F 29 =3D MOVAPD -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x29=
) {
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ /* fall through; awaiting test case */
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movapd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta +=3D 2+alen;
+ goto decode_success;
+ }
+ }
+
//.. /* 66 0F 6E =3D MOVD from r/m32 to xmm, zeroing high 3/4 of xmm.=
*/
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x6E) {
//.. modrm =3D getUChar(delta+2);
@@ -10028,42 +10029,42 @@
//.. /* fall through, apparently no mem case for this insn */
//.. }
//.. }
-//..=20
-//.. /* 66 0F 16 =3D MOVHPD -- move from mem to high half of XMM. */
-//.. /* These seems identical to MOVHPS. This instruction encoding i=
s
-//.. completely crazy. */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x16) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. /* fall through; apparently reg-reg is not possible */
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//.. putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
-//.. loadLE(Ity_I64, mkexpr(addr)) );
-//.. DIP("movhpd %s,%s\n", dis_buf,=20
-//.. nameXMMReg( gregOfRM(modrm) ));
-//.. goto decode_success;
-//.. }
-//.. }
-//..=20
-//.. /* 66 0F 17 =3D MOVHPD -- move from high half of XMM to mem. */
-//.. /* Again, this seems identical to MOVHPS. */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x17) {
-//.. if (!epartIsReg(insn[2])) {
-//.. delta +=3D 2;
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. delta +=3D alen;
-//.. storeLE( mkexpr(addr),=20
-//.. getXMMRegLane64( gregOfRM(insn[2]),
-//.. 1/*upper lane*/ ) );
-//.. DIP("movhpd %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ),
-//.. dis_buf);
-//.. goto decode_success;
-//.. }
-//.. /* else fall through */
-//.. }
=20
+ /* 66 0F 16 =3D MOVHPD -- move from mem to high half of XMM. */
+ /* These seems identical to MOVHPS. This instruction encoding is
+ completely crazy. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x16=
) {
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ /* fall through; apparently reg-reg is not possible */
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movhpd %s,%s\n", dis_buf,=20
+ nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ goto decode_success;
+ }
+ }
+
+ /* 66 0F 17 =3D MOVHPD -- move from high half of XMM to mem. */
+ /* Again, this seems identical to MOVHPS. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x17=
) {
+ if (!epartIsReg(insn[2])) {
+ delta +=3D 2;
+ addr =3D disAMode ( &alen, pfx, delta, dis_buf, 0 );
+ delta +=3D alen;
+ storeLE( mkexpr(addr),=20
+ getXMMRegLane64( gregOfRexRM(pfx,insn[2]),
+ 1/*upper lane*/ ) );
+ DIP("movhpd %s,%s\n", nameXMMReg( gregOfRexRM(pfx,insn[2]) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
/* 66 0F 12 =3D MOVLPD -- move from mem to low half of XMM. */
/* Identical to MOVLPS ? */
if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x12=
) {
@@ -10082,23 +10083,23 @@
}
}
=20
-//.. /* 66 0F 13 =3D MOVLPD -- move from low half of XMM to mem. */
-//.. /* Identical to MOVLPS ? */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x13) {
-//.. if (!epartIsReg(insn[2])) {
-//.. delta +=3D 2;
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. delta +=3D alen;
-//.. storeLE( mkexpr(addr),=20
-//.. getXMMRegLane64( gregOfRM(insn[2]),=20
-//.. 0/*lower lane*/ ) );
-//.. DIP("movlpd %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ),
-//.. dis_buf);
-//.. goto decode_success;
-//.. }
-//.. /* else fall through */
-//.. }
-//..=20
+ /* 66 0F 13 =3D MOVLPD -- move from low half of XMM to mem. */
+ /* Identical to MOVLPS ? */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x13=
) {
+ modrm =3D getUChar(delta+2);
+ if (!epartIsReg(modrm)) {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ storeLE( mkexpr(addr),=20
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),=20
+ 0/*lower lane*/ ) );
+ DIP("movlpd %s, %s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
//.. /* 66 0F 50 =3D MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(=
E) to
//.. 2 lowest bits of ireg(G) */
//.. if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x50) {
@@ -10237,11 +10238,12 @@
}
}
=20
-//.. /* 66 0F 59 =3D MULPD -- mul 64Fx2 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x59) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "mulpd", Iop_Mul=
64Fx2 );
-//.. goto decode_success;
-//.. }
+ /* 66 0F 59 =3D MULPD -- mul 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x59) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "mulpd", Iop_Mul64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 59 =3D MULSD -- mul 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && sz =3D=3D 4
@@ -10321,11 +10323,12 @@
goto decode_success;
}
=20
-//.. /* 66 0F 5C =3D SUBPD -- sub 64Fx2 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "subpd", Iop_Sub=
64Fx2 );
-//.. goto decode_success;
-//.. }
+ /* 66 0F 5C =3D SUBPD -- sub 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "subpd", Iop_Sub64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 5C =3D SUBSD -- sub 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C=
) {
@@ -11836,11 +11839,12 @@
goto decode_failure;
}
=20
-//.. /* ------------------------ opl imm, A ----------------- */
-//..=20
-//.. case 0x04: /* ADD Ib, AL */
-//.. delta =3D dis_op_imm_A( 1, Iop_Add8, True, delta, "add" );
-//.. break;
+ /* ------------------------ opl imm, A ----------------- */
+
+ case 0x04: /* ADD Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta =3D dis_op_imm_A( 1, Iop_Add8, True, delta, "add" );
+ break;
case 0x05: /* ADD Iv, eAX */
if (haveF2orF3(pfx)) goto decode_failure;
delta =3D dis_op_imm_A(sz, Iop_Add8, True, delta, "add" );
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -966,15 +966,15 @@
vassert(op !=3D Asse_MOV);
return i;
}
-//.. AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp op, HReg src, HReg dst=
) {
-//.. AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag =3D Xin_Sse64Fx2;
-//.. i->Xin.Sse64Fx2.op =3D op;
-//.. i->Xin.Sse64Fx2.src =3D src;
-//.. i->Xin.Sse64Fx2.dst =3D dst;
-//.. vassert(op !=3D Xsse_MOV);
-//.. return i;
-//.. }
+AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp op, HReg src, HReg dst ) {
+ AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag =3D Ain_Sse64Fx2;
+ i->Ain.Sse64Fx2.op =3D op;
+ i->Ain.Sse64Fx2.src =3D src;
+ i->Ain.Sse64Fx2.dst =3D dst;
+ vassert(op !=3D Asse_MOV);
+ return i;
+}
AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
i->tag =3D Ain_Sse64FLo;
@@ -1279,12 +1279,12 @@
vex_printf(",");
ppHRegAMD64(i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. vex_printf("%spd ", showAMD64SseOp(i->Xin.Sse64Fx2.op));
-//.. ppHRegAMD64(i->Xin.Sse64Fx2.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ vex_printf("%spd ", showAMD64SseOp(i->Ain.Sse64Fx2.op));
+ ppHRegAMD64(i->Ain.Sse64Fx2.src);
+ vex_printf(",");
+ ppHRegAMD64(i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
vex_printf("%ssd ", showAMD64SseOp(i->Ain.Sse64FLo.op));
ppHRegAMD64(i->Ain.Sse64FLo.src);
@@ -1537,15 +1537,15 @@
addHRegUse(u, unary ? HRmWrite : HRmModify,=20
i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. vassert(i->Xin.Sse64Fx2.op !=3D Xsse_MOV);
-//.. unary =3D i->Xin.Sse64Fx2.op =3D=3D Xsse_RCPF
-//.. || i->Xin.Sse64Fx2.op =3D=3D Xsse_RSQRTF
-//.. || i->Xin.Sse64Fx2.op =3D=3D Xsse_SQRTF;
-//.. addHRegUse(u, HRmRead, i->Xin.Sse64Fx2.src);
-//.. addHRegUse(u, unary ? HRmWrite : HRmModify,=20
-//.. i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ vassert(i->Ain.Sse64Fx2.op !=3D Asse_MOV);
+ unary =3D i->Ain.Sse64Fx2.op =3D=3D Asse_RCPF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_RSQRTF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_SQRTF;
+ addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
+ addHRegUse(u, unary ? HRmWrite : HRmModify,=20
+ i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
vassert(i->Ain.Sse64FLo.op !=3D Asse_MOV);
unary =3D toBool( i->Ain.Sse64FLo.op =3D=3D Asse_RCPF
@@ -1721,10 +1721,10 @@
mapReg(m, &i->Ain.Sse32FLo.src);
mapReg(m, &i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. mapReg(m, &i->Xin.Sse64Fx2.src);
-//.. mapReg(m, &i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ mapReg(m, &i->Ain.Sse64Fx2.src);
+ mapReg(m, &i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
mapReg(m, &i->Ain.Sse64FLo.src);
mapReg(m, &i->Ain.Sse64FLo.dst);
@@ -3100,30 +3100,33 @@
*p++ =3D toUChar(xtra & 0xFF);
goto done;
=20
-//.. case Xin_Sse64Fx2:
-//.. xtra =3D 0;
-//.. *p++ =3D 0x66;
-//.. *p++ =3D 0x0F;
-//.. switch (i->Xin.Sse64Fx2.op) {
-//.. case Xsse_ADDF: *p++ =3D 0x58; break;
+ case Ain_Sse64Fx2:
+ xtra =3D 0;
+ *p++ =3D 0x66;
+ *p++ =3D clearWBit(
+ rexAMode_R( vreg2ireg(i->Ain.Sse64Fx2.dst),
+ vreg2ireg(i->Ain.Sse64Fx2.src) ));
+ *p++ =3D 0x0F;
+ switch (i->Ain.Sse64Fx2.op) {
+ case Asse_ADDF: *p++ =3D 0x58; break;
//.. case Xsse_DIVF: *p++ =3D 0x5E; break;
//.. case Xsse_MAXF: *p++ =3D 0x5F; break;
//.. case Xsse_MINF: *p++ =3D 0x5D; break;
-//.. case Xsse_MULF: *p++ =3D 0x59; break;
+ case Asse_MULF: *p++ =3D 0x59; break;
//.. case Xsse_RCPF: *p++ =3D 0x53; break;
//.. case Xsse_RSQRTF: *p++ =3D 0x52; break;
//.. case Xsse_SQRTF: *p++ =3D 0x51; break;
-//.. case Xsse_SUBF: *p++ =3D 0x5C; break;
+ case Asse_SUBF: *p++ =3D 0x5C; break;
//.. case Xsse_CMPEQF: *p++ =3D 0xC2; xtra =3D 0x100; break;
//.. case Xsse_CMPLTF: *p++ =3D 0xC2; xtra =3D 0x101; break;
//.. case Xsse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
-//.. default: goto bad;
-//.. }
-//.. p =3D doAMode_R(p, fake(vregNo(i->Xin.Sse64Fx2.dst)),
-//.. fake(vregNo(i->Xin.Sse64Fx2.src)) );
-//.. if (xtra & 0x100)
-//.. *p++ =3D (UChar)(xtra & 0xFF);
-//.. goto done;
+ default: goto bad;
+ }
+ p =3D doAMode_R(p, vreg2ireg(i->Ain.Sse64Fx2.dst),
+ vreg2ireg(i->Ain.Sse64Fx2.src) );
+ if (xtra & 0x100)
+ *p++ =3D (UChar)(xtra & 0xFF);
+ goto done;
=20
case Ain_Sse32FLo:
xtra =3D 0;
@@ -3144,7 +3147,7 @@
case Asse_SUBF: *p++ =3D 0x5C; break;
//.. case Xsse_CMPEQF: *p++ =3D 0xC2; xtra =3D 0x100; break;
case Asse_CMPLTF: *p++ =3D 0xC2; xtra =3D 0x101; break;
-//.. case Xsse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
+ case Asse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
default: goto bad;
}
p =3D doAMode_R(p, vreg2ireg(i->Ain.Sse32FLo.dst),
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/hdefs.h 2005-05-05 12:05:54 UTC (rev 1162)
@@ -393,7 +393,7 @@
Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg *=
/
Ain_Sse32Fx4, /* SSE binary, 32Fx4 */
Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */
-//.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */
+ Ain_Sse64Fx2, /* SSE binary, 64Fx2 */
Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */
Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */
Ain_SseCMov, /* SSE conditional move */
@@ -620,15 +620,15 @@
HReg src;
HReg dst;
} Sse32FLo;
-//.. struct {
-//.. X86SseOp op;
-//.. HReg src;
-//.. HReg dst;
-//.. } Sse64Fx2;
struct {
AMD64SseOp op;
HReg src;
HReg dst;
+ } Sse64Fx2;
+ struct {
+ AMD64SseOp op;
+ HReg src;
+ HReg dst;
} Sse64FLo;
struct {
AMD64SseOp op;
@@ -691,7 +691,7 @@
extern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* );
extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg );
-//.. extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg );
+extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg =
dst );
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/isel.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -3272,26 +3272,25 @@
//.. case Iop_CmpEQ64Fx2: op =3D Xsse_CMPEQF; goto do_64Fx2;
//.. case Iop_CmpLT64Fx2: op =3D Xsse_CMPLTF; goto do_64Fx2;
//.. case Iop_CmpLE64Fx2: op =3D Xsse_CMPLEF; goto do_64Fx2;
-//.. case Iop_Add64Fx2: op =3D Xsse_ADDF; goto do_64Fx2;
+ case Iop_Add64Fx2: op =3D Asse_ADDF; goto do_64Fx2;
//.. case Iop_Div64Fx2: op =3D Xsse_DIVF; goto do_64Fx2;
//.. case Iop_Max64Fx2: op =3D Xsse_MAXF; goto do_64Fx2;
//.. case Iop_Min64Fx2: op =3D Xsse_MINF; goto do_64Fx2;
-//.. case Iop_Mul64Fx2: op =3D Xsse_MULF; goto do_64Fx2;
-//.. case Iop_Sub64Fx2: op =3D Xsse_SUBF; goto do_64Fx2;
-//.. do_64Fx2:
-//.. {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse64Fx2(op, argR, dst));
-//.. return dst;
-//.. }
+ case Iop_Mul64Fx2: op =3D Asse_MULF; goto do_64Fx2;
+ case Iop_Sub64Fx2: op =3D Asse_SUBF; goto do_64Fx2;
+ do_64Fx2:
+ {
+ HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(argL, dst));
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
+ return dst;
+ }
=20
//.. case Iop_CmpEQ32F0x4: op =3D Xsse_CMPEQF; goto do_32F0x4;
case Iop_CmpLT32F0x4: op =3D Asse_CMPLTF; goto do_32F0x4;
-//.. case Iop_CmpLE32F0x4: op =3D Xsse_CMPLEF; goto do_32F0x4;
+ case Iop_CmpLE32F0x4: op =3D Asse_CMPLEF; goto do_32F0x4;
case Iop_Add32F0x4: op =3D Asse_ADDF; goto do_32F0x4;
case Iop_Div32F0x4: op =3D Asse_DIVF; goto do_32F0x4;
case Iop_Max32F0x4: op =3D Asse_MAXF; goto do_32F0x4;
|
|
From: <sv...@va...> - 2005-05-05 12:05:16
|
Author: sewardj
Date: 2005-05-05 13:05:11 +0100 (Thu, 05 May 2005)
New Revision: 1161
Modified:
trunk/priv/guest-amd64/ghelpers.c
Log:
More %flags-helpers tuning.
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2005-05-05 12:04:14 UTC (rev 1160)
+++ trunk/priv/guest-amd64/ghelpers.c 2005-05-05 12:05:11 UTC (rev 1161)
@@ -696,6 +696,8 @@
=20
/* Fast-case some common ones. */
switch (cc_op) {
+ case AMD64G_CC_OP_COPY:
+ return (cc_dep1 >> AMD64G_CC_SHIFT_C) & 1;
case AMD64G_CC_OP_LOGICQ:=20
case AMD64G_CC_OP_LOGICL:=20
case AMD64G_CC_OP_LOGICW:=20
@@ -1045,37 +1047,37 @@
//.. /* SHRL, then Z --> test dep1 =3D=3D 0 */
//.. return unop(Iop_1Uto32,binop(Iop_CmpEQ32, cc_dep1, mkU32(0=
)));
//.. }
-//..=20
-//.. /*---------------- COPY ----------------*/
-//.. /* This can happen, as a result of x87 FP compares: "fcom ...=
;
-//.. fnstsw %ax ; sahf ; jbe" for example. */
-//..=20
-//.. if (isU32(cc_op, AMD64G_CC_OP_COPY) &&=20
-//.. (isU32(cond, X86CondBE) || isU32(cond, X86CondNBE))) {
-//.. /* COPY, then BE --> extract C and Z from dep1, and test (=
C
-//.. or Z =3D=3D 1). */
-//.. /* COPY, then NBE --> extract C and Z from dep1, and test =
(C
-//.. or Z =3D=3D 0). */
-//.. UInt nnn =3D isU32(cond, X86CondBE) ? 1 : 0;
-//.. return
-//.. unop(
-//.. Iop_1Uto32,
-//.. binop(
-//.. Iop_CmpEQ32,
-//.. binop(
-//.. Iop_And32,
-//.. binop(
-//.. Iop_Or32,
-//.. binop(Iop_Shr32, cc_dep1, mkU8(AMD64G_CC_SH=
IFT_C)),
-//.. binop(Iop_Shr32, cc_dep1, mkU8(AMD64G_CC_SH=
IFT_Z))
-//.. ),
-//.. mkU32(1)
-//.. ),
-//.. mkU32(nnn)
-//.. )
-//.. );
-//.. }
-//.. =20
+
+ /*---------------- COPY ----------------*/
+ /* This can happen, as a result of amd64 FP compares: "comisd ... =
;
+ jbe" for example. */
+
+ if (isU64(cc_op, AMD64G_CC_OP_COPY) &&=20
+ (isU64(cond, AMD64CondBE) || isU64(cond, AMD64CondNBE))) {
+ /* COPY, then BE --> extract C and Z from dep1, and test (C
+ or Z =3D=3D 1). */
+ /* COPY, then NBE --> extract C and Z from dep1, and test (C
+ or Z =3D=3D 0). */
+ ULong nnn =3D isU64(cond, AMD64CondBE) ? 1 : 0;
+ return
+ unop(
+ Iop_1Uto64,
+ binop(
+ Iop_CmpEQ64,
+ binop(
+ Iop_And64,
+ binop(
+ Iop_Or64,
+ binop(Iop_Shr64, cc_dep1, mkU8(AMD64G_CC_SHIFT_C=
)),
+ binop(Iop_Shr64, cc_dep1, mkU8(AMD64G_CC_SHIFT_Z=
))
+ ),
+ mkU64(1)
+ ),
+ mkU64(nnn)
+ )
+ );
+ }
+ =20
//.. if (isU32(cc_op, AMD64G_CC_OP_COPY) && isU32(cond, X86CondB))=
{
//.. /* COPY, then B --> extract C dep1, and test (C =3D=3D 1).=
*/
//.. return
@@ -1133,13 +1135,13 @@
/* If the thunk is dec or inc, the cflag is supplied as CC_NDEP=
. */
return cc_ndep;
}
-//.. if (isU32(cc_op, AMD64G_CC_OP_COPY)) {
+//.. if (isU64(cc_op, AMD64G_CC_OP_COPY)) {
//.. /* cflag after COPY is stored in DEP1. */
//.. return
//.. binop(
-//.. Iop_And32,
-//.. binop(Iop_Shr32, cc_dep1, mkU8(AMD64G_CC_SHIFT_C)),
-//.. mkU32(1)
+//.. Iop_And64,
+//.. binop(Iop_Shr64, cc_dep1, mkU8(AMD64G_CC_SHIFT_C)),
+//.. mkU64(1)
//.. );
//.. }
//.. # if 0
|
|
From: <sv...@va...> - 2005-05-05 12:04:23
|
Author: sewardj
Date: 2005-05-05 13:04:14 +0100 (Thu, 05 May 2005)
New Revision: 1160
Modified:
trunk/priv/guest-x86/toIR.c
Log:
Update comment.
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2005-05-03 12:20:15 UTC (rev 1159)
+++ trunk/priv/guest-x86/toIR.c 2005-05-05 12:04:14 UTC (rev 1160)
@@ -34,8 +34,12 @@
*/
=20
/* TODO:
- SBB reg with itself (copy from amd64 front end)
=20
+ Check the following. It afflicts the amd64 front end, not sure if
+ applicable here: MOVQ (sse) is wrong wrt is the upper half zeroed
+ or not? It always should be if dst is a reg; not quite the same as
+ MOVSD.
+
check flag settings for cmpxchg
FUCOMI(P): what happens to A and S flags? Currently are forced
to zero.
@@ -77,8 +81,7 @@
The delta values are 32-bit ints, not 64-bit ints. That means
this module may not work right if run on a 64-bit host. That should
be fixed properly, really -- if anyone ever wants to use Vex to
- translate x86 code for execution on a 64-bit host.
-*/
+ translate x86 code for execution on a 64-bit host. */
=20
/* Performance holes:
=20
|
|
From: <sv...@va...> - 2005-05-05 08:26:18
|
Author: tom
Date: 2005-05-05 09:26:14 +0100 (Thu, 05 May 2005)
New Revision: 3623
Modified:
trunk/coregrind/m_sigframe/sigframe-x86-linux.c
Log:
It helps if my changes actually compile...
Modified: trunk/coregrind/m_sigframe/sigframe-x86-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_sigframe/sigframe-x86-linux.c 2005-05-05 08:16:24 U=
TC (rev 3622)
+++ trunk/coregrind/m_sigframe/sigframe-x86-linux.c 2005-05-05 08:26:14 U=
TC (rev 3623)
@@ -682,7 +682,7 @@
else
size =3D restore_rt_sigframe(tst, (struct rt_sigframe *)esp, &sigN=
o);
=20
- VG_TRACK( die_mem_stack_signal - VGA_STACK_REDZONE_SIZE, esp, size );
+ VG_TRACK( die_mem_stack_signal, esp - VGA_STACK_REDZONE_SIZE, size );
=20
if (VG_(clo_trace_signals))
VG_(message)(
|
|
From: <sv...@va...> - 2005-05-05 08:16:36
|
Author: tom
Date: 2005-05-05 09:16:24 +0100 (Thu, 05 May 2005)
New Revision: 3622
Modified:
trunk/coregrind/m_sigframe/sigframe-amd64-linux.c
trunk/coregrind/m_sigframe/sigframe-x86-linux.c
trunk/coregrind/vg_signals.c
Log:
Allow for the red zone when generating new_mem_stack_signal and
die_mem_stack_signal events.
Modified: trunk/coregrind/m_sigframe/sigframe-amd64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_sigframe/sigframe-amd64-linux.c 2005-05-05 01:37:46=
UTC (rev 3621)
+++ trunk/coregrind/m_sigframe/sigframe-amd64-linux.c 2005-05-05 08:16:24=
UTC (rev 3622)
@@ -404,7 +404,7 @@
=20
/* For tracking memory events, indicate the entire frame has been
allocated. */
- VG_TRACK( new_mem_stack_signal, addr, size );
+ VG_TRACK( new_mem_stack_signal, addr - VGA_STACK_REDZONE_SIZE, size )=
;
=20
return True;
}
@@ -600,7 +600,7 @@
=20
size =3D restore_rt_sigframe(tst, (struct rt_sigframe *)rsp, &sigNo);
=20
- VG_TRACK( die_mem_stack_signal, rsp, size );
+ VG_TRACK( die_mem_stack_signal, rsp - VGA_STACK_REDZONE_SIZE, size );
=20
if (VG_(clo_trace_signals))
VG_(message)(
Modified: trunk/coregrind/m_sigframe/sigframe-x86-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_sigframe/sigframe-x86-linux.c 2005-05-05 01:37:46 U=
TC (rev 3621)
+++ trunk/coregrind/m_sigframe/sigframe-x86-linux.c 2005-05-05 08:16:24 U=
TC (rev 3622)
@@ -425,7 +425,7 @@
=20
/* For tracking memory events, indicate the entire frame has been
allocated. */
- VG_TRACK( new_mem_stack_signal, addr, size );
+ VG_TRACK( new_mem_stack_signal, addr - VGA_STACK_REDZONE_SIZE, size )=
;
=20
return True;
}
@@ -682,7 +682,7 @@
else
size =3D restore_rt_sigframe(tst, (struct rt_sigframe *)esp, &sigN=
o);
=20
- VG_TRACK( die_mem_stack_signal, esp, size );
+ VG_TRACK( die_mem_stack_signal - VGA_STACK_REDZONE_SIZE, esp, size );
=20
if (VG_(clo_trace_signals))
VG_(message)(
Modified: trunk/coregrind/vg_signals.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_signals.c 2005-05-05 01:37:46 UTC (rev 3621)
+++ trunk/coregrind/vg_signals.c 2005-05-05 08:16:24 UTC (rev 3622)
@@ -474,6 +474,10 @@
VG_(threads)[tid].altstack.ss_sp =3D ss->ss_sp;
VG_(threads)[tid].altstack.ss_size =3D ss->ss_size;
VG_(threads)[tid].altstack.ss_flags =3D 0;
+
+ VG_TRACK( new_mem_stack_signal,
+ ss->ss_sp + ss->ss_size - VGA_STACK_REDZONE_SIZE,
+ VGA_STACK_REDZONE_SIZE );
}
}
SET_SYSCALL_RETVAL(tid, 0);
|
|
From: <js...@ac...> - 2005-05-05 03:04:09
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-05-05 03:50:00 BST Checking out source tree ... done Configuring ... done Building ... done Running regression tests ... done Last 20 lines of log.verbose follow insn_mmxext: (skipping, prereq failed: ../../../tests/cputest x86-mmxext) insn_sse: valgrind ./insn_sse insn_sse2: (skipping, prereq failed: ../../../tests/cputest x86-sse2) int: valgrind ./int pushpopseg: valgrind ./pushpopseg rcl_assert: valgrind ./rcl_assert seg_override: valgrind ./seg_override -- Finished tests in none/tests/x86 ------------------------------------ yield: valgrind ./yield -- Finished tests in none/tests ---------------------------------------- == 201 tests, 5 stderr failures, 1 stdout failure ================= memcheck/tests/pth_once (stderr) memcheck/tests/scalar (stderr) memcheck/tests/threadederrno (stderr) memcheck/tests/writev (stderr) corecheck/tests/fdleak_fcntl (stderr) none/tests/map_unmap (stdout) make: *** [regtest] Error 1 |
|
From: Tom H. <to...@co...> - 2005-05-05 02:36:21
|
Nightly build on dunsmere ( athlon, Fedora Core 3 ) started at 2005-05-05 03:30:03 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 175 tests, 167 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/badaddrvalue (stderr) memcheck/tests/badfree-2trace (stderr) memcheck/tests/badfree (stderr) memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/badloop (stderr) memcheck/tests/badpoll (stderr) memcheck/tests/badrw (stderr) memcheck/tests/brk (stderr) memcheck/tests/brk2 (stderr) memcheck/tests/buflen_check (stderr) memcheck/tests/clientperm (stderr) memcheck/tests/custom_alloc (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/doublefree (stderr) memcheck/tests/error_counts (stdout) memcheck/tests/errs1 (stderr) memcheck/tests/execve (stderr) memcheck/tests/execve2 (stderr) memcheck/tests/exitprog (stderr) memcheck/tests/fprw (stderr) memcheck/tests/fwrite (stderr) memcheck/tests/inits (stderr) memcheck/tests/inline (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/malloc1 (stderr) memcheck/tests/malloc2 (stderr) memcheck/tests/malloc3 (stderr) memcheck/tests/manuel1 (stderr) memcheck/tests/manuel2 (stderr) memcheck/tests/manuel3 (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/memalign2 (stderr) memcheck/tests/memalign_test (stderr) memcheck/tests/memcmptest (stderr) memcheck/tests/mempool (stderr) memcheck/tests/mismatches (stderr) memcheck/tests/mmaptest (stderr) memcheck/tests/nanoleak (stderr) memcheck/tests/nanoleak_supp (stderr) memcheck/tests/new_nothrow (stderr) memcheck/tests/new_override (stderr) memcheck/tests/null_socket (stderr) memcheck/tests/overlap (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/post-syscall (stderr) memcheck/tests/realloc1 (stderr) memcheck/tests/realloc2 (stderr) memcheck/tests/realloc3 (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/signal2 (stderr) memcheck/tests/sigprocmask (stderr) memcheck/tests/str_tester (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp2 (stderr) memcheck/tests/suppfree (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/trivialleak (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/writev (stderr) memcheck/tests/x86/fpeflags (stderr) memcheck/tests/x86/pushfpopf (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_exit_group (stderr) memcheck/tests/x86/scalar_fork (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/scalar_vfork (stderr) memcheck/tests/x86/tronical (stderr) memcheck/tests/zeropage (stderr) cachegrind/tests/chdir (stderr) cachegrind/tests/dlclose (stderr) cachegrind/tests/x86/fpu-28-108 (stderr) corecheck/tests/as_mmap (stderr) corecheck/tests/as_shm (stderr) corecheck/tests/erringfds (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/fdleak_creat (stderr) corecheck/tests/fdleak_dup (stderr) corecheck/tests/fdleak_dup2 (stderr) corecheck/tests/fdleak_fcntl (stderr) corecheck/tests/fdleak_ipv4 (stderr) corecheck/tests/fdleak_open (stderr) corecheck/tests/fdleak_pipe (stderr) corecheck/tests/fdleak_socketpair (stderr) corecheck/tests/pth_atfork1 (stderr) corecheck/tests/pth_cancel1 (stderr) corecheck/tests/pth_cancel2 (stderr) corecheck/tests/pth_cvsimple (stderr) corecheck/tests/pth_empty (stderr) corecheck/tests/pth_exit (stderr) corecheck/tests/pth_exit2 (stderr) corecheck/tests/pth_mutexspeed (stderr) corecheck/tests/pth_once (stderr) corecheck/tests/pth_rwlock (stderr) corecheck/tests/res_search (stderr) corecheck/tests/sigkill (stderr) corecheck/tests/threadederrno (stderr) corecheck/tests/vgprintf (stderr) massif/tests/toobig-allocs (stderr) massif/tests/true_html (stderr) massif/tests/true_text (stderr) lackey/tests/true (stderr) none/tests/args (stderr) none/tests/async-sigs (stderr) none/tests/bitfield1 (stderr) none/tests/blockfault (stderr) none/tests/closeall (stderr) none/tests/coolo_sigaction (stderr) none/tests/coolo_strlen (stderr) none/tests/discard (stderr) none/tests/exec-sigmask (stderr) none/tests/execve (stderr) none/tests/faultstatus (stderr) none/tests/fcntl_setown (stderr) none/tests/floored (stderr) none/tests/fork (stderr) none/tests/fucomip (stderr) none/tests/gxx304 (stderr) none/tests/manythreads (stderr) none/tests/map_unaligned (stderr) none/tests/map_unmap (stderr) none/tests/mq (stderr) none/tests/mremap (stderr) none/tests/munmap_exe (stderr) none/tests/pending (stderr) none/tests/pth_blockedsig (stderr) none/tests/pth_stackalign (stderr) none/tests/rcrl (stderr) none/tests/readline1 (stderr) none/tests/resolv (stderr) none/tests/rlimit_nofile (stderr) none/tests/selfrun (stdout) none/tests/selfrun (stderr) none/tests/sem (stderr) none/tests/semlimit (stderr) none/tests/sha1_test (stderr) none/tests/shortpush (stderr) none/tests/shorts (stderr) none/tests/sigstackgrowth (stderr) none/tests/smc1 (stderr) none/tests/stackgrowth (stderr) none/tests/syscall-restart1 (stderr) none/tests/syscall-restart2 (stderr) none/tests/system (stderr) none/tests/thread-exits (stderr) none/tests/threaded-fork (stderr) none/tests/tls (stderr) none/tests/x86/badseg (stderr) none/tests/x86/bt_everything (stderr) none/tests/x86/bt_literal (stderr) none/tests/x86/cpuid (stderr) none/tests/x86/fpu_lazy_eflags (stderr) none/tests/x86/getseg (stderr) none/tests/x86/insn_basic (stderr) none/tests/x86/insn_cmov (stderr) none/tests/x86/insn_fpu (stderr) none/tests/x86/insn_mmx (stderr) none/tests/x86/insn_mmxext (stderr) none/tests/x86/insn_sse (stderr) none/tests/x86/int (stderr) none/tests/x86/pushpopseg (stderr) none/tests/x86/seg_override (stderr) none/tests/x86/sigcontext (stderr) none/tests/yield (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-05 02:30:45
|
Nightly build on audi ( i686, Red Hat 9 ) started at 2005-05-05 03:25:01 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 174 tests, 4 stderr failures, 0 stdout failures ================= memcheck/tests/x86/scalar (stderr) corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-05 02:25:44
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-05-05 03:20:02 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 173 tests, 4 stderr failures, 0 stdout failures ================= memcheck/tests/x86/scalar (stderr) corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-05 02:21:15
|
Nightly build on honda ( x86_64, Fedora Core 3 ) started at 2005-05-05 03:10:03 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 150 tests, 26 stderr failures, 4 stdout failures ================= memcheck/tests/badjump2 (stderr) memcheck/tests/badloop (stderr) memcheck/tests/brk (stderr) memcheck/tests/error_counts (stdout) memcheck/tests/fwrite (stderr) memcheck/tests/inits (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/manuel1 (stderr) memcheck/tests/post-syscall (stderr) memcheck/tests/signal2 (stderr) memcheck/tests/sigprocmask (stderr) memcheck/tests/supp2 (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/weirdioctl (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/fdleak_creat (stderr) corecheck/tests/fdleak_dup (stderr) corecheck/tests/fdleak_dup2 (stderr) corecheck/tests/fdleak_fcntl (stderr) corecheck/tests/fdleak_ipv4 (stderr) corecheck/tests/fdleak_open (stderr) corecheck/tests/fdleak_pipe (stderr) corecheck/tests/fdleak_socketpair (stderr) massif/tests/toobig-allocs (stderr) none/tests/faultstatus (stderr) none/tests/selfrun (stdout) none/tests/selfrun (stderr) none/tests/yield (stdout) |
|
From: Tom H. <th...@cy...> - 2005-05-05 02:20:28
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-05-05 03:15:01 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 173 tests, 13 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/x86/scalar (stderr) corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-05 02:04:53
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-05-05 03:00:04 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 150 tests, 77 stderr failures, 3 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/badaddrvalue (stderr) memcheck/tests/badfree-2trace (stderr) memcheck/tests/badfree (stderr) memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/badloop (stderr) memcheck/tests/badpoll (stderr) memcheck/tests/badrw (stderr) memcheck/tests/brk (stderr) memcheck/tests/brk2 (stderr) memcheck/tests/buflen_check (stderr) memcheck/tests/clientperm (stderr) memcheck/tests/custom_alloc (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/doublefree (stderr) memcheck/tests/error_counts (stdout) memcheck/tests/errs1 (stderr) memcheck/tests/execve (stderr) memcheck/tests/execve2 (stderr) memcheck/tests/exitprog (stderr) memcheck/tests/fprw (stderr) memcheck/tests/fwrite (stderr) memcheck/tests/inits (stderr) memcheck/tests/inline (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/malloc1 (stderr) memcheck/tests/malloc2 (stderr) memcheck/tests/malloc3 (stderr) memcheck/tests/manuel1 (stderr) memcheck/tests/manuel2 (stderr) memcheck/tests/manuel3 (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/memalign2 (stderr) memcheck/tests/memalign_test (stderr) memcheck/tests/memcmptest (stderr) memcheck/tests/mempool (stderr) memcheck/tests/mismatches (stderr) memcheck/tests/mmaptest (stderr) memcheck/tests/nanoleak (stderr) memcheck/tests/nanoleak_supp (stderr) memcheck/tests/new_nothrow (stderr) memcheck/tests/new_override (stderr) memcheck/tests/null_socket (stderr) memcheck/tests/overlap (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/post-syscall (stderr) memcheck/tests/realloc1 (stderr) memcheck/tests/realloc2 (stderr) memcheck/tests/realloc3 (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/signal2 (stderr) memcheck/tests/sigprocmask (stderr) memcheck/tests/str_tester (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp2 (stderr) memcheck/tests/suppfree (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/trivialleak (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/writev (stderr) memcheck/tests/zeropage (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/fdleak_creat (stderr) corecheck/tests/fdleak_dup (stderr) corecheck/tests/fdleak_dup2 (stderr) corecheck/tests/fdleak_fcntl (stderr) corecheck/tests/fdleak_ipv4 (stderr) corecheck/tests/fdleak_open (stderr) corecheck/tests/fdleak_pipe (stderr) corecheck/tests/fdleak_socketpair (stderr) massif/tests/toobig-allocs (stderr) none/tests/faultstatus (stderr) none/tests/selfrun (stdout) none/tests/selfrun (stderr) |
|
From: <sv...@va...> - 2005-05-05 01:37:50
|
Author: sewardj Date: 2005-05-05 02:37:46 +0100 (Thu, 05 May 2005) New Revision: 3621 Added: trunk/memcheck/tests/leak-tree.stderr.exp64 Modified: trunk/memcheck/tests/Makefile.am Log: Add expected output file for 64-bit platforms. Modified: trunk/memcheck/tests/Makefile.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/Makefile.am 2005-05-05 01:32:24 UTC (rev 3620) +++ trunk/memcheck/tests/Makefile.am 2005-05-05 01:37:46 UTC (rev 3621) @@ -34,7 +34,7 @@ inline.stderr.exp inline.stdout.exp inline.vgtest \ leak-0.vgtest leak-0.stderr.exp \ leak-cycle.vgtest leak-cycle.stderr.exp leak-cycle.stderr.exp64 \ - leak-tree.vgtest leak-tree.stderr.exp \ + leak-tree.vgtest leak-tree.stderr.exp leak-tree.stderr.exp64 \ leak-regroot.vgtest leak-regroot.stderr.exp \ leakotron.vgtest leakotron.stdout.exp leakotron.stderr.exp \ malloc1.stderr.exp malloc1.vgtest \ Added: trunk/memcheck/tests/leak-tree.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/leak-tree.stderr.exp64 2005-05-05 01:32:24 UTC (= rev 3620) +++ trunk/memcheck/tests/leak-tree.stderr.exp64 2005-05-05 01:37:46 UTC (= rev 3621) @@ -0,0 +1,52 @@ + +searching for pointers to 11 not-freed blocks. +checked ... bytes. + +80 (16 direct, 64 indirect) bytes in 1 blocks are definitely lost in los= s record 11 of 11 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-tree.c:11) + by 0x........: main (leak-tree.c:25) + +LEAK SUMMARY: + definitely lost: 16 bytes in 1 blocks. + indirectly lost: 64 bytes in 4 blocks. + possibly lost: 0 bytes in 0 blocks. + still reachable: 96 bytes in 6 blocks. + suppressed: 0 bytes in 0 blocks. +Reachable blocks (those to which a pointer was found) are not shown. +To see them, rerun with: --show-reachable=3Dyes +searching for pointers to 14 not-freed blocks. +checked ... bytes. + + +16 bytes in 1 blocks are definitely lost in loss record 1 of 14 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-tree.c:11) + by 0x........: main (leak-tree.c:39) + + +16 bytes in 1 blocks are definitely lost in loss record 2 of 14 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-tree.c:11) + by 0x........: main (leak-tree.c:38) + + +80 (16 direct, 64 indirect) bytes in 1 blocks are definitely lost in los= s record 14 of 14 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-tree.c:11) + by 0x........: main (leak-tree.c:25) + +LEAK SUMMARY: + definitely lost: 48 bytes in 3 blocks. + indirectly lost: 64 bytes in 4 blocks. + possibly lost: 0 bytes in 0 blocks. + still reachable: 112 bytes in 7 blocks. + suppressed: 0 bytes in 0 blocks. +Reachable blocks (those to which a pointer was found) are not shown. +To see them, rerun with: --show-reachable=3Dyes + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) +malloc/free: in use at exit: 224 bytes in 14 blocks. +malloc/free: 14 allocs, 0 frees, 224 bytes allocated. +For a detailed leak analysis, rerun with: --leak-check=3Dyes +For counts of detected errors, rerun with: -v |
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From: <sv...@va...> - 2005-05-05 01:32:56
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Author: sewardj Date: 2005-05-05 02:32:24 +0100 (Thu, 05 May 2005) New Revision: 3620 Added: trunk/memcheck/tests/mismatches.stderr.exp64 Modified: trunk/memcheck/tests/Makefile.am Log: Add expected output files for 64-bit platforms. Modified: trunk/memcheck/tests/Makefile.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/Makefile.am 2005-05-05 01:29:11 UTC (rev 3619) +++ trunk/memcheck/tests/Makefile.am 2005-05-05 01:32:24 UTC (rev 3620) @@ -48,7 +48,7 @@ memalign2.stderr.exp memalign2.vgtest \ memcmptest.stderr.exp memcmptest.stdout.exp memcmptest.vgtest \ mempool.stderr.exp mempool.stderr.exp64 mempool.vgtest \ - mismatches.stderr.exp mismatches.vgtest \ + mismatches.stderr.exp mismatches.stderr.exp64 mismatches.vgtest \ mmaptest.stderr.exp mmaptest.vgtest \ nanoleak.stderr.exp nanoleak.vgtest \ nanoleak_supp.stderr.exp nanoleak_supp.vgtest nanoleak.supp \ Added: trunk/memcheck/tests/mismatches.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/mismatches.stderr.exp64 2005-05-05 01:29:11 UTC = (rev 3619) +++ trunk/memcheck/tests/mismatches.stderr.exp64 2005-05-05 01:32:24 UTC = (rev 3620) @@ -0,0 +1,41 @@ +Mismatched free() / delete / delete [] + at 0x........: operator delete(void*) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:6) + Address 0x........ is 0 bytes inside a block of size 10 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:5) + +Mismatched free() / delete / delete [] + at 0x........: operator delete[](void*) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:8) + Address 0x........ is 0 bytes inside a block of size 10 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:7) + +Mismatched free() / delete / delete [] + at 0x........: operator delete(void*) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:13) + Address 0x........ is 0 bytes inside a block of size 40 alloc'd + at 0x........: operator new[](unsigned long) (vg_replace_malloc.c:...= ) + by 0x........: main (mismatches.cpp:12) + +Mismatched free() / delete / delete [] + at 0x........: free (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:15) + Address 0x........ is 0 bytes inside a block of size 40 alloc'd + at 0x........: operator new[](unsigned long) (vg_replace_malloc.c:...= ) + by 0x........: main (mismatches.cpp:14) + +Mismatched free() / delete / delete [] + at 0x........: operator delete[](void*) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:20) + Address 0x........ is 0 bytes inside a block of size 4 alloc'd + at 0x........: operator new(unsigned long) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:19) + +Mismatched free() / delete / delete [] + at 0x........: free (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:22) + Address 0x........ is 0 bytes inside a block of size 4 alloc'd + at 0x........: operator new(unsigned long) (vg_replace_malloc.c:...) + by 0x........: main (mismatches.cpp:21) |
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From: <sv...@va...> - 2005-05-05 01:29:15
|
Author: sewardj Date: 2005-05-05 02:29:11 +0100 (Thu, 05 May 2005) New Revision: 3619 Added: trunk/memcheck/tests/leak-cycle.stderr.exp64 trunk/memcheck/tests/mempool.stderr.exp64 Modified: trunk/memcheck/tests/Makefile.am Log: Add expected output files for 64-bit platforms. Modified: trunk/memcheck/tests/Makefile.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/Makefile.am 2005-05-05 01:23:50 UTC (rev 3618) +++ trunk/memcheck/tests/Makefile.am 2005-05-05 01:29:11 UTC (rev 3619) @@ -33,7 +33,7 @@ inits.stderr.exp inits.vgtest \ inline.stderr.exp inline.stdout.exp inline.vgtest \ leak-0.vgtest leak-0.stderr.exp \ - leak-cycle.vgtest leak-cycle.stderr.exp \ + leak-cycle.vgtest leak-cycle.stderr.exp leak-cycle.stderr.exp64 \ leak-tree.vgtest leak-tree.stderr.exp \ leak-regroot.vgtest leak-regroot.stderr.exp \ leakotron.vgtest leakotron.stdout.exp leakotron.stderr.exp \ @@ -47,7 +47,7 @@ memalign_test.stderr.exp memalign_test.vgtest \ memalign2.stderr.exp memalign2.vgtest \ memcmptest.stderr.exp memcmptest.stdout.exp memcmptest.vgtest \ - mempool.stderr.exp mempool.vgtest \ + mempool.stderr.exp mempool.stderr.exp64 mempool.vgtest \ mismatches.stderr.exp mismatches.vgtest \ mmaptest.stderr.exp mmaptest.vgtest \ nanoleak.stderr.exp nanoleak.vgtest \ Added: trunk/memcheck/tests/leak-cycle.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/leak-cycle.stderr.exp64 2005-05-05 01:23:50 UTC = (rev 3618) +++ trunk/memcheck/tests/leak-cycle.stderr.exp64 2005-05-05 01:29:11 UTC = (rev 3619) @@ -0,0 +1,45 @@ + +searching for pointers to 18 not-freed blocks. +checked ... bytes. + +48 (16 direct, 32 indirect) bytes in 1 blocks are definitely lost in los= s record 15 of 18 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cycle.c:11) + by 0x........: mkcycle (leak-cycle.c:22) + by 0x........: main (leak-cycle.c:36) + + +48 (16 direct, 32 indirect) bytes in 1 blocks are definitely lost in los= s record 16 of 18 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cycle.c:11) + by 0x........: mkcycle (leak-cycle.c:22) + by 0x........: main (leak-cycle.c:37) + + +96 (16 direct, 80 indirect) bytes in 1 blocks are definitely lost in los= s record 17 of 18 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cycle.c:11) + by 0x........: mkcycle (leak-cycle.c:22) + by 0x........: main (leak-cycle.c:45) + + +96 (16 direct, 80 indirect) bytes in 1 blocks are definitely lost in los= s record 18 of 18 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cycle.c:11) + by 0x........: mkcycle (leak-cycle.c:22) + by 0x........: main (leak-cycle.c:59) + +LEAK SUMMARY: + definitely lost: 64 bytes in 4 blocks. + indirectly lost: 224 bytes in 14 blocks. + possibly lost: 0 bytes in 0 blocks. + still reachable: 0 bytes in 0 blocks. + suppressed: 0 bytes in 0 blocks. +Reachable blocks (those to which a pointer was found) are not shown. +To see them, rerun with: --show-reachable=3Dyes + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) +malloc/free: in use at exit: 288 bytes in 18 blocks. +malloc/free: 18 allocs, 0 frees, 288 bytes allocated. +For a detailed leak analysis, rerun with: --leak-check=3Dyes +For counts of detected errors, rerun with: -v Added: trunk/memcheck/tests/mempool.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/mempool.stderr.exp64 2005-05-05 01:23:50 UTC (re= v 3618) +++ trunk/memcheck/tests/mempool.stderr.exp64 2005-05-05 01:29:11 UTC (re= v 3619) @@ -0,0 +1,42 @@ +Invalid write of size 1 + at 0x........: test (mempool.c:124) + by 0x........: main (mempool.c:148) + Address 0x........ is 7 bytes inside a block of size 100000 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: make_pool (mempool.c:38) + by 0x........: test (mempool.c:111) + by 0x........: main (mempool.c:148) + +Invalid write of size 1 + at 0x........: test (mempool.c:125) + by 0x........: main (mempool.c:148) + Address 0x........ is 18 bytes inside a block of size 100000 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: make_pool (mempool.c:38) + by 0x........: test (mempool.c:111) + by 0x........: main (mempool.c:148) + +Invalid write of size 1 + at 0x........: test (mempool.c:129) + by 0x........: main (mempool.c:148) + Address 0x........ is 70 bytes inside a block of size 100000 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: make_pool (mempool.c:38) + by 0x........: test (mempool.c:111) + by 0x........: main (mempool.c:148) + +Invalid write of size 1 + at 0x........: test (mempool.c:130) + by 0x........: main (mempool.c:148) + Address 0x........ is 96 bytes inside a block of size 100000 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: make_pool (mempool.c:38) + by 0x........: test (mempool.c:111) + by 0x........: main (mempool.c:148) + + +100048 (32 direct, 100016 indirect) bytes in 1 blocks are definitely los= t in loss record 2 of 3 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: make_pool (mempool.c:37) + by 0x........: test (mempool.c:111) + by 0x........: main (mempool.c:148) |
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From: <sv...@va...> - 2005-05-05 01:23:54
|
Author: sewardj Date: 2005-05-05 02:23:50 +0100 (Thu, 05 May 2005) New Revision: 3618 Added: trunk/memcheck/tests/manuel2.stderr.exp64 trunk/memcheck/tests/pointer-trace.stderr.exp64 Modified: trunk/memcheck/tests/Makefile.am Log: Add expected output files for 64-bit platforms. Modified: trunk/memcheck/tests/Makefile.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/Makefile.am 2005-05-05 01:16:24 UTC (rev 3617) +++ trunk/memcheck/tests/Makefile.am 2005-05-05 01:23:50 UTC (rev 3618) @@ -41,7 +41,7 @@ malloc2.stderr.exp malloc2.vgtest \ malloc3.stderr.exp malloc3.stdout.exp malloc3.vgtest \ manuel1.stderr.exp manuel1.stdout.exp manuel1.vgtest \ - manuel2.stderr.exp manuel2.stdout.exp manuel2.vgtest \ + manuel2.stderr.exp manuel2.stderr.exp64 manuel2.stdout.exp manuel2.vgte= st \ manuel3.stderr.exp manuel3.vgtest \ match-overrun.stderr.exp match-overrun.vgtest match-overrun.supp \ memalign_test.stderr.exp memalign_test.vgtest \ @@ -56,7 +56,8 @@ new_override.stderr.exp new_override.stdout.exp new_override.vgtest \ null_socket.stderr.exp null_socket.vgtest \ overlap.stderr.exp overlap.stdout.exp overlap.vgtest \ - pointer-trace.vgtest pointer-trace.stdout.exp pointer-trace.stderr.exp = \ + pointer-trace.vgtest pointer-trace.stdout.exp \ + pointer-trace.stderr.exp pointer-trace.stderr.exp64 \ post-syscall.stderr.exp post-syscall.stdout.exp post-syscall.vgtest \ realloc1.stderr.exp realloc1.vgtest \ realloc2.stderr.exp realloc2.vgtest \ Added: trunk/memcheck/tests/manuel2.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/manuel2.stderr.exp64 2005-05-05 01:16:24 UTC (re= v 3617) +++ trunk/memcheck/tests/manuel2.stderr.exp64 2005-05-05 01:23:50 UTC (re= v 3618) @@ -0,0 +1,2 @@ +Use of uninitialised value of size 8 + at 0x........: main (manuel2.c:10) Added: trunk/memcheck/tests/pointer-trace.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/pointer-trace.stderr.exp64 2005-05-05 01:16:24 U= TC (rev 3617) +++ trunk/memcheck/tests/pointer-trace.stderr.exp64 2005-05-05 01:23:50 U= TC (rev 3618) @@ -0,0 +1,30 @@ + +searching for pointers to 1 not-freed blocks. +checked ... bytes. + +LEAK SUMMARY: + definitely lost: 0 bytes in 0 blocks. + possibly lost: 0 bytes in 0 blocks. + still reachable: 2097152 bytes in 1 blocks. + suppressed: 0 bytes in 0 blocks. +Reachable blocks (those to which a pointer was found) are not shown. +To see them, rerun with: --show-reachable=3Dyes + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) +malloc/free: in use at exit: 2097152 bytes in 1 blocks. +malloc/free: 1 allocs, 0 frees, 2097152 bytes allocated. +For counts of detected errors, rerun with: -v +searching for pointers to 1 not-freed blocks. +checked ... bytes. + +2097152 bytes in 1 blocks are definitely lost in loss record 1 of 1 + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (pointer-trace.c:24) + +LEAK SUMMARY: + definitely lost: 2097152 bytes in 1 blocks. + possibly lost: 0 bytes in 0 blocks. + still reachable: 0 bytes in 0 blocks. + suppressed: 0 bytes in 0 blocks. +Reachable blocks (those to which a pointer was found) are not shown. +To see them, rerun with: --show-reachable=3Dyes |
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From: <sv...@va...> - 2005-05-05 01:16:30
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Author: sewardj Date: 2005-05-05 02:16:24 +0100 (Thu, 05 May 2005) New Revision: 3617 Modified: trunk/coregrind/vg_replace_malloc.c Log: Tidy up a bit. Modified: trunk/coregrind/vg_replace_malloc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/coregrind/vg_replace_malloc.c 2005-05-04 18:01:26 UTC (rev 3616= ) +++ trunk/coregrind/vg_replace_malloc.c 2005-05-05 01:16:24 UTC (rev 3617= ) @@ -215,58 +215,70 @@ ALLOC_or_NULL(m_libc_dot_so_dot_6, malloc, malloc); //ALLOC_or_NULL(m_libpgc_dot_so, malloc, malloc); =20 -// operator new(unsigned int), GNU mangling, 32-bit platforms + +// operator new(unsigned int), unmangled for some bizarre reason ALLOC_or_BOMB(m_libstc_plus_plus_star, builtin_new, __builtin_new); ALLOC_or_BOMB(m_libc_dot_so_dot_6, builtin_new, __builtin_new); =20 ALLOC_or_BOMB(m_libstc_plus_plus_star, __builtin_new, __builtin_new); ALLOC_or_BOMB(m_libc_dot_so_dot_6, __builtin_new, __builtin_new); =20 -// TODO: these should only exist on 32-bit platforms -ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znwj, __builtin_new); -ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znwj, __builtin_new); =20 -// TODO: these should only exist on 64-bit platforms +// operator new(unsigned int), GNU mangling, 32-bit platforms // operator new(unsigned long), GNU mangling, 64-bit platforms -ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znwm, __builtin_new); -ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znwm, __builtin_new); +#if VG_WORDSIZE =3D=3D 4 + ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znwj, __builtin_new); + ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znwj, __builtin_new); +#endif +#if VG_WORDSIZE =3D=3D 8 + ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znwm, __builtin_new); + ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znwm, __builtin_new); +#endif =20 =20 // operator new(unsigned int), ARM/cfront mangling //ALLOC_or_BOMB(m_libpgc_dot_so, __nw__FUi, __builtin_new); =20 -// TODO: these should only exist on 32-bit platforms -// operator new(unsigned, std::nothrow_t const&), GNU mangling -ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnwjRKSt9nothrow_t, __builtin_n= ew); -ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnwjRKSt9nothrow_t, __builtin_n= ew); =20 -// TODO: these should only exist on 64-bit platforms -// operator new(unsigned long, std::nothrow_t const&), GNU mangling -ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnwmRKSt9nothrow_t, __builtin_n= ew); -ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnwmRKSt9nothrow_t, __builtin_n= ew); +// operator new(unsigned, std::nothrow_t const&), GNU mangling, 32-bit +// operator new(unsigned long, std::nothrow_t const&), GNU mangling, 64-= bit +#if VG_WORDSIZE =3D=3D 4 + ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnwjRKSt9nothrow_t, __builtin_= new); + ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnwjRKSt9nothrow_t, __builtin_= new); +#endif +#if VG_WORDSIZE =3D=3D 8 + ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnwmRKSt9nothrow_t, __builtin_= new); + ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnwmRKSt9nothrow_t, __builtin_= new); +#endif =20 -// operator new[](unsigned int), GNU mangling + +// operator new[](unsigned int), , unmangled for some bizarre reason ALLOC_or_BOMB(m_libstc_plus_plus_star, __builtin_vec_new, __builtin_vec_= new ); ALLOC_or_BOMB(m_libc_dot_so_dot_6, __builtin_vec_new, __builtin_vec_= new ); =20 -// TODO: these should only exist on 32-bit platforms -ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znaj, __builtin_vec_= new ); -ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znaj, __builtin_vec_= new ); =20 -// TODO: these should only exist on 64-bit platforms +// operator new[](unsigned int), GNU mangling, 32-bit platforms // operator new[](unsigned long), GNU mangling, 64-bit platforms -ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znam, __builtin_vec_= new ); -ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znam, __builtin_vec_= new ); +#if VG_WORDSIZE =3D=3D 4 + ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znaj, __builtin_vec= _new ); + ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znaj, __builtin_vec= _new ); +#endif +#if VG_WORDSIZE =3D=3D 8 + ALLOC_or_BOMB(m_libstc_plus_plus_star, _Znam, __builtin_vec= _new ); + ALLOC_or_BOMB(m_libc_dot_so_dot_6, _Znam, __builtin_vec= _new ); +#endif =20 -// TODO: these should only exist on 32-bit platforms -// operator new[](unsigned, std::nothrow_t const&), GNU mangling -ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnajRKSt9nothrow_t, __builtin_ve= c_new ); -ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnajRKSt9nothrow_t, __builtin_ve= c_new ); =20 -// TODO: these should only exist on 64-bit platforms -// operator new[](unsigned long, std::nothrow_t const&), GNU mangling -ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnamRKSt9nothrow_t, __builtin_ve= c_new ); -ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnamRKSt9nothrow_t, __builtin_ve= c_new ); +// operator new[](unsigned, std::nothrow_t const&), GNU mangling, 32-bit +// operator new[](unsigned long, std::nothrow_t const&), GNU mangling, 6= 4-bit +#if VG_WORDSIZE =3D=3D 4 + ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnajRKSt9nothrow_t, __builtin_v= ec_new ); + ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnajRKSt9nothrow_t, __builtin_v= ec_new ); +#endif +#if VG_WORDSIZE =3D=3D 8 + ALLOC_or_NULL(m_libstc_plus_plus_star, _ZnamRKSt9nothrow_t, __builtin_v= ec_new ); + ALLOC_or_NULL(m_libc_dot_so_dot_6, _ZnamRKSt9nothrow_t, __builtin_v= ec_new ); +#endif =20 =20 /* Generate a replacement for 'fnname' in object 'soname', which calls |