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From: <sv...@va...> - 2005-05-11 23:37:23
|
Author: sewardj Date: 2005-05-12 00:37:18 +0100 (Thu, 12 May 2005) New Revision: 3668 Modified: trunk/NOTES.txt Log: Update a bit. Modified: trunk/NOTES.txt =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/NOTES.txt 2005-05-11 22:45:48 UTC (rev 3667) +++ trunk/NOTES.txt 2005-05-11 23:37:18 UTC (rev 3668) @@ -1,4 +1,11 @@ =20 +11 May 05 +~~~~~~~~~ +ToDo: vex-x86: check/fix behaviour on SSE MOVQ / MOVSD insns. + vex-amd64: ditto + * check above/below the line for reg-alloc + + 23 Apr 05 (memcheck-on-amd64 notes) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * If a thread is given an initial stack with address range [lo .. hi], @@ -7,14 +14,7 @@ x86-only systems. However, am not sure where to look for the call into memcheck that states the new stack area. =20 -* vg_replace_malloc.c: need to create intercepts for - 64-bit versions of - operator new(unsigned, std::nothrow_t const&) - and=20 - operator new[](unsigned, std::nothrow_t const&) =20 - - 9 Apr 05 (starting work on memcheck for 32/64-bit and big/little endian) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * get rid of memcheck/mc_asm.h and include/tool_asm.h. I think=20 |
|
From: <sv...@va...> - 2005-05-11 23:16:48
|
Author: sewardj
Date: 2005-05-12 00:16:43 +0100 (Thu, 12 May 2005)
New Revision: 1191
Modified:
trunk/priv/guest-amd64/ghelpers.c
Log:
Add a couple more %rflag-helper specialisations.
Modified: trunk/priv/guest-amd64/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/ghelpers.c 2005-05-11 23:16:13 UTC (rev 1190)
+++ trunk/priv/guest-amd64/ghelpers.c 2005-05-11 23:16:43 UTC (rev 1191)
@@ -875,24 +875,26 @@
cc_dep1 =3D args[2];
cc_dep2 =3D args[3];
=20
-//.. /*---------------- ADDL ----------------*/
-//..=20
-//.. if (isU32(cc_op, AMD64G_CC_OP_ADDL) && isU32(cond, X86CondZ))=
{
-//.. /* long add, then Z --> test (dst+src =3D=3D 0) */
-//.. return unop(Iop_1Uto32,
-//.. binop(Iop_CmpEQ32,=20
-//.. binop(Iop_Add32, cc_dep1, cc_dep2),
-//.. mkU32(0)));
-//.. }
+ /*---------------- ADDQ ----------------*/
=20
+ if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondZ)) {
+ /* long long add, then Z --> test (dst+src =3D=3D 0) */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64,=20
+ binop(Iop_Add64, cc_dep1, cc_dep2),
+ mkU64(0)));
+ }
+
/*---------------- SUBL ----------------*/
=20
-//.. if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondZ))=
{
-//.. /* long sub/cmp, then Z --> test dst=3D=3Dsrc */
-//.. return unop(Iop_1Uto32,
-//.. binop(Iop_CmpEQ32, cc_dep1, cc_dep2));
-//.. }
-//..=20
+ if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondZ)) {
+ /* long sub/cmp, then Z --> test dst=3D=3Dsrc */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpEQ32,=20
+ unop(Iop_64to32,cc_dep1),=20
+ unop(Iop_64to32,cc_dep2)));
+ }
+
//.. if (isU32(cc_op, AMD64G_CC_OP_SUBL) && isU32(cond, X86CondNZ)=
) {
//.. /* long sub/cmp, then NZ --> test dst!=3Dsrc */
//.. return unop(Iop_1Uto32,
|
|
From: <sv...@va...> - 2005-05-11 23:16:15
|
Author: sewardj
Date: 2005-05-12 00:16:13 +0100 (Thu, 12 May 2005)
New Revision: 1190
Modified:
trunk/priv/host-amd64/hdefs.c
Log:
Allow reg-alloc to use %rbx. This is a callee-saved register and
therefore particularly valuable - bringing it into circulation reduces
the volume of code generated by memcheck by about 3%.
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-11 22:55:08 UTC (rev 1189)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-11 23:16:13 UTC (rev 1190)
@@ -157,7 +157,7 @@
(*arr)[ 5] =3D hregAMD64_XMM9();
#endif
#if 1
- *nregs =3D 18;
+ *nregs =3D 19;
*arr =3D LibVEX_Alloc(*nregs * sizeof(HReg));
(*arr)[ 0] =3D hregAMD64_RSI();
(*arr)[ 1] =3D hregAMD64_RDI();
@@ -167,18 +167,19 @@
(*arr)[ 5] =3D hregAMD64_R13();
(*arr)[ 6] =3D hregAMD64_R14();
(*arr)[ 7] =3D hregAMD64_R15();
+ (*arr)[ 8] =3D hregAMD64_RBX();
=20
- (*arr)[ 8] =3D hregAMD64_XMM3();
- (*arr)[ 9] =3D hregAMD64_XMM4();
- (*arr)[10] =3D hregAMD64_XMM5();
- (*arr)[11] =3D hregAMD64_XMM6();
- (*arr)[12] =3D hregAMD64_XMM7();
+ (*arr)[ 9] =3D hregAMD64_XMM3();
+ (*arr)[10] =3D hregAMD64_XMM4();
+ (*arr)[11] =3D hregAMD64_XMM5();
+ (*arr)[12] =3D hregAMD64_XMM6();
+ (*arr)[13] =3D hregAMD64_XMM7();
+ (*arr)[14] =3D hregAMD64_XMM8();
+ (*arr)[15] =3D hregAMD64_XMM9();
+ (*arr)[16] =3D hregAMD64_XMM10();
+ (*arr)[17] =3D hregAMD64_XMM11();
+ (*arr)[18] =3D hregAMD64_XMM12();
=20
- (*arr)[13] =3D hregAMD64_XMM8();
- (*arr)[14] =3D hregAMD64_XMM9();
- (*arr)[15] =3D hregAMD64_XMM10();
- (*arr)[16] =3D hregAMD64_XMM11();
- (*arr)[17] =3D hregAMD64_XMM12();
#endif
}
=20
|
|
From: <sv...@va...> - 2005-05-11 22:55:09
|
Author: sewardj
Date: 2005-05-11 23:55:08 +0100 (Wed, 11 May 2005)
New Revision: 1189
Modified:
trunk/priv/host-amd64/hdefs.c
Log:
Ah, the joys of register allocation. You might think that giving
reg-alloc as many registers as possible maximises performance. You
would be wrong. Giving it more registers generates more spilling of
caller-saved regs around the innumerable helper calls created by
Memcheck. What we really need are zillions of callee-save registers,
but those are in short supply. Hmm, perhaps I should let it use %rbx
too -- that's listed as callee-save.
Anyway, the current arrangement allows reg-alloc to use 8
general-purpose regs and 10 xmm registers. The x87 registers are not
used at all. This seems to work fairly well.
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-11 22:47:32 UTC (rev 1188)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-11 22:55:08 UTC (rev 1189)
@@ -157,7 +157,7 @@
(*arr)[ 5] =3D hregAMD64_XMM9();
#endif
#if 1
- *nregs =3D 11;
+ *nregs =3D 18;
*arr =3D LibVEX_Alloc(*nregs * sizeof(HReg));
(*arr)[ 0] =3D hregAMD64_RSI();
(*arr)[ 1] =3D hregAMD64_RDI();
@@ -168,50 +168,18 @@
(*arr)[ 6] =3D hregAMD64_R14();
(*arr)[ 7] =3D hregAMD64_R15();
=20
- (*arr)[ 8] =3D hregAMD64_XMM7();
- (*arr)[ 9] =3D hregAMD64_XMM8();
- (*arr)[10] =3D hregAMD64_XMM9();
+ (*arr)[ 8] =3D hregAMD64_XMM3();
+ (*arr)[ 9] =3D hregAMD64_XMM4();
+ (*arr)[10] =3D hregAMD64_XMM5();
+ (*arr)[11] =3D hregAMD64_XMM6();
+ (*arr)[12] =3D hregAMD64_XMM7();
+
+ (*arr)[13] =3D hregAMD64_XMM8();
+ (*arr)[14] =3D hregAMD64_XMM9();
+ (*arr)[15] =3D hregAMD64_XMM10();
+ (*arr)[16] =3D hregAMD64_XMM11();
+ (*arr)[17] =3D hregAMD64_XMM12();
#endif
-#if 0
- *nregs =3D 30;
- *arr =3D LibVEX_Alloc(*nregs * sizeof(HReg));
- (*arr)[ 0] =3D hregAMD64_RAX();
- (*arr)[ 1] =3D hregAMD64_RBX();
- (*arr)[ 2] =3D hregAMD64_RCX();
- (*arr)[ 3] =3D hregAMD64_RDX();
- (*arr)[ 4] =3D hregAMD64_RSI();
- (*arr)[ 5] =3D hregAMD64_RDI();
- (*arr)[ 6] =3D hregAMD64_R8();
- (*arr)[ 7] =3D hregAMD64_R9();
- (*arr)[ 8] =3D hregAMD64_R10();
- (*arr)[ 9] =3D hregAMD64_R11();
- (*arr)[10] =3D hregAMD64_R12();
- (*arr)[11] =3D hregAMD64_R13();
- (*arr)[12] =3D hregAMD64_R14();
- (*arr)[13] =3D hregAMD64_R15();
- // (*arr)[6] =3D hregAMD64_FAKE0();
- //(*arr)[7] =3D hregAMD64_FAKE1();
- //(*arr)[8] =3D hregAMD64_FAKE2();
- //(*arr)[9] =3D hregAMD64_FAKE3();
- //(*arr)[10] =3D hregAMD64_FAKE4();
- //(*arr)[11] =3D hregAMD64_FAKE5();
- (*arr)[14] =3D hregAMD64_XMM0();
- (*arr)[15] =3D hregAMD64_XMM1();
- (*arr)[16] =3D hregAMD64_XMM2();
- (*arr)[17] =3D hregAMD64_XMM3();
- (*arr)[18] =3D hregAMD64_XMM4();
- (*arr)[19] =3D hregAMD64_XMM5();
- (*arr)[20] =3D hregAMD64_XMM6();
- (*arr)[21] =3D hregAMD64_XMM7();
- (*arr)[22] =3D hregAMD64_XMM8();
- (*arr)[23] =3D hregAMD64_XMM9();
- (*arr)[24] =3D hregAMD64_XMM10();
- (*arr)[25] =3D hregAMD64_XMM11();
- (*arr)[26] =3D hregAMD64_XMM12();
- (*arr)[27] =3D hregAMD64_XMM13();
- (*arr)[28] =3D hregAMD64_XMM14();
- (*arr)[29] =3D hregAMD64_XMM15();
-#endif
}
=20
=20
|
|
From: <sv...@va...> - 2005-05-11 22:47:33
|
Author: sewardj
Date: 2005-05-11 23:47:32 +0100 (Wed, 11 May 2005)
New Revision: 1188
Modified:
trunk/priv/host-amd64/isel.c
Log:
Do a bit better for (part of) a very common memcheck idiom: "is this
pointer defined ?"
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-11 16:24:00 UTC (rev 1187)
+++ trunk/priv/host-amd64/isel.c 2005-05-11 22:47:32 UTC (rev 1188)
@@ -2008,6 +2008,21 @@
=20
/* --- patterns rooted at: CmpNEZ64 --- */
=20
+ /* CmpNEZ64(Or64(x,y)) */
+ {
+ DECLARE_PATTERN(p_CmpNEZ64_Or64);
+ DEFINE_PATTERN(p_CmpNEZ64_Or64,
+ unop(Iop_CmpNEZ64, binop(Iop_Or64, bind(0), bind(1)=
)));
+ if (matchIRExpr(&mi, p_CmpNEZ64_Or64, e)) {
+ HReg r0 =3D iselIntExpr_R(env, mi.bindee[0]);
+ AMD64RMI* rmi1 =3D iselIntExpr_RMI(env, mi.bindee[1]);
+ HReg tmp =3D newVRegI(env);
+ addInstr(env, mk_iMOVsd_RR(r0, tmp));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_OR,rmi1,tmp));
+ return Acc_NZ;
+ }
+ }
+
/* CmpNEZ64(x) */
if (e->tag =3D=3D Iex_Unop=20
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
|
|
From: <sv...@va...> - 2005-05-11 22:45:50
|
Author: njn
Date: 2005-05-11 23:45:48 +0100 (Wed, 11 May 2005)
New Revision: 3667
Modified:
trunk/coregrind/core.h
trunk/coregrind/vg_main.c
trunk/coregrind/vg_translate.c
Log:
Moved Vex's arch/subarch detection out of main() into VG_(translate)()'s
init routine. This meant that VG_(vex_arch) and VG_(vex_subarch) could b=
e
made local to VG_(translate)().
Modified: trunk/coregrind/core.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/core.h 2005-05-11 22:36:07 UTC (rev 3666)
+++ trunk/coregrind/core.h 2005-05-11 22:45:48 UTC (rev 3667)
@@ -776,10 +776,6 @@
/* Stats ... */
extern void VG_(print_scheduler_stats) ( void );
=20
-/* Indicates what arch and subarch we are running on. */
-extern VexArch VG_(vex_arch);
-extern VexSubArch VG_(vex_subarch);
-
/* 64-bit counter for the number of basic blocks done. */
extern ULong VG_(bbs_done);
=20
Modified: trunk/coregrind/vg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_main.c 2005-05-11 22:36:07 UTC (rev 3666)
+++ trunk/coregrind/vg_main.c 2005-05-11 22:45:48 UTC (rev 3667)
@@ -153,11 +153,7 @@
Char** VG_(client_argv);
Char** VG_(client_envp);
=20
-/* Indicates what arch and subarch we are running on. */
-VexArch VG_(vex_arch) =3D VexArch_INVALID;
-VexSubArch VG_(vex_subarch) =3D VexSubArch_INVALID;
=20
-
/* ---------------------------------------------------------------------
Running stuff =20
------------------------------------------------------------------ */
@@ -2627,30 +2623,6 @@
VG_TDICT_CALL(tool_post_clo_init);
=20
//--------------------------------------------------------------
- // Determine CPU architecture and subarchitecture
- // p: none
- //--------------------------------------------------------------
- VG_(debugLog)(1, "main", "Check CPU arch/subarch\n");
- { Bool ok =3D VGA_(getArchAndSubArch)(
- & VG_(vex_arch), & VG_(vex_subarch) );
- if (!ok) {
- VG_(printf)("\n");
- VG_(printf)("valgrind: fatal error: unsupported CPU.\n");
- VG_(printf)(" Supported CPUs are:\n");
- VG_(printf)(" * x86 with SSE state (Pentium II or above, "
- "AMD Athlon or above)\n");
- VG_(printf)("\n");
- VG_(exit)(1);
- }
- if (VG_(clo_verbosity) > 2) {
- VG_(message)(Vg_DebugMsg,=20
- "Host CPU: arch =3D %s, subarch =3D %s",
- LibVEX_ppVexArch( VG_(vex_arch) ),
- LibVEX_ppVexSubArch( VG_(vex_subarch) ) );
- }
- }
-
- //--------------------------------------------------------------
// Build segment map (all segments)
// p: shadow/redzone segments
// p: setup_client_stack() [for 'sp_at_startup']
Modified: trunk/coregrind/vg_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_translate.c 2005-05-11 22:36:07 UTC (rev 3666)
+++ trunk/coregrind/vg_translate.c 2005-05-11 22:45:48 UTC (rev 3667)
@@ -342,7 +342,6 @@
VG_(tdict).track_die_mem_stack );
}
=20
-
Bool VG_(translate) ( ThreadId tid,=20
Addr64 orig_addr,
Bool debugging_translation,
@@ -355,11 +354,32 @@
Segment* seg;
VexGuestExtents vge;
=20
+ /* Indicates what arch and subarch we are running on. */
+ static VexArch vex_arch =3D VexArch_INVALID;
+ static VexSubArch vex_subarch =3D VexSubArch_INVALID;
+
/* Make sure Vex is initialised right. */
VexTranslateResult tres;
static Bool vex_init_done =3D False;
=20
if (!vex_init_done) {
+ Bool ok =3D VGA_(getArchAndSubArch)( &vex_arch, &vex_subarch );
+ if (!ok) {
+ VG_(printf)("\n");
+ VG_(printf)("valgrind: fatal error: unsupported CPU.\n");
+ VG_(printf)(" Supported CPUs are:\n");
+ VG_(printf)(" * x86 with SSE state (Pentium II or above, "
+ "AMD Athlon or above)\n");
+ VG_(printf)("\n");
+ VG_(exit)(1);
+ }
+ if (VG_(clo_verbosity) > 2) {
+ VG_(message)(Vg_DebugMsg,=20
+ "Host CPU: arch =3D %s, subarch =3D %s",
+ LibVEX_ppVexArch ( vex_arch ),
+ LibVEX_ppVexSubArch( vex_subarch ) );
+ }
+
LibVEX_Init ( &failure_exit, &log_bytes,=20
1, /* debug_paranoia */=20
False, /* valgrind support */
@@ -446,8 +466,8 @@
tl_assert2(VG_(tdict).tool_instrument,
"you forgot to set VgToolInterface function 'tool_instrume=
nt'");
tres =3D LibVEX_Translate (=20
- VG_(vex_arch), VG_(vex_subarch),
- VG_(vex_arch), VG_(vex_subarch),
+ vex_arch, vex_subarch,
+ vex_arch, vex_subarch,
(UChar*)ULong_to_Ptr(orig_addr),=20
(Addr64)orig_addr,=20
chase_into_ok,
|
|
From: <sv...@va...> - 2005-05-11 22:36:09
|
Author: njn Date: 2005-05-11 23:36:07 +0100 (Wed, 11 May 2005) New Revision: 3666 Modified: trunk/coregrind/core.h trunk/coregrind/m_syscalls/priv_syscalls.h Log: Make VG_(clone)() declaration private to m_syscalls. Modified: trunk/coregrind/core.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/coregrind/core.h 2005-05-11 22:32:39 UTC (rev 3665) +++ trunk/coregrind/core.h 2005-05-11 22:36:07 UTC (rev 3666) @@ -836,8 +836,6 @@ #define vgPlain_do_syscall5(s,a,b,c,d,e) VG_(do_syscall)((s),(a),(b),(= c),(d),(e),0) #define vgPlain_do_syscall6(s,a,b,c,d,e,f) VG_(do_syscall)((s),(a),(b),(= c),(d),(e),(f)) =20 -extern Int VG_(clone) ( Int (*fn)(void *), void *stack, Int flags, void = *arg,=20 - Int *child_tid, Int *parent_tid, vki_modify_ldt_t * ); extern void VG_(sigreturn)(void); =20 /* --------------------------------------------------------------------- Modified: trunk/coregrind/m_syscalls/priv_syscalls.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/coregrind/m_syscalls/priv_syscalls.h 2005-05-11 22:32:39 UTC (r= ev 3665) +++ trunk/coregrind/m_syscalls/priv_syscalls.h 2005-05-11 22:36:07 UTC (r= ev 3666) @@ -75,6 +75,9 @@ =20 extern void VGA_(restart_syscall)(ThreadArchState* arch); =20 +extern Int VG_(clone) ( Int (*fn)(void *), void *stack, Int flags, void = *arg,=20 + Int *child_tid, Int *parent_tid, vki_modify_ldt_t * ); + /* Perform a syscall on behalf of a client thread, using a specific signal mask. On completion, the signal mask is set to restore_mask |
|
From: <sv...@va...> - 2005-05-11 22:32:42
|
Author: njn
Date: 2005-05-11 23:32:39 +0100 (Wed, 11 May 2005)
New Revision: 3665
Modified:
trunk/coregrind/core.h
trunk/coregrind/vg_scheduler.c
Log:
Removed the obsolete client request numbers that were used in the old
libpthread. There seems to be no danger of old libpthread.so files causi=
ng
problems; I just tried installing a current Valgrind over a 2.2.0
installation and it worked fine.
Modified: trunk/coregrind/core.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/core.h 2005-05-11 19:03:57 UTC (rev 3664)
+++ trunk/coregrind/core.h 2005-05-11 22:32:39 UTC (rev 3665)
@@ -302,64 +302,15 @@
Exports of vg_intercept.c
------------------------------------------------------------------ */
=20
-/* This doesn't export code or data that valgrind.so needs to link
- against. However, the scheduler does need to know the following
- request codes. A few, publically-visible, request codes are also
- defined in valgrind.h, and similar headers for some tools. */
+/* These are the internal client request codes. The publically-visible
+ request codes are also defined in valgrind.h, and similar headers for
+ some tools. */
=20
-/* Obsolete pthread-related requests */
-#define VG_USERREQ__MALLOC 0x2001
-#define VG_USERREQ__FREE 0x2002
-#define VG_USERREQ__APPLY_IN_NEW_THREAD 0x3001
-#define VG_USERREQ__QUIT 0x3002
-#define VG_USERREQ__WAIT_JOINER 0x3003
-#define VG_USERREQ__PTHREAD_JOIN 0x3004
-#define VG_USERREQ__SET_CANCELSTATE 0x3005
-#define VG_USERREQ__SET_CANCELTYPE 0x3006
-#define VG_USERREQ__TESTCANCEL 0x3007
-#define VG_USERREQ__SET_CANCELPEND 0x3008
-#define VG_USERREQ__SET_OR_GET_DETACH 0x3009
-#define VG_USERREQ__PTHREAD_GET_THREADID 0x300A
-#define VG_USERREQ__PTHREAD_MUTEX_LOCK 0x300B
-#define VG_USERREQ__PTHREAD_MUTEX_TIMEDLOCK 0x300C
-#define VG_USERREQ__PTHREAD_MUTEX_TRYLOCK 0x300D
-#define VG_USERREQ__PTHREAD_MUTEX_UNLOCK 0x300E
-#define VG_USERREQ__PTHREAD_COND_WAIT 0x300F
-#define VG_USERREQ__PTHREAD_COND_TIMEDWAIT 0x3010
-#define VG_USERREQ__PTHREAD_COND_SIGNAL 0x3011
-#define VG_USERREQ__PTHREAD_COND_BROADCAST 0x3012
-#define VG_USERREQ__PTHREAD_KEY_CREATE 0x3013
-#define VG_USERREQ__PTHREAD_KEY_DELETE 0x3014
-#define VG_USERREQ__PTHREAD_SETSPECIFIC_PTR 0x3015
-#define VG_USERREQ__PTHREAD_GETSPECIFIC_PTR 0x3016
-#define VG_USERREQ__READ_MILLISECOND_TIMER 0x3017
-#define VG_USERREQ__PTHREAD_SIGMASK 0x3018
-#define VG_USERREQ__SIGWAIT 0x3019
-#define VG_USERREQ__PTHREAD_KILL 0x301A
-#define VG_USERREQ__PTHREAD_YIELD 0x301B
-#define VG_USERREQ__PTHREAD_KEY_VALIDATE 0x301C
-#define VG_USERREQ__CLEANUP_PUSH 0x3020
-#define VG_USERREQ__CLEANUP_POP 0x3021
-#define VG_USERREQ__GET_KEY_D_AND_S 0x3022
-#define VG_USERREQ__NUKE_OTHER_THREADS 0x3023
-#define VG_USERREQ__GET_N_SIGS_RETURNED 0x3024
-#define VG_USERREQ__SET_FHSTACK_USED 0x3025
-#define VG_USERREQ__GET_FHSTACK_USED 0x3026
-#define VG_USERREQ__SET_FHSTACK_ENTRY 0x3027
-#define VG_USERREQ__GET_FHSTACK_ENTRY 0x3028
-#define VG_USERREQ__GET_SIGRT_MIN 0x302B
-#define VG_USERREQ__GET_SIGRT_MAX 0x302C
-#define VG_USERREQ__ALLOC_RTSIG 0x302D
+/* Get the tool's malloc-wrapping functions */
#define VG_USERREQ__GET_MALLOCFUNCS 0x3030
-#define VG_USERREQ__GET_STACK_INFO 0x3033
-#define VG_USERREQ__GET_PTHREAD_TRACE_LEVEL 0x3101
-#define VG_USERREQ__PTHREAD_ERROR 0x3102
=20
-
/* Internal equivalent of VALGRIND_PRINTF . */
#define VG_USERREQ__INTERNAL_PRINTF 0x3103
-/* Internal equivalent of VALGRIND_PRINTF_BACKTRACE . (no longer used) *=
/
-//#define VG_USERREQ__INTERNAL_PRINTF_BACKTRACE 0x3104
=20
/* Denote the finish of __libc_freeres_wrapper().=20
A synonym for exit. */
Modified: trunk/coregrind/vg_scheduler.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_scheduler.c 2005-05-11 19:03:57 UTC (rev 3664)
+++ trunk/coregrind/vg_scheduler.c 2005-05-11 22:32:39 UTC (rev 3665)
@@ -1082,56 +1082,6 @@
SET_CLREQ_RETVAL( tid, VG_(get_n_errs_found)() );
break;
=20
- /* Obsolete requests: print a warning in case there's an old
- libpthread.so still hanging around. */
- case VG_USERREQ__APPLY_IN_NEW_THREAD:
- case VG_USERREQ__QUIT:
- case VG_USERREQ__WAIT_JOINER:
- case VG_USERREQ__PTHREAD_JOIN:
- case VG_USERREQ__SET_CANCELSTATE:
- case VG_USERREQ__SET_CANCELTYPE:
- case VG_USERREQ__TESTCANCEL:
- case VG_USERREQ__SET_CANCELPEND:
- case VG_USERREQ__SET_OR_GET_DETACH:
- case VG_USERREQ__PTHREAD_GET_THREADID:
- case VG_USERREQ__PTHREAD_MUTEX_LOCK:
- case VG_USERREQ__PTHREAD_MUTEX_TIMEDLOCK:
- case VG_USERREQ__PTHREAD_MUTEX_TRYLOCK:
- case VG_USERREQ__PTHREAD_MUTEX_UNLOCK:
- case VG_USERREQ__PTHREAD_COND_WAIT:
- case VG_USERREQ__PTHREAD_COND_TIMEDWAIT:
- case VG_USERREQ__PTHREAD_COND_SIGNAL:
- case VG_USERREQ__PTHREAD_COND_BROADCAST:
- case VG_USERREQ__PTHREAD_KEY_CREATE:
- case VG_USERREQ__PTHREAD_KEY_DELETE:
- case VG_USERREQ__PTHREAD_SETSPECIFIC_PTR:
- case VG_USERREQ__PTHREAD_GETSPECIFIC_PTR:
- case VG_USERREQ__READ_MILLISECOND_TIMER:
- case VG_USERREQ__PTHREAD_SIGMASK:
- case VG_USERREQ__SIGWAIT:
- case VG_USERREQ__PTHREAD_KILL:
- case VG_USERREQ__PTHREAD_YIELD:
- case VG_USERREQ__PTHREAD_KEY_VALIDATE:
- case VG_USERREQ__CLEANUP_PUSH:
- case VG_USERREQ__CLEANUP_POP:
- case VG_USERREQ__GET_KEY_D_AND_S:
- case VG_USERREQ__NUKE_OTHER_THREADS:
- case VG_USERREQ__GET_N_SIGS_RETURNED:
- case VG_USERREQ__SET_FHSTACK_USED:
- case VG_USERREQ__GET_FHSTACK_USED:
- case VG_USERREQ__SET_FHSTACK_ENTRY:
- case VG_USERREQ__GET_FHSTACK_ENTRY:
- case VG_USERREQ__GET_SIGRT_MIN:
- case VG_USERREQ__GET_SIGRT_MAX:
- case VG_USERREQ__ALLOC_RTSIG:
- case VG_USERREQ__MALLOC:
- case VG_USERREQ__FREE:
- VG_(message)(Vg_UserMsg, "It looks like you've got an old libpthread.s=
o* ");
- VG_(message)(Vg_UserMsg, "installed in \"%s\".", VG_(libdir));
- VG_(message)(Vg_UserMsg, "Please delete it and try again.");
- VG_(exit)(99);
- break;
-
default:
if (VGA_(client_request)(tid, arg)) {
/* architecture handled the client request */
|
|
From: <sv...@va...> - 2005-05-11 19:04:03
|
Author: njn
Date: 2005-05-11 20:03:57 +0100 (Wed, 11 May 2005)
New Revision: 3664
Modified:
trunk/include/tool.h
Log:
Remove dead macro.
Modified: trunk/include/tool.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/include/tool.h 2005-05-11 18:57:02 UTC (rev 3663)
+++ trunk/include/tool.h 2005-05-11 19:03:57 UTC (rev 3664)
@@ -47,9 +47,6 @@
/*=3D=3D=3D Build options and table sizes. =
=3D=3D=3D*/
/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
=20
-/* You should be able to change these options or sizes, recompile, and
- still have a working system. */
-
/* The maximum number of pthreads that we support. This is
deliberately not very high since our implementation of some of the
scheduler algorithms is surely O(N) in the number of threads, since
@@ -57,11 +54,7 @@
programs do not need many threads. */
#define VG_N_THREADS 100
=20
-/* Maximum number of pthread keys available. Again, we start low until
- the need for a higher number presents itself. */
-#define VG_N_THREAD_KEYS 50
=20
-
/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
/*=3D=3D=3D Useful macros =
=3D=3D=3D*/
/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
|
|
From: <sv...@va...> - 2005-05-11 18:57:06
|
Author: njn
Date: 2005-05-11 19:57:02 +0100 (Wed, 11 May 2005)
New Revision: 3663
Modified:
trunk/coregrind/vg_main.c
trunk/coregrind/vg_scheduler.c
Log:
Move VG_(dispatch_ctr) out of vg_main.c, which never touches it, into
vg_scheduler.c, which does.
Modified: trunk/coregrind/vg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_main.c 2005-05-11 18:51:53 UTC (rev 3662)
+++ trunk/coregrind/vg_main.c 2005-05-11 18:57:02 UTC (rev 3663)
@@ -162,9 +162,6 @@
Running stuff =20
------------------------------------------------------------------ */
=20
-/* Counts downwards in VG_(run_innerloop). */
-UInt VG_(dispatch_ctr);
-
/* 64-bit counter for the number of basic blocks done. */
ULong VG_(bbs_done) =3D 0;
=20
Modified: trunk/coregrind/vg_scheduler.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_scheduler.c 2005-05-11 18:51:53 UTC (rev 3662)
+++ trunk/coregrind/vg_scheduler.c 2005-05-11 18:57:02 UTC (rev 3663)
@@ -85,6 +85,9 @@
/* If true, a fault is Valgrind-internal (ie, a bug) */
Bool VG_(my_fault) =3D True;
=20
+/* Counts downwards in VG_(run_innerloop). */
+UInt VG_(dispatch_ctr);
+
/* Forwards */
static void do_client_request ( ThreadId tid );
static void scheduler_sanity ( ThreadId tid );
|
|
From: <sv...@va...> - 2005-05-11 18:51:56
|
Author: njn
Date: 2005-05-11 19:51:53 +0100 (Wed, 11 May 2005)
New Revision: 3662
Modified:
trunk/coregrind/core.h
trunk/coregrind/m_replacemalloc/vg_replace_malloc.c
trunk/coregrind/pub_core_replacemalloc.h
Log:
Move declaration of "struct vg_mallocfunc_info" from core.h into
pub_core_replacemalloc.h, to reduce its exposure.
Modified: trunk/coregrind/core.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/core.h 2005-05-11 18:48:33 UTC (rev 3661)
+++ trunk/coregrind/core.h 2005-05-11 18:51:53 UTC (rev 3662)
@@ -379,24 +379,6 @@
#define VG_WRAPPER_ALIAS(name) "_vgw_" #name
=20
=20
-struct vg_mallocfunc_info {
- /* things vg_replace_malloc.o needs to know about */
- void* (*tl_malloc) (ThreadId tid, SizeT n);
- void* (*tl___builtin_new) (ThreadId tid, SizeT n);
- void* (*tl___builtin_vec_new) (ThreadId tid, SizeT n);
- void* (*tl_memalign) (ThreadId tid, SizeT align, SizeT n);
- void* (*tl_calloc) (ThreadId tid, SizeT nmemb, SizeT n);
- void (*tl_free) (ThreadId tid, void* p);
- void (*tl___builtin_delete) (ThreadId tid, void* p);
- void (*tl___builtin_vec_delete)(ThreadId tid, void* p);
- void* (*tl_realloc) (ThreadId tid, void* p, SizeT size);
-
- SizeT (*arena_payload_szB) (ArenaId aid, void* payload);
-
- Bool clo_trace_malloc;
-};
-
-
/* ---------------------------------------------------------------------
Exports of vg_scheduler.c
------------------------------------------------------------------ */
Modified: trunk/coregrind/m_replacemalloc/vg_replace_malloc.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_replacemalloc/vg_replace_malloc.c 2005-05-11 18:48:=
33 UTC (rev 3661)
+++ trunk/coregrind/m_replacemalloc/vg_replace_malloc.c 2005-05-11 18:51:=
53 UTC (rev 3662)
@@ -47,6 +47,7 @@
=20
#include "valgrind.h" /* for VALGRIND_NON_SIMD_CALL[12] */
#include "core.h"
+#include "pub_core_replacemalloc.h"
=20
/* The general idea is: you can write a function like this:
=20
Modified: trunk/coregrind/pub_core_replacemalloc.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_replacemalloc.h 2005-05-11 18:48:33 UTC (rev=
3661)
+++ trunk/coregrind/pub_core_replacemalloc.h 2005-05-11 18:51:53 UTC (rev=
3662)
@@ -36,11 +36,24 @@
// replace malloc/free with their own versions.
//--------------------------------------------------------------------
=20
-// Nb: there are no exports in this header; all exports for this module
-// are in include/pub_tool_replacemalloc.h
-
#include "pub_tool_replacemalloc.h"
=20
+// things vg_replace_malloc.o needs to know about
+struct vg_mallocfunc_info {
+ void* (*tl_malloc) (ThreadId tid, SizeT n);
+ void* (*tl___builtin_new) (ThreadId tid, SizeT n);
+ void* (*tl___builtin_vec_new) (ThreadId tid, SizeT n);
+ void* (*tl_memalign) (ThreadId tid, SizeT align, SizeT n);
+ void* (*tl_calloc) (ThreadId tid, SizeT nmemb, SizeT n);
+ void (*tl_free) (ThreadId tid, void* p);
+ void (*tl___builtin_delete) (ThreadId tid, void* p);
+ void (*tl___builtin_vec_delete)(ThreadId tid, void* p);
+ void* (*tl_realloc) (ThreadId tid, void* p, SizeT size);
+
+ SizeT (*arena_payload_szB) (ArenaId aid, void* payload);
+ Bool clo_trace_malloc;
+};
+
#endif // __PUB_CORE_REPLACEMALLOC_H
=20
/*--------------------------------------------------------------------*/
|
|
From: <sv...@va...> - 2005-05-11 18:48:35
|
Author: njn
Date: 2005-05-11 19:48:33 +0100 (Wed, 11 May 2005)
New Revision: 3661
Modified:
trunk/coregrind/core.h
trunk/coregrind/vg_scheduler.c
trunk/coregrind/vg_signals.c
Log:
Move VG_(block_signals)() to vg_scheduler.c, the only file that uses
it, and make it private.
Modified: trunk/coregrind/core.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/core.h 2005-05-11 18:44:13 UTC (rev 3660)
+++ trunk/coregrind/core.h 2005-05-11 18:48:33 UTC (rev 3661)
@@ -593,10 +593,6 @@
Exports of vg_signals.c
------------------------------------------------------------------ */
=20
-/* Set the standard set of blocked signals, used wheneever we're not
- running a client syscall. */
-extern void VG_(block_signals)(ThreadId tid);
-
/* Highest signal the kernel will let us use */
extern Int VG_(max_signal);
=20
Modified: trunk/coregrind/vg_scheduler.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_scheduler.c 2005-05-11 18:44:13 UTC (rev 3660)
+++ trunk/coregrind/vg_scheduler.c 2005-05-11 18:48:33 UTC (rev 3661)
@@ -424,6 +424,32 @@
}
}
=20
+/* Set the standard set of blocked signals, used wheneever we're not
+ running a client syscall. */
+static void block_signals(ThreadId tid)
+{
+ vki_sigset_t mask;
+
+ VG_(sigfillset)(&mask);
+
+ /* Don't block these because they're synchronous */
+ VG_(sigdelset)(&mask, VKI_SIGSEGV);
+ VG_(sigdelset)(&mask, VKI_SIGBUS);
+ VG_(sigdelset)(&mask, VKI_SIGFPE);
+ VG_(sigdelset)(&mask, VKI_SIGILL);
+ VG_(sigdelset)(&mask, VKI_SIGTRAP);
+
+ /* Can't block these anyway */
+ VG_(sigdelset)(&mask, VKI_SIGSTOP);
+ VG_(sigdelset)(&mask, VKI_SIGKILL);
+
+ /* Master doesn't block this */
+ if (tid =3D=3D VG_(master_tid))
+ VG_(sigdelset)(&mask, VKI_SIGVGCHLD);
+
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &mask, NULL);
+}
+
#define SCHEDSETJMP(tid, jumped, stmt) \
do { \
ThreadState * volatile _qq_tst =3D VG_(get_ThreadState)(tid); \
@@ -511,7 +537,7 @@
signal handler to longjmp. */
vg_assert(trc =3D=3D 0);
trc =3D VG_TRC_FAULT_SIGNAL;
- VG_(block_signals)(tid);
+ block_signals(tid);
}=20
=20
done_this_time =3D (Int)dispatch_ctr_SAVED - (Int)VG_(dispatch_ctr) -=
0;
@@ -684,7 +710,7 @@
vg_assert(VG_(is_running_thread)(tid));
=20
if (jumped) {
- VG_(block_signals)(tid);
+ block_signals(tid);
VG_(poll_signals)(tid);
}
}
@@ -706,7 +732,7 @@
VGP_PUSHCC(VgpSched);
=20
/* set the proper running signal mask */
- VG_(block_signals)(tid);
+ block_signals(tid);
=20
vg_assert(VG_(is_running_thread)(tid));
=20
Modified: trunk/coregrind/vg_signals.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_signals.c 2005-05-11 18:44:13 UTC (rev 3660)
+++ trunk/coregrind/vg_signals.c 2005-05-11 18:48:33 UTC (rev 3661)
@@ -2050,32 +2050,6 @@
VG_(restore_all_host_signals)(&saved_mask);
}
=20
-/* Set the standard set of blocked signals, used wheneever we're not
- running a client syscall. */
-void VG_(block_signals)(ThreadId tid)
-{
- vki_sigset_t mask;
-
- VG_(sigfillset)(&mask);
-
- /* Don't block these because they're synchronous */
- VG_(sigdelset)(&mask, VKI_SIGSEGV);
- VG_(sigdelset)(&mask, VKI_SIGBUS);
- VG_(sigdelset)(&mask, VKI_SIGFPE);
- VG_(sigdelset)(&mask, VKI_SIGILL);
- VG_(sigdelset)(&mask, VKI_SIGTRAP);
-
- /* Can't block these anyway */
- VG_(sigdelset)(&mask, VKI_SIGSTOP);
- VG_(sigdelset)(&mask, VKI_SIGKILL);
-
- /* Master doesn't block this */
- if (tid =3D=3D VG_(master_tid))
- VG_(sigdelset)(&mask, VKI_SIGVGCHLD);
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &mask, NULL);
-}
-
/* At startup, copy the process' real signal state to the SCSS.
Whilst doing this, block all real signals. Then calculate SKSS and
set the kernel to that. Also initialise DCSS.=20
|
|
From: Tom H. <th...@cy...> - 2005-05-11 18:44:37
|
SVN commit 412455 by thughes:
Fix stabs parsing bug introduced by fix to bug 90128 which meant
that structDef() didn't always call VG_(st_setname) as it should.
M +1 -1 trunk/valgrind/coregrind/vg_stabs.c =20
--- trunk/valgrind/coregrind/vg_stabs.c #412454:412455
@@ -185,8 +185,8 @@
isstruct ? "struct" : "union", name, ref, def);
=20
def =3D VG_(st_mktypedef)(ref, name, VG_(st_basetype)(def, False))=
;
- VG_(st_setname)(def, name);
}
+ VG_(st_setname)(def, name);
return def;
}
=20
|
|
From: <sv...@va...> - 2005-05-11 18:44:20
|
Author: tom
Date: 2005-05-11 19:44:13 +0100 (Wed, 11 May 2005)
New Revision: 3660
Modified:
trunk/coregrind/vg_stabs.c
Log:
Fix stabs parsing bug introduced by fix to bug 90128 which meant
that structDef() didn't always call VG_(st_setname) as it should.
Modified: trunk/coregrind/vg_stabs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_stabs.c 2005-05-11 11:57:41 UTC (rev 3659)
+++ trunk/coregrind/vg_stabs.c 2005-05-11 18:44:13 UTC (rev 3660)
@@ -185,8 +185,8 @@
isstruct ? "struct" : "union", name, ref, def);
=20
def =3D VG_(st_mktypedef)(ref, name, VG_(st_basetype)(def, False))=
;
- VG_(st_setname)(def, name);
}
+ VG_(st_setname)(def, name);
return def;
}
=20
|
|
From: <sv...@va...> - 2005-05-11 16:24:04
|
Author: sewardj
Date: 2005-05-11 17:24:00 +0100 (Wed, 11 May 2005)
New Revision: 1187
Modified:
trunk/priv/guest-amd64/toIR.c
Log:
gcc-2.96 build fixes
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-11 16:13:37 UTC (rev 1186)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-11 16:24:00 UTC (rev 1187)
@@ -12302,7 +12302,8 @@
//.. break;
=20
case 0x8F: { /* POPQ m64 / POPW m16 */
- Int len;
+ Int len;
+ UChar rm;
/* There is no encoding for 32-bit pop in 64-bit mode.
So sz=3D=3D4 actually means sz=3D=3D8. */
if (haveF2orF3(pfx)) goto decode_failure;
@@ -12310,7 +12311,7 @@
if (sz =3D=3D 4) sz =3D 8;
if (sz !=3D 8) goto decode_failure; // until we know a sz=3D=3D2 t=
est case exists
=20
- UChar rm =3D getUChar(delta);
+ rm =3D getUChar(delta);
=20
/* make sure this instruction is correct POP */
if (epartIsReg(rm) || gregLO3ofRM(rm) !=3D 0)
|
|
From: <sv...@va...> - 2005-05-11 16:13:39
|
Author: sewardj
Date: 2005-05-11 17:13:37 +0100 (Wed, 11 May 2005)
New Revision: 1186
Modified:
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/isel.c
Log:
Make the amd64 back end capable of dealing with the stuff memcheck
generates for 128-bit vector primops.
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-11 15:37:50 UTC (rev 1185)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-11 16:13:37 UTC (rev 1186)
@@ -1603,9 +1603,12 @@
i->Ain.Sse64FLo.dst);
return;
case Ain_SseReRg:
- if (i->Ain.SseReRg.op =3D=3D Asse_XOR
- && i->Ain.SseReRg.src =3D=3D i->Ain.SseReRg.dst) {
- /* reg-alloc needs to understand 'xor r,r' as a write of r *=
/
+ if ( (i->Ain.SseReRg.op =3D=3D Asse_XOR
+ || i->Ain.SseReRg.op =3D=3D Asse_CMPEQ32)
+ && i->Ain.SseReRg.src =3D=3D i->Ain.SseReRg.dst) {
+ /* reg-alloc needs to understand 'xor r,r' and 'cmpeqd
+ r,r' as a write of a value to r, and independent of any
+ previous value in r */
/* (as opposed to a rite of passage :-) */
addHRegUse(u, HRmWrite, i->Ain.SseReRg.dst);
} else {
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-11 15:37:50 UTC (rev 1185)
+++ trunk/priv/host-amd64/isel.c 2005-05-11 16:13:37 UTC (rev 1186)
@@ -698,17 +698,31 @@
}
=20
=20
-/* Generate !src into a new vector register. Amazing that there isn't
- a less crappy way to do this.
+/* Generate all-zeroes into a new vector register.
*/
-static HReg do_sse_NotV128 ( ISelEnv* env, HReg src )
+static HReg generate_zeroes_V128 ( ISelEnv* env )
{
HReg dst =3D newVRegV(env);
- /* Set dst to zero. Not strictly necessary. */
addInstr(env, AMD64Instr_SseReRg(Asse_XOR, dst, dst));
- /* And now make it all 1s ... */
+ return dst;
+}
+
+/* Generate all-ones into a new vector register.
+*/
+static HReg generate_ones_V128 ( ISelEnv* env )
+{
+ HReg dst =3D newVRegV(env);
addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, dst, dst));
- /* Finally, xor 'src' into it. */
+ return dst;
+}
+
+
+/* Generate !src into a new vector register. Amazing that there isn't
+ a less crappy way to do this.
+*/
+static HReg do_sse_NotV128 ( ISelEnv* env, HReg src )
+{
+ HReg dst =3D generate_ones_V128(env);
addInstr(env, AMD64Instr_SseReRg(Asse_XOR, src, dst));
return dst;
}
@@ -3053,7 +3067,7 @@
HReg dst =3D newVRegV(env);
vassert(e->Iex.Const.con->tag =3D=3D Ico_V128);
if (e->Iex.Const.con->Ico.V128 =3D=3D 0x0000) {
- addInstr(env, AMD64Instr_SseReRg(Asse_XOR, dst, dst));
+ dst =3D generate_zeroes_V128(env);
return dst;
} else
if (e->Iex.Const.con->Ico.V128 =3D=3D 0x00FF) {
@@ -3108,9 +3122,8 @@
(2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)=20
*/
HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
- HReg tmp =3D newVRegV(env);
+ HReg tmp =3D generate_zeroes_V128(env);
HReg dst =3D newVRegV(env);
- addInstr(env, AMD64Instr_SseReRg(Asse_XOR, tmp, tmp));
addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, arg, tmp));
tmp =3D do_sse_NotV128(env, tmp);
addInstr(env, AMD64Instr_SseShuf(0xB1, tmp, dst));
@@ -3118,59 +3131,20 @@
return dst;
}
=20
-//.. case Iop_CmpNEZ32x4: {
-//.. /* Sigh, we have to generate lousy code since this has to
-//.. work on SSE1 hosts */
-//.. /* basically, the idea is: for each lane:
-//.. movl lane, %r ; negl %r (now CF =3D lane=3D=3D0 ? =
0 : 1)
-//.. sbbl %r, %r (now %r =3D 1Sto32(CF))
-//.. movl %r, lane
-//.. */
-//.. Int i;
-//.. X86AMode* am;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. HReg r32 =3D newVRegI(env);
-//.. sub_from_esp(env, 16);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, arg, esp0))=
;
-//.. for (i =3D 0; i < 4; i++) {
-//.. am =3D X86AMode_IR(i*4, hregX86_ESP());
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am),=
r32));
-//.. addInstr(env, X86Instr_Unary32(Xun_NEG, X86RM_Reg(r32))=
);
-//.. addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(r32)=
, r32));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r32),=
am));
-//.. }
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_CmpNEZ8x16:
-//.. case Iop_CmpNEZ16x8: {
-//.. /* We can use SSE2 instructions for this. */
-//.. HReg arg;
-//.. HReg vec0 =3D newVRegV(env);
-//.. HReg vec1 =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. X86SseOp cmpOp=20
-//.. =3D e->Iex.Unop.op=3D=3DIop_CmpNEZ16x8 ? Xsse_CMPEQ16
-//.. : Xsse_CMPEQ8;
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, vec0, vec0));
-//.. addInstr(env, mk_vMOVsd_RR(vec0, vec1));
-//.. addInstr(env, X86Instr_Sse32Fx4(Xsse_CMPEQF, vec1, vec1));
-//.. /* defer arg computation to here so as to give CMPEQF as l=
ong
-//.. as possible to complete */
-//.. arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. /* vec0 is all 0s; vec1 is all 1s */
-//.. addInstr(env, mk_vMOVsd_RR(arg, dst));
-//.. /* 16x8 or 8x16 comparison =3D=3D */
-//.. addInstr(env, X86Instr_SseReRg(cmpOp, vec0, dst));
-//.. /* invert result */
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, vec1, dst));
-//.. return dst;
-//.. }
+ case Iop_CmpNEZ32x4: op =3D Asse_CMPEQ32; goto do_CmpNEZ_vector;
+ case Iop_CmpNEZ16x8: op =3D Asse_CMPEQ16; goto do_CmpNEZ_vector;
+ case Iop_CmpNEZ8x16: op =3D Asse_CMPEQ8; goto do_CmpNEZ_vector;
+ do_CmpNEZ_vector:
+ {
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg tmp =3D newVRegV(env);
+ HReg zero =3D generate_zeroes_V128(env);
+ HReg dst;
+ addInstr(env, mk_vMOVsd_RR(arg, tmp));
+ addInstr(env, AMD64Instr_SseReRg(op, zero, tmp));
+ dst =3D do_sse_NotV128(env, tmp);
+ return dst;
+ }
=20
case Iop_Recip32Fx4: op =3D Asse_RCPF; goto do_32Fx4_unary;
case Iop_RSqrt32Fx4: op =3D Asse_RSQRTF; goto do_32Fx4_unary;
|
|
From: <sv...@va...> - 2005-05-11 15:37:58
|
Author: sewardj
Date: 2005-05-11 16:37:50 +0100 (Wed, 11 May 2005)
New Revision: 1185
Modified:
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
Log:
AMD64 backend cleanup: get rid of instruction variants which the insn
selector doesn't generate.
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-11 10:05:04 UTC (rev 1184)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-11 15:37:50 UTC (rev 1185)
@@ -681,7 +681,7 @@
vassert(op !=3D Aalu_MUL);
return i;
}
-AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp op, UInt src, AMD64RM* dst ) =
{
+AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp op, UInt src, HReg dst ) {
AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
i->tag =3D Ain_Sh64;
i->Ain.Sh64.op =3D op;
@@ -689,27 +689,25 @@
i->Ain.Sh64.dst =3D dst;
return i;
}
-AMD64Instr* AMD64Instr_Test64 ( AMD64RI* src, AMD64RM* dst ) {
- AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
- i->tag =3D Ain_Test64;
- i->Ain.Test64.src =3D src;
- i->Ain.Test64.dst =3D dst;
+AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ) {
+ AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag =3D Ain_Test64;
+ i->Ain.Test64.imm32 =3D imm32;
+ i->Ain.Test64.dst =3D dst;
return i;
}
-AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, AMD64RM* dst ) {
+AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ) {
AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
i->tag =3D Ain_Unary64;
i->Ain.Unary64.op =3D op;
i->Ain.Unary64.dst =3D dst;
return i;
}
-AMD64Instr* AMD64Instr_MulL ( Bool syned, Int sz, AMD64RM* src ) {
+AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* src ) {
AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
i->tag =3D Ain_MulL;
i->Ain.MulL.syned =3D syned;
- i->Ain.MulL.sz =3D sz;
i->Ain.MulL.src =3D src;
- vassert(sz =3D=3D 2 || sz =3D=3D 4 || sz =3D=3D 8);
return i;
}
AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* src ) {
@@ -1066,22 +1064,18 @@
vex_printf("%%cl,");=20
else=20
vex_printf("$%d,", (Int)i->Ain.Sh64.src);
- ppAMD64RM(i->Ain.Sh64.dst);
+ ppHRegAMD64(i->Ain.Sh64.dst);
return;
case Ain_Test64:
- vex_printf("testq ");
- ppAMD64RI(i->Ain.Test64.src);
- vex_printf(",");
- ppAMD64RM(i->Ain.Test64.dst);
+ vex_printf("testq $%d,", (Int)i->Ain.Test64.imm32);
+ ppHRegAMD64(i->Ain.Test64.dst);
return;
case Ain_Unary64:
vex_printf("%sq ", showAMD64UnaryOp(i->Ain.Unary64.op));
- ppAMD64RM(i->Ain.Unary64.dst);
+ ppHRegAMD64(i->Ain.Unary64.dst);
return;
case Ain_MulL:
- vex_printf("%cmul%s ",
- i->Ain.MulL.syned ? 's' : 'u',
- showAMD64ScalarSz(i->Ain.MulL.sz));
+ vex_printf("%cmulq ", i->Ain.MulL.syned ? 's' : 'u');
ppAMD64RM(i->Ain.MulL.src);
return;
case Ain_Div:
@@ -1386,16 +1380,15 @@
addRegUsage_AMD64AMode(u, i->Ain.Alu64M.dst);
return;
case Ain_Sh64:
- addRegUsage_AMD64RM(u, i->Ain.Sh64.dst, HRmModify);
+ addHRegUse(u, HRmModify, i->Ain.Sh64.dst);
if (i->Ain.Sh64.src =3D=3D 0)
addHRegUse(u, HRmRead, hregAMD64_RCX());
return;
case Ain_Test64:
- addRegUsage_AMD64RI(u, i->Ain.Test64.src);
- addRegUsage_AMD64RM(u, i->Ain.Test64.dst, HRmRead);
+ addHRegUse(u, HRmRead, i->Ain.Test64.dst);
return;
case Ain_Unary64:
- addRegUsage_AMD64RM(u, i->Ain.Unary64.dst, HRmModify);
+ addHRegUse(u, HRmModify, i->Ain.Unary64.dst);
return;
case Ain_MulL:
addRegUsage_AMD64RM(u, i->Ain.MulL.src, HRmRead);
@@ -1657,14 +1650,13 @@
mapRegs_AMD64AMode(m, i->Ain.Alu64M.dst);
return;
case Ain_Sh64:
- mapRegs_AMD64RM(m, i->Ain.Sh64.dst);
+ mapReg(m, &i->Ain.Sh64.dst);
return;
case Ain_Test64:
- mapRegs_AMD64RI(m, i->Ain.Test64.src);
- mapRegs_AMD64RM(m, i->Ain.Test64.dst);
+ mapReg(m, &i->Ain.Test64.dst);
return;
case Ain_Unary64:
- mapRegs_AMD64RM(m, i->Ain.Unary64.dst);
+ mapReg(m, &i->Ain.Unary64.dst);
return;
case Ain_MulL:
mapRegs_AMD64RM(m, i->Ain.MulL.src);
@@ -1827,14 +1819,7 @@
*dst =3D i->Ain.Alu64R.dst;
return True;
}
-//.. /* Moves between FP regs */
-//.. if (i->tag =3D=3D Xin_FpUnary) {
-//.. if (i->Xin.FpUnary.op !=3D Xfp_MOV)
-//.. return False;
-//.. *src =3D i->Xin.FpUnary.src;
-//.. *dst =3D i->Xin.FpUnary.dst;
-//.. return True;
-//.. }
+ /* Moves between vector regs */
if (i->tag =3D=3D Ain_SseReRg) {
if (i->Ain.SseReRg.op !=3D Asse_MOV)
return False;
@@ -1860,8 +1845,6 @@
switch (hregClass(rreg)) {
case HRcInt64:
return AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am );
- //case HRcFlt64:
- // return AMD64Instr_FpLdSt ( False/*store*/, 8, rreg, am );
case HRcVec128:
return AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am );
default:=20
@@ -1879,8 +1862,6 @@
switch (hregClass(rreg)) {
case HRcInt64:
return AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg );
- //case HRcFlt64:
- // return AMD64Instr_FpLdSt ( True/*load*/, 8, rreg, am );
case HRcVec128:
return AMD64Instr_SseLdSt ( True/*load*/, 16, rreg, am );
default:=20
@@ -1925,19 +1906,6 @@
return toUChar(n);
}
=20
-
-
-//.. static UInt fregNo ( HReg r )
-//.. {
-//.. UInt n;
-//.. vassert(hregClass(r) =3D=3D HRcFlt64);
-//.. vassert(!hregIsVirtual(r));
-//.. n =3D hregNumber(r);
-//.. vassert(n <=3D 5);
-//.. return n;
-//.. }
-
-
/* Given an xmm (128bit V-class) register number, produce the
equivalent numbered register in 64-bit I-class. This is a bit of
fakery which facilitates using functions that work on integer
@@ -2455,91 +2423,64 @@
default: goto bad;
}
if (i->Ain.Sh64.src =3D=3D 0) {
- *p++ =3D rexAMode_R(fake(0),=20
- i->Ain.Sh64.dst->Arm.Reg.reg);
+ *p++ =3D rexAMode_R(fake(0), i->Ain.Sh64.dst);
*p++ =3D toUChar(opc_cl);
- switch (i->Ain.Sh64.dst->tag) {
- case Arm_Reg:
- p =3D doAMode_R(p, fake(subopc),=20
- i->Ain.Sh64.dst->Arm.Reg.reg);
- goto done;
- default:
- goto bad;
- }
+ p =3D doAMode_R(p, fake(subopc), i->Ain.Sh64.dst);
+ goto done;
} else {
- *p++ =3D rexAMode_R(fake(0), i->Ain.Sh64.dst->Arm.Reg.reg);
+ *p++ =3D rexAMode_R(fake(0), i->Ain.Sh64.dst);
*p++ =3D toUChar(opc_imm);
- switch (i->Ain.Sh64.dst->tag) {
- case Arm_Reg:
- p =3D doAMode_R(p, fake(subopc),=20
- i->Ain.Sh64.dst->Arm.Reg.reg);
- *p++ =3D (UChar)(i->Ain.Sh64.src);
- goto done;
- default:
- goto bad;
- }
+ p =3D doAMode_R(p, fake(subopc), i->Ain.Sh64.dst);
+ *p++ =3D (UChar)(i->Ain.Sh64.src);
+ goto done;
}
break;
=20
case Ain_Test64:
- if (i->Ain.Test64.src->tag =3D=3D Ari_Imm
- && i->Ain.Test64.dst->tag =3D=3D Arm_Reg) {
- /* testq sign-extend($imm32), %reg */
- *p++ =3D rexAMode_R(fake(0), i->Ain.Test64.dst->Arm.Reg.reg);
+ /* testq sign-extend($imm32), %reg */
+ *p++ =3D rexAMode_R(fake(0), i->Ain.Test64.dst);
+ *p++ =3D 0xF7;
+ p =3D doAMode_R(p, fake(0), i->Ain.Test64.dst);
+ p =3D emit32(p, i->Ain.Test64.imm32);
+ goto done;
+
+ case Ain_Unary64:
+ if (i->Ain.Unary64.op =3D=3D Aun_NOT) {
+ *p++ =3D rexAMode_R(fake(0), i->Ain.Unary64.dst);
*p++ =3D 0xF7;
- p =3D doAMode_R(p, fake(0), i->Ain.Test64.dst->Arm.Reg.reg);
- p =3D emit32(p, i->Ain.Test64.src->Ari.Imm.imm32);
+ p =3D doAMode_R(p, fake(2), i->Ain.Unary64.dst);
goto done;
}
+ if (i->Ain.Unary64.op =3D=3D Aun_NEG) {
+ *p++ =3D rexAMode_R(fake(0), i->Ain.Unary64.dst);
+ *p++ =3D 0xF7;
+ p =3D doAMode_R(p, fake(3), i->Ain.Unary64.dst);
+ goto done;
+ }
break;
=20
- case Ain_Unary64:
- if (i->Ain.Unary64.op =3D=3D Aun_NOT) {
- if (i->Ain.Unary64.dst->tag =3D=3D Arm_Reg) {
- *p++ =3D rexAMode_R(fake(0), i->Ain.Unary64.dst->Arm.Reg.reg=
);
+ case Ain_MulL:
+ subopc =3D i->Ain.MulL.syned ? 5 : 4;
+ switch (i->Ain.MulL.src->tag) {
+ case Arm_Mem:
+ *p++ =3D rexAMode_M( fake(0),
+ i->Ain.MulL.src->Arm.Mem.am);
*p++ =3D 0xF7;
- p =3D doAMode_R(p, fake(2), i->Ain.Unary64.dst->Arm.Reg.reg)=
;
+ p =3D doAMode_M(p, fake(subopc),
+ i->Ain.MulL.src->Arm.Mem.am);
goto done;
- } else {
- goto bad;
- }
- }
- if (i->Ain.Unary64.op =3D=3D Aun_NEG) {
- if (i->Ain.Unary64.dst->tag =3D=3D Arm_Reg) {
- *p++ =3D rexAMode_R(fake(0), i->Ain.Unary64.dst->Arm.Reg.reg=
);
+ case Arm_Reg:
+ *p++ =3D rexAMode_R(fake(0),=20
+ i->Ain.MulL.src->Arm.Reg.reg);
*p++ =3D 0xF7;
- p =3D doAMode_R(p, fake(3), i->Ain.Unary64.dst->Arm.Reg.reg)=
;
+ p =3D doAMode_R(p, fake(subopc),=20
+ i->Ain.MulL.src->Arm.Reg.reg);
goto done;
- } else {
+ default:
goto bad;
- }
}
break;
=20
- case Ain_MulL:
- subopc =3D i->Ain.MulL.syned ? 5 : 4;
- if (i->Ain.MulL.sz =3D=3D 8) {
- switch (i->Ain.MulL.src->tag) {
- case Arm_Mem:
- *p++ =3D rexAMode_M( fake(0),
- i->Ain.MulL.src->Arm.Mem.am);
- *p++ =3D 0xF7;
- p =3D doAMode_M(p, fake(subopc),
- i->Ain.MulL.src->Arm.Mem.am);
- goto done;
- case Arm_Reg:
- *p++ =3D rexAMode_R(fake(0),=20
- i->Ain.MulL.src->Arm.Reg.reg);
- *p++ =3D 0xF7;
- p =3D doAMode_R(p, fake(subopc),=20
- i->Ain.MulL.src->Arm.Reg.reg);
- goto done;
- default:
- goto bad;
- }
- }
- break;
-
case Ain_Div:
subopc =3D i->Ain.Div.syned ? 7 : 6;
if (i->Ain.Div.sz =3D=3D 4) {
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-05-11 10:05:04 UTC (rev 1184)
+++ trunk/priv/host-amd64/hdefs.h 2005-05-11 15:37:50 UTC (rev 1185)
@@ -429,22 +429,21 @@
struct {
AMD64ShiftOp op;
UInt src; /* shift amount, or 0 means %cl */
- AMD64RM* dst;
+ HReg dst;
} Sh64;
struct {
- AMD64RI* src;
- AMD64RM* dst;
+ UInt imm32;
+ HReg dst;
} Test64;
/* Not and Neg */
struct {
AMD64UnaryOp op;
- AMD64RM* dst;
+ HReg dst;
} Unary64;
- /* DX:AX =3D AX *s/u r/m16, or EDX:EAX =3D EAX *s/u r/m32,
- or RDX:RAX =3D RAX *s/u r/m64 */
+ /* 64 x 64 -> 128 bit widening multiply: RDX:RAX =3D RAX *s/u
+ r/m64 */
struct {
Bool syned;
- Int sz; /* 2, 4 or 8 only */
AMD64RM* src;
} MulL;
/* amd64 div/idiv instruction. Modifies RDX and RAX and
@@ -651,10 +650,10 @@
extern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst );
extern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg )=
;
extern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64A=
Mode* );
-extern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, AMD64RM* dst=
);
-extern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, AMD64RM* =
);
-extern AMD64Instr* AMD64Instr_Test64 ( AMD64RI* src, AMD64RM* dst );
-extern AMD64Instr* AMD64Instr_MulL ( Bool syned, Int sz, AMD64RM* =
);
+extern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst );
+extern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, HReg );
+extern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst );
+extern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* );
extern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* =
);
//.. extern AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp, UInt amt, H=
Reg src, HReg dst );
extern AMD64Instr* AMD64Instr_Push ( AMD64RMI* );
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-11 10:05:04 UTC (rev 1184)
+++ trunk/priv/host-amd64/isel.c 2005-05-11 15:37:50 UTC (rev 1185)
@@ -659,7 +659,7 @@
addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Imm(3), reg));
addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
iselIntExpr_RMI(env, mode), reg));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 13, AMD64RM_Reg(reg)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 13, reg));
addInstr(env, AMD64Instr_Alu64R(
Aalu_OR, AMD64RMI_Imm(DEFAULT_MXCSR), reg));
addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(reg)));
@@ -689,7 +689,7 @@
*/
addInstr(env, mk_iMOVsd_RR(rrm, rrm2));
addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 10, AMD64RM_Reg(rrm2)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 10, rrm2));
addInstr(env, AMD64Instr_Alu64R(Aalu_OR,=20
AMD64RMI_Imm(DEFAULT_FPUCW), rrm2));
addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,=20
@@ -893,8 +893,8 @@
//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 16, X86RM_Reg(d=
st)));
//.. break;
case Iop_Sar32:
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, AMD64RM_Reg(ds=
t)));
- addInstr(env, AMD64Instr_Sh64(Ash_SAR, 32, AMD64RM_Reg(ds=
t)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, 32, dst));
break;
default:=20
ppIROp(e->Iex.Binop.op);
@@ -911,15 +911,12 @@
vassert(nshift >=3D 0);
if (nshift > 0)
/* Can't allow nshift=3D=3D0 since that means %cl */
- addInstr(env, AMD64Instr_Sh64(
- shOp,=20
- nshift,
- AMD64RM_Reg(dst)));
+ addInstr(env, AMD64Instr_Sh64(shOp, nshift, dst));
} else {
/* General case; we have to force the amount into %cl. */
HReg regR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, mk_iMOVsd_RR(regR,hregAMD64_RCX()));
- addInstr(env, AMD64Instr_Sh64(shOp, 0/* %cl */, AMD64RM_Reg(=
dst)));
+ addInstr(env, AMD64Instr_Sh64(shOp, 0/* %cl */, dst));
}
return dst;
}
@@ -1076,11 +1073,11 @@
HReg left64 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
addInstr(env, mk_iMOVsd_RR(left64, rdx));
addInstr(env, mk_iMOVsd_RR(left64, rax));
- addInstr(env, AMD64Instr_Sh64(Ash_SHR, 32, AMD64RM_Reg(rdx)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHR, 32, rdx));
addInstr(env, AMD64Instr_Div(syned, 4, rmRight));
addInstr(env, AMD64Instr_MovZLQ(rdx,rdx));
addInstr(env, AMD64Instr_MovZLQ(rax,rax));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, AMD64RM_Reg(rdx)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, rdx));
addInstr(env, mk_iMOVsd_RR(rax, dst));
addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(rdx), dst=
));
return dst;
@@ -1093,7 +1090,7 @@
HReg lo32s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, mk_iMOVsd_RR(hi32s, hi32));
addInstr(env, mk_iMOVsd_RR(lo32s, lo32));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, AMD64RM_Reg(hi32)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, hi32));
addInstr(env, AMD64Instr_MovZLQ(lo32,lo32));
addInstr(env, AMD64Instr_Alu64R(
Aalu_OR, AMD64RMI_Reg(lo32), hi32));
@@ -1107,7 +1104,7 @@
HReg lo16s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, mk_iMOVsd_RR(hi16s, hi16));
addInstr(env, mk_iMOVsd_RR(lo16s, lo16));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 16, AMD64RM_Reg(hi16)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 16, hi16));
addInstr(env, AMD64Instr_Alu64R(
Aalu_AND, AMD64RMI_Imm(0xFFFF), lo16));
addInstr(env, AMD64Instr_Alu64R(
@@ -1122,7 +1119,7 @@
HReg lo8s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, mk_iMOVsd_RR(hi8s, hi8));
addInstr(env, mk_iMOVsd_RR(lo8s, lo8));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 8, AMD64RM_Reg(hi8)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 8, hi8));
addInstr(env, AMD64Instr_Alu64R(
Aalu_AND, AMD64RMI_Imm(0xFF), lo8));
addInstr(env, AMD64Instr_Alu64R(
@@ -1154,10 +1151,10 @@
=20
addInstr(env, mk_iMOVsd_RR(a32s, a32));
addInstr(env, mk_iMOVsd_RR(b32s, b32));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, AMD64RM_Reg(a32))=
);
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, AMD64RM_Reg(b32))=
);
- addInstr(env, AMD64Instr_Sh64(shr_op, shift, AMD64RM_Reg(a32))=
);
- addInstr(env, AMD64Instr_Sh64(shr_op, shift, AMD64RM_Reg(b32))=
);
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, a32));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, b32));
+ addInstr(env, AMD64Instr_Sh64(shr_op, shift, a32));
+ addInstr(env, AMD64Instr_Sh64(shr_op, shift, b32));
addInstr(env, AMD64Instr_Alu64R(Aalu_MUL, AMD64RMI_Reg(a32), b3=
2));
return b32;
}
@@ -1259,8 +1256,8 @@
HReg dst =3D newVRegI(env);
HReg src =3D iselIntExpr_R(env, expr8);
addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, AMD64RM_Reg(dst)));
- addInstr(env, AMD64Instr_Sh64(Ash_SHR, 56, AMD64RM_Reg(dst)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHR, 56, dst));
return dst;
}
=20
@@ -1302,8 +1299,8 @@
HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
UInt amt =3D 32;
addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, AMD64RM_Reg(dst)=
));
- addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, AMD64RM_Reg(dst)=
));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, dst));
return dst;
}
case Iop_128HIto64: {
@@ -1342,8 +1339,8 @@
|| e->Iex.Unop.op=3D=3DIop_16Sto64 );
UInt amt =3D srcIs16 ? 48 : 56;
addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, AMD64RM_Reg(dst)=
));
- addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, AMD64RM_Reg(dst)=
));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, dst));
return dst;
}
case Iop_Not8:
@@ -1353,7 +1350,7 @@
HReg dst =3D newVRegI(env);
HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Unary64(Aun_NOT,AMD64RM_Reg(dst)));
+ addInstr(env, AMD64Instr_Unary64(Aun_NOT,dst));
return dst;
}
//.. case Iop_64HIto32: {
@@ -1378,8 +1375,7 @@
default: vassert(0);
}
addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Sh64(
- Ash_SHR, shift, AMD64RM_Reg(dst)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHR, shift, dst));
return dst;
}
case Iop_1Uto64:
@@ -1398,8 +1394,8 @@
HReg dst =3D newVRegI(env);
AMD64CondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
addInstr(env, AMD64Instr_Set64(cond,dst));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, AMD64RM_Reg(dst))=
);
- addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, AMD64RM_Reg(dst))=
);
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
return dst;
}
case Iop_Ctz64: {
@@ -1430,7 +1426,7 @@
HReg dst =3D newVRegI(env);
HReg reg =3D iselIntExpr_R(env, e->Iex.Unop.arg);
addInstr(env, mk_iMOVsd_RR(reg,dst));
- addInstr(env, AMD64Instr_Unary64(Aun_NEG,AMD64RM_Reg(dst)));
+ addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
return dst;
}
=20
@@ -1597,7 +1593,7 @@
HReg dst =3D newVRegI(env);
addInstr(env, mk_iMOVsd_RR(rX,dst));
r8 =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFF), AMD64RM_Reg(r=
8)));
+ addInstr(env, AMD64Instr_Test64(0xFF, r8));
addInstr(env, AMD64Instr_CMov64(Acc_Z,r0,dst));
return dst;
}
@@ -1958,8 +1954,8 @@
=20
/* 64to1 */
if (e->tag =3D=3D Iex_Unop && e->Iex.Unop.op =3D=3D Iop_64to1) {
- AMD64RM* rm =3D iselIntExpr_RM(env, e->Iex.Unop.arg);
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(1),rm));
+ HReg reg =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, AMD64Instr_Test64(1,reg));
return Acc_NZ;
}
=20
@@ -1969,7 +1965,7 @@
if (e->tag =3D=3D Iex_Unop=20
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ8) {
HReg r =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFF),AMD64RM_Reg(r)))=
;
+ addInstr(env, AMD64Instr_Test64(0xFF,r));
return Acc_NZ;
}
=20
@@ -1979,7 +1975,7 @@
if (e->tag =3D=3D Iex_Unop=20
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ16) {
HReg r =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFFFF),AMD64RM_Reg(r)=
));
+ addInstr(env, AMD64Instr_Test64(0xFFFF,r));
return Acc_NZ;
}
=20
@@ -2052,7 +2048,7 @@
HReg r =3D newVRegI(env);
addInstr(env, mk_iMOVsd_RR(r1,r));
addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, AMD64RM_Reg(r)));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, r));
switch (e->Iex.Binop.op) {
case Iop_CmpEQ32: return Acc_Z;
case Iop_CmpNE32: return Acc_NZ;
@@ -2265,7 +2261,7 @@
AMD64RM* rmLeft =3D iselIntExpr_RM(env, e->Iex.Binop.arg1);
HReg rRight =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, mk_iMOVsd_RR(rRight, hregAMD64_RAX()));
- addInstr(env, AMD64Instr_MulL(syned, 8, rmLeft));
+ addInstr(env, AMD64Instr_MulL(syned, rmLeft));
/* Result is now in RDX:RAX. Tell the caller. */
addInstr(env, mk_iMOVsd_RR(hregAMD64_RDX(), tHi));
addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), tLo));
@@ -2995,7 +2991,7 @@
r0 =3D iselDblExpr(env, e->Iex.Mux0X.expr0);
dst =3D newVRegV(env);
addInstr(env, mk_vMOVsd_RR(rX,dst));
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFF), AMD64RM_Reg(r8)=
));
+ addInstr(env, AMD64Instr_Test64(0xFF, r8));
addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
return dst;
}
@@ -3475,7 +3471,7 @@
HReg r0 =3D iselVecExpr(env, e->Iex.Mux0X.expr0);
HReg dst =3D newVRegV(env);
addInstr(env, mk_vMOVsd_RR(rX,dst));
- addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFF), AMD64RM_Reg(r8)=
));
+ addInstr(env, AMD64Instr_Test64(0xFF, r8));
addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
return dst;
}
|
|
From: <sv...@va...> - 2005-05-11 11:57:50
|
Author: sewardj
Date: 2005-05-11 12:57:41 +0100 (Wed, 11 May 2005)
New Revision: 3659
Modified:
trunk/none/tests/amd64/gen_insn_test.pl
Log:
Use hi-half xmm registers (REX.R, REX.B =3D=3D 1) (%xmm8-%xmm15) in an
attempt to flush out any register-number bugs that might be lurking.
It would be nice to be able to do the same with the integer registers,
but gcc-3.3.4 is too stupid to understand asms with clobbered
registers "r8d", etc (plain "r8" etc is OK) and I am too ignorant of
perl to know how to mash r8b/r8w/r8d back into plain "r8" etc for the
clobbered registers list.
Modified: trunk/none/tests/amd64/gen_insn_test.pl
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/gen_insn_test.pl 2005-05-11 11:21:29 UTC (rev =
3658)
+++ trunk/none/tests/amd64/gen_insn_test.pl 2005-05-11 11:57:41 UTC (rev =
3659)
@@ -208,8 +208,8 @@
=20
my @intregs =3D @IntRegs;
my @mmregs =3D map { "mm$_" } (6,7,0,1,2,3,4,5);
- my @xmmregs =3D map { "xmm$_" } (4,5,0,1,2,3,6,7);
-# my @xmmregs =3D map { "xmm$_" } (12,13,8,9,10,11,14,15);
+# my @xmmregs =3D map { "xmm$_" } (4,5,0,1,2,3,6,7);
+ my @xmmregs =3D map { "xmm$_" } (12,13,8,9,10,11,14,15);
my @fpregs =3D map { "st$_" } (0 .. 7);
=20
my @presets;
|
|
From: <sv...@va...> - 2005-05-11 11:21:34
|
Author: sewardj Date: 2005-05-11 12:21:29 +0100 (Wed, 11 May 2005) New Revision: 3658 Added: trunk/none/tests/amd64/filter_cpuid trunk/none/tests/amd64/filter_int trunk/none/tests/amd64/filter_stderr trunk/none/tests/amd64/insn_mmx.stderr.exp trunk/none/tests/amd64/insn_mmx.stdout.exp trunk/none/tests/amd64/insn_mmx.vgtest trunk/none/tests/amd64/insn_sse.stderr.exp trunk/none/tests/amd64/insn_sse.stdout.exp trunk/none/tests/amd64/insn_sse.vgtest trunk/none/tests/amd64/insn_sse2.stderr.exp trunk/none/tests/amd64/insn_sse2.stdout.exp trunk/none/tests/amd64/insn_sse2.vgtest Modified: trunk/none/tests/amd64/Makefile.am Log: Regression tests for amd64 instructions. Modified: trunk/none/tests/amd64/Makefile.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/Makefile.am 2005-05-11 10:42:49 UTC (rev 3657) +++ trunk/none/tests/amd64/Makefile.am 2005-05-11 11:21:29 UTC (rev 3658) @@ -0,0 +1,27 @@ + +noinst_SCRIPTS =3D filter_cpuid filter_stderr filter_int gen_insn_test.p= l + +CLEANFILES =3D $(addsuffix .c,$(INSN_TESTS)) +INSN_TESTS=3Dinsn_mmx insn_sse insn_sse2 + +EXTRA_DIST =3D $(noinst_SCRIPTS) \ + $(addsuffix .stderr.exp,$(INSN_TESTS)) \ + $(addsuffix .stdout.exp,$(INSN_TESTS)) \ + $(addsuffix .vgtest,$(INSN_TESTS)) + +check_PROGRAMS =3D \ + $(INSN_TESTS) + +AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/inc= lude +AM_CXXFLAGS =3D $(AM_CFLAGS) + +# generic C ones +insn_mmx_SOURCES =3D insn_mmx.def +insn_mmx_LDADD =3D -lm +insn_sse_SOURCES =3D insn_sse.def +insn_sse_LDADD =3D -lm +insn_sse2_SOURCES =3D insn_sse2.def +insn_sse2_LDADD =3D -lm + +.def.c: $(srcdir)/gen_insn_test.pl + $(PERL) $(srcdir)/gen_insn_test.pl < $< > $@ Added: trunk/none/tests/amd64/filter_cpuid =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/filter_cpuid 2005-05-11 10:42:49 UTC (rev 3657= ) +++ trunk/none/tests/amd64/filter_cpuid 2005-05-11 11:21:29 UTC (rev 3658= ) @@ -0,0 +1,5 @@ +#! /bin/sh + +dir=3D`dirname $0` + +$dir/filter_stderr Property changes on: trunk/none/tests/amd64/filter_cpuid ___________________________________________________________________ Name: svn:executable + * Added: trunk/none/tests/amd64/filter_int =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/filter_int 2005-05-11 10:42:49 UTC (rev 3657) +++ trunk/none/tests/amd64/filter_int 2005-05-11 11:21:29 UTC (rev 3658) @@ -0,0 +1,6 @@ +#! /bin/sh + +dir=3D`dirname $0` + +$dir/filter_stderr | $dir/../../../tests/filter_addresses + Property changes on: trunk/none/tests/amd64/filter_int ___________________________________________________________________ Name: svn:executable + * Added: trunk/none/tests/amd64/filter_stderr =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/filter_stderr 2005-05-11 10:42:49 UTC (rev 365= 7) +++ trunk/none/tests/amd64/filter_stderr 2005-05-11 11:21:29 UTC (rev 365= 8) @@ -0,0 +1,4 @@ +#! /bin/sh + +../filter_stderr + Property changes on: trunk/none/tests/amd64/filter_stderr ___________________________________________________________________ Name: svn:executable + * Added: trunk/none/tests/amd64/insn_mmx.stderr.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_mmx.stderr.exp 2005-05-11 10:42:49 UTC (r= ev 3657) +++ trunk/none/tests/amd64/insn_mmx.stderr.exp 2005-05-11 11:21:29 UTC (r= ev 3658) @@ -0,0 +1,2 @@ + + Added: trunk/none/tests/amd64/insn_mmx.stdout.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_mmx.stdout.exp 2005-05-11 10:42:49 UTC (r= ev 3657) +++ trunk/none/tests/amd64/insn_mmx.stdout.exp 2005-05-11 11:21:29 UTC (r= ev 3658) @@ -0,0 +1,105 @@ +movd_1 ... ok +movd_2 ... ok +movd_3 ... ok +movd_4 ... ok +movd_5 ... ok +movd_6 ... ok +movq_1 ... ok +movq_2 ... ok +movq_3 ... ok +packssdw_1 ... ok +packssdw_2 ... ok +packsswb_1 ... ok +packsswb_2 ... ok +packuswb_1 ... ok +packuswb_2 ... ok +paddb_1 ... ok +paddb_2 ... ok +paddd_1 ... ok +paddd_2 ... ok +paddsb_1 ... ok +paddsb_2 ... ok +paddsw_1 ... ok +paddsw_2 ... ok +paddusb_1 ... ok +paddusb_2 ... ok +paddusw_1 ... ok +paddusw_2 ... ok +paddw_1 ... ok +paddw_2 ... ok +pand_1 ... ok +pand_2 ... ok +pandn_1 ... ok +pandn_2 ... ok +pcmpeqb_1 ... ok +pcmpeqb_2 ... ok +pcmpeqd_1 ... ok +pcmpeqd_2 ... ok +pcmpeqw_1 ... ok +pcmpeqw_2 ... ok +pcmpgtb_1 ... ok +pcmpgtb_2 ... ok +pcmpgtd_1 ... ok +pcmpgtd_2 ... ok +pcmpgtw_1 ... ok +pcmpgtw_2 ... ok +pmaddwd_1 ... ok +pmaddwd_2 ... ok +pmulhw_1 ... ok +pmulhw_2 ... ok +pmullw_1 ... ok +pmullw_2 ... ok +por_1 ... ok +por_2 ... ok +pslld_1 ... ok +pslld_2 ... ok +pslld_3 ... ok +psllq_1 ... ok +psllq_2 ... ok +psllq_3 ... ok +psllw_1 ... ok +psllw_2 ... ok +psllw_3 ... ok +psrad_1 ... ok +psrad_2 ... ok +psrad_3 ... ok +psraw_1 ... ok +psraw_2 ... ok +psraw_3 ... ok +psrld_1 ... ok +psrld_2 ... ok +psrld_3 ... ok +psrlq_1 ... ok +psrlq_2 ... ok +psrlq_3 ... ok +psrlw_1 ... ok +psrlw_2 ... ok +psrlw_3 ... ok +psubb_1 ... ok +psubb_2 ... ok +psubd_1 ... ok +psubd_2 ... ok +psubsb_1 ... ok +psubsb_2 ... ok +psubsw_1 ... ok +psubsw_2 ... ok +psubusb_1 ... ok +psubusb_2 ... ok +psubusw_1 ... ok +psubusw_2 ... ok +psubw_1 ... ok +psubw_2 ... ok +punpckhbw_1 ... ok +punpckhbw_2 ... ok +punpckhdq_1 ... ok +punpckhdq_2 ... ok +punpckhwd_1 ... ok +punpckhwd_2 ... ok +punpcklbw_1 ... ok +punpcklbw_2 ... ok +punpckldq_1 ... ok +punpckldq_2 ... ok +punpcklwd_1 ... ok +punpcklwd_2 ... ok +pxor_1 ... ok +pxor_2 ... ok Added: trunk/none/tests/amd64/insn_mmx.vgtest =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_mmx.vgtest 2005-05-11 10:42:49 UTC (rev 3= 657) +++ trunk/none/tests/amd64/insn_mmx.vgtest 2005-05-11 11:21:29 UTC (rev 3= 658) @@ -0,0 +1 @@ +prog: insn_mmx Added: trunk/none/tests/amd64/insn_sse.stderr.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse.stderr.exp 2005-05-11 10:42:49 UTC (r= ev 3657) +++ trunk/none/tests/amd64/insn_sse.stderr.exp 2005-05-11 11:21:29 UTC (r= ev 3658) @@ -0,0 +1,2 @@ + + Added: trunk/none/tests/amd64/insn_sse.stdout.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse.stdout.exp 2005-05-11 10:42:49 UTC (r= ev 3657) +++ trunk/none/tests/amd64/insn_sse.stdout.exp 2005-05-11 11:21:29 UTC (r= ev 3658) @@ -0,0 +1,146 @@ +addps_1 ... ok +addps_2 ... ok +addss_1 ... ok +addss_2 ... ok +andnps_1 ... ok +andnps_2 ... ok +andps_1 ... ok +andps_2 ... ok +cmpeqps_1 ... ok +cmpeqps_2 ... ok +cmpeqss_1 ... ok +cmpeqss_2 ... ok +cmpleps_1 ... ok +cmpleps_2 ... ok +cmpless_1 ... ok +cmpless_2 ... ok +cmpltps_1 ... ok +cmpltps_2 ... ok +cmpltss_1 ... ok +cmpltss_2 ... ok +cmpneqps_1 ... ok +cmpneqps_2 ... ok +cmpneqss_1 ... ok +cmpneqss_2 ... ok +cmpnleps_1 ... ok +cmpnleps_2 ... ok +cmpnless_1 ... ok +cmpnless_2 ... ok +cmpnltps_1 ... ok +cmpnltps_2 ... ok +cmpnltss_1 ... ok +cmpnltss_2 ... ok +comiss_1 ... ok +comiss_2 ... ok +comiss_3 ... ok +comiss_4 ... ok +comiss_5 ... ok +comiss_6 ... ok +cvtpi2ps_1 ... ok +cvtpi2ps_2 ... ok +cvtps2pi_1 ... ok +cvtps2pi_2 ... ok +cvtsi2ss_1 ... ok +cvtsi2ss_2 ... ok +cvtss2si_1 ... ok +cvtss2si_2 ... ok +cvttps2pi_1 ... ok +cvttps2pi_2 ... ok +cvttss2si_1 ... ok +cvttss2si_2 ... ok +divps_1 ... ok +divps_2 ... ok +divss_1 ... ok +divss_2 ... ok +maxps_1 ... ok +maxps_2 ... ok +maxss_1 ... ok +maxss_2 ... ok +minps_1 ... ok +minps_2 ... ok +minss_1 ... ok +minss_2 ... ok +movaps_1 ... ok +movaps_2 ... ok +movhlps_1 ... ok +movhps_1 ... ok +movhps_2 ... ok +movlhps_1 ... ok +movlps_1 ... ok +movlps_2 ... ok +movmskps_1 ... ok +movntps_1 ... ok +movntq_1 ... ok +movss_1 ... ok +movss_2 ... ok +movss_3 ... ok +movups_1 ... ok +movups_2 ... ok +mulps_1 ... ok +mulps_2 ... ok +mulss_1 ... ok +mulss_2 ... ok +orps_1 ... ok +orps_2 ... ok +pavgb_1 ... ok +pavgb_2 ... ok +pavgw_1 ... ok +pavgw_2 ... ok +pextrw_1 ... ok +pextrw_2 ... ok +pextrw_3 ... ok +pextrw_4 ... ok +pinsrw_1 ... ok +pinsrw_2 ... ok +pinsrw_3 ... ok +pinsrw_4 ... ok +pinsrw_5 ... ok +pinsrw_6 ... ok +pinsrw_7 ... ok +pinsrw_8 ... ok +pmaxsw_1 ... ok +pmaxsw_2 ... ok +pmaxub_1 ... ok +pmaxub_2 ... ok +pminsw_1 ... ok +pminsw_2 ... ok +pminub_1 ... ok +pminub_2 ... ok +pmovmskb_1 ... ok +pmulhuw_1 ... ok +pmulhuw_2 ... ok +psadbw_1 ... ok +psadbw_2 ... ok +pshufw_1 ... ok +pshufw_2 ... ok +rcpps_1 ... ok +rcpps_2 ... ok +rcpss_1 ... ok +rcpss_2 ... ok +rsqrtps_1 ... ok +rsqrtps_2 ... ok +rsqrtss_1 ... ok +rsqrtss_2 ... ok +sfence_1 ... ok +shufps_1 ... ok +shufps_2 ... ok +sqrtps_1 ... ok +sqrtps_2 ... ok +sqrtss_1 ... ok +sqrtss_2 ... ok +subps_1 ... ok +subps_2 ... ok +subss_1 ... ok +subss_2 ... ok +ucomiss_1 ... ok +ucomiss_2 ... ok +ucomiss_3 ... ok +ucomiss_4 ... ok +ucomiss_5 ... ok +ucomiss_6 ... ok +unpckhps_1 ... ok +unpckhps_2 ... ok +unpcklps_1 ... ok +unpcklps_2 ... ok +xorps_1 ... ok +xorps_2 ... ok Added: trunk/none/tests/amd64/insn_sse.vgtest =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse.vgtest 2005-05-11 10:42:49 UTC (rev 3= 657) +++ trunk/none/tests/amd64/insn_sse.vgtest 2005-05-11 11:21:29 UTC (rev 3= 658) @@ -0,0 +1 @@ +prog: insn_sse Added: trunk/none/tests/amd64/insn_sse2.stderr.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse2.stderr.exp 2005-05-11 10:42:49 UTC (= rev 3657) +++ trunk/none/tests/amd64/insn_sse2.stderr.exp 2005-05-11 11:21:29 UTC (= rev 3658) @@ -0,0 +1,2 @@ + + Added: trunk/none/tests/amd64/insn_sse2.stdout.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse2.stdout.exp 2005-05-11 10:42:49 UTC (= rev 3657) +++ trunk/none/tests/amd64/insn_sse2.stdout.exp 2005-05-11 11:21:29 UTC (= rev 3658) @@ -0,0 +1,328 @@ +addpd_1 ... ok +addpd_2 ... ok +addsd_1 ... ok +addsd_2 ... ok +andpd_1 ... ok +andpd_2 ... ok +andnpd_1 ... ok +andnpd_2 ... ok +cmpeqpd_1 ... ok +cmpeqpd_2 ... ok +cmpltpd_1 ... ok +cmpltpd_2 ... ok +cmplepd_1 ... ok +cmplepd_2 ... ok +cmpneqpd_1 ... ok +cmpneqpd_2 ... ok +cmpnltpd_1 ... ok +cmpnltpd_2 ... ok +cmpnlepd_1 ... ok +cmpnlepd_2 ... ok +cmpeqsd_1 ... ok +cmpeqsd_2 ... ok +cmpltsd_1 ... ok +cmpltsd_2 ... ok +cmplesd_1 ... ok +cmplesd_2 ... ok +cmpneqsd_1 ... ok +cmpneqsd_2 ... ok +cmpnltsd_1 ... ok +cmpnltsd_2 ... ok +cmpnlesd_1 ... ok +cmpnlesd_2 ... ok +comisd_1 ... ok +comisd_2 ... ok +comisd_3 ... ok +comisd_4 ... ok +comisd_5 ... ok +comisd_6 ... ok +cvtdq2pd_1 ... ok +cvtdq2pd_2 ... ok +cvtdq2ps_1 ... ok +cvtdq2ps_2 ... ok +cvtpd2dq_1 ... ok +cvtpd2dq_2 ... ok +cvtpd2pi_1 ... ok +cvtpd2pi_2 ... ok +cvtpd2ps_1 ... ok +cvtpd2ps_2 ... ok +cvtpi2pd_1 ... ok +cvtpi2pd_2 ... ok +cvtps2dq_1 ... ok +cvtps2dq_2 ... ok +cvtps2pd_1 ... ok +cvtps2pd_2 ... ok +cvtsd2si_1 ... ok +cvtsd2si_2 ... ok +cvtsd2ss_1 ... ok +cvtsd2ss_2 ... ok +cvtsi2sd_1 ... ok +cvtsi2sd_2 ... ok +cvtss2sd_1 ... ok +cvtss2sd_2 ... ok +cvttpd2pi_1 ... ok +cvttpd2pi_2 ... ok +cvttpd2dq_1 ... ok +cvttpd2dq_2 ... ok +cvttps2dq_1 ... ok +cvttps2dq_2 ... ok +cvttsd2si_1 ... ok +cvttsd2si_2 ... ok +divpd_1 ... ok +divpd_2 ... ok +divsd_1 ... ok +divsd_2 ... ok +lfence_1 ... ok +maxpd_1 ... ok +maxpd_2 ... ok +maxsd_1 ... ok +maxsd_2 ... ok +mfence_1 ... ok +minpd_1 ... ok +minpd_2 ... ok +minsd_1 ... ok +minsd_2 ... ok +movapd_1 ... ok +movapd_2 ... ok +movd_1 ... ok +movd_2 ... ok +movd_3 ... ok +movd_4 ... ok +movdqa_1 ... ok +movdqa_2 ... ok +movdqa_3 ... ok +movdqu_1 ... ok +movdqu_2 ... ok +movdqu_3 ... ok +movdq2q_1 ... ok +movhpd_1 ... ok +movhpd_2 ... ok +movlpd_1 ... ok +movlpd_2 ... ok +movmskpd_1 ... ok +movntdq_1 ... ok +movnti_1 ... ok +movntpd_1 ... ok +movq2dq_1 ... ok +movsd_1 ... ok +movsd_2 ... ok +movsd_3 ... ok +movupd_1 ... ok +movupd_2 ... ok +mulpd_1 ... ok +mulpd_2 ... ok +mulsd_1 ... ok +mulsd_2 ... ok +orpd_1 ... ok +orpd_2 ... ok +packssdw_1 ... ok +packssdw_2 ... ok +packsswb_1 ... ok +packsswb_2 ... ok +packuswb_1 ... ok +packuswb_2 ... ok +paddb_1 ... ok +paddb_2 ... ok +paddd_1 ... ok +paddd_2 ... ok +paddq_1 ... ok +paddq_2 ... ok +paddq_3 ... ok +paddq_4 ... ok +paddsb_1 ... ok +paddsb_2 ... ok +paddsw_1 ... ok +paddsw_2 ... ok +paddusb_1 ... ok +paddusb_2 ... ok +paddusw_1 ... ok +paddusw_2 ... ok +paddw_1 ... ok +paddw_2 ... ok +pand_1 ... ok +pand_2 ... ok +pandn_1 ... ok +pandn_2 ... ok +pavgb_1 ... ok +pavgb_2 ... ok +pavgw_1 ... ok +pavgw_2 ... ok +pcmpeqb_1 ... ok +pcmpeqb_2 ... ok +pcmpeqd_1 ... ok +pcmpeqd_2 ... ok +pcmpeqw_1 ... ok +pcmpeqw_2 ... ok +pcmpgtb_1 ... ok +pcmpgtb_2 ... ok +pcmpgtd_1 ... ok +pcmpgtd_2 ... ok +pcmpgtw_1 ... ok +pcmpgtw_2 ... ok +pextrw_1 ... ok +pextrw_2 ... ok +pextrw_3 ... ok +pextrw_4 ... ok +pextrw_5 ... ok +pextrw_6 ... ok +pextrw_7 ... ok +pextrw_8 ... ok +pinsrw_1 ... ok +pinsrw_2 ... ok +pinsrw_3 ... ok +pinsrw_4 ... ok +pinsrw_5 ... ok +pinsrw_6 ... ok +pinsrw_7 ... ok +pinsrw_8 ... ok +pinsrw_9 ... ok +pinsrw_10 ... ok +pinsrw_11 ... ok +pinsrw_12 ... ok +pinsrw_13 ... ok +pinsrw_14 ... ok +pinsrw_15 ... ok +pinsrw_16 ... ok +pmaxsw_1 ... ok +pmaxsw_2 ... ok +pmaxub_1 ... ok +pmaxub_2 ... ok +pminsw_1 ... ok +pminsw_2 ... ok +pminub_1 ... ok +pminub_2 ... ok +pmovmskb_1 ... ok +pmulhuw_1 ... ok +pmulhuw_2 ... ok +pmulhw_1 ... ok +pmulhw_2 ... ok +pmullw_1 ... ok +pmullw_2 ... ok +pmuludq_1 ... ok +pmuludq_2 ... ok +pmuludq_3 ... ok +pmuludq_4 ... ok +por_1 ... ok +por_2 ... ok +pshufd_1 ... ok +pshufd_2 ... ok +pshufhw_1 ... ok +pshufhw_2 ... ok +pshuflw_1 ... ok +pshuflw_2 ... ok +pslld_1 ... ok +pslld_2 ... ok +pslld_3 ... ok +pslldq_1 ... ok +pslldq_2 ... ok +pslldq_3 ... ok +pslldq_4 ... ok +pslldq_5 ... ok +pslldq_6 ... ok +pslldq_7 ... ok +pslldq_8 ... ok +pslldq_9 ... ok +pslldq_10 ... ok +pslldq_11 ... ok +pslldq_12 ... ok +pslldq_13 ... ok +pslldq_14 ... ok +pslldq_15 ... ok +pslldq_16 ... ok +pslldq_17 ... ok +psllq_1 ... ok +psllq_2 ... ok +psllq_3 ... ok +psllw_1 ... ok +psllw_2 ... ok +psllw_3 ... ok +psrad_1 ... ok +psrad_2 ... ok +psrad_3 ... ok +psraw_1 ... ok +psraw_2 ... ok +psraw_3 ... ok +psrld_1 ... ok +psrld_2 ... ok +psrld_3 ... ok +psrldq_1 ... ok +psrldq_2 ... ok +psrldq_3 ... ok +psrldq_4 ... ok +psrldq_5 ... ok +psrldq_6 ... ok +psrldq_7 ... ok +psrldq_8 ... ok +psrldq_9 ... ok +psrldq_10 ... ok +psrldq_11 ... ok +psrldq_12 ... ok +psrldq_13 ... ok +psrldq_14 ... ok +psrldq_15 ... ok +psrldq_16 ... ok +psrldq_17 ... ok +psrlq_1 ... ok +psrlq_2 ... ok +psrlq_3 ... ok +psrlw_1 ... ok +psrlw_2 ... ok +psrlw_3 ... ok +psubb_1 ... ok +psubb_2 ... ok +psubd_1 ... ok +psubd_2 ... ok +psubq_1 ... ok +psubq_2 ... ok +psubq_3 ... ok +psubq_4 ... ok +psubsb_1 ... ok +psubsb_2 ... ok +psubsw_1 ... ok +psubsw_2 ... ok +psubusb_1 ... ok +psubusb_2 ... ok +psubusw_1 ... ok +psubusw_2 ... ok +psubw_1 ... ok +psubw_2 ... ok +punpckhbw_1 ... ok +punpckhbw_2 ... ok +punpckhdq_1 ... ok +punpckhdq_2 ... ok +punpckhqdq_1 ... ok +punpckhqdq_2 ... ok +punpckhwd_1 ... ok +punpckhwd_2 ... ok +punpcklbw_1 ... ok +punpcklbw_2 ... ok +punpckldq_1 ... ok +punpckldq_2 ... ok +punpcklqdq_1 ... ok +punpcklqdq_2 ... ok +punpcklwd_1 ... ok +punpcklwd_2 ... ok +pxor_1 ... ok +pxor_2 ... ok +shufpd_1 ... ok +shufpd_2 ... ok +sqrtpd_1 ... ok +sqrtpd_2 ... ok +sqrtsd_1 ... ok +sqrtsd_2 ... ok +subpd_1 ... ok +subpd_2 ... ok +subsd_1 ... ok +subsd_2 ... ok +ucomisd_1 ... ok +ucomisd_2 ... ok +ucomisd_3 ... ok +ucomisd_4 ... ok +ucomisd_5 ... ok +ucomisd_6 ... ok +unpckhpd_1 ... ok +unpckhpd_2 ... ok +unpcklpd_1 ... ok +unpcklpd_2 ... ok +xorpd_1 ... ok +xorpd_2 ... ok Added: trunk/none/tests/amd64/insn_sse2.vgtest =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/amd64/insn_sse2.vgtest 2005-05-11 10:42:49 UTC (rev = 3657) +++ trunk/none/tests/amd64/insn_sse2.vgtest 2005-05-11 11:21:29 UTC (rev = 3658) @@ -0,0 +1 @@ +prog: insn_sse2 |
|
From: <sv...@va...> - 2005-05-11 10:42:55
|
Author: sewardj
Date: 2005-05-11 11:42:49 +0100 (Wed, 11 May 2005)
New Revision: 3657
Modified:
trunk/none/tests/amd64/gen_insn_test.pl
Log:
* gcc-3.3.4 seems to generate non-working code for eq_double: workaround
* fix wrong stack offset for comparisons involving %rflags
* (unused): sets of register names for reg numbers >=3D 8
Modified: trunk/none/tests/amd64/gen_insn_test.pl
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/amd64/gen_insn_test.pl 2005-05-11 02:12:31 UTC (rev =
3656)
+++ trunk/none/tests/amd64/gen_insn_test.pl 2005-05-11 10:42:49 UTC (rev =
3657)
@@ -79,6 +79,17 @@
{ r8 =3D> "dh" }
);
=20
+#our @IntRegs =3D (
+# { r8 =3D> "r8b", r16 =3D> "r8w", r32 =3D> "r8d", r64 =3D=
> "r8" },
+# { r8 =3D> "r9b", r16 =3D> "r9w", r32 =3D> "r9d", r64 =3D=
> "r9" },
+# { r8 =3D> "r10b", r16 =3D> "r10w", r32 =3D> "r10d", r64=
=3D> "r10" },
+# { r8 =3D> "r11b", r16 =3D> "r11w", r32 =3D> "r11d", r64=
=3D> "r11" },
+# { r8 =3D> "ah" },
+# { r8 =3D> "bh" },
+# { r8 =3D> "ch" },
+# { r8 =3D> "dh" }
+# );
+
print <<EOF;
#include <math.h>
#include <setjmp.h>
@@ -144,13 +155,15 @@
__attribute__((unused))
static int eq_float(float f1, float f2)
{
- return f1 =3D=3D f2 || fabsf(f1 - f2) < fabsf(f1) * 1.5 * powf(2,-12)=
;
+ /* return f1 =3D=3D f2 || fabsf(f1 - f2) < fabsf(f1) * 1.5 * powf(2,-=
12); */
+ return f1 =3D=3D f2 || fabsf(f1 - f2) < fabsf(f1) * 1.5 / 4096.0;
}
=20
__attribute__((unused))
static int eq_double(double d1, double d2)
{
- return d1 =3D=3D d2 || fabs(d1 - d2) < fabs(d1) * 1.5 * pow(2,-12);
+ /* return d1 =3D=3D d2 || fabs(d1 - d2) < fabs(d1) * 1.5 * pow(2,-12)=
; */
+ return d1 =3D=3D d2 || fabs(d1 - d2) < fabs(d1) * 1.5 / 4096.0;
}
=20
EOF
@@ -196,6 +209,7 @@
my @intregs =3D @IntRegs;
my @mmregs =3D map { "mm$_" } (6,7,0,1,2,3,4,5);
my @xmmregs =3D map { "xmm$_" } (4,5,0,1,2,3,6,7);
+# my @xmmregs =3D map { "xmm$_" } (12,13,8,9,10,11,14,15);
my @fpregs =3D map { "st$_" } (0 .. 7);
=20
my @presets;
@@ -695,7 +709,7 @@
{
print qq| \"pushfq\\n\"\n|;
print qq| \"andl \$$eflagsmask, (%%rsp)\\n\"\n| if defin=
ed($eflagsmask);
- print qq| \"andl \$0, 8(%%rsp)\\n\"\n| if defined($eflag=
smask);
+ print qq| \"andl \$0, 4(%%rsp)\\n\"\n| if defined($eflag=
smask);
print qq| \"orq \$$eflagsset, (%%rsp)\\n\"\n| if defined=
($eflagsset);
print qq| \"popfq\\n\"\n|;
}
|
|
From: <sv...@va...> - 2005-05-11 10:05:07
|
Author: sewardj
Date: 2005-05-11 11:05:04 +0100 (Wed, 11 May 2005)
New Revision: 1184
Modified:
trunk/priv/host-x86/isel.c
Log:
These cases are now verified.
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2005-05-11 10:03:08 UTC (rev 1183)
+++ trunk/priv/host-x86/isel.c 2005-05-11 10:05:04 UTC (rev 1184)
@@ -571,7 +571,7 @@
=20
switch (elemSz) {
case 1: shift =3D 0; break;
- case 4: shift =3D 2; vassert(0); /* awaiting test case */ break;
+ case 4: shift =3D 2; break;
case 8: shift =3D 3; break;
default: vpanic("genGuestArrayOffset(x86 host)(2)");
}
@@ -1166,7 +1166,6 @@
return dst;
}
if (ty =3D=3D Ity_I32) {
- vassert(0); /* awaiting test case */
addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), dst));
return dst;
}
@@ -3376,7 +3375,6 @@
}
if (ty =3D=3D Ity_I32) {
HReg r =3D iselIntExpr_R(env, stmt->Ist.PutI.data);
- vassert(0); /* awaiting test case */
addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(r), am ));
return;
}
|
|
From: <sv...@va...> - 2005-05-11 10:03:18
|
Author: sewardj
Date: 2005-05-11 11:03:08 +0100 (Wed, 11 May 2005)
New Revision: 1183
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/hdefs.c
Log:
Placate icc.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-11 02:55:54 UTC (rev 1182)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-11 10:03:08 UTC (rev 1183)
@@ -891,7 +891,7 @@
/* Return True iff pfx has any of 66, F2 and F3 set */
static Bool have66orF2orF3 ( Prefix pfx )
{
- return ! haveNo66noF2noF3(pfx);
+ return toBool( ! haveNo66noF2noF3(pfx) );
}
=20
/* Clear all the segment-override bits in a prefix. */
@@ -2017,7 +2017,7 @@
return xmm_names[xmmreg];
}
=20
-static HChar* nameMMXGran ( UChar gran )
+static HChar* nameMMXGran ( Int gran )
{
switch (gran) {
case 0: return "b";
@@ -4305,7 +4305,7 @@
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_op_mem_ST_0 ( IRTemp addr, UChar* op_txt, UChar* dis_buf,=20
+void fp_do_op_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,=20
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
@@ -5039,7 +5039,7 @@
=20
case 0xC0 ... 0xC7: /* FCMOVB ST(i), ST(0) */
r_src =3D (UInt)modrm - 0xC0;
- DIP("fcmovb %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovb %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(0,=20
IRExpr_Mux0X(=20
unop(Iop_1Uto8,
@@ -5197,7 +5197,7 @@
=20
case 0xC0 ... 0xC7: /* FCMOVNB ST(i), ST(0) */
r_src =3D (UInt)modrm - 0xC0;
- DIP("fcmovnb %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnb %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(0,=20
IRExpr_Mux0X(=20
unop(Iop_1Uto8,
@@ -5883,7 +5883,7 @@
ULong dis_MMXop_regmem_to_reg ( Prefix pfx,
ULong delta,
UChar opc,
- Char* name,
+ HChar* name,
Bool show_granularity )
{
HChar dis_buf[50];
@@ -5898,7 +5898,7 @@
Bool invG =3D False;
IROp op =3D Iop_INVALID;
void* hAddr =3D NULL;
- Char* hName =3D NULL;
+ HChar* hName =3D NULL;
Bool eLeft =3D False;
=20
# define XXX(_name) do { hAddr =3D &_name; hName =3D #_name; } while (0=
)
@@ -6115,7 +6115,7 @@
vassert(epartIsReg(rm));
vassert(gregLO3ofRM(rm) =3D=3D 2=20
|| gregLO3ofRM(rm) =3D=3D 4 || gregLO3ofRM(rm) =3D=3D 6);
- amt =3D (Int)(getUChar(delta+1));
+ amt =3D getUChar(delta+1);
delta +=3D 2;
DIP("%s $%d,%s\n", opname,
(Int)amt,
@@ -6461,12 +6461,11 @@
case 0x72:=20
case 0x73: {
/* (sz=3D=3D4): PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */
- UChar byte1, byte2, subopc;
+ UChar byte2, subopc;
if (sz !=3D 4)=20
goto mmx_decode_failure;
- byte1 =3D opc; /* 0x71/72/73 */
- byte2 =3D getUChar(delta); /* amode / sub-opcode */
- subopc =3D (byte2 >> 3) & 7;
+ byte2 =3D getUChar(delta); /* amode / sub-opcode */
+ subopc =3D toUChar( (byte2 >> 3) & 7 );
=20
# define SHIFT_BY_IMM(_name,_op) \
do { delta =3D dis_MMX_shiftE_imm(delta,_name,_op); \
@@ -7755,7 +7754,7 @@
vassert(epartIsReg(rm));
vassert(gregLO3ofRM(rm) =3D=3D 2=20
|| gregLO3ofRM(rm) =3D=3D 4 || gregLO3ofRM(rm) =3D=3D 6);
- amt =3D (Int)(getUChar(delta+1));
+ amt =3D getUChar(delta+1);
delta +=3D 2;
DIP("%s $%d,%s\n", opname,
(Int)amt,
@@ -9223,7 +9222,7 @@
&& insn[0] =3D=3D 0x0F && (insn[1] =3D=3D 0x15 || insn[1] =3D=3D =
0x14)) {
IRTemp sV, dV;
IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- Bool hi =3D insn[1] =3D=3D 0x15;
+ Bool hi =3D toBool(insn[1] =3D=3D 0x15);
sV =3D newTemp(Ity_V128);
dV =3D newTemp(Ity_V128);
s3 =3D s2 =3D s1 =3D s0 =3D d3 =3D d2 =3D d1 =3D d0 =3D IRTemp_INV=
ALID;
@@ -9489,7 +9488,7 @@
IRTemp rmode =3D newTemp(Ity_I32);
IRTemp f64lo =3D newTemp(Ity_F64);
IRTemp f64hi =3D newTemp(Ity_F64);
- Bool r2zero =3D insn[1] =3D=3D 0x2C;
+ Bool r2zero =3D toBool(insn[1] =3D=3D 0x2C);
=20
do_MMX_preamble();
modrm =3D getUChar(delta+2);
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-11 02:55:54 UTC (rev 1182)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-11 10:03:08 UTC (rev 1183)
@@ -1593,9 +1593,9 @@
return;
case Ain_Sse64Fx2:
vassert(i->Ain.Sse64Fx2.op !=3D Asse_MOV);
- unary =3D i->Ain.Sse64Fx2.op =3D=3D Asse_RCPF
- || i->Ain.Sse64Fx2.op =3D=3D Asse_RSQRTF
- || i->Ain.Sse64Fx2.op =3D=3D Asse_SQRTF;
+ unary =3D toBool( i->Ain.Sse64Fx2.op =3D=3D Asse_RCPF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_RSQRTF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_SQRTF );
addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
addHRegUse(u, unary ? HRmWrite : HRmModify,=20
i->Ain.Sse64Fx2.dst);
@@ -3238,7 +3238,7 @@
p =3D doAMode_R(p, vreg2ireg(i->Ain.Sse64Fx2.dst),
vreg2ireg(i->Ain.Sse64Fx2.src) );
if (xtra & 0x100)
- *p++ =3D (UChar)(xtra & 0xFF);
+ *p++ =3D toUChar(xtra & 0xFF);
goto done;
=20
case Ain_Sse32FLo:
|
|
From: Tom H. <th...@cy...> - 2005-05-11 08:35:39
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-05-11 03:15:01 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 173 tests, 12 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/vgtest_ume (stderr) corecheck/tests/fdleak_cmsg (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-05-11 08:35:39
|
Nightly build on alvis ( Red Hat 7.3 ) started at 2005-05-11 03:05:02 BST Checking out source tree ... done Configuring ... done Building ... done Running regression tests ... done Last 20 lines of log.verbose follow == 205 tests, 17 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/distinguished-writes (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/pth_once (stderr) memcheck/tests/scalar (stderr) memcheck/tests/threadederrno (stderr) memcheck/tests/vgtest_ume (stderr) addrcheck/tests/leak-0 (stderr) addrcheck/tests/leak-cycle (stderr) addrcheck/tests/leak-regroot (stderr) addrcheck/tests/leak-tree (stderr) make: *** [regtest] Error 1 |
|
From: Tom H. <th...@cy...> - 2005-05-11 07:47:59
|
Nightly build on dellow ( x86_64, Fedora Core 3 ) started at 2005-05-11 03:10:05 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 150 tests, 23 stderr failures, 4 stdout failures ================= memcheck/tests/badloop (stderr) memcheck/tests/brk (stderr) memcheck/tests/error_counts (stdout) memcheck/tests/fwrite (stderr) memcheck/tests/inits (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/manuel1 (stderr) memcheck/tests/sigprocmask (stderr) memcheck/tests/supp2 (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/weirdioctl (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/fdleak_creat (stderr) corecheck/tests/fdleak_dup (stderr) corecheck/tests/fdleak_dup2 (stderr) corecheck/tests/fdleak_fcntl (stderr) corecheck/tests/fdleak_ipv4 (stderr) corecheck/tests/fdleak_open (stderr) corecheck/tests/fdleak_pipe (stderr) corecheck/tests/fdleak_socketpair (stderr) massif/tests/toobig-allocs (stderr) none/tests/faultstatus (stderr) none/tests/selfrun (stdout) none/tests/selfrun (stderr) none/tests/yield (stdout) |