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From: Mark W. <ma...@so...> - 2021-11-08 16:16:32
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f1afb63ffd15c3ee3791c43cf603272f08cbfb73 commit f1afb63ffd15c3ee3791c43cf603272f08cbfb73 Author: Mark Wielaard <ma...@kl...> Date: Mon Nov 8 17:12:12 2021 +0100 vbit-test F16 Iops are tested on the wrong architectures Because of what looks like some copy/paste issues the new F16 Iops seem to be tested on the wrong architectures. They are only implemented on arm64. So this patch only enables them for arm64. https://bugs.kde.org/show_bug.cgi?id=444831 Diff: --- memcheck/tests/vbit-test/irops.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 0cbd16e525..a094709059 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -200,9 +200,9 @@ static irop_t irops[] = { { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts { DEFOP(Iop_DivF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts { DEFOP(Iop_AddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AddF16, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_AddF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_SubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_SubF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_SubF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1,.ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_MulF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_DivF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, @@ -212,15 +212,15 @@ static irop_t irops[] = { { DEFOP(Iop_NegF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_AbsF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_NegF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_NegF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_NegF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AbsF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_AbsF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_SqrtF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_SqrtF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_CmpF16, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CmpF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, |
|
From: Carl L. <ca...@so...> - 2021-11-02 16:15:10
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ae8c6de01417023e78763de145b1c0e6ddd87277 commit ae8c6de01417023e78763de145b1c0e6ddd87277 Author: Carl Love <ce...@us...> Date: Wed Oct 20 20:40:13 2021 +0000 Fix for the prefixed stq instruction in PC relative mode. The pstq instruction for R=1, was not using the correct effective address. The EA_hi and EA_lo should have been based on the value of EA as calculated by the function calculate_prefix_EA. Unfortuanely, the EA_hi and EA_lo addresses were still using the previous code (not PC relative) to calculate the address from the contants of RA plus the offset. Diff: --- VEX/priv/guest_ppc_toIR.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 8afd774901..543fa95743 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -9838,23 +9838,24 @@ static Bool dis_int_store_ds_prefix ( UInt prefix, if (host_endness == VexEndnessBE) { /* upper 64-bits */ - assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val ) ); + assign( EA_hi, mkexpr(EA)); /* lower 64-bits */ - assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+8 ) ); + assign( EA_lo, binop(Iop_Add64, mkexpr(EA), mkU64(8))); + } else { /* upper 64-bits */ - assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+8 ) ); + assign( EA_hi, binop(Iop_Add64, mkexpr(EA), mkU64(8))); /* lower 64-bits */ - assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val ) ); + assign( EA_lo, mkexpr(EA)); } } else { /* upper half of upper 64-bits */ - assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+4 ) ); + assign( EA_hi, binop(Iop_Add32, mkexpr(EA), mkU32(4))); /* lower half of upper 64-bits */ - assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+12 ) ); + assign( EA_lo, binop(Iop_Add32, mkexpr(EA), mkU32(12))); } /* Note, the store order for stq instruction is the same for BE |
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From: Carl L. <ca...@so...> - 2021-11-02 16:10:12
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3950c5d661ee09526cddcf24daf5fc22bc83f70c commit 3950c5d661ee09526cddcf24daf5fc22bc83f70c Author: Carl Love <ce...@us...> Date: Mon Nov 1 11:18:32 2021 -0500 Valgrind Add powerpc R=1 tests Contributed by Will Schmidt <wil...@vn...> This includes updates and adjustments as suggested by Carl. Add tests that exercise PCRelative instructions. These instructions are encoded with R==1, which indicate that the memory accessed by the instruction is at a location relative to the currently executing instruction. These tests are built using -Wl,-text and -Wl,-bss options to ensure the location of the target array is at a location with a specific offset from the currently executing instruction. The write instructions are aimed at a large buffer in the bss section; which is checked for updates at the completion of each test. In order to ensure consistent output across assorted systems, the tests have been padded with ori, nop instructions and align directives. Detailed changes: * Makefile.am: Add test_isa_3_1_R1_RT and test_isa_3_1_R1_XT tests. * isa_3_1_helpers.h: Add identify_instruction_by_func_name() helper function to indicate if the test is for R==1. Add helpers to initialize and print changes to the pcrelative_write_target array. Add #define to help pad code with a series of eyecatcher ORI instructions. * test_isa_3_1_R1_RT.c: New test. * test_isa_3_1_R1_XT.c: New test. * test_isa_3_1_R1_XT.stdout.exp: New expected output. * test_isa_3_1_R1_XT.stdout.exp: New expected output. * test_isa_3_1_R1_RT.stderr.exp: New expected output. * test_isa_3_1_R1_RT.stderr.exp: New expected output. * test_isa_3_1_R1_RT.vgtest: New test handler. * test_isa_3_1_R1_XT.vgtest: New test handler. * test_isa_3_1_common.c: Add indicators (updates_byte,updates_halfword, updates_word) indicators to control the output from the R==1 tests. Add helper check for "_R1" to indicate if instruction is coded with R==1. Add init and print helpers for the pcrelative_write_target array. Diff: --- NEWS | 1 + none/tests/ppc64/Makefile.am | 16 +- none/tests/ppc64/isa_3_1_helpers.h | 18 + none/tests/ppc64/test_isa_3_1_R1_RT.c | 624 +++++++++++++++++++++++++ none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp | 2 + none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp | 138 ++++++ none/tests/ppc64/test_isa_3_1_R1_RT.vgtest | 2 + none/tests/ppc64/test_isa_3_1_R1_XT.c | 534 +++++++++++++++++++++ none/tests/ppc64/test_isa_3_1_R1_XT.stderr.exp | 2 + none/tests/ppc64/test_isa_3_1_R1_XT.stdout.exp | 127 +++++ none/tests/ppc64/test_isa_3_1_R1_XT.vgtest | 2 + none/tests/ppc64/test_isa_3_1_common.c | 166 ++++++- 12 files changed, 1616 insertions(+), 16 deletions(-) diff --git a/NEWS b/NEWS index 9a49fd0602..888f07bb6b 100644 --- a/NEWS +++ b/NEWS @@ -45,6 +45,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 444495 dhat/tests/copy fails on s390x 444571 PPC, fix the lxsibzx and lxsihzx so they only load their respective sized data. +444836 PPC, pstq instruction for R=1 is not storing to the correct address. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index b709f3ef49..f8eab9fc00 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -61,6 +61,8 @@ EXTRA_DIST = \ test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp \ test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp \ test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp \ + test_isa_3_1_R1_RT.vgtest test_isa_3_1_R1_RT.stderr.exp test_isa_3_1_R1_RT.stdout.exp \ + test_isa_3_1_R1_XT.vgtest test_isa_3_1_R1_XT.stderr.exp test_isa_3_1_R1_XT.stdout.exp \ subnormal_test.stderr.exp subnormal_test.stdout.exp \ subnormal_test.vgtest test_darn_inst.stderr.exp \ test_darn_inst.stdout.exp test_darn_inst.vgtest \ @@ -68,8 +70,8 @@ EXTRA_DIST = \ test_copy_paste.stderr.exp test_copy_paste.stdout.exp \ test_copy_paste.vgtest \ test_mcrxrx.vgtest test_mcrxrx.stderr.exp test_mcrxrx.stdout.exp \ - test_lxvx_stxvx.vgtest test_lxvx_stxvx.stderr.exp test_lxvx_stxvx.stdout.exp-p8 test_lxvx_stxvx.stdout.exp-p9 - + test_lxvx_stxvx.vgtest test_lxvx_stxvx.stderr.exp \ + test_lxvx_stxvx.stdout.exp-p8 test_lxvx_stxvx.stdout.exp-p9 check_PROGRAMS = \ allexec \ @@ -80,11 +82,12 @@ check_PROGRAMS = \ test_isa_3_0 test_mod_instructions \ test_isa_3_1_RT test_isa_3_1_XT test_isa_3_1_VRT \ test_isa_3_1_Misc test_isa_3_1_AT \ + test_isa_3_1_R1_RT test_isa_3_1_R1_XT \ subnormal_test test_darn_inst test_copy_paste \ test_tm test_touch_tm data-cache-instructions \ std_reg_imm \ twi_tdi tw_td power6_bcmp scv_test \ - test_mcrxrx test_lxvx_stxvx + test_mcrxrx test_lxvx_stxvx # lmw, stmw, lswi, lswx, stswi, stswx compile (and run) only on big endian. if VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX @@ -106,6 +109,8 @@ test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c +test_isa_3_1_R1_XT_SOURCES = test_isa_3_1_R1_XT.c test_isa_3_1_common.c +test_isa_3_1_R1_RT_SOURCES = test_isa_3_1_R1_RT.c test_isa_3_1_common.c test_darn_inst_SOURCES = test_darn_inst.c if HAS_ALTIVEC @@ -224,6 +229,11 @@ test_isa_3_1_VRT_CFLAGS = $(test_isa_3_1_CFLAGS) test_isa_3_1_Misc_CFLAGS = $(test_isa_3_1_CFLAGS) test_isa_3_1_AT_CFLAGS = $(test_isa_3_1_CFLAGS) +# The _R1_foo tests exercise pc-relative instructions, so require the bss and text sections +# exist at known offsets with respect to each other. +test_isa_3_1_R1_RT_CFLAGS = $(test_isa_3_1_CFLAGS) -Wl,-Tbss,0x20000 -Wl,-Ttext,0x40000 +test_isa_3_1_R1_XT_CFLAGS = $(test_isa_3_1_CFLAGS) -Wl,-Tbss,0x20000 -Wl,-Ttext,0x40000 + subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) diff --git a/none/tests/ppc64/isa_3_1_helpers.h b/none/tests/ppc64/isa_3_1_helpers.h index 338f55526d..716a6277b9 100644 --- a/none/tests/ppc64/isa_3_1_helpers.h +++ b/none/tests/ppc64/isa_3_1_helpers.h @@ -43,6 +43,9 @@ extern void debug_show_current_iteration(); extern void debug_dump_buffer(); extern void identify_form_components(const char *, const char *); +extern void identify_instruction_by_func_name(const char *); +extern void init_pcrelative_write_target(); +extern void print_pcrelative_write_target(); extern void dump_vsxargs(); extern void generic_prologue(); extern void build_args_table(); @@ -58,6 +61,21 @@ extern void initialize_source_registers(); extern void set_up_iterators(); extern void initialize_buffer(int); +/* This (TEXT_BSS_DELTA) is the relative distance between those + sections as set by the linker options for the R==1 tests. */ +#define TEXT_BSS_DELTA 0x20000 +#define RELOC_BUFFER_SIZE 0x1000 +extern unsigned long long pcrelative_buff_addr(int); +#define PAD_ORI \ + __asm__ __volatile__ ("ori 21,21,21"); \ + __asm__ __volatile__ ("ori 22,22,22");\ + __asm__ __volatile__ ("ori 23,23,23");\ + __asm__ __volatile__ ("ori 24,24,24");\ + __asm__ __volatile__ ("ori 25,25,25");\ + __asm__ __volatile__ ("ori 26,26,26");\ + __asm__ __volatile__ ("ori 27,27,27");\ + __asm__ __volatile__ ("ori 28,28,28"); + extern int verbose; #define debug_printf(X) if (verbose>0) printf(X); #define debug_show_labels (verbose>0) diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.c b/none/tests/ppc64/test_isa_3_1_R1_RT.c new file mode 100644 index 0000000000..d73b84b107 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_RT.c @@ -0,0 +1,624 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt <wil...@vn...> + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <stdio.h> +#ifdef HAS_ISA_3_1 +#include <stdint.h> +#include <assert.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <altivec.h> +#include <malloc.h> + +#include <string.h> +#include <signal.h> +#include <setjmp.h> + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" + +static void test_plxvp_off0_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plxvp 20, +0(0),1" ); + PAD_ORI +} +static void test_plxvp_off8_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plxvp 20, +8(0),1" ); + PAD_ORI +} +static void test_plxvp_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plxvp 20, +16(0),1" ); + PAD_ORI +} +static void test_plxvp_off24_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plxvp 20, +24(0),1" ); + PAD_ORI +} +static void test_plxvp_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plxvp 20, +32(0),1" ); + PAD_ORI +} +static void test_plbz_off0_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plbz %0, +0(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plbz_off8_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plbz %0, +8(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plbz_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plbz %0, +16(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plbz_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plbz %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plbz_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plbz %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_plhz_off0_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plhz %0, +0(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plhz_off8_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plhz %0, +8(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plhz_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plhz %0, +16(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plhz_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plhz %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plhz_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plhz %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_plha_off0_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plha %0, +0(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plha_off8_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plha %0, +8(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plha_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plha %0, +16(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plha_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plha %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plha_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plha %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_plwz_off0_R1 (void) { + __asm__ __volatile__ ("plwz %0, +0(0), 1" : "=r" (rt) ); +} +static void test_plwz_off8_R1 (void) { + __asm__ __volatile__ ("plwz %0, +8(0), 1" : "=r" (rt) ); +} +static void test_plwz_off16_R1 (void) { + __asm__ __volatile__ ("plwz %0, +16(0), 1" : "=r" (rt) ); +} +static void test_plwz_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plwz %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plwz_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plwz %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_plwa_off0_R1 (void) { + __asm__ __volatile__ ("plwa %0, +0(0), 1" : "=r" (rt) ); +} +static void test_plwa_off8_R1 (void) { + __asm__ __volatile__ ("plwa %0, +8(0), 1" : "=r" (rt) ); +} +static void test_plwa_off16_R1 (void) { + __asm__ __volatile__ ("plwa %0, +16(0), 1" : "=r" (rt) ); +} +static void test_plwa_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plwa %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_plwa_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plwa %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_pld_off0_R1 (void) { + __asm__ __volatile__ ("pld %0, +0(0), 1" : "=r" (rt) ); +} +static void test_pld_off8_R1 (void) { + __asm__ __volatile__ ("pld %0, +8(0), 1" : "=r" (rt) ); +} +static void test_pld_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("pld %0, +16(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_pld_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("pld %0, +32(0), 1" : "=r" (rt) ); + PAD_ORI +} +static void test_pld_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("pld %0, +64(0), 1" : "=r" (rt) ); + PAD_ORI + PAD_ORI +} +static void test_pstb_off0_R1 (void) { + __asm__ __volatile__ ("pstb %0, -0x1f400+0(0), 1" :: "r" (rs) ); +} +static void test_pstb_off8_R1 (void) { + __asm__ __volatile__ ("pstb %0, -0x1f400+8(0), 1" :: "r" (rs) ); +} +static void test_pstb_off16_R1 (void) { + __asm__ __volatile__ ("pstb %0, -0x1f400+16(0), 1" :: "r" (rs) ); +} +static void test_pstb_off32_R1 (void) { + __asm__ __volatile__ ("pstb %0, -0x1f400+32(0), 1" :: "r" (rs) ); +} +static void test_psth_off0_R1 (void) { + __asm__ __volatile__ ("psth %0, -0x1f400+0(0), 1" :: "r" (rs) ); +} +static void test_psth_off8_R1 (void) { + __asm__ __volatile__ ("psth %0, -0x1f400+8(0), 1" :: "r" (rs) ); +} +static void test_psth_off16_R1 (void) { + __asm__ __volatile__ ("psth %0, -0x1f400+16(0), 1" :: "r" (rs) ); +} +static void test_psth_off32_R1 (void) { + __asm__ __volatile__ ("psth %0, -0x1f400+32(0), 1" :: "r" (rs) ); +} +static void test_pstw_off0_R1 (void) { + __asm__ __volatile__ ("pstw %0, -0x1f400+0(0), 1" :: "r" (rs) ); +} +static void test_pstw_off8_R1 (void) { + __asm__ __volatile__ ("pstw %0, -0x1f400+8(0), 1" :: "r" (rs) ); +} +static void test_pstw_off16_R1 (void) { + __asm__ __volatile__ ("pstw %0, -0x1f400+16(0), 1" :: "r" (rs) ); +} +static void test_pstw_off32_R1 (void) { + __asm__ __volatile__ ("pstw %0, -0x1f400+32(0), 1" :: "r" (rs) ); +} +static void test_pstd_off0_R1 (void) { + __asm__ __volatile__ ("pstd %0, -0x1f400+0(0), 1" :: "r" (rs) ); +} +static void test_pstd_off8_R1 (void) { + __asm__ __volatile__ ("pstd %0, -0x1f400+8(0), 1" :: "r" (rs) ); +} +static void test_pstd_off16_R1 (void) { + __asm__ __volatile__ ("pstd %0, -0x1f400+16(0), 1" :: "r" (rs) ); +} +static void test_pstd_off32_R1 (void) { + __asm__ __volatile__ ("pstd %0, -0x1f400+32(0), 1" :: "r" (rs) ); +} + /* For the paddi tests; although we can get close to a read/write target + due to forcing where the .text and .bss sections are placed, there is + still enough codegen variability that having a raw value in the exp + file will not be determinative for these instructions. + Thus, compromise and just ensure that the generated value is an + address that lands within the reloc buffer, and use quasi magic + eyecatcher values in the return to indicate success. */ +static void test_paddi_0_R1 (void) { + __asm__ __volatile__ ("paddi %0, 0, 0+0, 1" : "=r" (rt) ); + rt = rt - TEXT_BSS_DELTA; + if (rt > pcrelative_buff_addr(0) && + rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE)) + rt = 0xffff0000; +} +static void test_paddi_12_R1 (void) { + __asm__ __volatile__ ("paddi %0, 0, 0+12, 1" : "=r" (rt) ); + rt = rt - TEXT_BSS_DELTA; + if (rt > pcrelative_buff_addr(0) && + rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE)) + rt = 0xffff0012; +} +static void test_paddi_48_R1 (void) { + __asm__ __volatile__ ("paddi %0, 0, 0+48, 1" : "=r" (rt) ); + rt = rt - TEXT_BSS_DELTA; + if (rt > pcrelative_buff_addr(0) && + rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE)) + rt = 0xffff0048; +} +static void test_paddi_98_R1 (void) { + __asm__ __volatile__ ("paddi %0, 0, 0+98, 1" : "=r" (rt) ); + rt = rt - TEXT_BSS_DELTA; + if (rt > pcrelative_buff_addr(0) && + rt < pcrelative_buff_addr(RELOC_BUFFER_SIZE)) + rt = 0xffff0098; +} +static void test_plq_off0_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +0(0), 1" ); + PAD_ORI +} +static void test_plq_off8_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +8(0), 1" ); + PAD_ORI +} +static void test_plq_off16_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +16(0), 1" ); + PAD_ORI +} +static void test_plq_off32_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +32(0), 1" ); + PAD_ORI +} +static void test_plq_off48_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +48(0), 1" ); + PAD_ORI +} +static void test_plq_off64_R1 (void) { + PAD_ORI + __asm__ __volatile__ ("plq 26, +64(0), 1" ); + PAD_ORI + PAD_ORI +} +static void test_pstq_off0_R1 (void) { + __asm__ __volatile__ ("pstq 24, -0x1f400+0(0), 1" ); +} +static void test_pstq_off8_R1 (void) { + __asm__ __volatile__ ("pstq 24, -0x1f400+8(0), 1" ); +} +static void test_pstq_off16_R1 (void) { + __asm__ __volatile__ ("pstq 24, -0x1f400+16(0), 1" ); +} +static void test_pstq_off32_R1 (void) { + __asm__ __volatile__ ("pstq 24, -0x1f400+32(0), 1" ); +} +static void test_pstq_off64_R1 (void) { + __asm__ __volatile__ ("pstq 24, -0x1f400+64(0), 1" ); +} + +static test_list_t testgroup_generic[] = { + { &test_paddi_0_R1, "paddi 0_R1", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_12_R1, "paddi 12_R1", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_48_R1, "paddi 48_R1", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_98_R1, "paddi 98_R1", "RT,RA,SI,R"}, /* bcwp */ + { &test_plbz_off0_R1, "plbz off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off8_R1, "plbz off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off16_R1, "plbz off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off32_R1, "plbz off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off64_R1, "plbz off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off0_R1, "pld off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off8_R1, "pld off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off16_R1, "pld off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off32_R1, "pld off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off64_R1, "pld off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off0_R1, "plha off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off8_R1, "plha off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off16_R1, "plha off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off32_R1, "plha off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off64_R1, "plha off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off0_R1, "plhz off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off8_R1, "plhz off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off16_R1, "plhz off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off32_R1, "plhz off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off64_R1, "plhz off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plq_off0_R1, "plq off0_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off8_R1, "plq off8_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off16_R1, "plq off16_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off32_R1, "plq off32_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off48_R1, "plq off48_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off64_R1, "plq off64_R1", "RTp,D(RA),R"}, /* bcwp */ + { &test_plwa_off0_R1, "plwa off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off8_R1, "plwa off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off16_R1, "plwa off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off32_R1, "plwa off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off64_R1, "plwa off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off0_R1, "plwz off0_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off8_R1, "plwz off8_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off16_R1, "plwz off16_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off32_R1, "plwz off32_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off64_R1, "plwz off64_R1", "RT,D(RA),R"}, /* bcwp */ + { &test_plxvp_off0_R1, "plxvp off0_R1", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off8_R1, "plxvp off8_R1", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off16_R1, "plxvp off16_R1", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off24_R1, "plxvp off24_R1", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off32_R1, "plxvp off32_R1", "XTp,D(RA),R"}, /* bcwp */ + { &test_pstb_off0_R1, "pstb off0_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off8_R1, "pstb off8_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off16_R1, "pstb off16_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off32_R1, "pstb off32_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off0_R1, "pstd off0_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off8_R1, "pstd off8_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off16_R1, "pstd off16_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off32_R1, "pstd off32_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off0_R1, "psth off0_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off8_R1, "psth off8_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off16_R1, "psth off16_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off32_R1, "psth off32_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstq_off0_R1, "pstq off0_R1", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off8_R1, "pstq off8_R1", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off16_R1, "pstq off16_R1", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off32_R1, "pstq off32_R1", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off64_R1, "pstq off64_R1", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstw_off0_R1, "pstw off0_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off8_R1, "pstw off8_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off16_R1, "pstw off16_R1", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off32_R1, "pstw off32_R1", "RS,D(RA),R"}, /* bcwp */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + init_pcrelative_write_target (); + debug_dump_buffer (); + + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + print_pcrelative_write_target (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + identify_instruction_by_func_name (current_test.name); + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a <foo> : limit number of a-iterations to <foo>\n" + "\t-b <foo> : limit number of b-iterations to <foo>\n" + "\t-c <foo> : limit number of c-iterations to <foo>\n" + "\t-n <foo> : limit to this number of tests.\n" + "\t-r <foo>: run only test # <foo> \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s <foo>: skip <foo> tests \n" + "\t-c <foo>: stop after running <foo> # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #<foo>. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp b/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_RT.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp new file mode 100644 index 0000000000..87594748fd --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp @@ -0,0 +1,138 @@ +paddi 0_R1 => ffff0000 + +paddi 12_R1 => ffff0012 + +paddi 48_R1 => ffff0048 + +paddi 98_R1 => ffff0098 + +plbz off0_R1 => 1a + +plbz off8_R1 => 1f + +plbz off16_R1 => 1f + +plbz off32_R1 => 1b + +plbz off64_R1 => 1b + +pld off0_R1 => e740000004100000 + +pld off8_R1 => 4e800020 + +pld off16_R1 => 6318001862f7001f + +pld off32_R1 => 639c001c637b001b + +pld off64_R1 => 639c001c637b001b + +plha off0_R1 => 1a + +plha off8_R1 => 1f + +plha off16_R1 => 1f + +plha off32_R1 => 1b + +plha off64_R1 => 1b + +plhz off0_R1 => 1a + +plhz off8_R1 => 1f + +plhz off16_R1 => 1f + +plhz off32_R1 => 1b + +plhz off64_R1 => 1b + +plq off0_R1 => e34000000410001a 62d6001662b5001f + +plq off8_R1 => 62d6001662b5001f 6318001862f7001f + +plq off16_R1 => 6318001862f7001f 635a001a6339001b + +plq off32_R1 => 639c001c637b001b 4e80003b + +plq off48_R1 => 1a 62d6001662b5001f + +plq off64_R1 => 639c001c637b001b 4e80003b + +plwa off0_R1 => 4100000 + +plwa off8_R1 => 4e800020 + +plwa off16_R1 => 0 + +plwa off32_R1 => 637b001b + +plwa off64_R1 => 637b001b + +plwz off0_R1 => 6100000 + +plwz off8_R1 => 4e800020 + +plwz off16_R1 => 0 + +plwz off32_R1 => 637b001b + +plwz off64_R1 => 637b001b + +plxvp off0_R1 => 6318001862f70017 635a001a63390019 ea80000004100000 62d6001662b50015 + +plxvp off8_R1 => 635a001a63390019 639c001c637b001b 62d6001662b50015 6318001862f70017 + +plxvp off16_R1 => 639c001c637b001b 000000004e800020 6318001862f70017 635a001a63390019 + +plxvp off24_R1 => 000000004e800020 0000000000000000 635a001a63390019 639c001c637b001b + +plxvp off32_R1 => 0000000000000000 62d6001662b50015 639c001c637b001b 000000004e800020 + +pstb off0_R1 102030405060708 => 08 + +pstb off8_R1 102030405060708 => 08 + +pstb off16_R1 102030405060708 => 08 + +pstb off32_R1 102030405060708 => 08 + +pstd off0_R1 102030405060708 => 0102030405060708 + +pstd off8_R1 102030405060708 => 0102030405060708 + +pstd off16_R1 102030405060708 => 0102030405060708 + +pstd off32_R1 102030405060708 => 0102030405060708 + +psth off0_R1 102030405060708 => 0708 + +psth off8_R1 102030405060708 => 0708 + +psth off16_R1 102030405060708 => 0708 + +psth off32_R1 102030405060708 => 0708 + +pstq off0_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 +pstq off0_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 + +pstq off8_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 +pstq off8_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 + +pstq off16_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 +pstq off16_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 + +pstq off32_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 +pstq off32_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 + +pstq off64_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 +pstq off64_R1 102030405060708 a5b4c3d2e1f00918 => 0102030405060708 a5b4c3d2e1f00918 + +pstw off0_R1 102030405060708 => 05060708 + +pstw off8_R1 102030405060708 => 05060708 + +pstw off16_R1 102030405060708 => 05060708 + +pstw off32_R1 102030405060708 => 05060708 + +All done. Tested 66 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_R1_RT.vgtest b/none/tests/ppc64/test_isa_3_1_R1_RT.vgtest new file mode 100644 index 0000000000..61d7f65a12 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_RT.vgtest @@ -0,0 +1,2 @@ +prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1 +prog: test_isa_3_1_R1_RT diff --git a/none/tests/ppc64/test_isa_3_1_R1_XT.c b/none/tests/ppc64/test_isa_3_1_R1_XT.c new file mode 100644 index 0000000000..58885b8d30 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_XT.c @@ -0,0 +1,534 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt <wil...@vn...> + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <stdio.h> +#ifdef HAS_ISA_3_1 +#include <stdint.h> +#include <assert.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <altivec.h> +#include <malloc.h> + +#include <string.h> +#include <signal.h> +#include <setjmp.h> + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" +static void test_pstxvp_off0_R1 (void) { + __asm__ __volatile__ ("pstxvp 20, -0x1f400+0(0),1"); +} +static void test_pstxvp_off16_R1 (void) { + __asm__ __volatile__ ("pstxvp 20, -0x1f400+16(0),1"); +} +static void test_pstxvp_off32_R1 (void) { + __asm__ __volatile__ ("pstxvp 20, -0x1f400+32(0),1"); +} +static void test_pstxvp_off48_R1 (void) { + __asm__ __volatile__ ("pstxvp 20, -0x1f400+48(0),1"); +} +static void test_plfd_64_R1 (void) { + __asm__ __volatile__ ("plfd 28, +64(0), 1"); + PAD_ORI + PAD_ORI +} +static void test_plfd_32_R1 (void) { + __asm__ __volatile__ ("plfd 28, +32(0), 1"); + PAD_ORI +} +static void test_plfd_16_R1 (void) { + __asm__ __volatile__ ("plfd 28, +16(0), 1"); + PAD_ORI +} +static void test_plfd_8_R1 (void) { + __asm__ __volatile__ ("plfd 28, +8(0), 1"); + PAD_ORI +} +static void test_plfd_4_R1 (void) { + __asm__ __volatile__ ("plfd 28, +4(0), 1"); + PAD_ORI +} +static void test_plfd_0_R1 (void) { + __asm__ __volatile__ ("plfd 28, +0(0), 1"); + PAD_ORI +} +static void test_plfs_64_R1 (void) { + __asm__ __volatile__ ("plfs 28, +64(0), 1"); + PAD_ORI + PAD_ORI +} +static void test_plfs_32_R1 (void) { + __asm__ __volatile__ ("plfs 28, +32(0), 1"); + PAD_ORI +} +static void test_plfs_16_R1 (void) { + __asm__ __volatile__ ("plfs 28, +16(0), 1"); + PAD_ORI +} +static void test_plfs_8_R1 (void) { + __asm__ __volatile__ ("plfs 28, +8(0), 1"); + PAD_ORI +} +static void test_plfs_4_R1 (void) { + __asm__ __volatile__ ("plfs 28, +4(0), 1"); + PAD_ORI +} +static void test_plfs_0_R1 (void) { + __asm__ __volatile__ ("plfs 28, +0(0), 1"); + PAD_ORI +} +static void test_pstfd_32_R1 (void) { + __asm__ __volatile__ ("pstfd 26, -0x1f400+32(0), 1"); +} +static void test_pstfd_16_R1 (void) { + __asm__ __volatile__ ("pstfd 26, -0x1f400+16(0), 1"); +} +static void test_pstfd_8_R1 (void) { + __asm__ __volatile__ ("pstfd 26, -0x1f400+8(0), 1"); +} +static void test_pstfd_4_R1 (void) { + __asm__ __volatile__ ("pstfd 26, -0x1f400+4(0), 1"); +} +static void test_pstfd_0_R1 (void) { + __asm__ __volatile__ ("pstfd 26, -0x1f400+0(0), 1"); +} +static void test_pstfs_32_R1 (void) { + __asm__ __volatile__ ("pstfs 26, -0x1f400+32(0), 1"); +} +static void test_pstfs_16_R1 (void) { + __asm__ __volatile__ ("pstfs 26, -0x1f400+16(0), 1"); +} +static void test_pstfs_8_R1 (void) { + __asm__ __volatile__ ("pstfs 26, -0x1f400+8(0), 1"); +} +static void test_pstfs_4_R1 (void) { + __asm__ __volatile__ ("pstfs 26, -0x1f400+4(0), 1"); +} +static void test_pstfs_0_R1 (void) { + __asm__ __volatile__ ("pstfs 26, -0x1f400+0(0), 1"); +} +static void test_plxsd_64_R1 (void) { + __asm__ __volatile__ ("plxsd %0, +64(0), 1" : "=v" (vrt) ); + PAD_ORI + PAD_ORI +} +static void test_plxsd_32_R1 (void) { + __asm__ __volatile__ (".align 2 ; plxsd %0, +32(0), 1" : "=v" (vrt) ); + PAD_ORI +} +static void test_plxsd_16_R1 (void) { + __asm__ __volatile__ ("plxsd %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxsd_8_R1 (void) { + __asm__ __volatile__ ("plxsd %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxsd_4_R1 (void) { + __asm__ __volatile__ ("plxsd %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxsd_0_R1 (void) { + __asm__ __volatile__ ("plxsd %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxssp_64_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +64(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI + PAD_ORI +} +static void test_plxssp_32_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +32(0), 1; pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxssp_16_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxssp_8_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxssp_4_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +static void test_plxssp_0_R1 (void) { + __asm__ __volatile__ ("plxssp %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) ); + PAD_ORI +} +/* Follow the short-range plxv instructions with nop in order to + pad out subsequent instructions. When written there are found + to be fluctuations in the instructions to store the result back + into the target variable. (pla,pstxv...). + */ +static void test_plxv_16_R1 (void) { + __asm__ __volatile__ ("plxv %x0, +16(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) ); + PAD_ORI +} +static void test_plxv_8_R1 (void) { + __asm__ __volatile__ ("plxv %x0, +8(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) ); + PAD_ORI +} +static void test_plxv_4_R1 (void) { + __asm__ __volatile__ ("plxv %x0, +4(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) ); + PAD_ORI +} +static void test_plxv_0_R1 (void) { + __asm__ __volatile__ ("plxv %x0, +0(0), 1; pnop;pnop;pnop; " : "=wa" (vec_xt) ); + PAD_ORI +} +static void test_pstxsd_64_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+64(0), 1" ); +} +static void test_pstxsd_32_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+32(0), 1" ); +} +static void test_pstxsd_16_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+16(0), 1" ); +} +static void test_pstxsd_8_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+8(0), 1" ); +} +static void test_pstxsd_4_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+4(0), 1" ); +} +static void test_pstxsd_0_R1 (void) { + __asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+0(0), 1" ); +} +static void test_pstxssp_64_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+64(0), 1" ); +} +static void test_pstxssp_32_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+32(0), 1"); +} +static void test_pstxssp_16_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+16(0), 1"); +} +static void test_pstxssp_8_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+8(0), 1"); +} +static void test_pstxssp_4_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+4(0), 1"); +} +static void test_pstxssp_0_R1 (void) { + __asm__ __volatile__ ("pstxssp 22, -0x1f400+0(0), 1"); +} +static void test_pstxv_16_R1 (void) { + __asm__ __volatile__ ("pstxv %x0, -0x1f400+16(0), 1" :: "wa" (vec_xs)); +} +static void test_pstxv_8_R1 (void) { + __asm__ __volatile__ ("pstxv %x0, -0x1f400+8(0), 1" :: "wa" (vec_xs)); +} +static void test_pstxv_4_R1 (void) { + __asm__ __volatile__ ("pstxv %x0, -0x1f400+4(0), 1" :: "wa" (vec_xs)); +} +static void test_pstxv_0_R1 (void) { + __asm__ __volatile__ ("pstxv %x0, -0x1f400+0(0), 1" :: "wa" (vec_xs)); +} + +static test_list_t testgroup_generic[] = { + { &test_plfd_0_R1, "plfd 0_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_4_R1, "plfd 4_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_8_R1, "plfd 8_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_16_R1, "plfd 16_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_32_R1, "plfd 32_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_64_R1, "plfd 64_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_0_R1, "plfs 0_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_4_R1, "plfs 4_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_8_R1, "plfs 8_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_16_R1, "plfs 16_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_32_R1, "plfs 32_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_64_R1, "plfs 64_R1", "FRT,D(RA),R"}, /* bcwp */ + { &test_plxsd_0_R1, "plxsd 0_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_4_R1, "plxsd 4_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_8_R1, "plxsd 8_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_16_R1, "plxsd 16_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_32_R1, "plxsd 32_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_64_R1, "plxsd 64_R1", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxssp_0_R1, "plxssp 0_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_4_R1, "plxssp 4_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_8_R1, "plxssp 8_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_16_R1, "plxssp 16_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_32_R1, "plxssp 32_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_64_R1, "plxssp 64_R1", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxv_0_R1, "plxv 0_R1", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_4_R1, "plxv 4_R1", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_8_R1, "plxv 8_R1", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_16_R1, "plxv 16_R1", "XT,D(RA),R"}, /* bcwp */ + { &test_pstfd_0_R1, "pstfd 0_R1", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_4_R1, "pstfd 4_R1", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_8_R1, "pstfd 8_R1", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_16_R1, "pstfd 16_R1", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_32_R1, "pstfd 32_R1", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfs_0_R1, "pstfs 0_R1", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_4_R1, "pstfs 4_R1", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_8_R1, "pstfs 8_R1", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_16_R1, "pstfs 16_R1", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_32_R1, "pstfs 32_R1", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstxsd_0_R1, "pstxsd 0_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_4_R1, "pstxsd 4_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_8_R1, "pstxsd 8_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_16_R1, "pstxsd 16_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_32_R1, "pstxsd 32_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_64_R1, "pstxsd 64_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_0_R1, "pstxssp 0_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_4_R1, "pstxssp 4_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_8_R1, "pstxssp 8_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_16_R1, "pstxssp 16_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_32_R1, "pstxssp 32_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_64_R1, "pstxssp 64_R1", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off0_R1, "pstxvp off0_R1", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off16_R1, "pstxvp off16_R1", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off32_R1, "pstxvp off32_R1", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off48_R1, "pstxvp off48_R1", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxv_0_R1, "pstxv 0_R1", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_4_R1, "pstxv 4_R1", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_8_R1, "pstxv 8_R1", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_16_R1, "pstxv 16_R1", "XS,D(RA),R"}, /* bcwp */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + init_pcrelative_write_target (); + debug_dump_buffer (); + + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + vec_xa[0]=0x1234; + vec_xa[1]=0x4567; + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + print_pcrelative_write_target (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + identify_instruction_by_func_name (current_test.name); + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a <foo> : limit number of a-iterations to <foo>\n" + "\t-b <foo> : limit number of b-iterations to <foo>\n" + "\t-c <foo> : limit number of c-iterations to <foo>\n" + "\t-n <foo> : limit to this number of tests.\n" + "\t-r <foo>: run only test # <foo> \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s <foo>: skip <foo> tests \n" + "\t-c <foo>: stop after running <foo> # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #<foo>. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_R1_XT.stderr.exp b/none/tests/ppc64/test_isa_3_1_R1_XT.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_XT.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_R1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_R1_XT.stdout.exp new file mode 100644 index 0000000000..48d591f4df --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_XT.stdout.exp @@ -0,0 +1,127 @@ +plfd 0_R1 =>_ -4.903986e+55 _ cb80000006100000, 0 + +plfd 4_R1 =>_ 3.095878e+167 _ 62b50015cb800004, 0 + +plfd 8_R1 =>_ 1.297320e+168 _ 62d6001662b50015, 0 + +plfd 16_R1 =>_ 2.264413e+169 _ 6318001862f70017, 0 + +plfd 32_R1 =>_ 6.763045e+171 _ 639c001c637b001b, 0 + +plfd 64_R1 =>_ 6.763045e+171 _ 639c001c637b001b, 0 + +plfs 0_R1 =>_ 2.708339e-35 _ 38c2000000000000, 0 + +plfs 4_R1 =>_ -2.560001e+02 _ c070000080000000, 0 + +plfs 8_R1 =>_ 1.669433e+21 _ 4456a002a0000000, 0 + +plfs 16_R1 =>_ 2.278176e+21 _ 445ee002e0000000, 0 + +plfs 32_R1 =>_ 4.630140e+21 _ 446f600360000000, 0 + +plfs 64_R1 =>_ 4.630140e+21 _ 446f600360000000, 0 + +plxsd 0_R1 => a800000004100000,0000000000000000 -5.07588375e-116 +Zero + +plxsd 4_R1 => 7000000a8000004,0000000000000000 5.77662562e-275 +Zero + +plxsd 8_R1 => 700000060000000,0000000000000000 5.77662407e-275 +Zero + +plxsd 16_R1 => 7000000,0000000000000000 +Den +Zero + +plxsd 32_R1 => 6339001963180018,0000000000000000 9.43505226e+169 +Zero + +plxsd 64_R1 => 6339001963180018,0000000000000000 9.43505226e+169 +Zero + +plxssp 0_R1 => 3882000000000000,0000000000000000 6.19888e-05 +Zero +Zero +Zero + +plxssp 4_R1 => bd80000080000000,0000000000000000 -6.25000e-02 -Zero +Zero +Zero + +plxssp 8_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero + +plxssp 16_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero + +plxssp 32_R1 => 445ac002c0000000,0000000000000000 8.75000e+02 -2.00000e+00 +Zero +Zero + +plxssp 64_R1 => 446b400340000000,0000000000000000 9.41000e+02 2.00000e+00 +Zero +Zero + +plxv 0_R1 => c800000004100000 7000000 + +plxv 4_R1 => 7000000c8000004 700000000000000 + +plxv 8_R1 => 7000000 7000000 + +plxv 16_R1 => 7000000 7000000 + +pstfd 0_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df +pstfd 0_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef + +pstfd 4_R1 43dfe000003fe000 43eff000000ff000 => e000003f e00043df +pstfd 4_R1 43eff000000ff000 43efefffffcff000 => f000000f f00043ef + +pstfd 8_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df +pstfd 8_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef + +pstfd 16_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df +pstfd 16_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef + +pstfd 32_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df +pstfd 32_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef + +pstfs 0_R1 000000005eff0000 000000005f7f8000 => 00005eff +pstfs 0_R1 000000005f7f8000 000000005f7f8000 => 80005f7f + +pstfs 4_R1 000000005eff0000 000000005f7f8000 => 00005eff +pstfs 4_R1 000000005f7f8000 000000005f7f8000 => 80005f7f + +pstfs 8_R1 000000005eff0000 000000005f7f8000 => 00005eff +pstfs 8_R1 000000005f7f8000 000000005f7f8000 => 80005f7f + +pstfs 16_R1 000000005eff0000 000000005f7f8000 => 00005eff +pstfs 16_R1 000000005f7f8000 000000005f7f8000 => 80005f7f + +pstfs 32_R1 000000005eff0000 000000005f7f8000 => 00005eff +pstfs 32_R1 000000005f7f8000 000000005f7f8000 => 80005f7f + +pstxsd 0_R1 => 0000000000000000 + +pstxsd 4_R1 => 00000000 00000000 + +pstxsd 8_R1 => 0000000000000000 + +pstxsd 16_R1 => 0000000000000000 + +pstxsd 32_R1 => 0000000000000000 + +pstxsd 64_R1 => 0000000000000000 + +pstxssp 0_R1 => 00000000 + +pstxssp 4_R1 => 00000000 + +pstxssp 8_R1 => 00000000 + +pstxssp 16_R1 => 00000000 + +pstxssp 32_R1 => 00000000 + +pstxssp 64_R1 => 00000000 + +pstxvp off0_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 077e0180055e0180 000e8080000e0080 + +pstxvp off16_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 077e0180055e0180 000e8080000e0080 + +pstxvp off32_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 077e0180055e0180 000e8080000e0080 + +pstxvp off48_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 077e0180055e0180 000e8080000e0080 + +pstxv 0_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 + +pstxv 4_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 + +pstxv 8_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 + +pstxv 16_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7f fffeff7f00007f80 0000ff80 + +All done. Tested 58 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_R1_XT.vgtest b/none/tests/ppc64/test_isa_3_1_R1_XT.vgtest new file mode 100644 index 0000000000..7331aafad5 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_R1_XT.vgtest @@ -0,0 +1,2 @@ +prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1 +prog: test_isa_3_1_R1_XT diff --git a/none/tests/ppc64/test_isa_3_1_common.c b/none/tests/ppc64/test_isa_3_1_common.c index 7c3dc6f009..b3320277bf 100644 --- a/none/tests/ppc64/test_isa_3_1_common.c +++ b/none/tests/ppc64/test_isa_3_1_common.c @@ -134,11 +134,13 @@ bool uses_acc_vsrs; bool uses_pmsk; bool uses_buffer; // Buffer related. bool uses_load_buffer, uses_store_buffer, uses_any_buffer; +bool updates_byte, updates_halfword, updates_word; // output helpers. bool uses_quad; unsigned long output_mask; // Output field special handling. bool instruction_is_sp, instruction_is_sp_estimate; bool instruction_is_dp, instruction_is_dp_estimate; bool instruction_is_b16; +bool instruction_is_relative; unsigned long long min (unsigned long long a, unsigned long long b) { if ( a < b ) @@ -236,6 +238,18 @@ void identify_form_components (const char *instruction_name, (strncmp (instruction_name, "pmst", 4) == 0) || (strncmp (instruction_name, "pst", 3) == 0) || (strncmp (instruction_name, "st", 2) == 0)); + updates_byte = ( + (strncmp (instruction_name, "pstb", 4) == 0) ); + updates_halfword = ( + (strncmp (instruction_name, "psth", 4) == 0) || + (strncmp (instruction_name, "pstfs", 4) == 0) || + (strncmp (instruction_name, "pstxsd", 4) == 0) || + (strncmp (instruction_name, "pstxssp", 4) == 0) || + (strncmp (instruction_name, "pstxv", 4) == 0) || + (strncmp (instruction_name, "psfs", 4) == 0) ); + updates_word = ( + (strncmp (instruction_name, "pstw", 4) == 0) ); + uses_any_buffer = (strstr (cur_form, "(RA)") != NULL); uses_buffer = uses_any_buffer||uses_load_buffer||uses_store_buffer; @@ -268,6 +282,15 @@ void identify_form_components (const char *instruction_name, instruction_is_b16 = ( current_test.mask & B16_MASK ); } +/* Parse the provided function name to set assorted values. + In particular, set an indicator when the instruction test has + indicated it will run with R==1 that indicates it is a PC-relative + instruction. Those tests should all have "_R1" as part of + the function name. */ +void identify_instruction_by_func_name(const char * function_name) { + instruction_is_relative = ( (strstr (function_name, "R1") != NULL)); +} + void display_form_components (char * cur_form) { printf (" %s\n", cur_form); printf ("Instruction form elements: "); @@ -288,7 +311,7 @@ void display_form_c... [truncated message content] |
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From: Mark W. <ma...@so...> - 2021-11-02 13:33:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=64ab89162906d5b9e2de6c3afe476fec861ef7ec commit 64ab89162906d5b9e2de6c3afe476fec861ef7ec Author: Mark Wielaard <ma...@kl...> Date: Tue Nov 2 14:27:45 2021 +0100 gdbserver_tests: Filter out glibc hwcaps libc.so On some systems the gdbserver_tests would fail because the filter for the optimized hwcaps subdir didn't match because the file is called slightly differently, with the version number before .so instead of after. For example: /lib64/glibc-hwcaps/power9/libc-2.28.so Add one extra filter for this pattern. Diff: --- gdbserver_tests/filter_gdb.in | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in index d0c94f3f1a..b753e01688 100755 --- a/gdbserver_tests/filter_gdb.in +++ b/gdbserver_tests/filter_gdb.in @@ -134,6 +134,7 @@ s/in \(.__\)\{0,1\}select () from \/.*$/in syscall .../ /^ from \/lib\/libc.so.*$/d /^ from \/lib64\/libc.so.*$/d /^ from \/lib64\/.*\/libc.so.*$/d +/^ from \/lib64\/.*\/libc-.*.so/d # and yet another (gdb 7.0 way) to get a system call s/in select ()$/in syscall .../ |
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From: Carl L. <ca...@so...> - 2021-11-01 17:52:19
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6e08ee95f7f1b1c3fd434fa380cc5b2cc3e3f7c7 commit 6e08ee95f7f1b1c3fd434fa380cc5b2cc3e3f7c7 Author: Carl Love <ce...@us...> Date: Fri Oct 29 16:30:33 2021 -0500 Bug 444571 - PPC, fix the lxsibzx and lxsihzx so they only load their respective sized data. The lxsibzx was doing a 64-bit load. The result was initializing additional bytes in the register that should not have been initialized. The memcheck/tests/linux/dlclose_leak test detected the issue. The code generation uses lxsibzx and stxsibx with -mcpu=power9. Previously the lbz and stb instructions were generated. The same issue was noted and fixed with the lxsihzx instruction. The memcheck/tests/linux/badrw test now passes as well. https://bugs.kde.org/show_bug.cgi?id=444571 Diff: --- NEWS | 3 ++- VEX/priv/guest_ppc_toIR.c | 17 +++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/NEWS b/NEWS index 908361039e..9a49fd0602 100644 --- a/NEWS +++ b/NEWS @@ -43,13 +43,14 @@ are not entered into bugzilla tend to get forgotten about or ignored. 444242 s390x: Valgrind crashes on EXRL with negative offset 444495 dhat/tests/copy fails on s390x +444571 PPC, fix the lxsibzx and lxsihzx so they only load their respective + sized data. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX where XXXXXX is the bug number as listed below. - Release 3.18.0 (15 Oct 2021) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index d90d566ed1..8afd774901 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -25359,19 +25359,17 @@ dis_vx_load ( UInt prefix, UInt theInstr ) else irx_addr = mkexpr( EA ); - - byte = load( Ity_I64, irx_addr ); + /* byte load */ + byte = load( Ity_I8, irx_addr ); putVSReg( XT, binop( Iop_64HLtoV128, - binop( Iop_And64, - byte, - mkU64( 0xFF ) ), + unop( Iop_8Uto64, byte ), mkU64( 0 ) ) ); break; } case 0x32D: // lxsihzx { - IRExpr *byte; + IRExpr *hword; IRExpr* irx_addr; DIP("lxsihzx %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); @@ -25382,11 +25380,10 @@ dis_vx_load ( UInt prefix, UInt theInstr ) else irx_addr = mkexpr( EA ); - byte = load( Ity_I64, irx_addr ); + hword = load( Ity_I16, irx_addr ); putVSReg( XT, binop( Iop_64HLtoV128, - binop( Iop_And64, - byte, - mkU64( 0xFFFF ) ), + unop( Iop_16Uto64, + hword ), mkU64( 0 ) ) ); break; } |
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From: Andreas A. <ar...@so...> - 2021-10-28 13:11:44
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b77dbefe72e4a5c7bcf1576a02c909010bd56991 commit b77dbefe72e4a5c7bcf1576a02c909010bd56991 Author: Andreas Arnez <ar...@li...> Date: Fri Oct 22 19:55:12 2021 +0200 Bug 444242 - s390x: Sign-extend "relative long" offset in EXRL In s390_irgen_EXRL, the offset is zero-extended instead of sign-extended, typically causing Valgrind to crash when a negative offset occurs. Fix this with a new helper function that calculates a "relative long" address from a 32-bit offset. Replace other calculations of "relative long" addresses by invocations of this function as well. And for consistency, do the same with "relative" (short) addresses. Diff: --- NEWS | 1 + VEX/priv/guest_s390_toIR.c | 144 ++++++++++++++++++--------------------- none/tests/s390x/exrl.c | 11 +++ none/tests/s390x/exrl.stdout.exp | 2 + 4 files changed, 82 insertions(+), 76 deletions(-) diff --git a/NEWS b/NEWS index 3f9439acf2..908361039e 100644 --- a/NEWS +++ b/NEWS @@ -41,6 +41,7 @@ bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather than mailing the developers (or mailing lists) directly -- bugs that are not entered into bugzilla tend to get forgotten about or ignored. +444242 s390x: Valgrind crashes on EXRL with negative offset 444495 dhat/tests/copy fails on s390x To see details of a given bug, visit diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 72222ab045..fffc563d46 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -399,6 +399,22 @@ mkF64i(ULong value) return IRExpr_Const(IRConst_F64i(value)); } +/* Return the 64-bit address with the given 32-bit "relative long" offset from + the current guest instruction being translated. */ +static __inline__ Addr64 +addr_rel_long(UInt offset) +{ + return guest_IA_curr_instr + ((Addr64)(Long)(Int)offset << 1); +} + +/* Return the 64-bit address with the given 16-bit "relative" offset from the + current guest instruction being translated. */ +static __inline__ Addr64 +addr_relative(UShort offset) +{ + return guest_IA_curr_instr + ((Addr64)(Long)(Short)offset << 1); +} + /* Little helper function for my sanity. ITE = if-then-else */ static IRExpr * mkite(IRExpr *condition, IRExpr *iftrue, IRExpr *iffalse) @@ -5516,7 +5532,7 @@ static const HChar * s390_irgen_BRAS(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(guest_IA_curr_instr + 4ULL)); - call_function_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + call_function_and_chase(addr_relative(i2)); return "bras"; } @@ -5525,7 +5541,7 @@ static const HChar * s390_irgen_BRASL(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64(guest_IA_curr_instr + 6ULL)); - call_function_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)); + call_function_and_chase(addr_rel_long(i2)); return "brasl"; } @@ -5538,12 +5554,11 @@ s390_irgen_BRC(UChar r1, UShort i2) if (r1 == 0) { } else { if (r1 == 15) { - always_goto_and_chase( - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + always_goto_and_chase(addr_relative(i2)); } else { assign(cond, s390_call_calculate_cond(r1)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); } } @@ -5561,11 +5576,11 @@ s390_irgen_BRCL(UChar r1, UInt i2) if (r1 == 0) { } else { if (r1 == 15) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)); + always_goto_and_chase(addr_rel_long(i2)); } else { assign(cond, s390_call_calculate_cond(r1)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)); + addr_rel_long(i2)); } } if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) @@ -5579,7 +5594,7 @@ s390_irgen_BRCT(UChar r1, UShort i2) { put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1))); if_condition_goto(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brct"; } @@ -5589,7 +5604,7 @@ s390_irgen_BRCTH(UChar r1, UInt i2) { put_gpr_w0(r1, binop(Iop_Sub32, get_gpr_w0(r1), mkU32(1))); if_condition_goto(binop(Iop_CmpNE32, get_gpr_w0(r1), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brcth"; } @@ -5599,7 +5614,7 @@ s390_irgen_BRCTG(UChar r1, UShort i2) { put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1))); if_condition_goto(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brctg"; } @@ -5612,7 +5627,7 @@ s390_irgen_BRXH(UChar r1, UChar r3, UShort i2) assign(value, get_gpr_w1(r3 | 1)); put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto(binop(Iop_CmpLT32S, mkexpr(value), get_gpr_w1(r1)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brxh"; } @@ -5625,7 +5640,7 @@ s390_irgen_BRXHG(UChar r1, UChar r3, UShort i2) assign(value, get_gpr_dw0(r3 | 1)); put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto(binop(Iop_CmpLT64S, mkexpr(value), get_gpr_dw0(r1)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brxhg"; } @@ -5638,7 +5653,7 @@ s390_irgen_BRXLE(UChar r1, UChar r3, UShort i2) assign(value, get_gpr_w1(r3 | 1)); put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto(binop(Iop_CmpLE32S, get_gpr_w1(r1), mkexpr(value)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brxle"; } @@ -5651,7 +5666,7 @@ s390_irgen_BRXLG(UChar r1, UChar r3, UShort i2) assign(value, get_gpr_dw0(r3 | 1)); put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto(binop(Iop_CmpLE64S, get_gpr_dw0(r1), mkexpr(value)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1)); + addr_relative(i2)); return "brxlg"; } @@ -5782,8 +5797,7 @@ s390_irgen_CRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I32); assign(op1, get_gpr_w1(r1)); - assign(op2, load(Ity_I32, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + assign(op2, load(Ity_I32, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); return "crl"; @@ -5796,8 +5810,7 @@ s390_irgen_CGRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, load(Ity_I64, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + assign(op2, load(Ity_I64, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); return "cgrl"; @@ -5810,8 +5823,7 @@ s390_irgen_CGFRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); return "cgfrl"; @@ -5875,15 +5887,14 @@ s390_irgen_CRJ(UChar r1, UChar r2, UShort i4, UChar m3) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase( - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_w1(r1)); assign(op2, get_gpr_w1(r2)); assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -5901,15 +5912,14 @@ s390_irgen_CGRJ(UChar r1, UChar r2, UShort i4, UChar m3) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase( - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_dw0(r1)); assign(op2, get_gpr_dw0(r2)); assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -5975,14 +5985,14 @@ s390_irgen_CIJ(UChar r1, UChar m3, UShort i4, UChar i2) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_w1(r1)); op2 = (Int)(Char)i2; assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32((UInt)op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -6000,14 +6010,14 @@ s390_irgen_CGIJ(UChar r1, UChar m3, UShort i4, UChar i2) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_dw0(r1)); op2 = (Long)(Char)i2; assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64((ULong)op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -6131,8 +6141,7 @@ s390_irgen_CHRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I32); assign(op1, get_gpr_w1(r1)); - assign(op2, unop(Iop_16Sto32, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_16Sto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); return "chrl"; @@ -6145,8 +6154,7 @@ s390_irgen_CGHRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); return "cghrl"; @@ -6401,8 +6409,7 @@ s390_irgen_CLRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I32); assign(op1, get_gpr_w1(r1)); - assign(op2, load(Ity_I32, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + assign(op2, load(Ity_I32, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); return "clrl"; @@ -6415,8 +6422,7 @@ s390_irgen_CLGRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, load(Ity_I64, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + assign(op2, load(Ity_I64, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); return "clgrl"; @@ -6429,8 +6435,7 @@ s390_irgen_CLGFRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); return "clgfrl"; @@ -6443,8 +6448,7 @@ s390_irgen_CLHRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I32); assign(op1, get_gpr_w1(r1)); - assign(op2, unop(Iop_16Uto32, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_16Uto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); return "clhrl"; @@ -6457,8 +6461,7 @@ s390_irgen_CLGHRL(UChar r1, UInt i2) IRTemp op2 = newTemp(Ity_I64); assign(op1, get_gpr_dw0(r1)); - assign(op2, unop(Iop_16Uto64, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + assign(op2, unop(Iop_16Uto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); return "clghrl"; @@ -6730,14 +6733,14 @@ s390_irgen_CLRJ(UChar r1, UChar r2, UShort i4, UChar m3) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_w1(r1)); assign(op2, get_gpr_w1(r2)); assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -6755,14 +6758,14 @@ s390_irgen_CLGRJ(UChar r1, UChar r2, UShort i4, UChar m3) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_dw0(r1)); assign(op2, get_gpr_dw0(r2)); assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -6828,14 +6831,14 @@ s390_irgen_CLIJ(UChar r1, UChar m3, UShort i4, UChar i2) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_w1(r1)); op2 = (UInt)i2; assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32(op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -6853,14 +6856,14 @@ s390_irgen_CLGIJ(UChar r1, UChar m3, UShort i4, UChar i2) if (m3 == 0) { } else { if (m3 == 14) { - always_goto_and_chase(guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + always_goto_and_chase(addr_relative(i4)); } else { assign(op1, get_gpr_dw0(r1)); op2 = (ULong)i2; assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64(op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), - guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1)); + addr_relative(i4)); } } @@ -7539,8 +7542,7 @@ s390_irgen_LGFI(UChar r1, UInt i2) static const HChar * s390_irgen_LRL(UChar r1, UInt i2) { - put_gpr_w1(r1, load(Ity_I32, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + put_gpr_w1(r1, load(Ity_I32, mkU64(addr_rel_long(i2)))); return "lrl"; } @@ -7548,8 +7550,7 @@ s390_irgen_LRL(UChar r1, UInt i2) static const HChar * s390_irgen_LGRL(UChar r1, UInt i2) { - put_gpr_dw0(r1, load(Ity_I64, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int) - i2 << 1)))); + put_gpr_dw0(r1, load(Ity_I64, mkU64(addr_rel_long(i2)))); return "lgrl"; } @@ -7557,8 +7558,7 @@ s390_irgen_LGRL(UChar r1, UInt i2) static const HChar * s390_irgen_LGFRL(UChar r1, UInt i2) { - put_gpr_dw0(r1, unop(Iop_32Sto64, load(Ity_I32, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_dw0(r1, unop(Iop_32Sto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); return "lgfrl"; } @@ -7598,7 +7598,7 @@ s390_irgen_LAEY(UChar r1, IRTemp op2addr) static const HChar * s390_irgen_LARL(UChar r1, UInt i2) { - put_gpr_dw0(r1, mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1))); + put_gpr_dw0(r1, mkU64(addr_rel_long(i2))); return "larl"; } @@ -8038,8 +8038,7 @@ s390_irgen_LGHI(UChar r1, UShort i2) static const HChar * s390_irgen_LHRL(UChar r1, UInt i2) { - put_gpr_w1(r1, unop(Iop_16Sto32, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_w1(r1, unop(Iop_16Sto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); return "lhrl"; } @@ -8047,8 +8046,7 @@ s390_irgen_LHRL(UChar r1, UInt i2) static const HChar * s390_irgen_LGHRL(UChar r1, UInt i2) { - put_gpr_dw0(r1, unop(Iop_16Sto64, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_dw0(r1, unop(Iop_16Sto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); return "lghrl"; } @@ -8088,8 +8086,7 @@ s390_irgen_LLGF(UChar r1, IRTemp op2addr) static const HChar * s390_irgen_LLGFRL(UChar r1, UInt i2) { - put_gpr_dw0(r1, unop(Iop_32Uto64, load(Ity_I32, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_dw0(r1, unop(Iop_32Uto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); return "llgfrl"; } @@ -8169,8 +8166,7 @@ s390_irgen_LLGH(UChar r1, IRTemp op2addr) static const HChar * s390_irgen_LLHRL(UChar r1, UInt i2) { - put_gpr_w1(r1, unop(Iop_16Uto32, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_w1(r1, unop(Iop_16Uto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); return "llhrl"; } @@ -8178,8 +8174,7 @@ s390_irgen_LLHRL(UChar r1, UInt i2) static const HChar * s390_irgen_LLGHRL(UChar r1, UInt i2) { - put_gpr_dw0(r1, unop(Iop_16Uto64, load(Ity_I16, mkU64(guest_IA_curr_instr + - ((ULong)(Long)(Int)i2 << 1))))); + put_gpr_dw0(r1, unop(Iop_16Uto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); return "llghrl"; } @@ -10064,8 +10059,7 @@ s390_irgen_STG(UChar r1, IRTemp op2addr) static const HChar * s390_irgen_STRL(UChar r1, UInt i2) { - store(mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)), - get_gpr_w1(r1)); + store(mkU64(addr_rel_long(i2)), get_gpr_w1(r1)); return "strl"; } @@ -10073,8 +10067,7 @@ s390_irgen_STRL(UChar r1, UInt i2) static const HChar * s390_irgen_STGRL(UChar r1, UInt i2) { - store(mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)), - get_gpr_dw0(r1)); + store(mkU64(addr_rel_long(i2)), get_gpr_dw0(r1)); return "stgrl"; } @@ -10203,8 +10196,7 @@ s390_irgen_STHY(UChar r1, IRTemp op2addr) static const HChar * s390_irgen_STHRL(UChar r1, UInt i2) { - store(mkU64(guest_IA_curr_instr + ((ULong)(Long)(Int)i2 << 1)), - get_gpr_hw3(r1)); + store(mkU64(addr_rel_long(i2)), get_gpr_hw3(r1)); return "sthrl"; } @@ -13282,7 +13274,7 @@ static const HChar * s390_irgen_EXRL(UChar r1, UInt offset) { IRTemp addr = newTemp(Ity_I64); - Addr64 bytes_addr = guest_IA_curr_instr + offset * 2UL; + Addr64 bytes_addr = addr_rel_long(offset); UChar *bytes = (UChar *)(HWord)bytes_addr; /* we might save one round trip because we know the target */ if (!last_execute_target) diff --git a/none/tests/s390x/exrl.c b/none/tests/s390x/exrl.c index 2c99602d82..e669e484fe 100644 --- a/none/tests/s390x/exrl.c +++ b/none/tests/s390x/exrl.c @@ -54,6 +54,17 @@ int main(void) printf("|\n"); printf("\n"); + printf("------- EXRL with negative offset\n"); + asm volatile( "j 2f\n\t" + "1:\n\t" + "mvc 2(1,%0),0(%0)\n\t" + "2:\n\t" + "lghi 1,8\n\t" + ".insn ril,0xc60000000000,1,1b\n\t" // exrl 1, 1b + : : "a" (target) + : "1", "2", "3", "4"); + printf(" target = |%s|\n", target); + return 0; } diff --git a/none/tests/s390x/exrl.stdout.exp b/none/tests/s390x/exrl.stdout.exp index 520919e925..30dcde8295 100644 --- a/none/tests/s390x/exrl.stdout.exp +++ b/none/tests/s390x/exrl.stdout.exp @@ -11,3 +11,5 @@ after: target = |0123456789aXXXXX| ------- EXRL to OR in the syscall number (writes out target) target = |0123456789aXXXXX| +------- EXRL with negative offset + target = |01010101010XXXXX| |
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From: Mark W. <ma...@so...> - 2021-10-28 12:13:36
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0cf05f82d4fb9b34ddea7de6932231bc5796e66a commit 0cf05f82d4fb9b34ddea7de6932231bc5796e66a Author: Mark Wielaard <ma...@kl...> Date: Thu Oct 28 14:10:49 2021 +0200 Set version to 3.19.0.GIT in configure.ac And update docs/internals/release-HOWTO.txt. Diff: --- configure.ac | 8 ++++---- docs/internals/release-HOWTO.txt | 35 +++++++++++++++++++++-------------- 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/configure.ac b/configure.ac index d5683f2b5b..e7381f205d 100755 --- a/configure.ac +++ b/configure.ac @@ -15,10 +15,10 @@ # Also set the (expected/last) release date here. # Do not forget to rerun ./autogen.sh m4_define([v_major_ver], [3]) -m4_define([v_minor_ver], [18]) -m4_define([v_micro_ver], [1]) -m4_define([v_suffix_ver], []) -m4_define([v_rel_date], ["15 Oct 2021"]) +m4_define([v_minor_ver], [19]) +m4_define([v_micro_ver], [0]) +m4_define([v_suffix_ver], [GIT]) +m4_define([v_rel_date], ["?? ??? 202?"]) m4_define([v_version], m4_if(v_suffix_ver, [], [v_major_ver.v_minor_ver.v_micro_ver], diff --git a/docs/internals/release-HOWTO.txt b/docs/internals/release-HOWTO.txt index 45cc41a435..17fa480ebc 100644 --- a/docs/internals/release-HOWTO.txt +++ b/docs/internals/release-HOWTO.txt @@ -17,12 +17,16 @@ First of all: - Go over the docs, make sure they're up to date. -- Update version number and date in docs/xml/vg-entities.xml. (Exact - release date probably won't be known yet, updating it is in the list below - of tasks for the official release.) +- Update version number and date in configure.ac. Probably just the + v_suffix_ver, set it to RC1. The v_rel_date probably won't be known yet, + updating it is in the list below of tasks for the official release. + Note that the date MUST be quoted with ["...date string..."]. -- Make sure __VALGRIND_MAJOR__ and __VALGRIND_MINOR__ are correct - for the release. (include/valgrind.h) +- Make sure the after ./autogen.sh && ./configure + __VALGRIND_MAJOR__ and __VALGRIND_MINOR__ are correct for the release. + (include/valgrind.h) + And that docs/xml/vg-entities.xml contains the correct release number + and release date. - Write release notes, add to NEWS. Include a list of fixed bugs from Bugzilla. It's unclear how to do this consistently. The approach @@ -105,11 +109,16 @@ releases, bug-fix-only releases might not need one): * s390x: Ensure README.s390 is up-to-date and URLs therein are not stale. -- Change release number in AC_INIT() in configure.ac to "X.Y.Z-rcN", where - 'N' is the release candidate number. +- Change release number (v_major_ver, v_minor_ver, v_micro_ver) + in configure.ac, set v_suffix_ver to RCN, where 'N' is the release + candidate number. Don't forget to ./autogen.sh and ./configure afterwards. - Make the tarball ("make dist") and put it on the web somewhere (it doesn't have to be on valgrind.org if another site is easier). + https://sourceware.org/pub/valgrind/ is the default release site now. + You need a shell account on sourceware.org, then scp it with: + scp valgrind-X.YY-RCN.tar.bz \ + US...@so...:/sourceware/ftp/pub/valgrind/ - Ensure the tarball builds, runs, regtests on the platforms of interest. However redundant this seems, sometimes it can be that a from-the-repo @@ -134,16 +143,14 @@ releases, bug-fix-only releases might not need one): For the official release: -- Again, update date in docs/xml/vg-entities.xml for the official release - date. +- Again, update date (v_rel_date) in configure.ac for the official release + date and set v_suffix_ver to empty [] in configure.ac. - Do pre-release testing: - Make sure regtests run ok on all platforms of interest. - Make sure Mozilla and OpenOffice run ok on all platforms of interest. -- Change release number in AC_INIT() in configure.ac to "X.Y.Z". - -- Make the tarball ("make dist"). +- Run ./autogen.sh && ./configure && make dist to make the tarball. - Check tarball builds, installs, regtests on platforms of interest. If not, fix and repeat until success. @@ -178,8 +185,8 @@ For the official release: - Update the "release-date" and "release-version" in php/.htconfx. - Other pages that might need updating: downloads/repository.html. -- Change release number in AC_INIT() in configure.ac to "X.Y.Z.GIT", where - X.Y.Z is one more than the release just done. +- Change release number in configure.ac with v_minor_ver one more than the + release just done. Set v_suffix_ver to [GIT]. - Make sure the release notes are present in the NEWS file on the master and the branch. |
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From: Andreas A. <ar...@so...> - 2021-10-28 11:49:23
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ffb3f77a22403089364c98a9372d9b13fe684e89 commit ffb3f77a22403089364c98a9372d9b13fe684e89 Author: Andreas Arnez <ar...@li...> Date: Thu Oct 28 12:21:28 2021 +0200 Prepare NEWS for the next release Add a placeholder for the next release to the NEWS file and start the list of fixed bugs with Bug 444495. Diff: --- NEWS | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/NEWS b/NEWS index 7d2cce734e..3f9439acf2 100644 --- a/NEWS +++ b/NEWS @@ -1,3 +1,53 @@ +Release 3.??.? (?? 202?) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux, +PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux, +MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android, +X86/Solaris, AMD64/Solaris, AMD64/MacOSX 10.12, X86/FreeBSD and +AMD64/FreeBSD. There is also preliminary support for X86/macOS 10.13, +AMD64/macOS 10.13 and nanoMIPS/Linux. + +* ==================== CORE CHANGES =================== + +* ================== PLATFORM CHANGES ================= + +* arm64: + +* s390: + +* ppc64: + +* ==================== TOOL CHANGES =================== + +* DHAT: + +* Cachegrind: + +* Callgrind: + +* Massif: + +* Memcheck: + +* =================== OTHER CHANGES ================== + +* ==================== FIXED BUGS ==================== + +The following bugs have been fixed or resolved. Note that "n-i-bz" +stands for "not in bugzilla" -- that is, a bug that was reported to us +but never got a bugzilla entry. We encourage you to file bugs in +bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather +than mailing the developers (or mailing lists) directly -- bugs that +are not entered into bugzilla tend to get forgotten about or ignored. + +444495 dhat/tests/copy fails on s390x + +To see details of a given bug, visit + https://bugs.kde.org/show_bug.cgi?id=XXXXXX +where XXXXXX is the bug number as listed below. + + Release 3.18.0 (15 Oct 2021) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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From: Paul F. <pa...@so...> - 2021-10-27 19:38:36
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=33aba8eef68b1745d3de96b609ff8296b70d9a1c commit 33aba8eef68b1745d3de96b609ff8296b70d9a1c Author: Paul Floyd <pj...@wa...> Date: Wed Oct 27 21:37:00 2021 +0200 Bug 444495 - dhat/tests/copy fails on s390x Add -fno-builtin to ensure that the copy functions get called and so dhat can intercept and count them. Diff: --- dhat/tests/Makefile.am | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dhat/tests/Makefile.am b/dhat/tests/Makefile.am index 86a9b6d647..b86fc416d4 100644 --- a/dhat/tests/Makefile.am +++ b/dhat/tests/Makefile.am @@ -29,3 +29,6 @@ AM_CXXFLAGS += $(AM_FLAG_M3264_PRI) # We don't care about uninitialized or unused malloc results basic_CFLAGS = $(AM_CFLAGS) -Wno-uninitialized big_CFLAGS = $(AM_CFLAGS) -Wno-unused-result + +# Prevent the copying functions from being inlined +copy_CFLAGS = $(AM_CFLAGS) -fno-builtin |
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From: Paul F. <pa...@so...> - 2021-10-23 07:20:26
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=eaf0525704e9344bfae8f923cc9f48a9d4d87484 commit eaf0525704e9344bfae8f923cc9f48a9d4d87484 Author: Paul Floyd <pj...@wa...> Date: Sat Oct 23 09:02:58 2021 +0200 Change nightly script to only print assembler if it is present. On FreeBSD 'as' is part of the optional 'binutils' packkage. By default, clang uses its built-in assembler and 'as' is not used. Diff: --- nightly/bin/nightly | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/nightly/bin/nightly b/nightly/bin/nightly index 370a181114..3bd5986de8 100755 --- a/nightly/bin/nightly +++ b/nightly/bin/nightly @@ -185,13 +185,14 @@ END=`date "+%F %H:%M:%S %Z"` # Gather some information about this run and its environment valgrind_revision=$( ./valgrind-new/vg-in-place -v --version ) +as_version="" if [ `uname -o` = "FreeBSD" ]; then gcc_version="`clang --version 2> /dev/null | head -1`" else gcc_version="`gcc --version 2> /dev/null | head -1`" + as_version="`as --version 2> /dev/null | head -1`" fi gdb_version="`gdb --version 2> /dev/null | head -1`" -as_version="`as --version 2> /dev/null | head -1`" if [ `uname -o` = "Solaris" ]; then libc="Solaris libc" elif [ `uname -o` = "FreeBSD" ]; then @@ -222,7 +223,9 @@ fi echo "valgrind revision: $valgrind_revision" > final echo "C compiler: $gcc_version" >> final echo "GDB: $gdb_version" >> final -echo "Assembler: $as_version" >> final +if [ -n "${as_version}" ] ; then + echo "Assembler: $as_version" >> final +fi echo "C library: $libc" >> final echo "uname -mrs: $uname_stuff" >> final echo "Vendor version: $vendor_stuff" >> final |
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From: Paul F. <pa...@so...> - 2021-10-19 19:32:48
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=717a82afe072a60afb66c4481716765766d32020 commit 717a82afe072a60afb66c4481716765766d32020 Author: Paul Floyd <pj...@wa...> Date: Tue Oct 19 21:31:10 2021 +0200 Make the nightly conf files for FreeBSD more generic I don't want to either rename or add new versions of these files for every release. Diff: --- nightly/conf/freebsd12.1.conf | 4 ---- nightly/conf/freebsd12.1.sendmail | 8 -------- 2 files changed, 12 deletions(-) diff --git a/nightly/conf/freebsd12.1.conf b/nightly/conf/freebsd12.1.conf deleted file mode 100644 index c76383ed5c..0000000000 --- a/nightly/conf/freebsd12.1.conf +++ /dev/null @@ -1,4 +0,0 @@ -export ABT_DETAILS=`uname -mrs` -export ABT_JOBS=2 -#export ABT_PERF="--tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-old --vg=../valgrind-new" -export ABT_CONFIGURE_OPTIONS="CC=clang CXX=clang++" diff --git a/nightly/conf/freebsd12.1.sendmail b/nightly/conf/freebsd12.1.sendmail deleted file mode 100755 index 6fc10f9deb..0000000000 --- a/nightly/conf/freebsd12.1.sendmail +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -subject=$1 -body=$2 -file=$3 -filename=$( basename $3 ) - -(cat "$body" "$file") | mail -s "$subject" val...@li... -f "Paul Floyd <pj...@wa...>" |
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From: Paul F. <pa...@so...> - 2021-10-19 18:06:10
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=aea6ca5ce73cc4fcb4f637091a7cd7c25803384a commit aea6ca5ce73cc4fcb4f637091a7cd7c25803384a Author: Paul Floyd <pj...@wa...> Date: Tue Oct 19 20:03:39 2021 +0200 Update a few FreeBSD suppressions Make one more generic Add one for the libc buffer used by libc++ std::cout Diff: --- freebsd.supp | 14 ++++++++++++-- nightly/conf/freebsd.conf | 4 ++++ nightly/conf/freebsd.sendmail | 8 ++++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/freebsd.supp b/freebsd.supp index 7345d713de..7f9b22bb30 100644 --- a/freebsd.supp +++ b/freebsd.supp @@ -23,13 +23,13 @@ Memcheck:Leak match-leak-kinds: reachable fun:malloc - obj:/usr/local/lib*/gcc9/libstdc++.so.* + obj:/usr/local/lib*/gcc*/libstdc++.so.* obj:/libexec/ld-elf*.so.1 obj:/libexec/ld-elf*.so.1 obj:/libexec/ld-elf*.so.1 } { - MEMCHECK-LIBC-REACHABLE + MEMCHECK-LIBC-REACHABLE-1 Memcheck:Leak match-leak-kinds: reachable fun:malloc @@ -49,3 +49,13 @@ Memcheck:Cond fun:posix_fallocate } +{ + MEMCHECK-LIBX-REACHABLE-2 + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc + obj:/lib/libc.so.7 + obj:/lib/libc.so.7 + obj:/lib/libc.so.7 + fun:fwrite +} diff --git a/nightly/conf/freebsd.conf b/nightly/conf/freebsd.conf new file mode 100644 index 0000000000..c76383ed5c --- /dev/null +++ b/nightly/conf/freebsd.conf @@ -0,0 +1,4 @@ +export ABT_DETAILS=`uname -mrs` +export ABT_JOBS=2 +#export ABT_PERF="--tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-old --vg=../valgrind-new" +export ABT_CONFIGURE_OPTIONS="CC=clang CXX=clang++" diff --git a/nightly/conf/freebsd.sendmail b/nightly/conf/freebsd.sendmail new file mode 100755 index 0000000000..6fc10f9deb --- /dev/null +++ b/nightly/conf/freebsd.sendmail @@ -0,0 +1,8 @@ +#!/bin/sh + +subject=$1 +body=$2 +file=$3 +filename=$( basename $3 ) + +(cat "$body" "$file") | mail -s "$subject" val...@li... -f "Paul Floyd <pj...@wa...>" |
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From: Julian S. <se...@so...> - 2021-10-19 14:20:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3abc6d815ccb970fc7e3f2d11150cc05e887592c commit 3abc6d815ccb970fc7e3f2d11150cc05e887592c Author: Julian Seward <js...@ac...> Date: Tue Oct 19 16:19:31 2021 +0200 guest_amd64_toIR.c: use the VexAbiInfo mechanism to remove an `ifdef freebsd`. n-i-bz. Diff: --- VEX/priv/guest_amd64_toIR.c | 132 ++++++++++++++++++++++---------------------- VEX/priv/main_main.c | 1 + VEX/pub/libvex.h | 5 ++ coregrind/m_translate.c | 1 + 4 files changed, 73 insertions(+), 66 deletions(-) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 86fe07fdc5..536577b60c 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -10139,34 +10139,34 @@ static IRTemp math_PALIGNR_XMM ( IRTemp sV, IRTemp dV, UInt imm8 ) This assumes that guest_RIP_curr_instr is set correctly! On FreeBSD, this kind of error generates a SIGBUS. */ static -void gen_SIGNAL_if_not_XX_aligned ( IRTemp effective_addr, ULong mask ) +void gen_SIGNAL_if_not_XX_aligned ( const VexAbiInfo* vbi, + IRTemp effective_addr, ULong mask ) { stmt( IRStmt_Exit( binop(Iop_CmpNE64, binop(Iop_And64,mkexpr(effective_addr),mkU64(mask)), mkU64(0)), -#if defined(VGO_freebsd) - Ijk_SigBUS, -#else - Ijk_SigSEGV, -#endif + vbi->guest_amd64_sigbus_on_misalign ? Ijk_SigBUS : Ijk_SigSEGV, IRConst_U64(guest_RIP_curr_instr), OFFB_RIP ) ); } -static void gen_SIGNAL_if_not_16_aligned ( IRTemp effective_addr ) { - gen_SIGNAL_if_not_XX_aligned(effective_addr, 16-1); +static void gen_SIGNAL_if_not_16_aligned ( const VexAbiInfo* vbi, + IRTemp effective_addr ) { + gen_SIGNAL_if_not_XX_aligned(vbi, effective_addr, 16-1); } -static void gen_SIGNAL_if_not_32_aligned ( IRTemp effective_addr ) { - gen_SIGNAL_if_not_XX_aligned(effective_addr, 32-1); +static void gen_SIGNAL_if_not_32_aligned ( const VexAbiInfo* vbi, + IRTemp effective_addr ) { + gen_SIGNAL_if_not_XX_aligned(vbi, effective_addr, 32-1); } -static void gen_SIGNAL_if_not_64_aligned ( IRTemp effective_addr ) { - gen_SIGNAL_if_not_XX_aligned(effective_addr, 64-1); +static void gen_SIGNAL_if_not_64_aligned ( const VexAbiInfo* vbi, + IRTemp effective_addr ) { + gen_SIGNAL_if_not_XX_aligned(vbi, effective_addr, 64-1); } @@ -11922,7 +11922,7 @@ static Long dis_XSAVE ( const VexAbiInfo* vbi, addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_64_aligned(addr); + gen_SIGNAL_if_not_64_aligned(vbi, addr); DIP("%sxsave %s\n", sz==8 ? "rex64/" : "", dis_buf); @@ -11966,7 +11966,7 @@ static Long dis_FXSAVE ( const VexAbiInfo* vbi, addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); DIP("%sfxsave %s\n", sz==8 ? "rex64/" : "", dis_buf); @@ -12177,7 +12177,7 @@ static Long dis_XRSTOR ( const VexAbiInfo* vbi, addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_64_aligned(addr); + gen_SIGNAL_if_not_64_aligned(vbi, addr); DIP("%sxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf); @@ -12247,7 +12247,7 @@ static Long dis_FXRSTOR ( const VexAbiInfo* vbi, addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); DIP("%sfxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf); @@ -12953,7 +12953,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("movapd %s,%s\n", dis_buf, @@ -12974,7 +12974,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("movaps %s,%s\n", dis_buf, @@ -12998,7 +12998,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movaps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf ); @@ -13018,7 +13018,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movapd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf ); @@ -13216,7 +13216,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, modrm = getUChar(delta); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s", dis_buf, @@ -13961,7 +13961,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("movdqa %s,%s\n", dis_buf, @@ -14261,7 +14261,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, nameXMMReg(eregOfRexRM(pfx,modrm))); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); delta += alen; storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf); @@ -14942,7 +14942,7 @@ Long dis_ESC_0F__SSE2 ( Bool* decode_OK, modrm = getUChar(delta); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movntdq %s,%s\n", dis_buf, nameXMMReg(gregOfRexRM(pfx,modrm))); @@ -15369,7 +15369,7 @@ static Long dis_MOVSxDUP_128 ( const VexAbiInfo* vbi, Prefix pfx, } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); if (!isAvx) - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); DIP("%smovs%cdup %s,%s\n", isAvx ? "v" : "", isL ? 'l' : 'h', dis_buf, nameXMMReg(rG)); @@ -15724,7 +15724,7 @@ static Long dis_PHADD_128 ( const VexAbiInfo* vbi, Prefix pfx, Long delta, } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); if (!isAvx) - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); DIP("%sph%s %s,%s\n", isAvx ? "v" : "", str, dis_buf, nameXMMReg(rG)); @@ -15884,7 +15884,7 @@ Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK, nameXMMReg(gregOfRexRM(pfx,modrm))); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("pshufb %s,%s\n", dis_buf, @@ -16036,7 +16036,7 @@ Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK, DIP("pmaddubsw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG)); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("pmaddubsw %s,%s\n", dis_buf, nameXMMReg(rG)); @@ -16131,7 +16131,7 @@ Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK, nameXMMReg(gregOfRexRM(pfx,modrm))); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("psign%s %s,%s\n", str, dis_buf, @@ -16215,7 +16215,7 @@ Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK, nameXMMReg(gregOfRexRM(pfx,modrm))); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("pmulhrsw %s,%s\n", dis_buf, @@ -16294,7 +16294,7 @@ Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK, nameXMMReg(gregOfRexRM(pfx,modrm))); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("pabs%s %s,%s\n", str, dis_buf, @@ -16401,7 +16401,7 @@ Long dis_ESC_0F3A__SupSSE3 ( Bool* decode_OK, nameXMMReg(gregOfRexRM(pfx,modrm))); } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); d64 = (Long)getUChar(delta+alen); delta += alen+1; @@ -16946,7 +16946,7 @@ static Long dis_xTESTy_128 ( const VexAbiInfo* vbi, Prefix pfx, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); if (!isAvx) - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign(vecE, loadLE( Ity_V128, mkexpr(addr) )); delta += alen; DIP( "%s%stest%s %s,%s\n", @@ -17748,7 +17748,7 @@ static Long dis_PHMINPOSUW_128 ( const VexAbiInfo* vbi, Prefix pfx, } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); if (!isAvx) - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); delta += alen; DIP("%sphminposuw %s,%s\n", mbV, dis_buf, nameXMMReg(rG)); @@ -17982,7 +17982,7 @@ Long dis_ESC_0F38__SSE4 ( Bool* decode_OK, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign(vecE, loadLE( Ity_V128, mkexpr(addr) )); delta += alen; DIP( "%s %s,%s\n", nm, @@ -18115,7 +18115,7 @@ Long dis_ESC_0F38__SSE4 ( Bool* decode_OK, modrm = getUChar(delta); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("movntdqa %s,%s\n", dis_buf, @@ -18144,7 +18144,7 @@ Long dis_ESC_0F38__SSE4 ( Bool* decode_OK, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( argL, loadLE( Ity_V128, mkexpr(addr) )); delta += alen; DIP( "packusdw %s,%s\n", @@ -18327,7 +18327,7 @@ Long dis_ESC_0F38__SSE4 ( Bool* decode_OK, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( argL, loadLE( Ity_V128, mkexpr(addr) )); delta += alen; DIP( "pmulld %s,%s\n", @@ -19298,7 +19298,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 ); - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); assign( src0, loadLE(Ity_F32, binop(Iop_Add64, mkexpr(addr), mkU64(0) ))); assign( src1, loadLE(Ity_F32, @@ -19360,7 +19360,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 ); - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); assign( src0, loadLE(Ity_F64, binop(Iop_Add64, mkexpr(addr), mkU64(0) ))); assign( src1, loadLE(Ity_F64, @@ -19465,7 +19465,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19501,7 +19501,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19538,7 +19538,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19760,7 +19760,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19793,7 +19793,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19829,7 +19829,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -19866,7 +19866,7 @@ Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK, } else { addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1/* imm8 is 1 byte after the amode */ ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); assign( svec, loadLE( Ity_V128, mkexpr(addr) ) ); imm8 = (Int)getUChar(delta+alen); delta += alen+1; @@ -22365,7 +22365,7 @@ Long dis_ESC_0F ( /* cmpxchg16b requires an alignment check. */ if (sz == 8) - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); /* Get the expected and new values. */ assign( expdHi64, getIReg64(R_RDX) ); @@ -24770,7 +24770,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) ); DIP("vmovapd %s,%s\n", dis_buf, nameXMMReg(rG)); delta += alen; @@ -24788,7 +24788,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_32_aligned( addr ); + gen_SIGNAL_if_not_32_aligned( vbi, addr ); putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) ); DIP("vmovapd %s,%s\n", dis_buf, nameYMMReg(rG)); delta += alen; @@ -24806,7 +24806,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) ); DIP("vmovaps %s,%s\n", dis_buf, nameXMMReg(rG)); delta += alen; @@ -24824,7 +24824,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_32_aligned( addr ); + gen_SIGNAL_if_not_32_aligned( vbi, addr ); putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) ); DIP("vmovaps %s,%s\n", dis_buf, nameYMMReg(rG)); delta += alen; @@ -24845,7 +24845,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(rG) ); DIP("vmovapd %s,%s\n", nameXMMReg(rG), dis_buf ); delta += alen; @@ -24863,7 +24863,7 @@ Long dis_ESC_0F__VEX ( delta += 1; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_32_aligned( addr ); + gen_SIGNAL_if_not_32_aligned( vbi, addr ); storeLE( mkexpr(addr), getYMMReg(rG) ); DIP("vmovapd %s,%s\n", nameYMMReg(rG), dis_buf ); delta += alen; @@ -24882,7 +24882,7 @@ Long dis_ESC_0F__VEX ( goto decode_success; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(rG) ); DIP("vmovaps %s,%s\n", nameXMMReg(rG), dis_buf ); delta += alen; @@ -24901,7 +24901,7 @@ Long dis_ESC_0F__VEX ( goto decode_success; } else { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_32_aligned( addr ); + gen_SIGNAL_if_not_32_aligned( vbi, addr ); storeLE( mkexpr(addr), getYMMReg(rG) ); DIP("vmovaps %s,%s\n", nameYMMReg(rG), dis_buf ); delta += alen; @@ -25040,7 +25040,7 @@ Long dis_ESC_0F__VEX ( assign(tS, getXMMReg(rS)); addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); storeLE(mkexpr(addr), mkexpr(tS)); DIP("vmovntp%c %s,%s\n", have66(pfx) ? 'd' : 's', nameXMMReg(rS), dis_buf); @@ -25056,7 +25056,7 @@ Long dis_ESC_0F__VEX ( assign(tS, getYMMReg(rS)); addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_32_aligned(addr); + gen_SIGNAL_if_not_32_aligned(vbi, addr); storeLE(mkexpr(addr), mkexpr(tS)); DIP("vmovntp%c %s,%s\n", have66(pfx) ? 'd' : 's', nameYMMReg(rS), dis_buf); @@ -26047,7 +26047,7 @@ Long dis_ESC_0F__VEX ( addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; if (isA) - gen_SIGNAL_if_not_32_aligned(addr); + gen_SIGNAL_if_not_32_aligned(vbi, addr); assign(tD, loadLE(Ity_V256, mkexpr(addr))); DIP("vmovdq%c %s,%s\n", ch, dis_buf, nameYMMReg(rD)); } @@ -26072,7 +26072,7 @@ Long dis_ESC_0F__VEX ( addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; if (isA) - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); assign(tD, loadLE(Ity_V128, mkexpr(addr))); DIP("vmovdq%c %s,%s\n", ch, dis_buf, nameXMMReg(rD)); } @@ -26610,7 +26610,7 @@ Long dis_ESC_0F__VEX ( addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; if (isA) - gen_SIGNAL_if_not_32_aligned(addr); + gen_SIGNAL_if_not_32_aligned(vbi, addr); storeLE(mkexpr(addr), mkexpr(tS)); DIP("vmovdq%c %s,%s\n", ch, nameYMMReg(rS), dis_buf); } @@ -26635,7 +26635,7 @@ Long dis_ESC_0F__VEX ( addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; if (isA) - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); storeLE(mkexpr(addr), mkexpr(tS)); DIP("vmovdq%c %s,%s\n", ch, nameXMMReg(rS), dis_buf); } @@ -27307,7 +27307,7 @@ Long dis_ESC_0F__VEX ( UInt rG = gregOfRexRM(pfx,modrm); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_16_aligned( addr ); + gen_SIGNAL_if_not_16_aligned( vbi, addr ); storeLE( mkexpr(addr), getXMMReg(rG) ); DIP("vmovntdq %s,%s\n", dis_buf, nameXMMReg(rG)); delta += alen; @@ -27321,7 +27321,7 @@ Long dis_ESC_0F__VEX ( UInt rG = gregOfRexRM(pfx,modrm); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); - gen_SIGNAL_if_not_32_aligned( addr ); + gen_SIGNAL_if_not_32_aligned( vbi, addr ); storeLE( mkexpr(addr), getYMMReg(rG) ); DIP("vmovntdq %s,%s\n", dis_buf, nameYMMReg(rG)); delta += alen; @@ -28942,7 +28942,7 @@ Long dis_ESC_0F38__VEX ( IRTemp tD = newTemp(Ity_V128); addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_16_aligned(addr); + gen_SIGNAL_if_not_16_aligned(vbi, addr); assign(tD, loadLE(Ity_V128, mkexpr(addr))); DIP("vmovntdqa %s,%s\n", dis_buf, nameXMMReg(rD)); putYMMRegLoAndZU(rD, mkexpr(tD)); @@ -28956,7 +28956,7 @@ Long dis_ESC_0F38__VEX ( IRTemp tD = newTemp(Ity_V256); addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 ); delta += alen; - gen_SIGNAL_if_not_32_aligned(addr); + gen_SIGNAL_if_not_32_aligned(vbi, addr); assign(tD, loadLE(Ity_V256, mkexpr(addr))); DIP("vmovntdqa %s,%s\n", dis_buf, nameYMMReg(rD)); putYMMReg(rD, mkexpr(tD)); diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 43f053ea55..1253cf5889 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1563,6 +1563,7 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) vbi->guest_stack_redzone_size = 0; vbi->guest_amd64_assume_fs_is_const = False; vbi->guest_amd64_assume_gs_is_const = False; + vbi->guest_amd64_sigbus_on_misalign = False; vbi->guest_ppc_zap_RZ_at_blr = False; vbi->guest_ppc_zap_RZ_at_bl = NULL; vbi->guest__use_fallback_LLSC = False; diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 8d911db440..143ec85e94 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -440,6 +440,11 @@ typedef the same value? (typically 0x60 on darwin)? */ Bool guest_amd64_assume_gs_is_const; + /* AMD64 GUESTS only: for a misaligned memory access, for which we should + generate a trap, should we generate SigBUS (a la FreeBSD) or SIGSEGV + (Linux, OSX) ?? */ + Bool guest_amd64_sigbus_on_misalign; + /* PPC GUESTS only: should we zap the stack red zone at a 'blr' (function return) ? */ Bool guest_ppc_zap_RZ_at_blr; diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c index c3f84a9d5b..60d5a05c86 100644 --- a/coregrind/m_translate.c +++ b/coregrind/m_translate.c @@ -1690,6 +1690,7 @@ Bool VG_(translate) ( ThreadId tid, # endif # if defined(VGP_amd64_freebsd) vex_abiinfo.guest_amd64_assume_fs_is_const = True; + vex_abiinfo.guest_amd64_sigbus_on_misalign = True; # endif # if defined(VGP_amd64_darwin) vex_abiinfo.guest_amd64_assume_gs_is_const = True; |
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From: Paul F. <pj...@wa...> - 2021-10-18 09:33:04
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> Message du 18/10/21 10:41 > De : "Ryan Cai" > A : val...@li... > Copie à : > Objet : [Valgrind-developers] About the functionalities of Helgrind > > > I am Ryan Cai, coming from HK. Helgrind is a wonderful > thread error detector I have ever used. I look into the > detected errors due to the misuses of the POSIX pthreads > API and am curious what’s the difference between these two errors? > > unlocking an invalid mutex > unlocking a not-locked mutex > > I am also wondering what’s the difference between an invalid mutex > and an not-locked mutex. Thank you very much for your time! Hi Ryan When you create a mutex, it needs to be correctly initialized. >From the manpage for pthread_mutex_init there is int pthread_mutex_init(pthread_mutex_t *restrict mutex, const pthread_mutexattr_t *restrict attr); pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; It is also possible for a correctly initialized mutex to be corrupted, for instance by an out of bounds write. You can't unlock an uninitialized or corrupt mutex - Helgrind will generate an error. A not-locked mutex is one that has been correctly initialized and then either nothing has happened to it or it has been locked and unlocked an equal number of times and in that order. Thus the lock count is zero when there is an attempt to unlock. You will get an error if you do this mutex init mutex unlock // never locked or this mutex init mutex lock mutex unlock mutex unlock // has been locked but the lock count is zero Regards Paul |
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From: Ryan C. <rya...@gm...> - 2021-10-18 08:41:00
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Dear Valgrind developers,
I am Ryan Cai, coming from HK. Helgrind is a wonderful thread error detector I have ever used. I look into the detected errors due to the misuses of the POSIX pthreads API and am curious what’s the difference between these two errors?
unlocking an invalid mutex
unlocking a not-locked mutex
I am also wondering what’s the difference between an invalid mutex and an not-locked mutex. Thank you very much for your time!
Best
Ryan
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From: Mark W. <ma...@so...> - 2021-10-17 21:49:04
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5aca524f5a2980aee2596b9425f52060370e4279 commit 5aca524f5a2980aee2596b9425f52060370e4279 Author: Mark Wielaard <ma...@kl...> Date: Sun Oct 17 22:13:25 2021 +0200 Set version once in configure.ac, use in valgrind.h andvg-entities.xml Currently the version is updated in 3 places, configure.ac, include/valgrind.h and docs/xml/vg-entities.xml. This goes wrong from time to time. So only define the version (and release date) once in configure.ac and update both other places at configure time. Diff: --- .gitignore | 5 +++++ configure.ac | 28 +++++++++++++++++++++++- docs/xml/{vg-entities.xml => vg-entities.xml.in} | 4 ++-- include/{valgrind.h => valgrind.h.in} | 4 ++-- 4 files changed, 36 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 077058207e..6a94e6c82d 100644 --- a/.gitignore +++ b/.gitignore @@ -68,6 +68,10 @@ # /auxprogs/auxchecks/ /auxprogs/auxchecks/* +# /docs/ +/docs/print/ +/docs/xml/vg-entities.xml + # /cachegrind/ /cachegrind/*.so /cachegrind/.deps @@ -693,6 +697,7 @@ /include/Makefile.in /include/Makefile /include/tool.h +/include/valgrind.h /include/vgversion.h # /include/vki/ diff --git a/configure.ac b/configure.ac index b851798f51..d5683f2b5b 100755 --- a/configure.ac +++ b/configure.ac @@ -8,7 +8,30 @@ ##------------------------------------------------------------## # Process this file with autoconf to produce a configure script. -AC_INIT([Valgrind],[3.18.1],[val...@li...]) +# +# Define major, minor, micro and suffix here once, then reuse them +# for version number in valgrind.h and vg-entities (documentation). +# suffix must be empty for a release, otherwise it is GIT or RC1, etc. +# Also set the (expected/last) release date here. +# Do not forget to rerun ./autogen.sh +m4_define([v_major_ver], [3]) +m4_define([v_minor_ver], [18]) +m4_define([v_micro_ver], [1]) +m4_define([v_suffix_ver], []) +m4_define([v_rel_date], ["15 Oct 2021"]) +m4_define([v_version], + m4_if(v_suffix_ver, [], + [v_major_ver.v_minor_ver.v_micro_ver], + [v_major_ver.v_minor_ver.v_micro_ver.v_suffix_ver])) +AC_INIT([Valgrind],[v_version],[val...@li...]) + +# For valgrind.h +AC_SUBST(VG_VER_MAJOR, v_major_ver) +AC_SUBST(VG_VER_MINOR, v_minor_ver) + +# For docs/xml/vg-entities.xml +AC_SUBST(VG_DATE, v_rel_date) + AC_CONFIG_SRCDIR(coregrind/m_main.c) AC_CONFIG_HEADERS([config.h]) AM_INIT_AUTOMAKE([foreign dist-bzip2 subdir-objects]) @@ -5121,7 +5144,9 @@ AC_CONFIG_FILES([ glibc-2.X.supp glibc-2.X-helgrind.supp glibc-2.X-drd.supp + include/valgrind.h docs/Makefile + docs/xml/vg-entities.xml tests/Makefile tests/vg_regtest perf/Makefile @@ -5255,6 +5280,7 @@ AC_OUTPUT cat<<EOF + Version: ${VERSION} Maximum build arch: ${ARCH_MAX} Primary build arch: ${VGCONF_ARCH_PRI} Secondary build arch: ${VGCONF_ARCH_SEC} diff --git a/docs/xml/vg-entities.xml b/docs/xml/vg-entities.xml.in similarity index 97% rename from docs/xml/vg-entities.xml rename to docs/xml/vg-entities.xml.in index d986a02573..681f607711 100644 --- a/docs/xml/vg-entities.xml +++ b/docs/xml/vg-entities.xml.in @@ -6,8 +6,8 @@ <!-- valgrind release + version stuff --> <!ENTITY rel-type "Release"> -<!ENTITY rel-version "3.18.0"> -<!ENTITY rel-date "15 Oct 2021"> +<!ENTITY rel-version "@VERSION@"> +<!ENTITY rel-date "@VG_DATE@"> <!-- where the docs are installed --> <!ENTITY vg-docs-path "$INSTALL/share/doc/valgrind/html/index.html"> diff --git a/include/valgrind.h b/include/valgrind.h.in similarity index 99% rename from include/valgrind.h rename to include/valgrind.h.in index 04254df8c7..aa0b431256 100644 --- a/include/valgrind.h +++ b/include/valgrind.h.in @@ -88,8 +88,8 @@ && (__VALGRIND_MAJOR__ > 3 \ || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6)) */ -#define __VALGRIND_MAJOR__ 3 -#define __VALGRIND_MINOR__ 18 +#define __VALGRIND_MAJOR__ @VG_VER_MAJOR@ +#define __VALGRIND_MINOR__ @VG_VER_MINOR@ #include <stdarg.h> |
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From: Mark W. <ma...@so...> - 2021-10-15 16:02:45
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=95468b34f128b9972a125cc4ce60f48e2db55759 commit 95468b34f128b9972a125cc4ce60f48e2db55759 Author: Mark Wielaard <ma...@kl...> Date: Fri Oct 15 18:00:52 2021 +0200 Remove executable bits from source files (drd_main.c, pub_tool_machine.h) Diff: --- drd/drd_main.c | 0 include/pub_tool_machine.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/drd/drd_main.c b/drd/drd_main.c old mode 100755 new mode 100644 diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h old mode 100755 new mode 100644 |
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From: Mark W. <ma...@so...> - 2021-10-15 12:55:15
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The signed tag 'VALGRIND_3_18_1' was created pointing to:
42b08ed5bd... -> 3.18.1 final
Tagger: Mark Wielaard <ma...@kl...>
Date: Fri Oct 15 14:48:18 2021 +0200
valgrind 3.18.1 release
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From: Mark W. <ma...@so...> - 2021-10-15 12:26:41
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=42b08ed5bda9aa2b18d826a99a10312f826e3b85 commit 42b08ed5bda9aa2b18d826a99a10312f826e3b85 Author: Mark Wielaard <ma...@kl...> Date: Fri Oct 15 14:23:54 2021 +0200 -> 3.18.1 final Now with __VALGRIND_MINOR__ set to 18 in include/valgrind.h Diff: --- configure.ac | 2 +- include/valgrind.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index e6e78d947c..b851798f51 100755 --- a/configure.ac +++ b/configure.ac @@ -8,7 +8,7 @@ ##------------------------------------------------------------## # Process this file with autoconf to produce a configure script. -AC_INIT([Valgrind],[3.18.0],[val...@li...]) +AC_INIT([Valgrind],[3.18.1],[val...@li...]) AC_CONFIG_SRCDIR(coregrind/m_main.c) AC_CONFIG_HEADERS([config.h]) AM_INIT_AUTOMAKE([foreign dist-bzip2 subdir-objects]) diff --git a/include/valgrind.h b/include/valgrind.h index ae04c0faa7..04254df8c7 100644 --- a/include/valgrind.h +++ b/include/valgrind.h @@ -89,7 +89,7 @@ || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6)) */ #define __VALGRIND_MAJOR__ 3 -#define __VALGRIND_MINOR__ 17 +#define __VALGRIND_MINOR__ 18 #include <stdarg.h> |
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From: Mark W. <ma...@so...> - 2021-10-15 11:16:58
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The signed tag 'VALGRIND_3_18_0' was created pointing to:
048e16ea5a... -> 3.18.0 final
Tagger: Mark Wielaard <ma...@kl...>
Date: Fri Oct 15 13:15:53 2021 +0200
valgrind 3.18.0 release
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From: Mark W. <ma...@so...> - 2021-10-15 11:12:28
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=048e16ea5a6fbe97bbea80c55603ac0476bd900c commit 048e16ea5a6fbe97bbea80c55603ac0476bd900c Author: Mark Wielaard <ma...@kl...> Date: Fri Oct 15 13:00:42 2021 +0200 -> 3.18.0 final Diff: --- NEWS | 35 +++++++++++++++++++---------------- configure.ac | 2 +- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/NEWS b/NEWS index 93e8b725fc..7d2cce734e 100644 --- a/NEWS +++ b/NEWS @@ -11,18 +11,18 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * ==================== CORE CHANGES =================== -* The libiberty demangler has been updated, which brings support for Rust v0 - name demangling +* The libiberty demangler has been updated, which brings support for + Rust v0 name demangling -* __libc_freeres isn't called anymore after the program recieves a fatal - signal. Causing some internal glibc resources to hang around, but preventing - any crashes after the program has ended. +* __libc_freeres isn't called anymore after the program recieves a + fatal signal. Causing some internal glibc resources to hang around, + but preventing any crashes after the program has ended. * The DWARF reader is now very much faster at startup when just --read-inline-info=yes (the default in most cases) is given. -* glibc 2.34, which moved various functions from libpthread.so into libc.so, - is now supported. +* glibc 2.34, which moved various functions from libpthread.so into + libc.so, is now supported. * ================== PLATFORM CHANGES ================= @@ -34,9 +34,10 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * s390: - - Support the miscellaneous-instruction-extensions facility 3 and the - vector-enhancements facility 2. This enables programs compiled with - "-march=arch13" or "-march=z15" to be executed under Valgrind. + - Support the miscellaneous-instruction-extensions facility 3 and + the vector-enhancements facility 2. This enables programs + compiled with "-march=arch13" or "-march=z15" to be executed + under Valgrind. * ppc64: @@ -49,7 +50,8 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * ==================== OTHER CHANGES ==================== -* Memcheck on amd64: minor fixes to remove some false positive undef-value errors +* Memcheck on amd64: minor fixes to remove some false positive + undef-value errors * ==================== FIXED BUGS ==================== @@ -89,12 +91,12 @@ are not entered into bugzilla tend to get forgotten about or ignored. 435665 PPC ISA 3.0 copy, paste, cpabort instructions are not supported 435908 valgrind tries to fetch from deubginfod for files which already have debug information -438871 unhandled instruction bytes: 0xF3 0x49 0xF 0x6F 0x9C 0x24 0x60 0x2 0x0 0x0 +438871 unhandled instruction bytes: 0xF3 0x49 0xF 0x6F 0x9C 0x24 0x60 0x2 439046 valgrind is unusably large when linked with lld 439090 Implement close_range(2) 439326 Valgrind 3.17.0 won't compile with Intel 2021 oneAPI compilers 439590 glibc-2.34 breaks suppressions against obj:*/lib*/libc-2.*so* -440670 unhandled ppc64le-linux syscall: 252 (statfs64) and 253 (fstatfs64) +440670 unhandled ppc64le-linux syscall: 252 statfs64 and 253 fstatfs64 440906 Fix impossible constraint issue in P10 testcase. 441512 Remove a unneeded / unnecessary prefix check. 441534 Update the expected output for test_isa_3_1_VRT. @@ -105,9 +107,9 @@ are not entered into bugzilla tend to get forgotten about or ignored. 443178 Powerpc, test jm-mfspr expected output needs to be updated. 443179 Need new test for the lxvx and stxvx instructions on ISA 2.07 and ISA 3.0 systems. -443180 The subnormal test and the ISA 3.0 test generate compiler warnings. -443314 In the latest GIT version, Valgrind with "--trace-flags" crashes at - "al" register +443180 The subnormal test and the ISA 3.0 test generate compiler warnings +443314 In the latest GIT version, Valgrind with "--trace-flags" crashes + at "al" register 443605 Don't call final_tidyup (__libc_freeres) on FatalSignal To see details of a given bug, visit @@ -115,6 +117,7 @@ To see details of a given bug, visit where XXXXXX is the bug number as listed below. (3.18.0.RC1: 12 Oct 2021) +(3.18.0: 15 Oct 2021) diff --git a/configure.ac b/configure.ac index 3caebab1b8..e6e78d947c 100755 --- a/configure.ac +++ b/configure.ac @@ -8,7 +8,7 @@ ##------------------------------------------------------------## # Process this file with autoconf to produce a configure script. -AC_INIT([Valgrind],[3.18.0.RC1],[val...@li...]) +AC_INIT([Valgrind],[3.18.0],[val...@li...]) AC_CONFIG_SRCDIR(coregrind/m_main.c) AC_CONFIG_HEADERS([config.h]) AM_INIT_AUTOMAKE([foreign dist-bzip2 subdir-objects]) |
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From: Carl L. <ce...@us...> - 2021-10-13 17:11:29
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Mark:
On Wed, 2021-10-13 at 00:13 +0200, Mark Wielaard wrote:
> An RC1 tarball for 3.18.0 is now available at
>
I have tested the RC1 tarball on Power 7, Power 8 BE, Power8 LE, Power
9 and Power 10. The regression tests look fine with no new failures
from the expected failures.
Looks like the RC1 is go for Power.
I have included the specific regression test results below just for the
record.
Carl
-----------------------------------------------------------------------
Power 7
== 665 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdou\
tB failures, 0 post failures ==
memcheck/tests/bug340392 (stderr)
memcheck/tests/leak_cpp_interior (stderr)
drd/tests/std_mutex (stderr)
...checking makefile consistency
...checking header files and include directives
--------------------------------------------------------------
Power 8 BE
== 701 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 2 stdou\
tB failures, 0 post failures ==
gdbserver_tests/nlgone_abrt (stdoutB)
gdbserver_tests/nlpasssigalrm (stdoutB)
memcheck/tests/bug340392 (stderr)
memcheck/tests/leak_cpp_interior (stderr)
drd/tests/std_mutex (stderr)
...checking makefile consistency
...checking header files and include directives
make: *** [regtest] Error 1
-------------------------------------------------------------
Power 8 LE
== 661 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 1 stdou\
tB failure, 2 post failures ==
gdbserver_tests/nlcontrolc (stdoutB)
memcheck/tests/bug340392 (stderr)
memcheck/tests/leak_cpp_interior (stderr)
memcheck/tests/linux/rfcomm (stderr)
memcheck/tests/linux/sys-execveat (stderr)
massif/tests/new-cpp (post)
massif/tests/overloaded-new (post)
...checking makefile consistency
...checking header files and include directives
make: *** [Makefile:1405: regtest] Error 1
--------------------------------------------------------------
Power 9
== 665 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 1 st\
doutB failure, 2 post failures ==
gdbserver_tests/nlcontrolc (stdoutB)
memcheck/tests/bug340392 (stderr)
memcheck/tests/leak_cpp_interior (stderr)
memcheck/tests/linux/rfcomm (stderr)
memcheck/tests/linux/sys-execveat (stderr)
massif/tests/new-cpp (post)
massif/tests/overloaded-new (post)
...checking makefile consistency
...checking header files and include directives
-------------------------------------------------------------------
Power 10
== 671 tests, 3 stderr failures, 1 stdout failure, 0 stderrB failures, 2 stdoutB failure\
s, 2 post failures ==
gdbserver_tests/mcclean_after_fork (stdoutB)
gdbserver_tests/nlcontrolc (stdoutB)
memcheck/tests/bug340392 (stderr)
memcheck/tests/linux/rfcomm (stderr)
memcheck/tests/linux/sys-execveat (stderr)
memcheck/tests/ppc64/power_ISA2_05 (stdout)
massif/tests/new-cpp (post)
massif/tests/overloaded-new (post)
...checking makefile consistency
...checking header files and include directives
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From: Mark W. <ma...@so...> - 2021-10-13 15:13:57
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ecc22f252fe081200a3a123efafac0bf3aff53f3 commit ecc22f252fe081200a3a123efafac0bf3aff53f3 Author: Mark Wielaard <ma...@kl...> Date: Wed Oct 13 17:05:29 2021 +0200 coregrind: Vg_FnNameKind recognize __libc_start_call_main as below main Depending on architecture glibc has various functions that set things up to call "main". glibc 2.34 added __libc_start_call_main (at least on ppc64le and s390x). Other variants recognized are __libc_start_main, generic_start_main and variants of those names. This fixes the massif/tests/deep-D and massif/tests/mmapunmap on ppc64le. Diff: --- coregrind/m_debuginfo/debuginfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c index 2e5b9b0192..60f9ea195d 100644 --- a/coregrind/m_debuginfo/debuginfo.c +++ b/coregrind/m_debuginfo/debuginfo.c @@ -2293,6 +2293,7 @@ Vg_FnNameKind VG_(get_fnname_kind) ( const HChar* name ) } else if ( # if defined(VGO_linux) VG_STREQ("__libc_start_main", name) || // glibc glibness + VG_STREQ("__libc_start_call_main", name) || // glibc glibness VG_STREQN(18, "__libc_start_main.", name) || // gcc optimization VG_STREQ("generic_start_main", name) || // Yellow Dog doggedness VG_STREQN(19, "generic_start_main.", name) || // gcc optimization |
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From: Julian S. <se...@so...> - 2021-10-13 15:06:53
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=eb41d3be47aafe6458c9ce3e006da83d9f60b1a6 commit eb41d3be47aafe6458c9ce3e006da83d9f60b1a6 Author: Julian Seward <js...@ac...> Date: Wed Oct 13 17:06:10 2021 +0200 Very minor updates for 3.18. Diff: --- NEWS | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/NEWS b/NEWS index 7ab64c1431..93e8b725fc 100644 --- a/NEWS +++ b/NEWS @@ -1,3 +1,4 @@ + Release 3.18.0 (15 Oct 2021) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -10,18 +11,18 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * ==================== CORE CHANGES =================== - - The libiberty demangler has been updated, which brings support - for Rust v0 name demangling +* The libiberty demangler has been updated, which brings support for Rust v0 + name demangling - - __libc_freeres isn't called anymore after the program recieves - a fatal signal. Causing some internal glibc resources to hang - around, but preventing any crashes after the program has ended. +* __libc_freeres isn't called anymore after the program recieves a fatal + signal. Causing some internal glibc resources to hang around, but preventing + any crashes after the program has ended. - - The DWARF reader is now much faster at startup when just - --read-inline-info=yes (the default in most cases) is given. +* The DWARF reader is now very much faster at startup when just + --read-inline-info=yes (the default in most cases) is given. - - glibc 2.34, which moved various functions from libpthread.so - into libc.so, is now supported. +* glibc 2.34, which moved various functions from libpthread.so into libc.so, + is now supported. * ================== PLATFORM CHANGES ================= @@ -46,6 +47,10 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * Support for X86/FreeBSD and AMD64/FreeBSD has been added. +* ==================== OTHER CHANGES ==================== + +* Memcheck on amd64: minor fixes to remove some false positive undef-value errors + * ==================== FIXED BUGS ==================== The following bugs have been fixed or resolved. Note that "n-i-bz" @@ -111,6 +116,8 @@ where XXXXXX is the bug number as listed below. (3.18.0.RC1: 12 Oct 2021) + + Release 3.17.0 (19 Mar 2021) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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From: Mark W. <ma...@so...> - 2021-10-13 11:52:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d37cedc1ef3de663e4e227d962a40f44d4398179 commit d37cedc1ef3de663e4e227d962a40f44d4398179 Author: Mark Wielaard <ma...@kl...> Date: Wed Oct 13 13:49:15 2021 +0200 NEWS: add various core changes and arm64 additions Add demangler update, __libc_freeres not being called on fatal signal, DWARF reader improvements, glibc 2.34 support and various new arm64 v8.2 updates. Remove Tool Changes section, since there were no user visible changes to the tools in 3.18.0. Diff: --- NEWS | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index c294c85c3a..7ab64c1431 100644 --- a/NEWS +++ b/NEWS @@ -10,10 +10,27 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * ==================== CORE CHANGES =================== + - The libiberty demangler has been updated, which brings support + for Rust v0 name demangling + + - __libc_freeres isn't called anymore after the program recieves + a fatal signal. Causing some internal glibc resources to hang + around, but preventing any crashes after the program has ended. + + - The DWARF reader is now much faster at startup when just + --read-inline-info=yes (the default in most cases) is given. + + - glibc 2.34, which moved various functions from libpthread.so + into libc.so, is now supported. + * ================== PLATFORM CHANGES ================= * arm64: + - v8.2 scalar and vector FABD, FACGE, FACGT and FADD. + - v8.2 FP compare & conditional compare instructions. + - Zero variants of v8.2 FP compare instructions. + * s390: - Support the miscellaneous-instruction-extensions facility 3 and the @@ -29,8 +46,6 @@ AMD64/macOS 10.13 and nanoMIPS/Linux. * Support for X86/FreeBSD and AMD64/FreeBSD has been added. -* ==================== TOOL CHANGES ==================== - * ==================== FIXED BUGS ==================== The following bugs have been fixed or resolved. Note that "n-i-bz" |