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From: Mark W. <ma...@kl...> - 2022-03-23 23:28:47
|
Hi valgrind hackers, At the last valgrind dev meetup (end of November) we said we would do a new valgrind 3.19.0 release in April (6 months after 3.18.1). I propose we do that Friday April 8th. ~2 weeks from now. To coordinate the release we will have a Valgrind dev meetup through jitsi again the last Friday of March. That is this Friday, 2 weeks before the planned 3.19.0 release. The 25th of March at 1600 UTC / 1700 CET / 0900 PDT. https://meet.jit.si/ValgrindDevMeeting Cheers, Mark |
|
From: Mark W. <ma...@so...> - 2022-03-21 11:57:28
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=957339db27f7d1603a7217a0f891d91d204d64aa commit 957339db27f7d1603a7217a0f891d91d204d64aa Author: Mark Wielaard <ma...@kl...> Date: Sat Mar 19 01:06:40 2022 +0100 bpf attr->raw_tracepoint.name may be NULL for BPF_RAW_TRACEPOINT_OPEN. For BPF_RAW_TRACEPOINT_OPEN attr->raw_tracepoint.name may be NULL. Otherwise it should point to a valid (max 128 char) string. Only raw_tracepoint.prog_fd needs to be set. https://bugs.kde.org/show_bug.cgi?id=451626 Diff: --- NEWS | 1 + coregrind/m_syswrap/syswrap-linux.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 8ed4898aab..404467180e 100644 --- a/NEWS +++ b/NEWS @@ -71,6 +71,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 450025 Powerc: ACC file not implemented as a logical overlay of the VSR registers. 450536 Powerpc: valgrind throws 'facility scv unavailable exception' +451626 Syscall param bpf(attr->raw_tracepoint.name) points to unaddressable byte(s) To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index b9d531de38..38edccc983 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -12920,8 +12920,9 @@ PRE(sys_bpf) break; } /* Name is limited to 128 characters in kernel/bpf/syscall.c. */ - pre_asciiz_str(tid, attr->raw_tracepoint.name, 128, - "bpf(attr->raw_tracepoint.name)"); + if (attr->raw_tracepoint.name != NULL) + pre_asciiz_str(tid, attr->raw_tracepoint.name, 128, + "bpf(attr->raw_tracepoint.name)"); } break; case VKI_BPF_BTF_LOAD: |
|
From: Mark W. <ma...@kl...> - 2022-02-20 12:07:12
|
Hi valgrind hackers, TLDR; The Fosdem talks are online, the next valgrind 3.19.0 release is proposed for April 8th and there will be a Valgrind dev meetup the last Friday of March 25th. At the start of February we had a Virtual Valgrind Devroom at Fosdem: https://fosdem.org/2022/schedule/track/valgrind/ There are slides and videos for the talks given: - Upstreaming the FreeBSD Port, Paul Floyd https://fosdem.org/2022/schedule/event/valgrind_freebsd/ - Enable AVX-512 instructions in Valgrind, Tanya Volnina https://fosdem.org/2022/schedule/event/valgrind_avx512/ - Valgrind and debuginfo, Mark Wielaard https://fosdem.org/2022/schedule/event/valgrind_debuginfo/ - Valgrind on RISC-V, Petr Pavlu https://fosdem.org/2022/schedule/event/valgrind_riscv/ - Adding Power ISA 3.1 instruction support, Carl Love https://fosdem.org/2022/schedule/event/valgrind_isa31/ Unfortunately the last session called 20 years of Valgrind, wasn't recorded because of audio/video problems, it was just a text chat. At the last valgrind dev meetup (end of November) we said we would do a new valgrind 3.19.0 release in April (6 months after 3.18.1). I propose we do that Friday April 8th. 7 weeks from now. To coordinate the release we will have a Valgrind dev meetup through jitsi again the last Friday of March. That is 2 weeks before the planned 3.19.0 release. The 25th of March at 1600 UTC / 1700 CET / 0900 PDT. https://meet.jit.si/ValgrindDevMeeting. Cheers, Mark |
|
From: will s. <wil...@vn...> - 2022-02-19 00:01:41
|
On Fri, 2022-02-18 at 16:55 -0600, Peter Bergner wrote:
> On 2/14/22 5:13 PM, will schmidt wrote:
> > Taking a step back, I have a question here.
> > A call to
> > builtin_cpu_supports('scv') should be made before an application
> > actually uses the scv feature.
> > Should Valgrind be attempting to
> > intercept that bad call in case an app is coded in violation of
> > those
> > rules?
>
> Valgrind cannot intercept calls to __builtin_cpu_supports('scv')
> because
> it isn't really a call. The compiler will expand that builtin to a
> load
> from the HWCAP2 slot in the Thread Control Block (TCB) and a compare
> to
> see if bit PPC_FEATURE2_SCV is set. By the time Valgrind sees the
> application, that builtin is long gone.
Poor phrasing on my part. By "bad call", I mean the scv instruction
executed by the application. (which should never happen, if the
application is written on compliance with those rules).
>
> Peter
>
|
|
From: Peter B. <be...@li...> - 2022-02-18 23:27:05
|
On 2/14/22 5:13 PM, will schmidt wrote:
> Taking a step back, I have a question here.
> A call to
> builtin_cpu_supports('scv') should be made before an application
> actually uses the scv feature.
> Should Valgrind be attempting to
> intercept that bad call in case an app is coded in violation of those
> rules?
Valgrind cannot intercept calls to __builtin_cpu_supports('scv') because
it isn't really a call. The compiler will expand that builtin to a load
from the HWCAP2 slot in the Thread Control Block (TCB) and a compare to
see if bit PPC_FEATURE2_SCV is set. By the time Valgrind sees the
application, that builtin is long gone.
Peter
|
|
From: Carl L. <ca...@so...> - 2022-02-18 19:13:09
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7f11271403219d21c46e3b831cc1709336e792f1 commit 7f11271403219d21c46e3b831cc1709336e792f1 Author: Carl Love <ca...@us...> Date: Fri Feb 11 14:07:20 2022 -0600 Powerpc: Fix checking for scv support, add check to scv instruction parsing. The check for the scv instruction in coregrind/m_machine.c issues an scv instruction and uses sigill to determine if the instruction is supported. Issuing scv on systems that don't support scv, i.e. scv support is not in HWCAPS2, generates a message in dmesg "Facility 'SCV' unavailable (12), exception". This patch removes the sigill based scv instruction test from coregrind/m_machine.c. The scv support is now determined by reading the HWCAPS2 in setup_client_stack(). VG_(machine_ppc64_set_scv_support) is called to set the flag ppc_scv_supported in struct VexArchInfo. The allow_scv flag is added in disInstr_PPC_WRK. The allow_scv flag is used to ensure the host has support for scv before generating the iops for the scv instruction. Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 20 +++++++++++++----- VEX/pub/libvex.h | 2 ++ coregrind/m_initimg/initimg-linux.c | 17 +++++++-------- coregrind/m_machine.c | 42 +++++++++++++++++++++++-------------- coregrind/pub_core_machine.h | 2 ++ 6 files changed, 54 insertions(+), 30 deletions(-) diff --git a/NEWS b/NEWS index e4f2b71411..8ed4898aab 100644 --- a/NEWS +++ b/NEWS @@ -70,6 +70,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 449838 sigsegv liburing the 'impossible' happened for io_uring_setup 450025 Powerc: ACC file not implemented as a logical overlay of the VSR registers. +450536 Powerpc: valgrind throws 'facility scv unavailable exception' To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index afe66c0be5..e340562bf0 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -10755,7 +10755,8 @@ static Bool dis_trap ( UInt prefix, UInt theInstr, */ static Bool dis_syslink ( UInt prefix, UInt theInstr, - const VexAbiInfo* abiinfo, DisResult* dres ) + const VexAbiInfo* abiinfo, DisResult* dres, + Bool allow_scv, Bool sigill_diag ) { IRType ty = mode64 ? Ity_I64 : Ity_I32; @@ -10776,9 +10777,14 @@ static Bool dis_syslink ( UInt prefix, UInt theInstr, DIP("sc\n"); put_syscall_flag( mkU32(SC_FLAG) ); } else if (theInstr == 0x44000001) { - // scv - DIP("scv\n"); - put_syscall_flag( mkU32(SCV_FLAG) ); + if (allow_scv) { // scv + DIP("scv\n"); + put_syscall_flag( mkU32(SCV_FLAG) ); + } else { + if (sigill_diag) + vex_printf("The scv instruction is not supported in this environment per the HWCAPS2 capability flags.\n"); + return False; + } } else { /* Unknown instruction */ return False; @@ -35703,6 +35709,7 @@ DisResult disInstr_PPC_WRK ( Bool allow_isa_2_07 = False; Bool allow_isa_3_0 = False; Bool allow_isa_3_1 = False; + Bool allow_scv = False; Bool is_prefix; /* In ISA 3.1 the ACC is implemented on top of the vsr0 thru vsr31. @@ -35731,6 +35738,7 @@ DisResult disInstr_PPC_WRK ( allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07)); allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_0)); allow_isa_3_1 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_1)); + allow_scv = archinfo->ppc_scv_supported; } else { allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F)); allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V)); @@ -35741,6 +35749,7 @@ DisResult disInstr_PPC_WRK ( allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07)); allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0)); /* ISA 3.1 is not supported in 32-bit mode */ + /* The scv instruction is not supported in 32-bit mode */ } /* Enable writting the OV32 and CA32 bits added with ISA3.0 */ @@ -36140,7 +36149,8 @@ DisResult disInstr_PPC_WRK ( /* System Linkage Instructions */ case 0x11: // sc, scv - if (dis_syslink( prefix, theInstr, abiinfo, &dres)) + if (dis_syslink( prefix, theInstr, abiinfo, &dres, allow_scv, + sigill_diag)) goto decode_success; goto decode_failure; diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 143ec85e94..ec50d52ca9 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -362,6 +362,8 @@ typedef /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions (bug#135264) */ UInt ppc_dcbz_szB; + /* PPC32/PPC64 only: True scv is supported */ + Bool ppc_scv_supported; UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */ /* ARM64: I- and D- minimum line sizes in log2(bytes), as obtained from ctr_el0.DminLine and .IminLine. For example, a diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c index 95508ad1ed..48df8c1225 100644 --- a/coregrind/m_initimg/initimg-linux.c +++ b/coregrind/m_initimg/initimg-linux.c @@ -727,7 +727,7 @@ Addr setup_client_stack( void* init_sp, Bool auxv_2_07, hw_caps_2_07; Bool auxv_3_0, hw_caps_3_0; Bool auxv_3_1, hw_caps_3_1; - Bool auxv_scv_supported, hw_caps_scv_supported; + Bool auxv_scv_supported; /* The HWCAP2 field may contain an arch_2_07 entry that indicates * if the processor is compliant with the 2.07 ISA. (i.e. Power 8 @@ -799,17 +799,16 @@ Addr setup_client_stack( void* init_sp, ADD PUBLIC LINK WHEN AVAILABLE */ - /* Check for SCV support */ + /* Check for SCV support, Can not test scv instruction to see + if the system supports scv. Issuing an scv intruction on a + system that does not have scv in the HWCAPS results in a + message in dmsg "Facility 'SCV' unavailable (12), exception". + Will have to just use the scv setting from HWCAPS2 to determine + if the host supports scv. */ auxv_scv_supported = (auxv->u.a_val & 0x00100000ULL) == 0x00100000ULL; - hw_caps_scv_supported = - (vex_archinfo->hwcaps & VEX_HWCAPS_PPC64_SCV) - == VEX_HWCAPS_PPC64_SCV; - /* Verify the scv_supported setting in HWCAP2 matches the setting - in VEX HWCAPS. - */ - vg_assert(auxv_scv_supported == hw_caps_scv_supported); + VG_(machine_ppc64_set_scv_support)(auxv_scv_supported); /* ISA 3.1 */ auxv_3_1 = (auxv->u.a_val & 0x00040000ULL) == 0x00040000ULL; diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 7aa15133f5..052b5d186b 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1251,6 +1251,8 @@ Bool VG_(machine_get_hwcaps)( void ) // ISA 3.1 not supported on 32-bit systems + // scv instruction not supported on 32-bit systems. + /* determine dcbz/dcbzl sizes while we still have the signal * handlers registered */ find_ppc_dcbz_sz(&vai); @@ -1289,6 +1291,7 @@ Bool VG_(machine_get_hwcaps)( void ) if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA2_07; if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA3_0; /* ISA 3.1 not supported on 32-bit systems. */ + /* SCV not supported on PPC32 */ VG_(machine_get_cache_info)(&vai); @@ -1306,7 +1309,6 @@ Bool VG_(machine_get_hwcaps)( void ) volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP; volatile Bool have_isa_2_07, have_isa_3_0, have_isa_3_1; - volatile Bool have_scv_support; Int r; /* This is a kludge. Really we ought to back-convert saved_act @@ -1409,6 +1411,19 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0x7f140434":::"r20"); /* cnttzw r20,r24 */ } + /* Check if Host supports scv instruction. + Note, can not use the usual method of issuing the scv instruction and + checking if it is supported or not. Issuing scv on a system that does + not have scv support in the HWCAPS generates a message in dmesg, + "Facility 'SCV' unavailable (12), exception". It is considered bad + form to issue and scv on systems that do not support it. + + The function VG_(machine_ppc64_set_scv_support), is called in + initimg-linux.c to set the flag ppc_scv_supported based on HWCAPS2 + value. The flag ppc_scv_supported is defined struct VexArchInfo, + in file libvex.h The setting of ppc_scv_supported in VexArchInfo + is checked in disInstr_PPC_WRK() to set the allow_scv flag. */ + /* Check for ISA 3.1 support. */ have_isa_3_1 = True; if (VG_MINIMAL_SETJMP(env_unsup_insn)) { @@ -1417,18 +1432,6 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0x7f1401b6":::"r20"); /* brh r20,r24 */ } - /* Check if Host supports scv instruction */ - have_scv_support = True; - if (VG_MINIMAL_SETJMP(env_unsup_insn)) { - have_scv_support = False; - } else { - /* Set r0 to 13 for the system time call. Don't want to make a random - system call. */ - __asm__ __volatile__(".long 0x7c000278"); /* clear r0 with xor r0,r0,r0 */ - __asm__ __volatile__(".long 0x6000000d"); /* set r0 to 13 with ori r0,r0,13 */ - __asm__ __volatile__(".long 0x44000001"); /* scv 0 */ - } - /* determine dcbz/dcbzl sizes while we still have the signal * handlers registered */ find_ppc_dcbz_sz(&vai); @@ -1464,12 +1467,12 @@ Bool VG_(machine_get_hwcaps)( void ) if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA2_07; if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA3_0; if (have_isa_3_1) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA3_1; - if (have_scv_support) vai.hwcaps |= VEX_HWCAPS_PPC64_SCV; VG_(machine_get_cache_info)(&vai); - /* But we're not done yet: VG_(machine_ppc64_set_clszB) must be - called before we're ready to go. */ + /* But we're not done yet: VG_(machine_ppc64_set_clszB) and + VG_(machine_ppc64_set_scv_support) must be called before we're + ready to go. */ return True; } @@ -2262,6 +2265,13 @@ void VG_(machine_ppc64_set_clszB)( Int szB ) vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128); vai.ppc_icache_line_szB = szB; } + +void VG_(machine_ppc64_set_scv_support)( Int is_supported ) +{ + vg_assert(hwcaps_done); + vai.ppc_scv_supported = is_supported; +} + #endif diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h index 38c9ce99c4..a9b7dd8b17 100644 --- a/coregrind/pub_core_machine.h +++ b/coregrind/pub_core_machine.h @@ -221,6 +221,7 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, ------------- ppc64: initially: call VG_(machine_get_hwcaps) call VG_(machine_ppc64_set_clszB) + call VG_(machine_ppc64_set_scv_support) then safe to use VG_(machine_get_VexArchInfo) and VG_(machine_ppc64_has_VMX) @@ -255,6 +256,7 @@ extern void VG_(machine_ppc32_set_clszB)( Int ); #if defined(VGA_ppc64be) || defined(VGA_ppc64le) extern void VG_(machine_ppc64_set_clszB)( Int ); +extern void VG_(machine_ppc64_set_scv_support)( Int ); #endif #if defined(VGA_arm) |
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From: Andreas A. <ar...@so...> - 2022-02-18 18:57:05
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=03a8b24ae362f13c7f97746f72f40240aeb5aade commit 03a8b24ae362f13c7f97746f72f40240aeb5aade Author: Andreas Arnez <ar...@li...> Date: Wed Jan 5 19:49:19 2022 +0100 Bug 444552 - s390x: Fix sys_ipc semtimedop syscall On s390x Linux platforms the sys_ipc semtimedop call has four instead of five parameters, where the timeout is passed in the third instead of the fifth. Reflect this difference in the handling of VKI_SEMTIMEDOP. Diff: --- NEWS | 1 + coregrind/m_syswrap/syswrap-linux.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/NEWS b/NEWS index 3151e560ed..e4f2b71411 100644 --- a/NEWS +++ b/NEWS @@ -46,6 +46,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. == 434283 444481 gdb_server test failures on s390x 444495 dhat/tests/copy fails on s390x +444552 memcheck/tests/sem fails on s390x with glibc 2.34 444571 PPC, fix the lxsibzx and lxsihzx so they only load their respective sized data. 444836 PPC, pstq instruction for R=1 is not storing to the correct address. diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index 792589766b..b9d531de38 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -4774,10 +4774,20 @@ PRE(sys_ipc) break; } case VKI_SEMTIMEDOP: +#ifdef VGP_s390x_linux + /* On s390x Linux platforms the sys_ipc semtimedop call has four instead + of five parameters, where the timeout is passed in the third instead of + the fifth. */ + PRE_REG_READ5(int, "ipc", + vki_uint, call, int, first, int, second, long, third, + void *, ptr); + ML_(generic_PRE_sys_semtimedop)( tid, ARG2, ARG5, ARG3, ARG4 ); +#else PRE_REG_READ6(int, "ipc", vki_uint, call, int, first, int, second, int, third, void *, ptr, long, fifth); ML_(generic_PRE_sys_semtimedop)( tid, ARG2, ARG5, ARG3, ARG6 ); +#endif *flags |= SfMayBlock; break; case VKI_MSGSND: |
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From: Mark W. <ma...@so...> - 2022-02-17 23:12:58
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=536e869f1675f8fdf27675b454f84fba178b6e57 commit 536e869f1675f8fdf27675b454f84fba178b6e57 Author: Mark Wielaard <ma...@kl...> Date: Fri Feb 18 00:07:44 2022 +0100 NEWS: Add bug 445916 Demangle Rust v0 symbols with .llvm suffix Diff: --- NEWS | 1 + 1 file changed, 1 insertion(+) diff --git a/NEWS b/NEWS index 907b7c5662..3151e560ed 100644 --- a/NEWS +++ b/NEWS @@ -55,6 +55,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 445354 arm64 backend: incorrect code emitted for doubleword CAS 445415 arm64 front end: alignment checks missing for atomic instructions 445668 Inline stack frame generation is broken for Rust binaries +445916 Demangle Rust v0 symbols with .llvm suffix 446139 DRD/Helgrind with std::shared_timed_mutex::try_lock_until and try_lock_shared_until false positives 446138 DRD/Helgrind with std::timed_mutex::try_lock_until false positives 446281 Add a DRD suppression for fwrite |
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From: Mark W. <ma...@so...> - 2022-02-17 17:43:04
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e0b62fe05559003b731b4d786f3b71e9a66fb94d commit e0b62fe05559003b731b4d786f3b71e9a66fb94d Author: Mark Wielaard <ma...@kl...> Date: Thu Feb 17 18:35:38 2022 +0100 Update libiberty demangler Update the libiberty demangler using the auxprogs/update-demangler script to gcc git commit d3b2ead595467166c849950ecd3710501a5094d9. This update includes: - libiberty rust-demangle, ignore .suffix - libiberty: Fix infinite recursion in rust demangler - Update copyright years - libiberty: support digits in cpp mangled clone names - d-demangle: properly skip anonymous symbols - d-demangle: remove parenthesis where it is not needed Diff: --- auxprogs/update-demangler | 4 +-- coregrind/m_demangle/ansidecl.h | 4 +-- coregrind/m_demangle/cp-demangle.c | 7 ++-- coregrind/m_demangle/cp-demangle.h | 2 +- coregrind/m_demangle/cplus-dem.c | 2 +- coregrind/m_demangle/d-demangle.c | 28 +++++++++------ coregrind/m_demangle/demangle.h | 2 +- coregrind/m_demangle/dyn-string.c | 2 +- coregrind/m_demangle/dyn-string.h | 2 +- coregrind/m_demangle/rust-demangle.c | 70 ++++++++++++++++++++++++++++++------ coregrind/m_demangle/safe-ctype.c | 2 +- coregrind/m_demangle/safe-ctype.h | 2 +- 12 files changed, 92 insertions(+), 35 deletions(-) diff --git a/auxprogs/update-demangler b/auxprogs/update-demangler index 00c0904678..307a0ea366 100755 --- a/auxprogs/update-demangler +++ b/auxprogs/update-demangler @@ -17,8 +17,8 @@ set -e #--------------------------------------------------------------------- # You need to modify these revision numbers for your update. -old_gcc_revision=01d92cfd79872e4cffc78bf233bb9b767336beb8 # the revision of the previous update -new_gcc_revision=b3585c0836e729bed56b9afd4292177673a25ca0 # the revision for this update +old_gcc_revision=b3585c0836e729bed56b9afd4292177673a25ca0 # the revision of the previous update +new_gcc_revision=d3b2ead595467166c849950ecd3710501a5094d9 # the revision for this update # Unless the organization of demangler related files has changed, no # changes below this line should be necessary. diff --git a/coregrind/m_demangle/ansidecl.h b/coregrind/m_demangle/ansidecl.h index 2329c8655a..4275c9b9cb 100644 --- a/coregrind/m_demangle/ansidecl.h +++ b/coregrind/m_demangle/ansidecl.h @@ -1,5 +1,5 @@ -/* ANSI and traditional C compatibility macros - Copyright (C) 1991-2021 Free Software Foundation, Inc. +/* ANSI and traditional C compatability macros + Copyright (C) 1991-2022 Free Software Foundation, Inc. This file is part of the GNU C Library. This program is free software; you can redistribute it and/or modify diff --git a/coregrind/m_demangle/cp-demangle.c b/coregrind/m_demangle/cp-demangle.c index 1f4cd3d28e..ca82c330d3 100644 --- a/coregrind/m_demangle/cp-demangle.c +++ b/coregrind/m_demangle/cp-demangle.c @@ -1,5 +1,5 @@ /* Demangler for g++ V3 ABI. - Copyright (C) 2003-2021 Free Software Foundation, Inc. + Copyright (C) 2003-2022 Free Software Foundation, Inc. Written by Ian Lance Taylor <ia...@wa...>. This file is part of the libiberty library, which is part of GCC. @@ -3901,10 +3901,11 @@ d_clone_suffix (struct d_info *di, struct demangle_component *encoding) const char *pend = suffix; struct demangle_component *n; - if (*pend == '.' && (IS_LOWER (pend[1]) || pend[1] == '_')) + if (*pend == '.' && (IS_LOWER (pend[1]) || IS_DIGIT (pend[1]) + || pend[1] == '_')) { pend += 2; - while (IS_LOWER (*pend) || *pend == '_') + while (IS_LOWER (*pend) || IS_DIGIT (*pend) || *pend == '_') ++pend; } while (*pend == '.' && IS_DIGIT (pend[1])) diff --git a/coregrind/m_demangle/cp-demangle.h b/coregrind/m_demangle/cp-demangle.h index cb47bdf0d2..c6445036d6 100644 --- a/coregrind/m_demangle/cp-demangle.h +++ b/coregrind/m_demangle/cp-demangle.h @@ -1,5 +1,5 @@ /* Internal demangler interface for g++ V3 ABI. - Copyright (C) 2003-2021 Free Software Foundation, Inc. + Copyright (C) 2003-2022 Free Software Foundation, Inc. Written by Ian Lance Taylor <ia...@wa...>. This file is part of the libiberty library, which is part of GCC. diff --git a/coregrind/m_demangle/cplus-dem.c b/coregrind/m_demangle/cplus-dem.c index bf43790544..5d6e04d962 100644 --- a/coregrind/m_demangle/cplus-dem.c +++ b/coregrind/m_demangle/cplus-dem.c @@ -1,5 +1,5 @@ /* Demangler for GNU C++ - Copyright (C) 1989-2021 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. Written by James Clark (jjc@jclark.uucp) Rewritten by Fred Fish (fn...@cy...) for ARM and Lucid demangling Modified by Satish Pai (pa...@ap...) for HP demangling diff --git a/coregrind/m_demangle/d-demangle.c b/coregrind/m_demangle/d-demangle.c index 4525c48d4b..c2c3e08c8d 100644 --- a/coregrind/m_demangle/d-demangle.c +++ b/coregrind/m_demangle/d-demangle.c @@ -1,5 +1,5 @@ /* Demangler for the D programming language - Copyright (C) 2014-2021 Free Software Foundation, Inc. + Copyright (C) 2014-2022 Free Software Foundation, Inc. Written by Iain Buclaw (ib...@gd...) This file is part of the libiberty library. @@ -269,15 +269,15 @@ dlang_hexdigit (const char *mangled, char *ret) c = mangled[0]; if (!ISDIGIT (c)) - (*ret) = (c - (ISUPPER (c) ? 'A' : 'a') + 10); + *ret = c - (ISUPPER (c) ? 'A' : 'a') + 10; else - (*ret) = (c - '0'); + *ret = c - '0'; c = mangled[1]; if (!ISDIGIT (c)) - (*ret) = (*ret << 4) | (c - (ISUPPER (c) ? 'A' : 'a') + 10); + *ret = (*ret << 4) | (c - (ISUPPER (c) ? 'A' : 'a') + 10); else - (*ret) = (*ret << 4) | (c - '0'); + *ret = (*ret << 4) | (c - '0'); mangled += 2; @@ -354,7 +354,7 @@ dlang_decode_backref (const char *mangled, long *ret) static const char * dlang_backref (const char *mangled, const char **ret, struct dlang_info *info) { - (*ret) = NULL; + *ret = NULL; if (mangled == NULL || *mangled != 'Q') return NULL; @@ -372,7 +372,7 @@ dlang_backref (const char *mangled, const char **ret, struct dlang_info *info) return NULL; /* Set the position of the back reference. */ - (*ret) = qpos - refpos; + *ret = qpos - refpos; return mangled; } @@ -1666,13 +1666,19 @@ dlang_parse_qualified (string *decl, const char *mangled, size_t n = 0; do { + /* Skip over anonymous symbols. */ + if (*mangled == '0') + { + do + mangled++; + while (*mangled == '0'); + + continue; + } + if (n++) string_append (decl, "."); - /* Skip over anonymous symbols. */ - while (*mangled == '0') - mangled++; - mangled = dlang_identifier (decl, mangled, info); /* Consume the encoded arguments. However if this is not followed by the diff --git a/coregrind/m_demangle/demangle.h b/coregrind/m_demangle/demangle.h index 2acb3bd4ee..bbce948c5c 100644 --- a/coregrind/m_demangle/demangle.h +++ b/coregrind/m_demangle/demangle.h @@ -1,5 +1,5 @@ /* Defs for interface to demanglers. - Copyright (C) 1992-2021 Free Software Foundation, Inc. + Copyright (C) 1992-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License diff --git a/coregrind/m_demangle/dyn-string.c b/coregrind/m_demangle/dyn-string.c index 66948debff..89ce8e12cc 100644 --- a/coregrind/m_demangle/dyn-string.c +++ b/coregrind/m_demangle/dyn-string.c @@ -1,5 +1,5 @@ /* An abstract string datatype. - Copyright (C) 1998-2021 Free Software Foundation, Inc. + Copyright (C) 1998-2022 Free Software Foundation, Inc. Contributed by Mark Mitchell (ma...@ma...). This file is part of GNU CC. diff --git a/coregrind/m_demangle/dyn-string.h b/coregrind/m_demangle/dyn-string.h index 6c5e66012d..be2184aa93 100644 --- a/coregrind/m_demangle/dyn-string.h +++ b/coregrind/m_demangle/dyn-string.h @@ -1,5 +1,5 @@ /* An abstract string datatype. - Copyright (C) 1998-2021 Free Software Foundation, Inc. + Copyright (C) 1998-2022 Free Software Foundation, Inc. Contributed by Mark Mitchell (ma...@ma...). This file is part of GCC. diff --git a/coregrind/m_demangle/rust-demangle.c b/coregrind/m_demangle/rust-demangle.c index 0cafa3df9c..0a9331ac2e 100644 --- a/coregrind/m_demangle/rust-demangle.c +++ b/coregrind/m_demangle/rust-demangle.c @@ -1,5 +1,5 @@ /* Demangler for the Rust programming language - Copyright (C) 2016-2021 Free Software Foundation, Inc. + Copyright (C) 2016-2022 Free Software Foundation, Inc. Written by David Tolnay (dt...@gm...). Rewritten by Eduard-Mihai Burtescu (ed...@ly...) for v0 support. @@ -101,6 +101,12 @@ struct rust_demangler /* Rust mangling version, with legacy mangling being -1. */ int version; + /* Recursion depth. */ + unsigned int recursion; + /* Maximum number of times demangle_path may be called recursively. */ +#define RUST_MAX_RECURSION_COUNT 1024 +#define RUST_NO_RECURSION_LIMIT ((unsigned int) -1) + uint64_t bound_lifetime_depth; }; @@ -698,6 +704,15 @@ demangle_path (struct rust_demangler *rdm, int in_value) if (rdm->errored) return; + if (rdm->recursion != RUST_NO_RECURSION_LIMIT) + { + ++ rdm->recursion; + if (rdm->recursion > RUST_MAX_RECURSION_COUNT) + /* FIXME: There ought to be a way to report + that the recursion limit has been reached. */ + goto fail_return; + } + switch (tag = next (rdm)) { case 'C': @@ -715,10 +730,7 @@ demangle_path (struct rust_demangler *rdm, int in_value) case 'N': ns = next (rdm); if (!ISLOWER (ns) && !ISUPPER (ns)) - { - rdm->errored = 1; - return; - } + goto fail_return; demangle_path (rdm, in_value); @@ -803,9 +815,15 @@ demangle_path (struct rust_demangler *rdm, int in_value) } break; default: - rdm->errored = 1; - return; + goto fail_return; } + goto pass_return; + + fail_return: + rdm->errored = 1; + pass_return: + if (rdm->recursion != RUST_NO_RECURSION_LIMIT) + -- rdm->recursion; } static void @@ -897,6 +915,19 @@ demangle_type (struct rust_demangler *rdm) return; } + if (rdm->recursion != RUST_NO_RECURSION_LIMIT) + { + ++ rdm->recursion; + if (rdm->recursion > RUST_MAX_RECURSION_COUNT) + /* FIXME: There ought to be a way to report + that the recursion limit has been reached. */ + { + rdm->errored = 1; + -- rdm->recursion; + return; + } + } + switch (tag) { case 'R': @@ -1057,6 +1088,9 @@ demangle_type (struct rust_demangler *rdm) rdm->next--; demangle_path (rdm, 0); } + + if (rdm->recursion != RUST_NO_RECURSION_LIMIT) + -- rdm->recursion; } /* A trait in a trait object may have some "existential projections" @@ -1347,6 +1381,7 @@ rust_demangle_callback (const char *mangled, int options, rdm.skipping_printing = 0; rdm.verbose = (options & DMGL_VERBOSE) != 0; rdm.version = 0; + rdm.recursion = (options & DMGL_NO_RECURSE_LIMIT) ? RUST_NO_RECURSION_LIMIT : 0; rdm.bound_lifetime_depth = 0; /* Rust symbols always start with _R (v0) or _ZN (legacy). */ @@ -1367,13 +1402,19 @@ rust_demangle_callback (const char *mangled, int options, /* Rust symbols (v0) use only [_0-9a-zA-Z] characters. */ for (p = rdm.sym; *p; p++) { + /* Rust v0 symbols can have '.' suffixes, ignore those. */ + if (rdm.version == 0 && *p == '.') + break; + rdm.sym_len++; if (*p == '_' || ISALNUM (*p)) continue; - /* Legacy Rust symbols can also contain [.:$] characters. */ - if (rdm.version == -1 && (*p == '$' || *p == '.' || *p == ':')) + /* Legacy Rust symbols can also contain [.:$] characters. + Or @ in the .suffix (which will be skipped, see below). */ + if (rdm.version == -1 && (*p == '$' || *p == '.' || *p == ':' + || *p == '@')) continue; return 0; @@ -1382,7 +1423,16 @@ rust_demangle_callback (const char *mangled, int options, /* Legacy Rust symbols need to be handled separately. */ if (rdm.version == -1) { - /* Legacy Rust symbols always end with E. */ + /* Legacy Rust symbols always end with E. But can be followed by a + .suffix (which we want to ignore). */ + int dot_suffix = 1; + while (rdm.sym_len > 0 && + !(dot_suffix && rdm.sym[rdm.sym_len - 1] == 'E')) + { + dot_suffix = rdm.sym[rdm.sym_len - 1] == '.'; + rdm.sym_len--; + } + if (!(rdm.sym_len > 0 && rdm.sym[rdm.sym_len - 1] == 'E')) return 0; rdm.sym_len--; diff --git a/coregrind/m_demangle/safe-ctype.c b/coregrind/m_demangle/safe-ctype.c index 14da119183..97bc436675 100644 --- a/coregrind/m_demangle/safe-ctype.c +++ b/coregrind/m_demangle/safe-ctype.c @@ -1,6 +1,6 @@ /* <ctype.h> replacement macros. - Copyright (C) 2000-2021 Free Software Foundation, Inc. + Copyright (C) 2000-2022 Free Software Foundation, Inc. Contributed by Zack Weinberg <za...@st...>. This file is part of the libiberty library. diff --git a/coregrind/m_demangle/safe-ctype.h b/coregrind/m_demangle/safe-ctype.h index a7389c32e0..86157ed4b1 100644 --- a/coregrind/m_demangle/safe-ctype.h +++ b/coregrind/m_demangle/safe-ctype.h @@ -1,6 +1,6 @@ /* <ctype.h> replacement macros. - Copyright (C) 2000-2021 Free Software Foundation, Inc. + Copyright (C) 2000-2022 Free Software Foundation, Inc. Contributed by Zack Weinberg <za...@st...>. This file is part of the libiberty library. |
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From: Mark W. <ma...@so...> - 2022-02-16 22:26:47
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=df214356db9ec0555e1f022688a381cee40f68c3 commit df214356db9ec0555e1f022688a381cee40f68c3 Author: Mark Wielaard <ma...@kl...> Date: Tue Feb 8 13:12:46 2022 +0100 none/tests/amd64/avx_estimate_insn.vgtest fails on AMD processors commit ef9ac3aa0fd3ed41d74707ffe49abe9ad2797ddd "fix avx-1 amd64 test" split off the estimate instructions into their own testcase avx_estimate_insn. The commit message suggested that two .exp files would be added, one for the intel and one for the amd cases. It seems the .exp-amd variant was forgotten. This commit adds it. https://bugs.kde.org/show_bug.cgi?id=413330 Diff: --- none/tests/amd64/Makefile.am | 3 +- none/tests/amd64/avx_estimate_insn.stdout.exp-amd | 891 ++++++++++++++++++++++ 2 files changed, 893 insertions(+), 1 deletion(-) diff --git a/none/tests/amd64/Makefile.am b/none/tests/amd64/Makefile.am index 27a244a9e5..2e688e3ca7 100644 --- a/none/tests/amd64/Makefile.am +++ b/none/tests/amd64/Makefile.am @@ -27,7 +27,8 @@ EXTRA_DIST = \ aes.vgtest aes.stdout.exp aes.stderr.exp \ amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \ avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \ - avx_estimate_insn.vgtest avx_estimate_insn.stdout.exp avx_estimate_insn.stderr.exp \ + avx_estimate_insn.vgtest avx_estimate_insn.stderr.exp \ + avx_estimate_insn.stdout.exp avx_estimate_insn.stdout.exp-amd \ avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \ asorep.stderr.exp asorep.stdout.exp asorep.vgtest \ bmi.stderr.exp bmi.stdout.exp bmi.vgtest \ diff --git a/none/tests/amd64/avx_estimate_insn.stdout.exp-amd b/none/tests/amd64/avx_estimate_insn.stdout.exp-amd new file mode 100644 index 0000000000..f1e9571eb7 --- /dev/null +++ b/none/tests/amd64/avx_estimate_insn.stdout.exp-amd @@ -0,0 +1,891 @@ +VRCPSS_128(reg) + before + 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700 + b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50 + 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38 + cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5 + 56b01a12b0ca1583 + after + 0000000000000000.0000000000000000.60b160857d45c484.47b8d8c0a3208000 + b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50 + 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38 + cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5 + 56b01a12b0ca1583 +VRCPSS_128(mem) + before + 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db + 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|
From: Mark W. <ma...@so...> - 2022-02-16 22:03:44
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=29954981d84563139b1c3a77a74e906b383c8d60 commit 29954981d84563139b1c3a77a74e906b383c8d60 Author: Mark Wielaard <ma...@kl...> Date: Wed Feb 16 23:03:00 2022 +0100 Add power_ISA2_05.stdout.exp_Without_FPPO_2 to EXTRA_DIST Diff: --- memcheck/tests/ppc64/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/memcheck/tests/ppc64/Makefile.am b/memcheck/tests/ppc64/Makefile.am index 176d680f09..7d1f364703 100644 --- a/memcheck/tests/ppc64/Makefile.am +++ b/memcheck/tests/ppc64/Makefile.am @@ -5,7 +5,7 @@ dist_noinst_SCRIPTS = filter_stderr EXTRA_DIST = $(noinst_SCRIPTS) \ power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \ - power_ISA2_05.stdout.exp_Without_FPPO \ + power_ISA2_05.stdout.exp_Without_FPPO power_ISA2_05.stdout.exp_Without_FPPO_2 \ power_ISA2_07.stdout.exp power_ISA2_07.stdout.exp-LE \ power_ISA2_07.stderr.exp power_ISA2_07.vgtest |
|
From: will s. <wil...@vn...> - 2022-02-14 23:48:04
|
On Fri, 2022-02-11 at 17:02 -0800, Carl Love wrote:
> Julian:
>
> Here is the patch to remove the scv instruction testing that is
> generating the dmesg on systems that do not support scv.
>
> Per our discussion, the HWCAPS2 string is parsed to determine if the
> host supports the scv instruction. The result is recorded in the new
> VexArchInfo struct argument ppc_scv_supported.
>
> Also, the missing check for scv support has been added to the
> instruction parsing in disInstr_PPC_WRK() to ensure the host supports
> scv before generating the scv instruction Iop.
>
> The changes in the patch are all within Power specific code with the
> execption of adding ppc_scv_supported to VexArchInfo.
>
> I have done manual testing of the patch on an Power 10 system that
> supports scv and on a Power 8 system that does not support to verify
> the flag allow_scv in disInstr_PPC_WRK() is set correctly. I also
> verified that attempting to parse an scv instruction on a system that
> does not support scv prints the warning that Vagrind attempted to
> parse
> and scv instruction on a system that does not support scv and exits
> with the message "disInstr(ppc): unhandled instruction".
>
> The regression testsuite has also been run on both systems. No new
> regession failures occurred.
>
> Please let me know if the patch is OK to commit. Thanks for your
> help
> on the patch.
>
> Carl
>
> -----------------------------------------------------------
> Powerpc: Fix checking for scv support, add check to scv instruction
> parsing.
>
> The check for the scv instruction in coregrind/m_machine.c issues an
> scv
> instruction and uses sigill to determine if the instruction is
> supported.
> Issuing scv on systems that don't support scv, i.e. scv support is
> not in
> HWCAPS2, generates a message in dmesg "Facility 'SCV' unavailable
> (12),
> exception".
>
> This patch removes the sigill based scv instruction test from
> coregrind/m_machine.c. The scv support is now determined by reading
> the
> HWCAPS2 in setup_client_stack(). VG_(machine_ppc64_set_scv_support)
> is
> called to set the flag ppc_scv_supported in struct VexArchInfo.
>
> The allow_scv flag is added in disInstr_PPC_WRK. The allow_scv flag
> is
> used to ensure the host has support for scv before generating the
> iops for
> the scv instruction.
> ---
> VEX/priv/guest_ppc_toIR.c | 18 +++++++++----
> VEX/pub/libvex.h | 2 ++
> coregrind/m_initimg/initimg-linux.c | 17 ++++++------
> coregrind/m_machine.c | 42 ++++++++++++++++++---------
> --
> coregrind/pub_core_machine.h | 2 ++
> 5 files changed, 51 insertions(+), 30 deletions(-)
>
> diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
> index afe66c0be..2759a770b 100644
> --- a/VEX/priv/guest_ppc_toIR.c
> +++ b/VEX/priv/guest_ppc_toIR.c
> @@ -10755,7 +10755,8 @@ static Bool dis_trap ( UInt prefix, UInt
> theInstr,
> */
>
> static Bool dis_syslink ( UInt prefix, UInt theInstr,
> - const VexAbiInfo* abiinfo, DisResult* dres
> )
> + const VexAbiInfo* abiinfo, DisResult*
> dres,
> + Bool allow_scv )
> {
> IRType ty = mode64 ? Ity_I64 : Ity_I32;
>
> @@ -10776,9 +10777,13 @@ static Bool dis_syslink ( UInt prefix, UInt
> theInstr,
> DIP("sc\n");
> put_syscall_flag( mkU32(SC_FLAG) );
> } else if (theInstr == 0x44000001) {
> - // scv
> - DIP("scv\n");
> - put_syscall_flag( mkU32(SCV_FLAG) );
> + if (allow_scv) { // scv
> + DIP("scv\n");
> + put_syscall_flag( mkU32(SCV_FLAG) );
> + } else {
> + vex_printf("The scv instruction is not supported in
> HWCAPS2.\n");
> + return False;
> + }
Taking a step back, I have a question here.
A call to
builtin_cpu_supports('scv') should be made before an application
actually uses the scv feature.
Should Valgrind be attempting to
intercept that bad call in case an app is coded in violation of those
rules?
Thanks
-Will
|
|
From: Carl L. <ca...@so...> - 2022-02-14 17:30:40
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ac8f8e9039b8666379e1943e3b8cc25d029ff6d4 commit ac8f8e9039b8666379e1943e3b8cc25d029ff6d4 Author: Carl Love <ce...@us...> Date: Mon Feb 14 17:26:50 2022 +0000 Powerpc: Additional expected output for memcheck/tests/ppc64/power_ISA2_05 test. Latest compiler is generating slightly different effective address. Diff: --- .../ppc64/power_ISA2_05.stdout.exp_Without_FPPO_2 | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO_2 b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO_2 new file mode 100644 index 0000000000..cf496a6cf8 --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO_2 @@ -0,0 +1,119 @@ +lwarx => 0xbad0beef +ldarx => 0xbad0beef44556677 +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfiwax (-1024.000000) => FRT=(ffffffff, c4800000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1 |
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From: Carl L. <ce...@us...> - 2022-02-12 01:03:19
|
Julian:
Here is the patch to remove the scv instruction testing that is
generating the dmesg on systems that do not support scv.
Per our discussion, the HWCAPS2 string is parsed to determine if the
host supports the scv instruction. The result is recorded in the new
VexArchInfo struct argument ppc_scv_supported.
Also, the missing check for scv support has been added to the
instruction parsing in disInstr_PPC_WRK() to ensure the host supports
scv before generating the scv instruction Iop.
The changes in the patch are all within Power specific code with the
execption of adding ppc_scv_supported to VexArchInfo.
I have done manual testing of the patch on an Power 10 system that
supports scv and on a Power 8 system that does not support to verify
the flag allow_scv in disInstr_PPC_WRK() is set correctly. I also
verified that attempting to parse an scv instruction on a system that
does not support scv prints the warning that Vagrind attempted to parse
and scv instruction on a system that does not support scv and exits
with the message "disInstr(ppc): unhandled instruction".
The regression testsuite has also been run on both systems. No new
regession failures occurred.
Please let me know if the patch is OK to commit. Thanks for your help
on the patch.
Carl
-----------------------------------------------------------
Powerpc: Fix checking for scv support, add check to scv instruction parsing.
The check for the scv instruction in coregrind/m_machine.c issues an scv
instruction and uses sigill to determine if the instruction is supported.
Issuing scv on systems that don't support scv, i.e. scv support is not in
HWCAPS2, generates a message in dmesg "Facility 'SCV' unavailable (12),
exception".
This patch removes the sigill based scv instruction test from
coregrind/m_machine.c. The scv support is now determined by reading the
HWCAPS2 in setup_client_stack(). VG_(machine_ppc64_set_scv_support) is
called to set the flag ppc_scv_supported in struct VexArchInfo.
The allow_scv flag is added in disInstr_PPC_WRK. The allow_scv flag is
used to ensure the host has support for scv before generating the iops for
the scv instruction.
---
VEX/priv/guest_ppc_toIR.c | 18 +++++++++----
VEX/pub/libvex.h | 2 ++
coregrind/m_initimg/initimg-linux.c | 17 ++++++------
coregrind/m_machine.c | 42 ++++++++++++++++++-----------
coregrind/pub_core_machine.h | 2 ++
5 files changed, 51 insertions(+), 30 deletions(-)
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index afe66c0be..2759a770b 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -10755,7 +10755,8 @@ static Bool dis_trap ( UInt prefix, UInt theInstr,
*/
static Bool dis_syslink ( UInt prefix, UInt theInstr,
- const VexAbiInfo* abiinfo, DisResult* dres )
+ const VexAbiInfo* abiinfo, DisResult* dres,
+ Bool allow_scv )
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
@@ -10776,9 +10777,13 @@ static Bool dis_syslink ( UInt prefix, UInt theInstr,
DIP("sc\n");
put_syscall_flag( mkU32(SC_FLAG) );
} else if (theInstr == 0x44000001) {
- // scv
- DIP("scv\n");
- put_syscall_flag( mkU32(SCV_FLAG) );
+ if (allow_scv) { // scv
+ DIP("scv\n");
+ put_syscall_flag( mkU32(SCV_FLAG) );
+ } else {
+ vex_printf("The scv instruction is not supported in HWCAPS2.\n");
+ return False;
+ }
} else {
/* Unknown instruction */
return False;
@@ -35703,6 +35708,7 @@ DisResult disInstr_PPC_WRK (
Bool allow_isa_2_07 = False;
Bool allow_isa_3_0 = False;
Bool allow_isa_3_1 = False;
+ Bool allow_scv = False;
Bool is_prefix;
/* In ISA 3.1 the ACC is implemented on top of the vsr0 thru vsr31.
@@ -35731,6 +35737,7 @@ DisResult disInstr_PPC_WRK (
allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07));
allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_0));
allow_isa_3_1 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_1));
+ allow_scv = archinfo->ppc_scv_supported;
} else {
allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F));
allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));
@@ -35741,6 +35748,7 @@ DisResult disInstr_PPC_WRK (
allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07));
allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0));
/* ISA 3.1 is not supported in 32-bit mode */
+ /* The scv instruction is not supported in 32-bit mode */
}
/* Enable writting the OV32 and CA32 bits added with ISA3.0 */
@@ -36140,7 +36148,7 @@ DisResult disInstr_PPC_WRK (
/* System Linkage Instructions */
case 0x11: // sc, scv
- if (dis_syslink( prefix, theInstr, abiinfo, &dres))
+ if (dis_syslink( prefix, theInstr, abiinfo, &dres, allow_scv))
goto decode_success;
goto decode_failure;
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 143ec85e9..ec50d52ca 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -362,6 +362,8 @@ typedef
/* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions
(bug#135264) */
UInt ppc_dcbz_szB;
+ /* PPC32/PPC64 only: True scv is supported */
+ Bool ppc_scv_supported;
UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */
/* ARM64: I- and D- minimum line sizes in log2(bytes), as
obtained from ctr_el0.DminLine and .IminLine. For example, a
diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index 95508ad1e..48df8c122 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -727,7 +727,7 @@ Addr setup_client_stack( void* init_sp,
Bool auxv_2_07, hw_caps_2_07;
Bool auxv_3_0, hw_caps_3_0;
Bool auxv_3_1, hw_caps_3_1;
- Bool auxv_scv_supported, hw_caps_scv_supported;
+ Bool auxv_scv_supported;
/* The HWCAP2 field may contain an arch_2_07 entry that indicates
* if the processor is compliant with the 2.07 ISA. (i.e. Power 8
@@ -799,17 +799,16 @@ Addr setup_client_stack( void* init_sp,
ADD PUBLIC LINK WHEN AVAILABLE
*/
- /* Check for SCV support */
+ /* Check for SCV support, Can not test scv instruction to see
+ if the system supports scv. Issuing an scv intruction on a
+ system that does not have scv in the HWCAPS results in a
+ message in dmsg "Facility 'SCV' unavailable (12), exception".
+ Will have to just use the scv setting from HWCAPS2 to determine
+ if the host supports scv. */
auxv_scv_supported = (auxv->u.a_val & 0x00100000ULL)
== 0x00100000ULL;
- hw_caps_scv_supported =
- (vex_archinfo->hwcaps & VEX_HWCAPS_PPC64_SCV)
- == VEX_HWCAPS_PPC64_SCV;
- /* Verify the scv_supported setting in HWCAP2 matches the setting
- in VEX HWCAPS.
- */
- vg_assert(auxv_scv_supported == hw_caps_scv_supported);
+ VG_(machine_ppc64_set_scv_support)(auxv_scv_supported);
/* ISA 3.1 */
auxv_3_1 = (auxv->u.a_val & 0x00040000ULL) == 0x00040000ULL;
diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 7aa15133f..052b5d186 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -1251,6 +1251,8 @@ Bool VG_(machine_get_hwcaps)( void )
// ISA 3.1 not supported on 32-bit systems
+ // scv instruction not supported on 32-bit systems.
+
/* determine dcbz/dcbzl sizes while we still have the signal
* handlers registered */
find_ppc_dcbz_sz(&vai);
@@ -1289,6 +1291,7 @@ Bool VG_(machine_get_hwcaps)( void )
if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA2_07;
if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA3_0;
/* ISA 3.1 not supported on 32-bit systems. */
+ /* SCV not supported on PPC32 */
VG_(machine_get_cache_info)(&vai);
@@ -1306,7 +1309,6 @@ Bool VG_(machine_get_hwcaps)( void )
volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP;
volatile Bool have_isa_2_07, have_isa_3_0, have_isa_3_1;
- volatile Bool have_scv_support;
Int r;
/* This is a kludge. Really we ought to back-convert saved_act
@@ -1409,6 +1411,19 @@ Bool VG_(machine_get_hwcaps)( void )
__asm__ __volatile__(".long 0x7f140434":::"r20"); /* cnttzw r20,r24 */
}
+ /* Check if Host supports scv instruction.
+ Note, can not use the usual method of issuing the scv instruction and
+ checking if it is supported or not. Issuing scv on a system that does
+ not have scv support in the HWCAPS generates a message in dmesg,
+ "Facility 'SCV' unavailable (12), exception". It is considered bad
+ form to issue and scv on systems that do not support it.
+
+ The function VG_(machine_ppc64_set_scv_support), is called in
+ initimg-linux.c to set the flag ppc_scv_supported based on HWCAPS2
+ value. The flag ppc_scv_supported is defined struct VexArchInfo,
+ in file libvex.h The setting of ppc_scv_supported in VexArchInfo
+ is checked in disInstr_PPC_WRK() to set the allow_scv flag. */
+
/* Check for ISA 3.1 support. */
have_isa_3_1 = True;
if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
@@ -1417,18 +1432,6 @@ Bool VG_(machine_get_hwcaps)( void )
__asm__ __volatile__(".long 0x7f1401b6":::"r20"); /* brh r20,r24 */
}
- /* Check if Host supports scv instruction */
- have_scv_support = True;
- if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
- have_scv_support = False;
- } else {
- /* Set r0 to 13 for the system time call. Don't want to make a random
- system call. */
- __asm__ __volatile__(".long 0x7c000278"); /* clear r0 with xor r0,r0,r0 */
- __asm__ __volatile__(".long 0x6000000d"); /* set r0 to 13 with ori r0,r0,13 */
- __asm__ __volatile__(".long 0x44000001"); /* scv 0 */
- }
-
/* determine dcbz/dcbzl sizes while we still have the signal
* handlers registered */
find_ppc_dcbz_sz(&vai);
@@ -1464,12 +1467,12 @@ Bool VG_(machine_get_hwcaps)( void )
if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA2_07;
if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA3_0;
if (have_isa_3_1) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA3_1;
- if (have_scv_support) vai.hwcaps |= VEX_HWCAPS_PPC64_SCV;
VG_(machine_get_cache_info)(&vai);
- /* But we're not done yet: VG_(machine_ppc64_set_clszB) must be
- called before we're ready to go. */
+ /* But we're not done yet: VG_(machine_ppc64_set_clszB) and
+ VG_(machine_ppc64_set_scv_support) must be called before we're
+ ready to go. */
return True;
}
@@ -2262,6 +2265,13 @@ void VG_(machine_ppc64_set_clszB)( Int szB )
vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128);
vai.ppc_icache_line_szB = szB;
}
+
+void VG_(machine_ppc64_set_scv_support)( Int is_supported )
+{
+ vg_assert(hwcaps_done);
+ vai.ppc_scv_supported = is_supported;
+}
+
#endif
diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h
index 38c9ce99c..a9b7dd8b1 100644
--- a/coregrind/pub_core_machine.h
+++ b/coregrind/pub_core_machine.h
@@ -221,6 +221,7 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
-------------
ppc64: initially: call VG_(machine_get_hwcaps)
call VG_(machine_ppc64_set_clszB)
+ call VG_(machine_ppc64_set_scv_support)
then safe to use VG_(machine_get_VexArchInfo)
and VG_(machine_ppc64_has_VMX)
@@ -255,6 +256,7 @@ extern void VG_(machine_ppc32_set_clszB)( Int );
#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
extern void VG_(machine_ppc64_set_clszB)( Int );
+extern void VG_(machine_ppc64_set_scv_support)( Int );
#endif
#if defined(VGA_arm)
--
2.32.0
|
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From: Mark W. <ma...@so...> - 2022-02-11 17:00:31
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=13427e2ae745f9c5a665174b245d6dcebcf159d9 commit 13427e2ae745f9c5a665174b245d6dcebcf159d9 Author: Mark Wielaard <ma...@kl...> Date: Fri Feb 11 17:50:47 2022 +0100 arm64: Mismatch detected between RDMA and atomics features check_hwcaps contains code that tries to enforce Arm architecture's rules for the support of features (FEAT_) on v8.1. Specifically for v8.1 FEAT_RDM and FEAT_LSE (named FEAT_ATOMICS in Valgrind) are mandatory. But an v8.x implementation can implement any of the v8.{x+1} features, or not, as it chooses. Also under QEMU, which tends to implement features on an "as-demanded" basis, you sometimes end up with an odd combination of features, which does not strictly comply with the architecture. So ignore the "v8.x" architecture levels, and look only only at "is feature X present or not". Unless the features are really not independent. https://bugs.kde.org/show_bug.cgi?id=449494 Diff: --- VEX/priv/main_main.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 1253cf5889..482047c7aa 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -2163,11 +2163,6 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps ) if (have_fp16 != have_vfp16) invalid_hwcaps(arch, hwcaps, "Mismatch detected between scalar and vector FP16 features.\n"); - Bool have_rdm = ((hwcaps & VEX_HWCAPS_ARM64_RDM) != 0); - Bool have_atomics = ((hwcaps & VEX_HWCAPS_ARM64_ATOMICS) != 0); - if (have_rdm != have_atomics) - invalid_hwcaps(arch, hwcaps, - "Mismatch detected between RDMA and atomics features.\n"); return; } |
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From: Carl L. <ca...@so...> - 2022-02-11 16:31:00
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=193ced6bb34a49b5b41756b2c8616e392295328c commit 193ced6bb34a49b5b41756b2c8616e392295328c Author: Carl Love <ca...@us...> Date: Tue Feb 8 17:52:33 2022 -0600 Powerpc: Update ACC support to reflect being mapped over vsr registers The ISA 3.1 implemention provides the effect of ACC and VSRs logically containing the same data. Future versions of the hardware may define new state or redefine the backing state of the registers. This reworks the code to support the ACC as implemented as a logical mapping over the VSR registers, and lays groundwork for a future implementation utilizing a separate register file. There is a single boolean variable, ACC_mapped_on_VSR, that can be set in disInstr_PPC_WRK(), based on the ISA being used, to select which implementation model to use. Diff: --- NEWS | 2 + VEX/priv/guest_ppc_toIR.c | 619 +++++++++++++++---------------------------- VEX/pub/libvex_guest_ppc64.h | 7 + 3 files changed, 219 insertions(+), 409 deletions(-) diff --git a/NEWS b/NEWS index a60a07c915..907b7c5662 100644 --- a/NEWS +++ b/NEWS @@ -66,6 +66,8 @@ are not entered into bugzilla tend to get forgotten about or ignored. condition code correctly. 449672 ppc64 --track-origins=yes failures because of bad cmov addHRegUse 449838 sigsegv liburing the 'impossible' happened for io_uring_setup +450025 Powerc: ACC file not implemented as a logical overlay of the VSR + registers. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index b2ff4bfe2a..afe66c0be5 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -343,38 +343,9 @@ static Bool OV32_CA32_supported = False; #define OFFB_PPR offsetofPPCGuestState(guest_PPR) #define OFFB_PSPB offsetofPPCGuestState(guest_PSPB) #define OFFB_DSCR offsetofPPCGuestState(guest_DSCR) +/* Note the offset for the various ACC entries are calculated based on + the OFFB_ACC_0_r0 value. */ #define OFFB_ACC_0_r0 offsetofPPCGuestState(guest_ACC_0_r0) -#define OFFB_ACC_0_r1 offsetofPPCGuestState(guest_ACC_0_r1) -#define OFFB_ACC_0_r2 offsetofPPCGuestState(guest_ACC_0_r2) -#define OFFB_ACC_0_r3 offsetofPPCGuestState(guest_ACC_0_r3) -#define OFFB_ACC_1_r0 offsetofPPCGuestState(guest_ACC_1_r0) -#define OFFB_ACC_1_r1 offsetofPPCGuestState(guest_ACC_1_r1) -#define OFFB_ACC_1_r2 offsetofPPCGuestState(guest_ACC_1_r2) -#define OFFB_ACC_1_r3 offsetofPPCGuestState(guest_ACC_1_r3) -#define OFFB_ACC_2_r0 offsetofPPCGuestState(guest_ACC_2_r0) -#define OFFB_ACC_2_r1 offsetofPPCGuestState(guest_ACC_2_r1) -#define OFFB_ACC_2_r2 offsetofPPCGuestState(guest_ACC_2_r2) -#define OFFB_ACC_2_r3 offsetofPPCGuestState(guest_ACC_2_r3) -#define OFFB_ACC_3_r0 offsetofPPCGuestState(guest_ACC_3_r0) -#define OFFB_ACC_3_r1 offsetofPPCGuestState(guest_ACC_3_r1) -#define OFFB_ACC_3_r2 offsetofPPCGuestState(guest_ACC_3_r2) -#define OFFB_ACC_3_r3 offsetofPPCGuestState(guest_ACC_3_r3) -#define OFFB_ACC_4_r0 offsetofPPCGuestState(guest_ACC_4_r0) -#define OFFB_ACC_4_r1 offsetofPPCGuestState(guest_ACC_4_r1) -#define OFFB_ACC_4_r2 offsetofPPCGuestState(guest_ACC_4_r2) -#define OFFB_ACC_4_r3 offsetofPPCGuestState(guest_ACC_4_r3) -#define OFFB_ACC_5_r0 offsetofPPCGuestState(guest_ACC_5_r0) -#define OFFB_ACC_5_r1 offsetofPPCGuestState(guest_ACC_5_r1) -#define OFFB_ACC_5_r2 offsetofPPCGuestState(guest_ACC_5_r2) -#define OFFB_ACC_5_r3 offsetofPPCGuestState(guest_ACC_5_r3) -#define OFFB_ACC_6_r0 offsetofPPCGuestState(guest_ACC_6_r0) -#define OFFB_ACC_6_r1 offsetofPPCGuestState(guest_ACC_6_r1) -#define OFFB_ACC_6_r2 offsetofPPCGuestState(guest_ACC_6_r2) -#define OFFB_ACC_6_r3 offsetofPPCGuestState(guest_ACC_6_r3) -#define OFFB_ACC_7_r0 offsetofPPCGuestState(guest_ACC_7_r0) -#define OFFB_ACC_7_r1 offsetofPPCGuestState(guest_ACC_7_r1) -#define OFFB_ACC_7_r2 offsetofPPCGuestState(guest_ACC_7_r2) -#define OFFB_ACC_7_r3 offsetofPPCGuestState(guest_ACC_7_r3) #define OFFB_syscall_flag offsetofPPCGuestState(guest_syscall_flag) @@ -4084,258 +4055,42 @@ static void put_syscall_flag( IRExpr* src ) /*-----------------------------------------------------------*/ /* Helpers to access VSX Accumulator register file *-----------------------------------------------------------*/ -static void putACC( UInt index, UInt reg, IRExpr* src ) +static UInt ACC_offset( UInt index, UInt reg ) { - switch (index) { - case 0: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_0_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_0_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_0_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_0_r3, src ) ); - break; - } - break; - - case 1: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_1_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_1_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_1_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_1_r3, src ) ); - break; - } - break; - - case 2: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_2_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_2_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_2_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_2_r3, src ) ); - break; - } - break; - - case 3: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_3_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_3_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_3_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_3_r3, src ) ); - break; - } - break; +#define SizeofACC_row 16 /* size of ACC row in bytes */ +#define ACC_row_per_entry 4 +#define ACC_num_entries 8 - case 4: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_4_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_4_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_4_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_4_r3, src ) ); - break; - } - break; + vassert(index < ACC_num_entries); + vassert(reg < ACC_row_per_entry); + return index * ACC_row_per_entry * SizeofACC_row + reg * SizeofACC_row; +} - case 5: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_5_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_5_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_5_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_5_r3, src ) ); - break; - } - break; +static UInt base_acc_addr( Bool ACC_mapped_on_VSR ) +{ + /* Return base ACC address if ACC mapped over vsrs or as a separate + register file. */ + if ( ACC_mapped_on_VSR ) /* ISA 3.1 implementation */ + return offsetofPPCGuestState( guest_VSR0 ); + else + return offsetofPPCGuestState( guest_ACC_0_r0 ); +} - case 6: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_6_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_6_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_6_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_6_r3, src ) ); - break; - } - break; +static void putACC( UInt index, UInt reg, IRExpr* src, Bool ACC_mapped_on_VSR) - case 7: - switch (reg) { - case 0: - stmt( IRStmt_Put( OFFB_ACC_7_r0, src ) ); - break; - case 1: - stmt( IRStmt_Put( OFFB_ACC_7_r1, src ) ); - break; - case 2: - stmt( IRStmt_Put( OFFB_ACC_7_r2, src ) ); - break; - case 3: - stmt( IRStmt_Put( OFFB_ACC_7_r3, src ) ); - break; - } - break; - } +{ + stmt( IRStmt_Put( base_acc_addr( ACC_mapped_on_VSR ) + + ACC_offset( index, reg), src ) ); } -static IRExpr* /* :: Ity_V128 */ getACC ( UInt index, UInt reg ) +static IRExpr* /* :: Ity_V128 */ getACC ( UInt index, UInt reg, + Bool ACC_mapped_on_VSR) { vassert( (index >= 0) && (index < 8) ); vassert( (reg >= 0) && (reg < 4) ); - // vex_printf("getACC (%d, %d)) \n", index, reg); - switch (index) { - case 0: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_0_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_0_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_0_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_0_r3, Ity_V128 ); - } - break; - - case 1: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_1_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_1_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_1_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_1_r3, Ity_V128 ); - } - break; - - case 2: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_2_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_2_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_2_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_2_r3, Ity_V128 ); - } - break; - - case 3: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_3_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_3_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_3_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_3_r3, Ity_V128 ); - } - break; - - case 4: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_4_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_4_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_4_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_4_r3, Ity_V128 ); - } - break; - - case 5: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_5_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_5_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_5_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_5_r3, Ity_V128 ); - } - break; - - case 6: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_6_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_6_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_6_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_6_r3, Ity_V128 ); - } - break; - case 7: - switch (reg) { - case 0: - return IRExpr_Get( OFFB_ACC_7_r0, Ity_V128 ); - case 1: - return IRExpr_Get( OFFB_ACC_7_r1, Ity_V128 ); - case 2: - return IRExpr_Get( OFFB_ACC_7_r2, Ity_V128 ); - case 3: - return IRExpr_Get( OFFB_ACC_7_r3, Ity_V128 ); - } - break; - } - return 0; // error + return IRExpr_Get( base_acc_addr( ACC_mapped_on_VSR ) + + ACC_offset( index, reg), Ity_V128 ); } @@ -5885,7 +5640,10 @@ static IRExpr * vector_evaluate_inst ( const VexAbiInfo* vbi, return binop( Iop_64HLtoV128, mkexpr( result_hi ), mkexpr( result_lo ) ); } -static void setup_fxstate_struct( IRDirty* d, UInt AT, IREffect AT_fx ) { +static void setup_fxstate_struct( IRDirty* d, UInt AT, IREffect AT_fx, + Bool ACC_mapped_on_VSR ) { + UInt acc_base_address; + /* declare guest state effects, writing to four ACC 128-bit regs. */ d->nFxState = 4; vex_bzero(&d->fxState, sizeof(d->fxState)); @@ -5898,58 +5656,14 @@ static void setup_fxstate_struct( IRDirty* d, UInt AT, IREffect AT_fx ) { d->fxState[3].fx = AT_fx; d->fxState[3].size = sizeof(U128); - switch (AT) { - case 0: - d->fxState[0].offset = OFFB_ACC_0_r0; - d->fxState[1].offset = OFFB_ACC_0_r1; - d->fxState[2].offset = OFFB_ACC_0_r2; - d->fxState[3].offset = OFFB_ACC_0_r3; - break; - case 1: - d->fxState[0].offset = OFFB_ACC_1_r0; - d->fxState[1].offset = OFFB_ACC_1_r1; - d->fxState[2].offset = OFFB_ACC_1_r2; - d->fxState[3].offset = OFFB_ACC_1_r3; - break; - case 2: - d->fxState[0].offset = OFFB_ACC_2_r0; - d->fxState[1].offset = OFFB_ACC_2_r1; - d->fxState[2].offset = OFFB_ACC_2_r2; - d->fxState[3].offset = OFFB_ACC_2_r3; - break; - case 3: - d->fxState[0].offset = OFFB_ACC_3_r0; - d->fxState[1].offset = OFFB_ACC_3_r1; - d->fxState[2].offset = OFFB_ACC_3_r2; - d->fxState[3].offset = OFFB_ACC_3_r3; - break; - case 4: - d->fxState[0].offset = OFFB_ACC_4_r0; - d->fxState[1].offset = OFFB_ACC_4_r1; - d->fxState[2].offset = OFFB_ACC_4_r2; - d->fxState[3].offset = OFFB_ACC_4_r3; - break; - case 5: - d->fxState[0].offset = OFFB_ACC_5_r0; - d->fxState[1].offset = OFFB_ACC_5_r1; - d->fxState[2].offset = OFFB_ACC_5_r2; - d->fxState[3].offset = OFFB_ACC_5_r3; - break; - case 6: - d->fxState[0].offset = OFFB_ACC_6_r0; - d->fxState[1].offset = OFFB_ACC_6_r1; - d->fxState[2].offset = OFFB_ACC_6_r2; - d->fxState[3].offset = OFFB_ACC_6_r3; - break; - case 7: - d->fxState[0].offset = OFFB_ACC_7_r0; - d->fxState[1].offset = OFFB_ACC_7_r1; - d->fxState[2].offset = OFFB_ACC_7_r2; - d->fxState[3].offset = OFFB_ACC_7_r3; - break; - default: - vassert( (AT >= 0) && (AT < 8)); - } + vassert( (AT >= 0) && (AT < 8)); + + acc_base_address = base_acc_addr( ACC_mapped_on_VSR ); + + d->fxState[0].offset = acc_base_address + ACC_offset( AT, 0); + d->fxState[1].offset = acc_base_address + ACC_offset( AT, 1); + d->fxState[2].offset = acc_base_address + ACC_offset( AT, 2); + d->fxState[3].offset = acc_base_address + ACC_offset( AT, 3); return; } #define MATRIX_4BIT_INT_GER 1 @@ -5962,7 +5676,11 @@ static void setup_fxstate_struct( IRDirty* d, UInt AT, IREffect AT_fx ) { static void vsx_matrix_ger ( const VexAbiInfo* vbi, UInt inst_class, IRExpr *srcA, IRExpr *srcB, - UInt AT, UInt mask_inst ) { + UInt AT, UInt mask_inst, + Bool ACC_mapped_on_VSR) { + + UInt acc_base_addr = base_acc_addr( ACC_mapped_on_VSR ); + /* This helper function does the VSX Matrix 4-bit Signed Integer GER (Rank-8 Update) instructions xvi4ger8, xvi4ger8pp, pmxvi4ger8, pmxvi4ger8pp. The instructions work on four V128 values, and three @@ -5986,7 +5704,7 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, The dirty helper does not return data. */ IRExpr** args = mkIRExprVec_7( IRExpr_GSPTR(), - mkU32(offsetofPPCGuestState(guest_ACC_0_r0)), + mkU32( acc_base_addr ), mkexpr(srcA_hi), mkexpr(srcA_lo), mkexpr(srcB_hi), mkexpr(srcB_lo), mkU32( (mask_inst << 5) | AT )); @@ -6079,7 +5797,7 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, return; } - setup_fxstate_struct( d, AT, AT_fx ); + setup_fxstate_struct( d, AT, AT_fx, ACC_mapped_on_VSR ); /* execute the dirty call, side-effecting guest state */ stmt( IRStmt_Dirty(d) ); @@ -6088,7 +5806,11 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, IRExpr *srcA, IRExpr *srcA1, IRExpr *srcB, - UInt AT, UInt mask_inst ) { + UInt AT, UInt mask_inst, + Bool ACC_mapped_on_VSR ) { + + UInt acc_base_addr = base_acc_addr( ACC_mapped_on_VSR ); + /* This helper function does the VSX Matrix 64-bit floating-point GER (Rank-1 Update) instructions xvf64ger, xvf64gerpp, xvf64gerpn, xvf64gernp, xvf64gernn, pmxvf64ger, pmxvf64gerpp, pmxvf64gerpn, @@ -6125,7 +5847,7 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, IRExpr** args1 = mkIRExprVec_7( IRExpr_GSPTR(), - mkU32( offsetofPPCGuestState(guest_ACC_0_r0) ), + mkU32( acc_base_addr ), mkexpr(srcX1_hi), mkexpr(srcX1_lo), mkexpr(srcY_hi), mkexpr(srcY_lo), mkU32( combined_args )); @@ -6153,7 +5875,7 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, fnptr_to_fnentry( vbi, &vsx_matrix_64bit_float_ger_dirty_helper ), args1 ); - setup_fxstate_struct( d, AT, AT_fx ); + setup_fxstate_struct( d, AT, AT_fx, ACC_mapped_on_VSR ); /* execute the dirty call, side-effecting guest state */ stmt( IRStmt_Dirty(d) ); @@ -6163,7 +5885,7 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, IRExpr** args2 = mkIRExprVec_7( IRExpr_GSPTR(), - mkU32( offsetofPPCGuestState(guest_ACC_0_r0) ), + mkU32( acc_base_addr ), mkexpr(srcX_hi), mkexpr(srcX_lo), mkexpr(srcY_hi), mkexpr(srcY_lo), mkU32( combined_args )); @@ -6174,7 +5896,7 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, fnptr_to_fnentry( vbi, &vsx_matrix_64bit_float_ger_dirty_helper ), args2 ); - setup_fxstate_struct( d, AT, AT_fx ); + setup_fxstate_struct( d, AT, AT_fx, ACC_mapped_on_VSR ); /* execute the dirty call, side-effecting guest state */ stmt( IRStmt_Dirty(d) ); @@ -35028,7 +34750,8 @@ static Bool dis_test_LSB_by_bit ( UInt prefix, UInt theInstr ) } static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, - const VexAbiInfo* vbi ) + const VexAbiInfo* vbi, + Bool ACC_mapped_on_VSR ) { UChar opc1 = ifieldOPC(theInstr); UChar opc2 = IFIELD( theInstr, 1, 10); @@ -35051,55 +34774,64 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, DIP("xvi4ger8 %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_4BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI4GER8PP: DIP("xvi4ger8pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_4BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4: DIP("xvi8ger4 %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4PP: DIP("xvi8ger4pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4SPP: DIP("xvi8ger4spp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2S: DIP("xvi16ger2s %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2SPP: DIP("xvi16ger2pps %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2: DIP("xvi16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2PP: DIP("xvi16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), - AT, ( ( inst_prefix << 8 ) | XO ) ); + AT, ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2: @@ -35107,140 +34839,160 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2PP: DIP("xvf16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2PN: DIP("xvf16ger2pn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2NP: DIP("xvf16ger2np %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2NN: DIP("xvf16ger2nn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2: DIP("xvbf16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2PP: DIP("xvbf16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2PN: DIP("xvbf16ger2pn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2NP: DIP("xvbf16ger2np %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2NN: DIP("xvbf16ger2nn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GER: DIP("xvf32ger %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERPP: DIP("xvf32gerpp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERPN: DIP("xvf32gerpn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERNP: DIP("xvf32gernp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERNN: DIP("xvf32gernn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GER: DIP("xvf64ger %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_64bit_float_ger( vbi, getVSReg( rA_addr ), getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERPP: DIP("xvfd642gerpp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_64bit_float_ger( vbi, getVSReg( rA_addr ), getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERPN: DIP("xvf64gerpn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_64bit_float_ger( vbi, getVSReg( rA_addr ), getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERNP: DIP("xvf64gernp %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_64bit_float_ger( vbi, getVSReg( rA_addr ), getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERNN: DIP("xvf64gernn %u,r%u, r%u\n", AT, rA_addr, rB_addr); vsx_matrix_64bit_float_ger( vbi, getVSReg( rA_addr ), getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, - ( ( inst_prefix << 8 ) | XO ) ); + ( ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; default: vex_printf("ERROR, dis_vsx_accumulator_prefix, Unknown X0 = 0x%x value.\n", XO); @@ -35265,7 +35017,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_4BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO), + ACC_mapped_on_VSR ); break; case XVI4GER8PP: PMSK = IFIELD( prefix, 8, 8); @@ -35276,7 +35029,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_4BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4: PMSK = IFIELD( prefix, 12, 4); @@ -35287,7 +35041,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4PP: PMSK = IFIELD( prefix, 12, 4); @@ -35298,7 +35053,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI8GER4SPP: PMSK = IFIELD( prefix, 12, 4); @@ -35309,7 +35065,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2: PMSK = IFIELD( prefix, 12, 4); @@ -35320,7 +35077,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2PP: PMSK = IFIELD( prefix, 12, 4); @@ -35331,7 +35089,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2S: PMSK = IFIELD( prefix, 14, 2); @@ -35342,7 +35101,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVI16GER2SPP: PMSK = IFIELD( prefix, 14, 2); @@ -35353,7 +35113,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2: PMSK = IFIELD( prefix, 14, 2); @@ -35364,7 +35125,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2PP: PMSK = IFIELD( prefix, 14, 2); @@ -35375,7 +35137,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2PN: PMSK = IFIELD( prefix, 14, 2); @@ -35386,7 +35149,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2NP: PMSK = IFIELD( prefix, 14, 2); @@ -35397,7 +35161,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVBF16GER2NN: PMSK = IFIELD( prefix, 14, 2); @@ -35408,7 +35173,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2: PMSK = IFIELD( prefix, 14, 2); @@ -35419,7 +35185,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2PP: PMSK = IFIELD( prefix, 14, 2); @@ -35430,7 +35197,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2PN: PMSK = IFIELD( prefix, 14, 2); @@ -35441,7 +35209,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2NP: PMSK = IFIELD( prefix, 14, 2); @@ -35452,7 +35221,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF16GER2NN: PMSK = IFIELD( prefix, 14, 2); @@ -35463,7 +35233,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, ( (MASKS << 9 ) - | ( inst_prefix << 8 ) | XO ) ); + | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GER: PMSK = IFIELD( prefix, 14, 2); @@ -35473,7 +35244,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + ( ( MASKS << 9 ) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERPP: PMSK = IFIELD( prefix, 14, 2); @@ -35483,7 +35255,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ) ); + ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERPN: PMSK = 0; @@ -35493,7 +35266,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ) ); + ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERNP: PMSK = 0; @@ -35503,7 +35277,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ) ); + ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF32GERNN: PMSK = 0; @@ -35513,7 +35288,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, getVSReg( rA_addr ), getVSReg( rB_addr ), AT, - ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ) ); + ( ( MASKS << 9) | ( inst_prefix << 8 ) | XO ), + ACC_mapped_on_VSR ); break; case XVF64GER: PMSK = 0; @@ -35524,7 +35300,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, ( ( MASKS << 9) | ( inst_prefix << 8 ) - | XO ) ); + | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERPP: PMSK = 0; @@ -35535,7 +35312,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, ( ( MASKS << 9) | ( inst_prefix << 8 ) - | XO ) ); + | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERPN: PMSK = 0; @@ -35546,7 +35324,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, ( ( MASKS << 9) | ( inst_prefix << 8 ) - | XO ) ); + | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERNP: PMSK = 0; @@ -35557,7 +35336,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, ( ( MASKS << 9) | ( inst_prefix << 8 ) - | XO ) ); + | XO ), + ACC_mapped_on_VSR ); break; case XVF64GERNN: PMSK = 0; @@ -35568,7 +35348,8 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, getVSReg( rA_addr+1 ), getVSReg( rB_addr ), AT, ( ( MASKS << 9) | ( inst_prefix << 8 ) - | XO ) ); + | XO ), + ACC_mapped_on_VSR ); break; default: return False; @@ -35578,10 +35359,10 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, // FYI, this is not a prefix instruction DIP("xxmfacc %u\n", AT); - putVSReg( 4*AT+0, getACC( AT, 0 ) ); - putVSReg( 4*AT+1, getACC( AT, 1 ) ); - putVSReg( 4*AT+2, getACC( AT, 2 ) ); - putVSReg( 4*AT+3, getACC( AT, 3 ) ); + putVSReg( 4*AT+0, getACC( AT, 0, ACC_mapped_on_VSR ) ); + putVSReg( 4*AT+1, getACC( AT, 1, ACC_mapped_on_VSR ) ); + putVSReg( 4*AT+2, getACC( AT, 2, ACC_mapped_on_VSR ) ); + putVSReg( 4*AT+3, getACC( AT, 3, ACC_mapped_on_VSR ) ); } else if ((opc1 == 0x1F) && (opc2 == 0xB1) && (bit11_15 == 3) && !prefix) { // FYI, this is not a prefix instruction @@ -35590,19 +35371,19 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, DIP("xxsetaccz %u\n", AT); assign( zero128, binop(Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) ); - putACC( AT, 0, mkexpr( zero128 ) ); - putACC( AT, 1, mkexpr( zero128 ) ); - putACC( AT, 2, mkexpr( zero128 ) ); - putACC( AT, 3, mkexpr( zero128 ) ); + putACC( AT, 0, mkexpr( zero128 ), ACC_mapped_on_VSR ); + putACC( AT, 1, mkexpr( zero128 ), ACC_mapped_on_VSR ); + putACC( AT, 2, mkexpr( zero128 ), ACC_mapped_on_VSR ); + putACC( AT, 3, mkexpr( zero128 ), ACC_mapped_on_VSR ); } else if ((opc1 == 0x1F) && (opc2 == 0xB1) && (bit11_15 == 1) && !prefix) { // FYI, this is not a prefix instruction DIP("xxmtacc %u\n", AT); - putACC( AT, 0, getVSReg( 4*AT+0 ) ); - putACC( AT, 1, getVSReg( 4*AT+1 ) ); - putACC( AT, 2, getVSReg( 4*AT+2 ) ); - putACC( AT, 3, getVSReg( 4*AT+3 ) ); + putACC( AT, 0, getVSReg( 4*AT+0 ), ACC_mapped_on_VSR ); + putACC( AT, 1, getVSReg( 4*AT+1 ), ACC_mapped_on_VSR ); + putACC( AT, 2, getVSReg( 4*AT+2 ), ACC_mapped_on_VSR ); + putACC( AT, 3, getVSReg( 4*AT+3 ), ACC_mapped_on_VSR ); } else { vex_printf("ERROR, dis_vsx_accumulator_prefix, Unknown instruction theInstr = 0x%x\n", @@ -35924,6 +35705,21 @@ DisResult disInstr_PPC_WRK ( Bool allow_isa_3_1 = False; Bool is_prefix; + /* In ISA 3.1 the ACC is implemented on top of the vsr0 thru vsr31. + + NOTE, ISA 3.1 says in the future the ACC implentation may change. It + doesn't say how it might change but the assumption is the ACC might be + implemented as a separate register file. If/when the ACC is implemented + as a separate register file, ACC_mapped_on_VSR can be set to False, and + Valgrind will instead utilize the separate register file. 2/8/2022 + + For example, if ISA_3.2 implements the ACC as a separate register + file, there will need to be a check after the if (mode64) statement below + of the form: if (allow_isa_3_2) ACC_mapped_on_VSR = False; + to set the flag to indicate the ACC is implemented as a separate register + file. */ + Bool ACC_mapped_on_VSR = True; + /* What insn variants are we supporting today? */ if (mode64) { allow_F = True; @@ -36702,7 +36498,8 @@ DisResult disInstr_PPC_WRK ( (opc2 == XVF64GERPN) || // xvf64gerpn (opc2 == XVF64GERNP) || // xvf64gernp (opc2 == XVF64GERNN)) { // xvf64gernn - if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo ) ) + if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo, + ACC_mapped_on_VSR ) ) goto decode_success; goto decode_failure; } else { @@ -36713,7 +36510,8 @@ DisResult disInstr_PPC_WRK ( } else { // lxacc - if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo ) ) + if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo, + ACC_mapped_on_VSR ) ) goto decode_success; goto decode_failure; } @@ -36982,7 +36780,8 @@ DisResult disInstr_PPC_WRK ( case 0x3F: if ( prefix_instruction( prefix ) ) { // stxacc if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; - if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo ) ) + if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo, + ACC_mapped_on_VSR ) ) goto decode_success; goto decode_failure; } @@ -37324,7 +37123,8 @@ DisResult disInstr_PPC_WRK ( case 0x1F: if ( prefix_instruction( prefix ) ) { // stxacc if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; - if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo ) ) + if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo, + ACC_mapped_on_VSR ) ) goto decode_success; goto decode_failure; } @@ -37392,7 +37192,8 @@ DisResult disInstr_PPC_WRK ( case 0xB1: // xxmfacc, xxsetaccz { if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; - if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo ) ) + if (dis_vsx_accumulator_prefix( prefix, theInstr, abiinfo, + ACC_mapped_on_VSR ) ) goto decode_success; goto decode_failure; } diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h index 92e93cb881..c7fe874a89 100644 --- a/VEX/pub/libvex_guest_ppc64.h +++ b/VEX/pub/libvex_guest_ppc64.h @@ -292,6 +292,13 @@ typedef /* 1700 */ UInt guest_PSPB; // Problem State Priority Boost register /* 1704 */ ULong guest_DSCR; // Data Stream Control register + /* Historical note, Initial ACC support was implemented to use a separate + register file, but in practice (ISA 3.1) the hardware implementation + logically overlays over the existing VSR registers. This may change + in future hardware, so the current implementation assumes ACC and VSRs + logically contain the same data, but code remains in place to support + future implementations that may require a separate register file. + 02/08/2022. */ /* The guest_ACC_entries must be in order and sequential. The helper routines get_ACC_entry(), write_ACC_entry() calculate the offset of the ACC entry based on a address of guest_ACC_0_r0. */ |
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From: Carl L. <ca...@so...> - 2022-02-10 17:35:30
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=762dcd854a7103f29674132e5660c8bebf77d50d commit 762dcd854a7103f29674132e5660c8bebf77d50d Author: Carl Love <ce...@us...> Date: Thu Feb 10 12:01:06 2022 -0500 Powerpc: Fix typo in assembly code specification. The extra 0 results in an assebler error: Error: junk at end of line, first unrecognized character is `x' Diff: --- coregrind/m_machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 089acee649..7aa15133f5 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1246,7 +1246,7 @@ Bool VG_(machine_get_hwcaps)( void ) if (VG_MINIMAL_SETJMP(env_unsup_insn)) { have_isa_3_0 = False; } else { - __asm__ __volatile__(".long 00x7f140434":::"r20"); /* cnttzw r20,r24 */ + __asm__ __volatile__(".long 0x7f140434":::"r20"); /* cnttzw r20,r24 */ } // ISA 3.1 not supported on 32-bit systems |
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From: Julian S. <se...@so...> - 2022-02-10 04:34:39
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4908f9723100cf241f72be6ad24cdf5781041ca7 commit 4908f9723100cf241f72be6ad24cdf5781041ca7 Author: Julian Seward <js...@ac...> Date: Thu Feb 10 05:33:38 2022 +0100 Add missing \n in debug printing. No end-user functional change. Diff: --- VEX/priv/guest_amd64_toIR.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 536577b60c..f7c3d34ce7 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -20580,7 +20580,7 @@ Long dis_ESC_NONE ( if (haveF2orF3(pfx)) goto decode_failure; if (sz == 8) { putIRegRAX( 8, unop(Iop_32Sto64, getIRegRAX(4)) ); - DIP(/*"cdqe\n"*/"cltq"); + DIP(/*"cdqe\n"*/"cltq\n"); return delta; } if (sz == 4) { |
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From: Mark W. <ma...@so...> - 2022-02-09 22:41:34
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c90561e20f7df2e9c5ae30f1cdafd330b0172345 commit c90561e20f7df2e9c5ae30f1cdafd330b0172345 Author: Mark Wielaard <ma...@kl...> Date: Wed Feb 9 23:37:53 2022 +0100 Do not try to record fd name for io_uring_setup In POST(sys_io_uring_setup) we tried to use record_fd_open_with_given_name with ARG1 as name. But ARG1 isn't a char pointer. So this might crash with --track-fds=yes. Since no (file) name is associated with the fd returned by io_uring_setup use record_fd_open_nameless instead. https://bugs.kde.org/show_bug.cgi?id=449838 Diff: --- NEWS | 1 + coregrind/m_syswrap/syswrap-linux.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index 718b8aef0a..a60a07c915 100644 --- a/NEWS +++ b/NEWS @@ -65,6 +65,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 449483 Powerpc: vcmpgtsq., vcmpgtuq,, vcmpequq. instructions not setting the condition code correctly. 449672 ppc64 --track-origins=yes failures because of bad cmov addHRegUse +449838 sigsegv liburing the 'impossible' happened for io_uring_setup To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index ac2a9f0c36..792589766b 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -13206,7 +13206,7 @@ POST(sys_io_uring_setup) SET_STATUS_Failure( VKI_EMFILE ); } else { if (VG_(clo_track_fds)) - ML_(record_fd_open_with_given_name)(tid, RES, (HChar*)(Addr)ARG1); + ML_(record_fd_open_nameless)(tid, RES); POST_MEM_WRITE(ARG2 + offsetof(struct vki_io_uring_params, sq_off), sizeof(struct vki_io_sqring_offsets) + sizeof(struct vki_io_cqring_offsets)); |
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From: Andreas A. <ar...@so...> - 2022-02-08 16:56:13
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8229569cb8b1d564a97392237ebffa1d467b03ce commit 8229569cb8b1d564a97392237ebffa1d467b03ce Author: Andreas Arnez <ar...@li...> Date: Mon Jan 3 18:15:05 2022 +0100 s390: Fix VFLRX and WFLRX instructions Due to a typo in s390_irgen_VFLR, the VFLR instruction behaves incorrectly when its m3 field contains 4, meaning extended format. In that case VFLR is also written as VFLRX (or WFLRX) and supposed to round down from the extended 128-bit format to the long 64-bit format. However, the typo checks for m3 == 2 instead, so the value of 4 is unhandled, causing Valgrind to throw a specification exception. This fixes the typo. Diff: --- NEWS | 1 + VEX/priv/guest_s390_toIR.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index ff8af76566..718b8aef0a 100644 --- a/NEWS +++ b/NEWS @@ -60,6 +60,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 446281 Add a DRD suppression for fwrite 446103 Memcheck: `--track-origins=yes` causes extreme slowdowns for large mmap/munmap 446823 FreeBSD - missing syscalls when using libzm4 +447991 s390x: Valgrind indicates illegal instruction on wflrx 447995 Valgrind segfault on power10 due to hwcap checking code 449483 Powerpc: vcmpgtsq., vcmpgtuq,, vcmpequq. instructions not setting the condition code correctly. diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index fffc563d46..3ef104fcd9 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -19008,7 +19008,7 @@ s390_irgen_VFLL(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) static const HChar * s390_irgen_VFLR(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vflr", m3 == 3 || (s390_host_has_vxe && m3 == 2)); + s390_insn_assert("vflr", m3 == 3 || (s390_host_has_vxe && m3 == 4)); if (m3 == 3) s390_vector_fp_convert(Iop_F64toF32, Ity_F64, Ity_F32, True, |
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From: Mark W. <ma...@so...> - 2022-02-08 15:42:38
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fb6a77ed78876083e8ba4c2f92384db5c2e41be8 commit fb6a77ed78876083e8ba4c2f92384db5c2e41be8 Author: Mark Wielaard <ma...@kl...> Date: Tue Feb 8 16:36:08 2022 +0100 ppc64 --track-origins=yes failure because of bad cmov addHRegUse For Pin_CMov getRegUsage_PPCInstr called addHRegUse for the dst register with HRmWrite, but since this is a conditional move the register could be both read and written (read + write = modify). This matches the dst of Pin_FpCMov and Pin_AvCMov. In a very rare case, and only with --track-origins=yes, this could cause bad code generation. This is slightly amazing, this code is from 2005 and as far as I know we never seen an issue with --track-origins=yes on power before. And I have been unable to come up simple reproducer. https://bugs.kde.org/show_bug.cgi?id=449672 Diff: --- NEWS | 1 + VEX/priv/host_ppc_defs.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index ef3eef23dd..ff8af76566 100644 --- a/NEWS +++ b/NEWS @@ -63,6 +63,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 447995 Valgrind segfault on power10 due to hwcap checking code 449483 Powerpc: vcmpgtsq., vcmpgtuq,, vcmpequq. instructions not setting the condition code correctly. +449672 ppc64 --track-origins=yes failures because of bad cmov addHRegUse To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index 3ae0f6e082..4222b47868 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -2590,7 +2590,7 @@ void getRegUsage_PPCInstr ( HRegUsage* u, const PPCInstr* i, Bool mode64 ) return; case Pin_CMov: addRegUsage_PPCRI(u, i->Pin.CMov.src); - addHRegUse(u, HRmWrite, i->Pin.CMov.dst); + addHRegUse(u, HRmModify, i->Pin.CMov.dst); return; case Pin_Load: addRegUsage_PPCAMode(u, i->Pin.Load.src); |
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From: <Fah...@bm...> - 2022-02-07 07:58:43
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Hello Folks-- First time posting to this list! I have a review request for the attached patch. Relevant bug is https://bugs.kde.org/show_bug.cgi?id=449309 Any feedback will be appreciated. Best Regards BMW Car IT GmbH Faheem Sheikh Spezialist Entwicklung Lise-Meitner-Straße 14 89081 Ulm Tel.: +49-731-37804-072 Mail: fah...@bm...<mailto:vor...@bm...> Web: http://www.bmw-carit.de<http://www.bmw-carit.de/> |
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From: Carl L. <ca...@so...> - 2022-02-02 01:22:37
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ab740a1741322b6d0a02ea00499c2497e35e7022 commit ab740a1741322b6d0a02ea00499c2497e35e7022 Author: Carl Love <ce...@us...> Date: Tue Feb 1 21:22:37 2022 +0000 Powerpc test_isa_3_1_VRT fix The vcmpequq, vcmpgtsq, vcmpgtuq test cases for the dotted versions of the instructions were issuing the non-dotted instruction. This patch fixes the issues and updates the expected output. Note, the issue exposed a bug in the VEX/priv/guest_ppc_toIR.c handling of the instructions. That fix is in a separate patch. Diff: --- NEWS | 2 + none/tests/ppc64/test_isa_3_1_VRT.c | 6 +- none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 1014 +++++++++++++------------- 3 files changed, 512 insertions(+), 510 deletions(-) diff --git a/NEWS b/NEWS index d1b13c0fc8..ef3eef23dd 100644 --- a/NEWS +++ b/NEWS @@ -61,6 +61,8 @@ are not entered into bugzilla tend to get forgotten about or ignored. 446103 Memcheck: `--track-origins=yes` causes extreme slowdowns for large mmap/munmap 446823 FreeBSD - missing syscalls when using libzm4 447995 Valgrind segfault on power10 due to hwcap checking code +449483 Powerpc: vcmpgtsq., vcmpgtuq,, vcmpequq. instructions not setting the + condition code correctly. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index fb5d3d10f1..5df2360059 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -142,7 +142,7 @@ static void test_vcmpequq (void) { } static void test_dotted_vcmpequq (void) { SET_CR_ZERO; - __asm__ __volatile__ ("vcmpequq %0, %1, %2" + __asm__ __volatile__ ("vcmpequq. %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); GET_CR(current_cr); SET_CR_ZERO; } @@ -152,7 +152,7 @@ static void test_vcmpgtsq (void) { } static void test_dotted_vcmpgtsq (void) { SET_CR_ZERO; - __asm__ __volatile__ ("vcmpgtsq %0, %1, %2" + __asm__ __volatile__ ("vcmpgtsq. %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); GET_CR(current_cr); SET_CR_ZERO; } @@ -162,7 +162,7 @@ static void test_vcmpgtuq (void) { } static void test_dotted_vcmpgtuq (void) { SET_CR_ZERO; - __asm__ __volatile__ ("vcmpgtuq %0, %1, %2" + __asm__ __volatile__ ("vcmpgtuq. %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); GET_CR(current_cr); SET_CR_ZERO; } diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 8f04ee2cbb..fd98883ba9 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -20,515 +20,515 @@ dctfixqq 900000000001 * 10^6111 => 7fffffffffffffff,ffffffffffffffff dctfixqq 9999999999999999999999999999999999 * 10^6111 => 7fffffffffffffff,ffffffffffffffff dctfixqq 1 * 10^-6176 => 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpequq. 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 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ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff8000007f800000,ff7ffffe7f7ffffe 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ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e 0000000000000009,ffff000180000001 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e ffff000180000001,0000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e 0000000000000000,8000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 0000111e8000222e,7ff0000000000000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 2208400000000000,0000000000000009 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 0000000000000009,ffff000180000001 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 ffff000180000001,0000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 0000111e8000222e,7ff0000000000000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff -vcmpgtsq. 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff0000000000000 ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 -vcmpgtsq. 7ff0000000000000,fff00000000... [truncated message content] |
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From: Carl L. <ca...@so...> - 2022-02-02 01:22:34
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=27fc72dfb185733fed3dfd974ad2e7c5476852f6 commit 27fc72dfb185733fed3dfd974ad2e7c5476852f6 Author: Carl Love <ce...@us...> Date: Tue Feb 1 21:29:30 2022 +0000 Fix setting condition code for Vector Compare quad word instructions. The vcmpgtsq., vcmpgtuq,, vcmpequq. instructions set the condition code field 6 to 0b1000 for true, 0b0010 for false. The condition code was being set according to the typical condition code values for equal and greater than which is incorrect for these instructions. The patch fixes the setting of the condition code as specified in the instructions. Diff: --- VEX/priv/guest_ppc_toIR.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 543fa95743..b2ff4bfe2a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -29155,9 +29155,15 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) assign ( eq, Quad_precision_int_eq( vA, vB ) ); - assign( cc, binop( Iop_Shl32, - unop( Iop_1Uto32, mkexpr( eq ) ), - mkU8( 1 ) ) ); + /* if true cc = 0b0100, if flase cc= 0b0010 */ + assign( cc, binop( Iop_Or32, + binop( Iop_Shl32, + unop( Iop_1Uto32, mkexpr( eq ) ), + mkU8( 3 ) ), + binop( Iop_Shl32, + unop( Iop_1Uto32, + unop( Iop_Not1, mkexpr( eq ) ) ), + mkU8( 1 ) ) ) ); if (Rc) putGST_field( PPC_GST_CR, mkexpr( cc ), cc_field ); @@ -29190,10 +29196,15 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) assign ( gt, Quad_precision_sint_gt( vA, vB ) ); } - assign( cc, binop( Iop_Shl32, - unop( Iop_1Uto32, mkexpr( gt ) ), - mkU8( 2 ) ) ); - + /* if true cc = 0b0100, if flase cc= 0b0010 */ + assign( cc, binop( Iop_Or32, + binop( Iop_Shl32, + unop( Iop_1Uto32, mkexpr( gt ) ), + mkU8( 3 ) ), + binop( Iop_Shl32, + unop( Iop_1Uto32, + unop( Iop_Not1, mkexpr( gt ) ) ), + mkU8( 1 ) ) ) ); if (Rc) putGST_field( PPC_GST_CR, mkexpr( cc ), cc_field ); putVReg( vT_addr, binop( Iop_64HLtoV128, |
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From: Mark W. <ma...@kl...> - 2022-01-30 22:09:57
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Hi valgrind hackers, Next Sunday, February 6, Valgrind will participate in the Virtual Fosdem. https://fosdem.org/2022/schedule/track/valgrind/ 14:20-15:15 Upstreaming the FreeBSD Port, Paul Floyd 15:20-15:45 Enable AVX-512 instructions in Valgrind, Tanya Volnina 15:50-16:25 Valgrind and debuginfo, Mark Wielaard 16:30-16:55 Valgrind on RISC-V, Petr Pavlu 17:00-17:25 Adding Power ISA 3.1 instruction support, Carl Love 17:30-18:00 20 years of Valgrind, Celebration, Julian Seward All times are as if the the conference was in Brussels (CET/UTC+1) The last session, 20 years of Valgrind, Celebration, will not be a presentation, but an oppertunity for everybody to share their experiences with Valgrind these last 20 years and to discuss ideas for the next 20 years. Participation is free to anybody and registration is optional. But you might want to read the pratical information beforehand: https://fosdem.org/2022/practical/online/ See you next Sunday, Mark |