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From: Paul F. <pa...@so...> - 2023-08-24 19:39:36
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=dc6669cee7b557945fd41417bf531c7f5c9f1093 commit dc6669cee7b557945fd41417bf531c7f5c9f1093 Author: Paul Floyd <pj...@wa...> Date: Thu Aug 24 21:38:46 2023 +0200 Solaris: update cxx17_aligned_new expected Diff: --- .../tests/cxx17_aligned_new.stderr.exp-solaris | 34 ++++++++++++---------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/memcheck/tests/cxx17_aligned_new.stderr.exp-solaris b/memcheck/tests/cxx17_aligned_new.stderr.exp-solaris index 54659a4dba..275620856e 100644 --- a/memcheck/tests/cxx17_aligned_new.stderr.exp-solaris +++ b/memcheck/tests/cxx17_aligned_new.stderr.exp-solaris @@ -1,23 +1,27 @@ -_ZnwmSt11align_val_t(size 64, al 64) = 0x........ +_ZnwjSt11align_val_t(size 64, al 64) = 0x........ _ZdlPvSt11align_val_t(0x........) -_ZnamSt11align_val_t(size 320, al 64) = 0x........ +_ZnajSt11align_val_t(size 320, al 64) = 0x........ _ZdaPvSt11align_val_t(0x........) -_ZnwmSt11align_val_t(size 64, al 64) = 0x........ -_ZdlPvmSt11align_val_t(0x........) -_ZnamSt11align_val_t(size 320, al 64) = 0x........ -_ZdaPvmSt11align_val_t(0x........) -_ZnwmSt11align_val_tRKSt9nothrow_t(size 64, al 64) = 0x........ -_ZdlPvSt11align_val_tRKSt9nothrow_t(0x........) -_ZnamSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ -_ZdaPvSt11align_val_tRKSt9nothrow_t(0x........) -_Znwm(4) = 0x........ +_ZnwjSt11align_val_t(size 64, al 64) = 0x........ +_ZdlPvjSt11align_val_t(0x........) +_ZnajSt11align_val_t(size 320, al 64) = 0x........ +_ZdaPvjSt11align_val_t(0x........) +_ZnwjSt11align_val_t(size 64, al 64) = 0x........ _ZdlPvSt11align_val_t(0x........) -_ZnwmRKSt9nothrow_t(4) = 0x........ -_ZdlPvm(0x........) -_Znam(20) = 0x........ +_ZnajSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ +_ZdaPvSt11align_val_t(0x........) +_ZnwjSt11align_val_t(size 64, al 64) = 0x........ +_ZdlPvjSt11align_val_t(0x........) +_ZnajSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ +_ZdaPvjSt11align_val_t(0x........) +_Znwj(4) = 0x........ +_ZdlPvSt11align_val_t(0x........) +_ZnwjRKSt9nothrow_t(4) = 0x........ +_ZdlPv(0x........) +_Znaj(20) = 0x........ _ZdaPv(0x........) -_ZnamRKSt9nothrow_t(20) = 0x........ +_ZnajRKSt9nothrow_t(20) = 0x........ _ZdaPv(0x........) HEAP SUMMARY: |
|
From: Paul F. <pa...@so...> - 2023-08-24 19:07:42
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ae53295e6a400b5f434ff1047d39c56114747818 commit ae53295e6a400b5f434ff1047d39c56114747818 Author: Paul Floyd <pj...@wa...> Date: Thu Aug 24 21:06:23 2023 +0200 regtest: fix wrong interfaces in calls to operator delete Will update Solaris later Diff: --- memcheck/tests/cxx17_aligned_new.cpp | 11 ++++++++--- memcheck/tests/cxx17_aligned_new.stderr.exp | 8 ++++++-- memcheck/tests/cxx17_aligned_new.stderr.exp_32 | 20 ++++++++++++-------- 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/memcheck/tests/cxx17_aligned_new.cpp b/memcheck/tests/cxx17_aligned_new.cpp index 6f574d066f..1a7ac3c299 100644 --- a/memcheck/tests/cxx17_aligned_new.cpp +++ b/memcheck/tests/cxx17_aligned_new.cpp @@ -28,10 +28,16 @@ int main() { operator delete [](myClass5, 320U, std::align_val_t(64U)); MyClass* myClassNt = new (std::nothrow) MyClass; - operator delete(myClassNt, std::align_val_t(64U), std::nothrow); + operator delete(myClassNt, std::align_val_t(64U)); MyClass* myClass5Nt = new (std::nothrow) MyClass[5]; - operator delete [](myClass5Nt, std::align_val_t(64U), std::nothrow); + operator delete [](myClass5Nt, std::align_val_t(64U)); + + myClassNt = new (std::nothrow) MyClass; + operator delete(myClassNt, sizeof(MyClass), std::align_val_t(64U)); + + myClass5Nt = new (std::nothrow) MyClass[5]; + operator delete [](myClass5Nt, sizeof(MyClass)*5, std::align_val_t(64U)); OrdinaryClass* oClass = new OrdinaryClass; // this is a limitation, VG does not use enough bits @@ -48,4 +54,3 @@ int main() { oClass = new (std::nothrow) OrdinaryClass[5]; delete [] oClass; } - diff --git a/memcheck/tests/cxx17_aligned_new.stderr.exp b/memcheck/tests/cxx17_aligned_new.stderr.exp index 1c08b82f90..cf52836c69 100644 --- a/memcheck/tests/cxx17_aligned_new.stderr.exp +++ b/memcheck/tests/cxx17_aligned_new.stderr.exp @@ -8,9 +8,13 @@ _ZdlPvmSt11align_val_t(0x........) _ZnamSt11align_val_t(size 320, al 64) = 0x........ _ZdaPvmSt11align_val_t(0x........) _ZnwmSt11align_val_tRKSt9nothrow_t(size 64, al 64) = 0x........ -_ZdlPvSt11align_val_tRKSt9nothrow_t(0x........) +_ZdlPvSt11align_val_t(0x........) +_ZnamSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ +_ZdaPvSt11align_val_t(0x........) +_ZnwmSt11align_val_tRKSt9nothrow_t(size 64, al 64) = 0x........ +_ZdlPvmSt11align_val_t(0x........) _ZnamSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ -_ZdaPvSt11align_val_tRKSt9nothrow_t(0x........) +_ZdaPvmSt11align_val_t(0x........) _Znwm(4) = 0x........ _ZdlPvSt11align_val_t(0x........) _ZnwmRKSt9nothrow_t(4) = 0x........ diff --git a/memcheck/tests/cxx17_aligned_new.stderr.exp_32 b/memcheck/tests/cxx17_aligned_new.stderr.exp_32 index e6d6db40a4..d40deebe81 100644 --- a/memcheck/tests/cxx17_aligned_new.stderr.exp_32 +++ b/memcheck/tests/cxx17_aligned_new.stderr.exp_32 @@ -1,16 +1,20 @@ -_ZnwjSt11align_val_t(size 64, al 64) = 0x........ +_Znwj(64) = 0x........ _ZdlPvSt11align_val_t(0x........) -_ZnajSt11align_val_t(size 320, al 64) = 0x........ +_Znaj(320) = 0x........ _ZdaPvSt11align_val_t(0x........) -_ZnwjSt11align_val_t(size 64, al 64) = 0x........ +_Znwj(64) = 0x........ _ZdlPvjSt11align_val_t(0x........) -_ZnajSt11align_val_t(size 320, al 64) = 0x........ +_Znaj(320) = 0x........ +_ZdaPvjSt11align_val_t(0x........) +_ZnwjRKSt9nothrow_t(64) = 0x........ +_ZdlPvSt11align_val_t(0x........) +_ZnajRKSt9nothrow_t(320) = 0x........ +_ZdaPvSt11align_val_t(0x........) +_ZnwjRKSt9nothrow_t(64) = 0x........ +_ZdlPvjSt11align_val_t(0x........) +_ZnajRKSt9nothrow_t(320) = 0x........ _ZdaPvjSt11align_val_t(0x........) -_ZnwjSt11align_val_tRKSt9nothrow_t(size 64, al 64) = 0x........ -_ZdlPvSt11align_val_tRKSt9nothrow_t(0x........) -_ZnajSt11align_val_tRKSt9nothrow_t(size 320, al 64) = 0x........ -_ZdaPvSt11align_val_tRKSt9nothrow_t(0x........) _Znwj(4) = 0x........ _ZdlPvSt11align_val_t(0x........) _ZnwjRKSt9nothrow_t(4) = 0x........ |
|
From: Nicholas N. <nj...@so...> - 2023-08-23 06:45:56
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bc2f62950ccb12f79072b7eacc9ec43ec244496a commit bc2f62950ccb12f79072b7eacc9ec43ec244496a Author: Nicholas Nethercote <n.n...@gm...> Date: Wed Aug 23 16:45:23 2023 +1000 Fix an error in `docs/README`. Diff: --- docs/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/README b/docs/README index bae567c908..ea4c0af398 100644 --- a/docs/README +++ b/docs/README @@ -24,7 +24,7 @@ Stylesheets, catalogs, parsing/formatting scripts: Some files of note: docs/xml/index.xml: Top-level book-set wrapper docs/xml/FAQ.xml: The FAQ - docs/valgrind-manpage.xml The valgrind manpage + docs/xml/valgrind-manpage.xml The valgrind manpage docs/xml/vg-entities.xml: Various strings, dates etc. used all over docs/xml/xml_help.txt: Basic guide to common XML tags. |
|
From: Nicholas N. <nj...@so...> - 2023-08-23 06:20:41
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e7bfa5a8e9f450fe1391a16359651157f46bb736 commit e7bfa5a8e9f450fe1391a16359651157f46bb736 Author: Nicholas Nethercote <n.n...@gm...> Date: Thu Aug 10 14:19:36 2023 +1000 Update Cachegrind description in the usage message and header comments. This matches an earlier change to the description in the user manual. And fix indentation of the license in a couple of files. Diff: --- cachegrind/cg_annotate.in | 4 ++-- cachegrind/cg_arch.c | 4 ++-- cachegrind/cg_arch.h | 4 ++-- cachegrind/cg_branchpred.c | 4 ++-- cachegrind/cg_diff.in | 30 +++++++++++++++--------------- cachegrind/cg_main.c | 6 +++--- cachegrind/cg_merge.in | 30 +++++++++++++++--------------- cachegrind/cg_sim.c | 4 ++-- cachegrind/tests/filter_stderr | 2 +- 9 files changed, 44 insertions(+), 44 deletions(-) diff --git a/cachegrind/cg_annotate.in b/cachegrind/cg_annotate.in index c76a760be0..4d9d3e32cd 100755 --- a/cachegrind/cg_annotate.in +++ b/cachegrind/cg_annotate.in @@ -5,8 +5,8 @@ # --- Cachegrind's annotator. cg_annotate.in --- # -------------------------------------------------------------------- -# This file is part of Cachegrind, a Valgrind tool for cache -# profiling programs. +# This file is part of Cachegrind, a high-precision tracing profiler +# built with Valgrind. # # Copyright (C) 2002-2023 Nicholas Nethercote # nj...@va... diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c index 52e8982184..6ff2247e84 100644 --- a/cachegrind/cg_arch.c +++ b/cachegrind/cg_arch.c @@ -3,8 +3,8 @@ /*--------------------------------------------------------------------*/ /* - This file is part of Cachegrind, a Valgrind tool for cache - profiling programs. + This file is part of Cachegrind, a high-precision tracing profiler + built with Valgrind. Copyright (C) 2011-2017 Nicholas Nethercote nj...@va... diff --git a/cachegrind/cg_arch.h b/cachegrind/cg_arch.h index add18e13da..5bb56b082b 100644 --- a/cachegrind/cg_arch.h +++ b/cachegrind/cg_arch.h @@ -4,8 +4,8 @@ /*--------------------------------------------------------------------*/ /* - This file is part of Cachegrind, a Valgrind tool for cache - profiling programs. + This file is part of Cachegrind, a high-precision tracing profiler + built with Valgrind. Copyright (C) 2002-2017 Nicholas Nethercote nj...@va... diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c index ba433ec2ce..927b7bf21c 100644 --- a/cachegrind/cg_branchpred.c +++ b/cachegrind/cg_branchpred.c @@ -4,8 +4,8 @@ /*--------------------------------------------------------------------*/ /* - This file is part of Cachegrind, a Valgrind tool for cache - profiling programs. + This file is part of Cachegrind, a high-precision tracing profiler + built with Valgrind. Copyright (C) 2002-2017 Nicholas Nethercote nj...@va... diff --git a/cachegrind/cg_diff.in b/cachegrind/cg_diff.in index d3a63189ea..e193e99d78 100755 --- a/cachegrind/cg_diff.in +++ b/cachegrind/cg_diff.in @@ -5,26 +5,26 @@ # --- Cachegrind's differencer. cg_diff.in --- # -------------------------------------------------------------------- -# This file is part of Cachegrind, a Valgrind tool for cache -# profiling programs. +# This file is part of Cachegrind, a high-precision tracing profiler +# built with Valgrind. # -# Copyright (C) 2002-2023 Nicholas Nethercote -# nj...@va... +# Copyright (C) 2002-2023 Nicholas Nethercote +# nj...@va... # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of the -# License, or (at your option) any later version. +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of the +# License, or (at your option) any later version. # -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. # -# You should have received a copy of the GNU General Public License -# along with this program; if not, see <http://www.gnu.org/licenses/>. +# You should have received a copy of the GNU General Public License +# along with this program; if not, see <http://www.gnu.org/licenses/>. # -# The GNU General Public License is contained in the file COPYING. +# The GNU General Public License is contained in the file COPYING. # This script diffs Cachegrind output files. # diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c index 8cdbbe9b3f..d8e476adcb 100644 --- a/cachegrind/cg_main.c +++ b/cachegrind/cg_main.c @@ -5,8 +5,8 @@ /*--------------------------------------------------------------------*/ /* - This file is part of Cachegrind, a Valgrind tool for cache - profiling programs. + This file is part of Cachegrind, a high-precision tracing profiler + built with Valgrind. Copyright (C) 2002-2017 Nicholas Nethercote nj...@va... @@ -1786,7 +1786,7 @@ static void cg_pre_clo_init(void) { VG_(details_name) ("Cachegrind"); VG_(details_version) (NULL); - VG_(details_description) ("a cache and branch-prediction profiler"); + VG_(details_description) ("a high-precision tracing profiler"); VG_(details_copyright_author)( "Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); diff --git a/cachegrind/cg_merge.in b/cachegrind/cg_merge.in index 7c385b4c8e..1201114ded 100755 --- a/cachegrind/cg_merge.in +++ b/cachegrind/cg_merge.in @@ -5,26 +5,26 @@ # --- Cachegrind's merger. cg_merge.in --- # -------------------------------------------------------------------- -# This file is part of Cachegrind, a Valgrind tool for cache -# profiling programs. +# This file is part of Cachegrind, a high-precision tracing profiler +# built with Valgrind. # -# Copyright (C) 2002-2023 Nicholas Nethercote -# nj...@va... +# Copyright (C) 2002-2023 Nicholas Nethercote +# nj...@va... # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of the -# License, or (at your option) any later version. +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of the +# License, or (at your option) any later version. # -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. # -# You should have received a copy of the GNU General Public License -# along with this program; if not, see <http://www.gnu.org/licenses/>. +# You should have received a copy of the GNU General Public License +# along with this program; if not, see <http://www.gnu.org/licenses/>. # -# The GNU General Public License is contained in the file COPYING. +# The GNU General Public License is contained in the file COPYING. # This script merges Cachegrind output files. # diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c index c8f0a8fc26..c2ea3791b9 100644 --- a/cachegrind/cg_sim.c +++ b/cachegrind/cg_sim.c @@ -4,8 +4,8 @@ /*--------------------------------------------------------------------*/ /* - This file is part of Cachegrind, a Valgrind tool for cache - profiling programs. + This file is part of Cachegrind, a high-precision tracing profiler + built with Valgrind. Copyright (C) 2002-2017 Nicholas Nethercote nj...@va... diff --git a/cachegrind/tests/filter_stderr b/cachegrind/tests/filter_stderr index a0ae89968b..703d807b64 100755 --- a/cachegrind/tests/filter_stderr +++ b/cachegrind/tests/filter_stderr @@ -5,7 +5,7 @@ dir=`dirname $0` $dir/../../tests/filter_stderr_basic | # Remove "Cachegrind, ..." line and the following copyright line. -sed "/^Cachegrind, a cache and branch-prediction profiler/ , /./ d" | +sed "/^Cachegrind, a high-precision tracing profiler/ , /./ d" | # Remove numbers from I/D/LL "refs:" lines perl -p -e 's/((I|D|LL) *refs:)[ 0-9,()+rdw]*$/\1/' | |
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From: Nicholas N. <nj...@so...> - 2023-08-23 04:21:13
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fd3719c1edb7aad30cae8c6fb8c64aa9b2833378 commit fd3719c1edb7aad30cae8c6fb8c64aa9b2833378 Author: Nicholas Nethercote <n.n...@gm...> Date: Wed Aug 23 14:20:42 2023 +1000 Correct an error in Cachegrind's usage message. Diff: --- cachegrind/cg_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c index ef3ea03ebc..8cdbbe9b3f 100644 --- a/cachegrind/cg_main.c +++ b/cachegrind/cg_main.c @@ -1763,7 +1763,7 @@ static void cg_print_usage(void) { VG_(printf)( " --cachegrind-out-file=<file> output file name [cachegrind.out.%%p]\n" -" --cache-sim=yes|no collect cache stats? [yes]\n" +" --cache-sim=yes|no collect cache stats? [no]\n" " --branch-sim=yes|no collect branch prediction stats? [no]\n" ); VG_(print_cache_clo_opts)(); |
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From: Paul F. <pa...@so...> - 2023-08-22 19:35:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bdd5f0bad19eb9544511a9c40241901d34f16781 commit bdd5f0bad19eb9544511a9c40241901d34f16781 Author: Paul Floyd <pj...@wa...> Date: Tue Aug 22 21:35:00 2023 +0200 Bug 473604 - Fix bug472219.c compile failure with Clang 16 Diff: --- NEWS | 1 + memcheck/tests/bug472219.c | 1 + 2 files changed, 2 insertions(+) diff --git a/NEWS b/NEWS index e3e3b21d5e..2ce35472dd 100644 --- a/NEWS +++ b/NEWS @@ -50,6 +50,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 471807 Add support for lazy reading and downloading of DWARF debuginfo 472219 Syscall param ppoll(ufds.events) points to uninitialised byte(s) 472963 Broken regular expression in configure.ac +473604 Fix bug472219.c compile failure with Clang 16 To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/memcheck/tests/bug472219.c b/memcheck/tests/bug472219.c index 88567caa2c..cb9fefe4cb 100644 --- a/memcheck/tests/bug472219.c +++ b/memcheck/tests/bug472219.c @@ -1,3 +1,4 @@ +#define _GNU_SOURCE /* for ppoll */ #include <poll.h> #include <stdlib.h> #include "../../config.h" |
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From: Paul F. <pa...@so...> - 2023-08-22 19:24:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bec7089812614ce9e0ab3a53da82ba7972e64251 commit bec7089812614ce9e0ab3a53da82ba7972e64251 Author: Paul Floyd <pj...@wa...> Date: Tue Aug 22 21:23:00 2023 +0200 Add bug 426751 to NEWS Diff: --- NEWS | 1 + 1 file changed, 1 insertion(+) diff --git a/NEWS b/NEWS index ee0dc582fe..e3e3b21d5e 100644 --- a/NEWS +++ b/NEWS @@ -33,6 +33,7 @@ bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather than mailing the developers (or mailing lists) directly -- bugs that are not entered into bugzilla tend to get forgotten about or ignored. +426751 Valgrind reports «still reachable» memory using musl (alpine running inside docker) 460192 Add epoll_pwait2 469049 link failure on ppc64 (big endian) valgrind 3.20 469146 massif --ignore-fn does not ignore inlined functions |
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From: Floyd, P. <pj...@wa...> - 2023-08-22 13:58:40
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On 22/08/2023 15:16, Mark Wielaard wrote: > Hi Feiyang, > > On Fri, 2023-08-04 at 11:22 +0800, Feiyang Chen wrote: >> I want to inquire about the status of my patch. As of now, I haven't >> received any feedback or response regarding its review or potential >> inclusion in the upcoming release. I understand that everyone in the >> team is busy with their respective tasks, but I am eager to know if >> there are any plans to consider my contribution for integration. > Sorry review is taking so long. I think it is fair to say nobody really > made time for this. And we promise a new release in October. It seems > LoonArch64 is making good progress overall. I saw it is a Debian port > now:https://lwn.net/Articles/941743/ > And the GCC Compile Farm now has two machines for testing: > https://cfarm.tetaneutral.net/news/37 > > There are a couple of larger features that could use more people to > take a look: > > - AVX-512 support, incomplete and we lost contact with the original > developer:https://bugs.kde.org/show_bug.cgi?id=383010 > - Risc-V port, seems to have a dedicated developers: > https://bugs.kde.org/show_bug.cgi?id=468575 > There also is active development to extend it with > Vector Register support > https://sourceforge.net/p/valgrind/mailman/valgrind-developers/thread/20230526135944.1959407-5-fei2.wu%40intel.com/ > - Loongarch64 port, seems pretty complete, split out in 40 commits: > https://bugs.kde.org/show_bug.cgi?id=457504 > > Unfortunately I cannot promise to have time before October to look at > all of these. So if others could take a look and report on status that > would be great. Hi Mark Do we have any contacts at Intel (or AMD) for help with AVX512? My wishlist for the October release of 3.22 includes all of the above plus * get at least one dev each for RISC-V and Loongson on board with sourceware git write access in order to be able to support the platforms directly * the long running question of what to do with macOS * memcheck aligned and sized checks plus maybe c23 free_sized and free_sized_aligned plus Linux aligned_alloc * detect whether a debug version of libstdc++ is being used and then use that to automatically turn on or off mismatch detection And I expect the usual steady stream of smaller fixes. A+ Paul |
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From: Mark W. <ma...@kl...> - 2023-08-22 13:16:59
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Hi Feiyang, On Fri, 2023-08-04 at 11:22 +0800, Feiyang Chen wrote: > I want to inquire about the status of my patch. As of now, I haven't > received any feedback or response regarding its review or potential > inclusion in the upcoming release. I understand that everyone in the > team is busy with their respective tasks, but I am eager to know if > there are any plans to consider my contribution for integration. Sorry review is taking so long. I think it is fair to say nobody really made time for this. And we promise a new release in October. It seems LoonArch64 is making good progress overall. I saw it is a Debian port now: https://lwn.net/Articles/941743/ And the GCC Compile Farm now has two machines for testing: https://cfarm.tetaneutral.net/news/37 There are a couple of larger features that could use more people to take a look: - AVX-512 support, incomplete and we lost contact with the original developer: https://bugs.kde.org/show_bug.cgi?id=383010 - Risc-V port, seems to have a dedicated developers: https://bugs.kde.org/show_bug.cgi?id=468575 There also is active development to extend it with Vector Register support https://sourceforge.net/p/valgrind/mailman/valgrind-developers/thread/20230526135944.1959407-5-fei2.wu%40intel.com/ - Loongarch64 port, seems pretty complete, split out in 40 commits: https://bugs.kde.org/show_bug.cgi?id=457504 Unfortunately I cannot promise to have time before October to look at all of these. So if others could take a look and report on status that would be great. Cheers, Mark |
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From: Mark W. <ma...@so...> - 2023-08-21 15:29:45
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b35a8ed5a9575dbadb7e2a84bd4b6c4ab9eda21a commit b35a8ed5a9575dbadb7e2a84bd4b6c4ab9eda21a Author: Mark Wielaard <ma...@kl...> Date: Thu Aug 17 15:40:30 2023 +0200 gdb --multi mode stdout redirecting to stderr When in stdio mode (talking to gdb through stdin/stdout, not through a socket), redirect stdout to stderr and close stdin for the inferior. That way at least some output can be seen, but there will be no input. This is workaround till we have real terminal handling. * coregrind/vgdb.c (main): Pass in_port to do_multi_mode. (do_multi_mode): Pass in_port to fork_and_exec_valgrind. (fork_and_exec_valgrind): Close stdin, redirect stdout to stderr if in_port <= 0. https://bugs.kde.org/show_bug.cgi?id=471311 Diff: --- NEWS | 1 + coregrind/vgdb.c | 20 +++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/NEWS b/NEWS index 56f4701e00..ee0dc582fe 100644 --- a/NEWS +++ b/NEWS @@ -45,6 +45,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. Assertion 'resolved' failed 470830 Don't print actions vgdb me ... continue for vgdb --multi mode 470978 s390x: Valgrind cannot start qemu-kvm when "sysctl vm.allocate_pgste=0" +471311 gdb --multi mode stdout redirecting to stderr 471807 Add support for lazy reading and downloading of DWARF debuginfo 472219 Syscall param ppoll(ufds.events) points to uninitialised byte(s) 472963 Broken regular expression in configure.ac diff --git a/coregrind/vgdb.c b/coregrind/vgdb.c index 56a969de78..c024ffca6b 100644 --- a/coregrind/vgdb.c +++ b/coregrind/vgdb.c @@ -1159,7 +1159,7 @@ static void gdb_relay(int pid, int send_noack_mode, char *q_buf); or the errno from the child on failure. */ static int fork_and_exec_valgrind (int argc, char **argv, const char *working_dir, - pid_t *pid) + int in_port, pid_t *pid) { int err = 0; // We will use a pipe to track what the child does, @@ -1243,6 +1243,19 @@ int fork_and_exec_valgrind (int argc, char **argv, const char *working_dir, } } + /* When in stdio mode (talking to gdb through stdin/stdout, not + through a socket), redirect stdout to stderr and close stdin + for the inferior. That way at least some output can be seen, + but there will be no input. */ + if (in_port <= 0) { + /* close stdin */ + close (0); + /* open /dev/null as new stdin */ + open ("/dev/null", O_RDONLY); + /* redirect stdout as stderr */ + dup2 (2, 1); + } + /* Try to launch valgrind. Add --vgdb-error=0 to stop immediately so we can attach and --launched-with-multi to let valgrind know it doesn't need to show a banner how to connect to gdb, we will do that @@ -1309,7 +1322,7 @@ int fork_and_exec_valgrind (int argc, char **argv, const char *working_dir, /* Do multi stuff. */ static -void do_multi_mode(int check_trials) +void do_multi_mode(int check_trials, int in_port) { char *buf = vmalloc(PBUFSIZ+1); char *q_buf = vmalloc(PBUFSIZ+1); //save the qSupported packet sent by gdb @@ -1459,6 +1472,7 @@ void do_multi_mode(int check_trials) int res = fork_and_exec_valgrind (count, decoded_string, working_dir, + in_port, &valgrind_pid); if (res == 0) { @@ -2427,7 +2441,7 @@ int main(int argc, char** argv) if (multi_mode) { /* check_trails is the --wait argument in seconds, defaulting to 1 * if not given. */ - do_multi_mode (check_trials); + do_multi_mode (check_trials, in_port); } else if (last_command >= 0) { standalone_send_commands(pid, last_command, commands); } else { |
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From: Wu, F. <fe...@in...> - 2023-08-21 08:59:13
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On 5/26/2023 10:08 PM, Wu, Fei wrote: > On 5/26/2023 9:59 PM, Fei Wu wrote: >> I'm from Intel RISC-V team and working on a RISC-V International >> development partner project to add RISC-V vector (RVV) support on >> Valgrind, the target tool is memcheck. My work bases on commit >> 71272b252977 of Petr's riscv64-linux branch, many thanks to Petr for his >> great work first. >> https://github.com/petrpavlu/valgrind-riscv64 >> A vector IR version has been added into this repo (branch poc-rvv): https://github.com/intel/valgrind-rvv/commits/poc-rvv A bunch of RVV instructions have been enabled, and I plan to enable more instructions to run some general benchmarks, coremark is the first one. This version solves the vector register group at the backend w/o a new register allocation algorithm, instead of using helper functions at the backend, this also enables the fast prototype by leveraging the code from QEMU, so this prototype does borrow a lot of QEMU code right now. But it's just an intermediate step, finally we will replace the QEMU code with intrinsics or generate the binary encoding directly to avoid the helper functions for performance. The framework itself is generic enough and don't need change during the transition. Thanks, Fei. >> This RFC is a starting point of RVV support on Valgrind, It's far from >> complete, which will take huge time, but I do think it's more effective >> to have some real code for discussion, so this series adds the RVV >> support to run memcpy/strcmp/strcpy/strlen/strncpy in: >> https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/examples >> > In case the intrinsic version is built with extra RVV instructions which > are not supported yet, here is an assembly version. All C code is from > the above link with a small tweak, and the asm code is copied from: > https://github.com/riscv/riscv-v-spec/tree/master/example > > diff --git a/rvv-examples/Makefile b/rvv-examples/Makefile > new file mode 100644 > index 000000000..dfae4ac31 > --- /dev/null > +++ b/rvv-examples/Makefile > @@ -0,0 +1,23 @@ > +CC := clang > +CFLAGS := -g -march=rv64gcv -mllvm -riscv-v-vector-bits-min=128 -O2 > +ASFLAGS := -g -march=rv64gcv -mllvm -riscv-v-vector-bits-min=128 -O2 > + > +BINARY = rvv_strcmp rvv_memcpy rvv_strcpy rvv_strlen rvv_strncpy > + > +.PHONY: all clean test > + > +all: $(BINARY) > + > +clean: > + rm -f $(BINARY) > + > +test: $(BINARY) > + for t in $(BINARY); do \ > + valgrind ./$$t; \ > + done > + > +rvv_strcmp: rvv_strcmp.c strcmp.s > +rvv_memcpy: rvv_memcpy.c memcpy.s > +rvv_strcpy: rvv_strcpy.c strcpy.s > +rvv_strlen: rvv_strlen.c strlen.s > +rvv_strncpy: rvv_strncpy.c strncpy.s > diff --git a/rvv-examples/common.h b/rvv-examples/common.h > new file mode 100644 > index 000000000..cec96ed2b > --- /dev/null > +++ b/rvv-examples/common.h > @@ -0,0 +1,112 @@ > +// common.h > +// common utilites for the test code under exmaples/ > + > +#include <math.h> > +#include <stdbool.h> > +#include <stddef.h> > +#include <stdint.h> > +#include <stdio.h> > +#include <stdlib.h> > + > +extern void *memcpy_vec(void *dst, void *src, size_t n); > +extern int strcmp_vec(const char *src1, const char *src2); > +extern char *strcpy_vec(char *dst, const char *src); > +extern size_t strlen_vec(char *src); > +extern char *strncpy_vec(char *dst, char *src, size_t count); > + > +void gen_rand_1d(double *a, int n) { > + for (int i = 0; i < n; ++i) > + a[i] = (double)rand() / (double)RAND_MAX + (double)(rand() % 1000); > +} > + > +void gen_string(char *s, int n) { > + // char value range: -128 ~ 127 > + for (int i = 0; i < n - 1; ++i) > + s[i] = (char)(rand() % 127) + 1; > + s[n - 1] = '\0'; > +} > + > +void gen_rand_2d(double **ar, int n, int m) { > + for (int i = 0; i < n; ++i) > + for (int j = 0; j < m; ++j) > + ar[i][j] = (double)rand() / (double)RAND_MAX + (double)(rand() % > 1000); > +} > + > +void print_string(const char *a, const char *name) { > + printf("const char *%s = \"", name); > + int i = 0; > + while (a[i] != 0) > + putchar(a[i++]); > + printf("\"\n"); > + puts(""); > +} > + > +void print_array_1d(double *a, int n, const char *type, const char *name) { > + printf("%s %s[%d] = {\n", type, name, n); > + for (int i = 0; i < n; ++i) { > + printf("%06.2f%s", a[i], i != n - 1 ? "," : "};\n"); > + if (i % 10 == 9) > + puts(""); > + } > + puts(""); > +} > + > +void print_array_2d(double **a, int n, int m, const char *type, > + const char *name) { > + printf("%s %s[%d][%d] = {\n", type, name, n, m); > + for (int i = 0; i < n; ++i) { > + for (int j = 0; j < m; ++j) { > + printf("%06.2f", a[i][j]); > + if (j == m - 1) > + puts(i == n - 1 ? "};" : ","); > + else > + putchar(','); > + } > + } > + puts(""); > +} > + > +bool double_eq(double golden, double actual, double relErr) { > + return (fabs(actual - golden) < relErr); > +} > + > +bool compare_1d(double *golden, double *actual, int n) { > + for (int i = 0; i < n; ++i) > + if (!double_eq(golden[i], actual[i], 1e-6)) > + return false; > + return true; > +} > + > +bool compare_string(const char *golden, const char *actual, int n) { > + for (int i = 0; i < n; ++i) > + if (golden[i] != actual[i]) > + return false; > + return true; > +} > + > +bool compare_2d(double **golden, double **actual, int n, int m) { > + for (int i = 0; i < n; ++i) > + for (int j = 0; j < m; ++j) > + if (!double_eq(golden[i][j], actual[i][j], 1e-6)) > + return false; > + return true; > +} > + > +double **alloc_array_2d(int n, int m) { > + double **ret; > + ret = (double **)malloc(sizeof(double *) * n); > + for (int i = 0; i < n; ++i) > + ret[i] = (double *)malloc(sizeof(double) * m); > + return ret; > +} > + > +void init_array_one_1d(double *ar, int n) { > + for (int i = 0; i < n; ++i) > + ar[i] = 1; > +} > + > +void init_array_one_2d(double **ar, int n, int m) { > + for (int i = 0; i < n; ++i) > + for (int j = 0; j < m; ++j) > + ar[i][j] = 1; > +} > diff --git a/rvv-examples/memcpy.s b/rvv-examples/memcpy.s > new file mode 100644 > index 000000000..1b50ab670 > --- /dev/null > +++ b/rvv-examples/memcpy.s > @@ -0,0 +1,17 @@ > + .text > + .balign 4 > + .global memcpy_vec > + # void *memcpy_vec(void* dest, const void* src, size_t n) > + # a0=dest, a1=src, a2=n > + # > + memcpy_vec: > + mv a3, a0 # Copy destination > + loop: > + vsetvli t0, a2, e8, m8, ta, ma # Vectors of 8b > + vle8.v v0, (a1) # Load bytes > + add a1, a1, t0 # Bump pointer > + sub a2, a2, t0 # Decrement count > + vse8.v v0, (a3) # Store bytes > + add a3, a3, t0 # Bump pointer > + bnez a2, loop # Any more? > + ret # Return > diff --git a/rvv-examples/rvv_memcpy.c b/rvv-examples/rvv_memcpy.c > new file mode 100644 > index 000000000..d78b9b604 > --- /dev/null > +++ b/rvv-examples/rvv_memcpy.c > @@ -0,0 +1,21 @@ > +#include "common.h" > +#include <riscv_vector.h> > +#include <string.h> > + > +int main() { > + const int N = 127; > + const uint32_t seed = 0xdeadbeef; > + srand(seed); > + > + // data gen > + double A[N]; > + gen_rand_1d(A, N); > + > + // compute > + double golden[N], actual[N]; > + memcpy(golden, A, sizeof(A)); > + memcpy_vec(actual, A, sizeof(A)); > + > + // compare > + puts(compare_1d(golden, actual, N) ? "pass" : "fail"); > +} > diff --git a/rvv-examples/rvv_strcmp.c b/rvv-examples/rvv_strcmp.c > new file mode 100644 > index 000000000..d10cac133 > --- /dev/null > +++ b/rvv-examples/rvv_strcmp.c > @@ -0,0 +1,25 @@ > +#include "common.h" > +#include <riscv_vector.h> > +#include <string.h> > + > +int main() { > + const int N = 1023; > + const uint32_t seed = 0xdeadbeef; > + srand(seed); > + > + // data gen > + char s0[N], s1[N]; > + gen_string(s0, N); > + gen_string(s1, N); > + > + // compute > + int golden, actual; > + golden = strcmp(s0, s1); > + actual = strcmp_vec(s0, s1); > + > + golden = (golden == 0) ? 0 : (golden > 0) ? 1 : -1; > + actual = (golden == 0) ? 0 : (golden > 0) ? 1 : -1; > + > + // compare > + puts(golden == actual ? "pass" : "fail"); > +} > diff --git a/rvv-examples/rvv_strcpy.c b/rvv-examples/rvv_strcpy.c > new file mode 100644 > index 000000000..7e5af8673 > --- /dev/null > +++ b/rvv-examples/rvv_strcpy.c > @@ -0,0 +1,22 @@ > +#include "common.h" > +#include <assert.h> > +#include <riscv_vector.h> > +#include <string.h> > + > +int main() { > + const int N = 2000; > + const uint32_t seed = 0xdeadbeef; > + srand(seed); > + > + // data gen > + char s0[N]; > + gen_string(s0, N); > + > + // compute > + char golden[N], actual[N]; > + strcpy(golden, s0); > + strcpy_vec(actual, s0); > + > + // compare > + puts(strcmp(golden, actual) == 0 ? "pass" : "fail"); > +} > diff --git a/rvv-examples/rvv_strlen.c b/rvv-examples/rvv_strlen.c > new file mode 100644 > index 000000000..e1142f883 > --- /dev/null > +++ b/rvv-examples/rvv_strlen.c > @@ -0,0 +1,22 @@ > +#include "common.h" > +#include <riscv_vector.h> > +#include <string.h> > + > +int main() { > + const uint32_t seed = 0xdeadbeef; > + srand(seed); > + > + int N = rand() % 2000; > + > + // data gen > + char s0[N]; > + gen_string(s0, N); > + > + // compute > + size_t golden, actual; > + golden = strlen(s0); > + actual = strlen_vec(s0); > + > + // compare > + puts(golden == actual ? "pass" : "fail"); > +} > diff --git a/rvv-examples/rvv_strncpy.c b/rvv-examples/rvv_strncpy.c > new file mode 100644 > index 000000000..f1d14ac52 > --- /dev/null > +++ b/rvv-examples/rvv_strncpy.c > @@ -0,0 +1,25 @@ > +#include "common.h" > +#include <riscv_vector.h> > +#include <string.h> > + > +int main() { > + const int N = 1320; > + const uint32_t seed = 0xdeadbeef; > + srand(seed); > + > + // data gen > + char s0[N]; > + gen_string(s0, N); > + char s1[] = "the quick brown fox jumps over the lazy dog"; > + size_t count = strlen(s1) + rand() % 500; > + > + // compute > + char golden[N], actual[N]; > + strcpy(golden, s0); > + strcpy(actual, s0); > + strncpy(golden, s1, count); > + strncpy_vec(actual, s1, count); > + > + // compare > + puts(compare_string(golden, actual, N) ? "pass" : "fail"); > +} > diff --git a/rvv-examples/strcmp.s b/rvv-examples/strcmp.s > new file mode 100644 > index 000000000..85d32c96d > --- /dev/null > +++ b/rvv-examples/strcmp.s > @@ -0,0 +1,34 @@ > + .text > + .balign 4 > + .global strcmp_vec > + # int strcmp_vec(const char *src1, const char* src2) > +strcmp_vec: > + ## Using LMUL=2, but same register names work for larger LMULs > + li t1, 0 # Initial pointer bump > +loop: > + vsetvli t0, x0, e8, m2, ta, ma # Max length vectors of bytes > + add a0, a0, t1 # Bump src1 pointer > + vle8ff.v v8, (a0) # Get src1 bytes > + add a1, a1, t1 # Bump src2 pointer > + vle8ff.v v16, (a1) # Get src2 bytes > + > + vmseq.vi v0, v8, 0 # Flag zero bytes in src1 > + vmsne.vv v1, v8, v16 # Flag if src1 != src2 > + vmor.mm v0, v0, v1 # Combine exit conditions > + > + vfirst.m a2, v0 # ==0 or != ? > + csrr t1, vl # Get number of bytes fetched > + > + bltz a2, loop # Loop if all same and no zero byte > + > + add a0, a0, a2 # Get src1 element address > + lbu a3, (a0) # Get src1 byte from memory > + > + add a1, a1, a2 # Get src2 element address > + lbu a4, (a1) # Get src2 byte from memory > + > + sub a0, a3, a4 # Return value. > + > + ret > + > + > diff --git a/rvv-examples/strcpy.s b/rvv-examples/strcpy.s > new file mode 100644 > index 000000000..292df25ac > --- /dev/null > +++ b/rvv-examples/strcpy.s > @@ -0,0 +1,20 @@ > + .text > + .balign 4 > + .global strcpy_vec > + # char* strcpy_vec(char *dst, const char* src) > +strcpy_vec: > + mv a2, a0 # Copy dst > + li t0, -1 # Infinite AVL > +loop: > + vsetvli x0, t0, e8, m8, ta, ma # Max length vectors of bytes > + vle8ff.v v8, (a1) # Get src bytes > + csrr t1, vl # Get number of bytes fetched > + vmseq.vi v1, v8, 0 # Flag zero bytes > + vfirst.m a3, v1 # Zero found? > + add a1, a1, t1 # Bump pointer > + vmsif.m v0, v1 # Set mask up to and including zero byte. > + vse8.v v8, (a2), v0.t # Write out bytes > + add a2, a2, t1 # Bump pointer > + bltz a3, loop # Zero byte not found, so loop > + > + ret > diff --git a/rvv-examples/strlen.s b/rvv-examples/strlen.s > new file mode 100644 > index 000000000..721c0257e > --- /dev/null > +++ b/rvv-examples/strlen.s > @@ -0,0 +1,22 @@ > + .text > + .balign 4 > + .global strlen_vec > +# size_t strlen_vec(const char *str) > +# a0 holds *str > + > +strlen_vec: > + mv a3, a0 # Save start > +loop: > + vsetvli a1, x0, e8, m8, ta, ma # Vector of bytes of maximum length > + vle8ff.v v8, (a3) # Load bytes > + csrr a1, vl # Get bytes read > + vmseq.vi v0, v8, 0 # Set v0[i] where v8[i] = 0 > + vfirst.m a2, v0 # Find first set bit > + add a3, a3, a1 # Bump pointer > + bltz a2, loop # Not found? > + > + add a0, a0, a1 # Sum start + bump > + add a3, a3, a2 # Add index > + sub a0, a3, a0 # Subtract start address+bump > + > + ret > diff --git a/rvv-examples/strncpy.s b/rvv-examples/strncpy.s > new file mode 100644 > index 000000000..f7114c5ca > --- /dev/null > +++ b/rvv-examples/strncpy.s > @@ -0,0 +1,36 @@ > + .text > + .balign 4 > + .global strncpy_vec > + # char* strncpy_vec(char *dst, const char* src, size_t n) > +strncpy_vec: > + mv a3, a0 # Copy dst > +loop: > + vsetvli x0, a2, e8, m8, ta, ma # Vectors of bytes. > + vle8ff.v v8, (a1) # Get src bytes > + vmseq.vi v1, v8, 0 # Flag zero bytes > + csrr t1, vl # Get number of bytes fetched > + vfirst.m a4, v1 # Zero found? > + vmsbf.m v0, v1 # Set mask up to before zero byte. > + vse8.v v8, (a3), v0.t # Write out non-zero bytes > + bgez a4, zero_tail # Zero remaining bytes. > + sub a2, a2, t1 # Decrement count. > + add a3, a3, t1 # Bump dest pointer > + add a1, a1, t1 # Bump src pointer > + bnez a2, loop # Anymore? > + > + ret > + > +zero_tail: > + sub a2, a2, a4 # Subtract count on non-zero bytes. > + add a3, a3, a4 # Advance past non-zero bytes. > + vsetvli t1, a2, e8, m8, ta, ma # Vectors of bytes. > + vmv.v.i v0, 0 # Splat zero. > + > +zero_loop: > + vse8.v v0, (a3) # Store zero. > + sub a2, a2, t1 # Decrement count. > + add a3, a3, t1 # Bump pointer > + vsetvli t1, a2, e8, m8, ta, ma # Vectors of bytes. > + bnez a2, zero_loop # Anymore? > + > + ret > > Thanks, > Fei. > >> The whole idea is splitting the vector instructions into scalar >> instructions which have already been well supported on Petr's branch, >> the correctness of binary translation (tool=none) is simple to ensure, >> but the logic of tool=memcheck should not be broken, one of the keys is >> to deal with the instructions with mask: >> >> * for load/store with mask, LoadG/StoreG are enabled, the same semantics >> as other architectures >> >> * for other instructions such as vadd, if the vector mask agnostic (vma) >> is set to undisturbed, the masked original value is read first then >> write back, the V bit won't change even after write back, it's not >> necessary to have another guard type like LoadG/StoreG. >> >> Pros >> ---- >> * by leveraging the existing scalar instructions support on Valgrind, >> usually adding a new instruction involves only the frontend in >> guest_riscv64_toIR, other parts are rare touched, so effort is much >> reduced to enable new instructions. >> >> * As the backend only sees the scalar IRs and generates scalar >> instructions, it's possible to run valgrind ./vec-test on non-RVV host. >> >> Cons >> ---- >> * as this method splits RVV instruction at frontend, there is less >> chance to optimize at other stages, e.g. the vbits tracking. >> >> * with larger vlen such as 1K, at most 1 RVV instruction will split into >> 1K ops, besides the performance penalty, it causes pressure to other >> components such as tmp space too. Some of this can be relieved by >> grouping multiple elements together. >> >> >> There are some alternatives, but none seems perfect: >> * helper function. It's much easier to make tool=none work, but how good >> is it to handle the V+A tracking and other tools? Generally speaking, it >> should not be a general solution for too many instructions. >> >> * define and pass the RVV IR to backend, instead of splitting it too >> early. This introduces much effort, we should evaluate what level of >> profit can be attained. >> >> At last, if the performance is tolerable, is this the right way to go? >> >> >> Fei Wu (12): >> riscv64: Starting Vector support, registers added >> riscv64: Pass riscv guest_state for translation >> riscv64: Add SyncupEnv & TooManyIR jump kinds >> riscv64: Add LoadG/StoreG support >> riscv64: Shift guest_state -2048 on calling helper >> riscv64: Add cpu_state to TB >> riscv64: Introduce dis_RV64V and add vsetvl >> riscv64: Add load/store >> riscv64: Add csrr vl >> riscv64: add vfirst >> riscv64: Add vmsgtu/vmseq/vmsne/vmsbf/vmsif/vmor/vmv/vid >> riscv64: Add vadd >> >> VEX/priv/guest_riscv64_toIR.c | 974 +++++++++++++++++++++++++++++- >> VEX/priv/host_riscv64_defs.c | 133 ++++ >> VEX/priv/host_riscv64_defs.h | 23 + >> VEX/priv/host_riscv64_isel.c | 89 ++- >> VEX/priv/ir_defs.c | 8 + >> VEX/priv/ir_opt.c | 4 +- >> VEX/pub/libvex.h | 4 + >> VEX/pub/libvex_guest_riscv64.h | 47 +- >> VEX/pub/libvex_ir.h | 9 +- >> coregrind/m_scheduler/scheduler.c | 17 +- >> coregrind/m_translate.c | 5 + >> coregrind/m_transtab.c | 26 +- >> coregrind/pub_core_transtab.h | 5 + >> memcheck/mc_machine.c | 35 ++ >> memcheck/mc_translate.c | 4 + >> 15 files changed, 1368 insertions(+), 15 deletions(-) >> > |
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From: Mark W. <ma...@kl...> - 2023-08-20 14:16:30
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Hi Paul, On Sat, Aug 19, 2023 at 10:26:15PM +0200, Paul Floyd wrote: > On 19-08-23 21:49, Paul Floyd wrote: > >https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 > > > >commit a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 > >Author: Paul Floyd <pj...@wa...> > >Date: Sat Aug 19 21:37:33 2023 +0200 > > > > Always cleanup on exit from ML_(read_elf_object) > > On second thoughts, I think that this was a real leak in the > deferred loading of debuginfo. I just happened to do a kernel > upgrade at the same time. I think you are correct. Thanks for the patch fixing it. > However I still have one testcase that is failing because of this change. > > The TC uses capability mode (a bit like Linux seccomp). Previously > the VG_(open) for the eager read of debuginfo was allowed because it > happened before entering capability mode. > > Now the deferred load is being attempted after entering capability mode. > > > 68833 memcheck-amd64-free CALL openat(AT_FDCWD,0x1002884a30,0<O_RDONLY>) > 68833 memcheck-amd64-free NAMI "/usr/home/paulf/scratch/valgrind/memcheck/vgpreload_memcheck-amd64-freebsd.so" > 68833 memcheck-amd64-free CAP restricted VFS lookup > 68833 memcheck-amd64-free RET openat -1 errno 94 Not permitted in > capability mode > > That fails so the TC has a few more warnings. I saw your patch adding VG_(load_all_debuginfo). That is a nice trick. Hopefully we can also use something like that for seccomp support. Cheers, Mark |
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From: Paul F. <pa...@so...> - 2023-08-20 13:26:45
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0c37fa39c104f9c7c5f0b2297e3d52e8b8d58cac commit 0c37fa39c104f9c7c5f0b2297e3d52e8b8d58cac Author: Paul Floyd <pj...@wa...> Date: Sun Aug 20 15:24:25 2023 +0200 musl: enable libstdc++ freeres Both libc and libstdc++ freeres were disabled for musl. That means that libstdc++ was showing still reachable memory on systems like Alpine. Diff: --- coregrind/vg_preloaded.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/coregrind/vg_preloaded.c b/coregrind/vg_preloaded.c index 86f6ac5a26..a792081b11 100644 --- a/coregrind/vg_preloaded.c +++ b/coregrind/vg_preloaded.c @@ -76,7 +76,7 @@ DEFINE_GDB_PY_SCRIPT(VG_GDBSCRIPTS_DIR "/valgrind-monitor.py") void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run); void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run) { -# if !defined(__UCLIBC__) && !defined(MUSL_LIBC) \ +# if !defined(__UCLIBC__) \ && !defined(VGPV_arm_linux_android) \ && !defined(VGPV_x86_linux_android) \ && !defined(VGPV_mips32_linux_android) \ @@ -89,6 +89,14 @@ void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run) _ZN9__gnu_cxx9__freeresEv(); } +# endif + +# if !defined(__UCLIBC__) && !defined(MUSL_LIBC) \ + && !defined(VGPV_arm_linux_android) \ + && !defined(VGPV_x86_linux_android) \ + && !defined(VGPV_mips32_linux_android) \ + && !defined(VGPV_arm64_linux_android) + extern void __libc_freeres(void) __attribute__((weak)); if (((to_run & VG_RUN__LIBC_FREERES) != 0) && (__libc_freeres != NULL)) { |
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From: Paul F. <pa...@so...> - 2023-08-20 07:05:51
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3ee80eb4584424498147215e31603e2a2223d315 commit 3ee80eb4584424498147215e31603e2a2223d315 Author: Paul Floyd <pj...@wa...> Date: Sun Aug 20 09:04:17 2023 +0200 FreeBSD: try to make eventfd2 testcase deterministic Add a sleep to give child 1 a chance to run. Flush stdout every time. Diff: --- memcheck/tests/freebsd/eventfd2.c | 8 ++++++++ memcheck/tests/freebsd/eventfd2.stdout.exp | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/memcheck/tests/freebsd/eventfd2.c b/memcheck/tests/freebsd/eventfd2.c index 8e2309f96d..d620907c9d 100644 --- a/memcheck/tests/freebsd/eventfd2.c +++ b/memcheck/tests/freebsd/eventfd2.c @@ -18,6 +18,7 @@ static void xsem_wait(int fd) fprintf(stdout, "wait completed on %d: count=%" PRIu64 "\n", fd, cntr); + fflush(stdout); } static void xsem_post(int fd, int count) @@ -38,21 +39,27 @@ static void sem_player(int fd1, int fd2) * (also xsem_wait above) */ fprintf(stdout, "posting 1 on %d\n", fd1); + fflush(stdout); xsem_post(fd1, 1); fprintf(stdout, "waiting on %d\n", fd2); + fflush(stdout); xsem_wait(fd2); fprintf(stdout, "posting 1 on %d\n", fd1); + fflush(stdout); xsem_post(fd1, 1); fprintf(stdout, "waiting on %d\n", fd2); + fflush(stdout); xsem_wait(fd2); fprintf(stdout, "posting 5 on %d\n", fd1); + fflush(stdout); xsem_post(fd1, 5); fprintf(stdout, "waiting 5 times on %d\n", fd2); + fflush(stdout); xsem_wait(fd2); xsem_wait(fd2); xsem_wait(fd2); @@ -88,6 +95,7 @@ int main(int argc, char **argv) sem_player(fd1, fd2); exit(0); } + sleep(1); if ((cpid_waiter = fork()) == 0) { sem_player(fd2, fd1); exit(0); diff --git a/memcheck/tests/freebsd/eventfd2.stdout.exp b/memcheck/tests/freebsd/eventfd2.stdout.exp index 6a2cd1944e..00ecdcaca7 100644 --- a/memcheck/tests/freebsd/eventfd2.stdout.exp +++ b/memcheck/tests/freebsd/eventfd2.stdout.exp @@ -1,26 +1,26 @@ posting 1 on 3 waiting on 4 +posting 1 on 4 wait completed on 4: count=1 +waiting on 3 posting 1 on 3 waiting on 4 -wait completed on 4: count=1 -posting 5 on 3 -waiting 5 times on 4 -wait completed on 4: count=1 -wait completed on 4: count=1 -wait completed on 4: count=1 -wait completed on 4: count=1 -wait completed on 4: count=1 -posting 1 on 4 -waiting on 3 wait completed on 3: count=1 posting 1 on 4 +wait completed on 4: count=1 waiting on 3 wait completed on 3: count=1 +posting 5 on 3 posting 5 on 4 +waiting 5 times on 4 +wait completed on 4: count=1 waiting 5 times on 3 +wait completed on 4: count=1 wait completed on 3: count=1 +wait completed on 4: count=1 wait completed on 3: count=1 +wait completed on 4: count=1 wait completed on 3: count=1 +wait completed on 4: count=1 wait completed on 3: count=1 wait completed on 3: count=1 |
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From: Paul F. <pa...@so...> - 2023-08-20 06:53:34
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b9326bb1db5fff20332fd6bdbf37741784c215ea commit b9326bb1db5fff20332fd6bdbf37741784c215ea Author: Paul Floyd <pj...@wa...> Date: Sun Aug 20 08:52:36 2023 +0200 FreeBSD: complete loading debuginfo if entering capability mode Diff: --- coregrind/m_debuginfo/debuginfo.c | 15 +++++++++++++++ coregrind/m_syswrap/syswrap-freebsd.c | 2 ++ coregrind/pub_core_debuginfo.h | 7 +++++++ 3 files changed, 24 insertions(+) diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c index 8d1fdc6960..c37e50b9d3 100644 --- a/coregrind/m_debuginfo/debuginfo.c +++ b/coregrind/m_debuginfo/debuginfo.c @@ -5102,6 +5102,21 @@ static void caches__invalidate ( void ) { debuginfo_generation++; } +#if defined(VGO_freebsd) +void VG_(load_all_debuginfo) (void) +{ + for (DebugInfo* di = debugInfo_list; di; di = di->next) { + if (di->deferred == True) { + di->deferred = False; + ML_(read_elf_debug)( di ); + ML_(canonicaliseTables)( di ); + check_CFSI_related_invariants(di); + ML_(finish_CFSI_arrays)(di); + } + } +} +#endif + /*--------------------------------------------------------------------*/ /*--- end ---*/ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/syswrap-freebsd.c b/coregrind/m_syswrap/syswrap-freebsd.c index 9af37cfb83..a59872b3c9 100644 --- a/coregrind/m_syswrap/syswrap-freebsd.c +++ b/coregrind/m_syswrap/syswrap-freebsd.c @@ -5645,6 +5645,8 @@ PRE(sys_cap_enter) " Please consider disabling capability by using the RUNNING_ON_VALGRIND mechanism.\n" " See http://valgrind.org/docs/manual/manual-core-adv.html#manual-core-adv.clientreq\n"); } + /* now complete loading debuginfo since it is not allowed after entering cap mode */ + VG_(load_all_debuginfo)(); } // SYS_cap_getmode 517 diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h index ce72462178..6e93bb93c5 100644 --- a/coregrind/pub_core_debuginfo.h +++ b/coregrind/pub_core_debuginfo.h @@ -150,6 +150,13 @@ extern Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregs, info (e.g. CFI info or FPO info or ...). */ extern UInt VG_(debuginfo_generation) (void); +#if defined(VGO_freebsd) +/* Force completion of loading all debuginfo. + Needed on FreeBSD when entering capability mode since + we can't open executable files to get the debuginfo after + entering capability mode. */ +extern void VG_(load_all_debuginfo) (void); +#endif /* True if some FPO information is loaded. |
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From: Paul F. <pj...@wa...> - 2023-08-19 20:26:30
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On 19-08-23 21:49, Paul Floyd wrote: > https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 > > commit a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 > Author: Paul Floyd <pj...@wa...> > Date: Sat Aug 19 21:37:33 2023 +0200 > > Always cleanup on exit from ML_(read_elf_object) On second thoughts, I think that this was a real leak in the deferred loading of debuginfo. I just happened to do a kernel upgrade at the same time. However I still have one testcase that is failing because of this change. The TC uses capability mode (a bit like Linux seccomp). Previously the VG_(open) for the eager read of debuginfo was allowed because it happened before entering capability mode. Now the deferred load is being attempted after entering capability mode. 68833 memcheck-amd64-free CALL openat(AT_FDCWD,0x1002884a30,0<O_RDONLY>) 68833 memcheck-amd64-free NAMI "/usr/home/paulf/scratch/valgrind/memcheck/vgpreload_memcheck-amd64-freebsd.so" 68833 memcheck-amd64-free CAP restricted VFS lookup 68833 memcheck-amd64-free RET openat -1 errno 94 Not permitted in capability mode That fails so the TC has a few more warnings. A+ Paul |
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From: Paul F. <pa...@so...> - 2023-08-19 19:49:52
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 commit a0d555a0dfe078ef04ea49d991a8090ab14bd4a5 Author: Paul Floyd <pj...@wa...> Date: Sat Aug 19 21:37:33 2023 +0200 Always cleanup on exit from ML_(read_elf_object) I'm still a but baffled as to why this wasn't seen earlier. A FreeBSD testcase started failing with kernel 13.2 patch 2, which is quite a minor change. The testcase gets an fd from pdfork and the parent does a printf with the fd then zaps the process with pdkill. Standalone the fd is 3, and that's what the expected contains. However, when it started failing I saw with lsof that fds 3 and 4 were associated with the guest exe and ld-elf.so.1. Diff: --- coregrind/m_debuginfo/readelf.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c index f99d3dfd2c..ac72f98fb5 100644 --- a/coregrind/m_debuginfo/readelf.c +++ b/coregrind/m_debuginfo/readelf.c @@ -1916,6 +1916,7 @@ Bool ML_(read_elf_object) ( struct _DebugInfo* di ) Word i, j; Bool dynbss_present = False; Bool sdynbss_present = False; + Bool retval = False; /* Image for the main ELF file we're working with. */ DiImage* mimg = NULL; @@ -2944,19 +2945,16 @@ Bool ML_(read_elf_object) ( struct _DebugInfo* di ) } } - return True; + retval = True; - out: - { - /* Last, but not least, detach from the image. */ - if (mimg) ML_(img_done)(mimg); + out: - if (svma_ranges) VG_(deleteXA)(svma_ranges); + /* Last, but not least, detach from the image. */ + if (mimg) ML_(img_done)(mimg); - return False; - } /* out: */ + if (svma_ranges) VG_(deleteXA)(svma_ranges); - /* NOTREACHED */ + return retval; } Bool ML_(read_elf_debug) ( struct _DebugInfo* di ) |
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From: Paul F. <pj...@wa...> - 2023-08-18 06:15:38
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On 18-08-23 00:21, John Reiser wrote:
>> -hex=$( $DIS_PATH -F scf_handle_bind $libscf | perl -pe '($_) =
>> /0x(?:4d01)?526570(\d{2}),/' )
>> +hex=$( $DIS_PATH -F scf_handle_bind $libscf | grep 526570 | sed
>> 's/.*526570//;s/,.*//' )
>
> Surely the string "526570" deserves a code comment about its origin,
> maintenance, etc.
Done, but it is just "the bytes before the protocol version".
A+
Paul
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From: Paul F. <pa...@so...> - 2023-08-18 06:14:09
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=639fa4053d8ef97bd211dc541029622ce86dd6fc commit 639fa4053d8ef97bd211dc541029622ce86dd6fc Author: Paul Floyd <pj...@wa...> Date: Fri Aug 18 08:12:53 2023 +0200 Solaris: explain configure detection of scf repository door version Diff: --- configure.ac | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/configure.ac b/configure.ac index 913e8e8c5d..e9592f47ec 100755 --- a/configure.ac +++ b/configure.ac @@ -4537,6 +4537,16 @@ AC_PATH_PROG(DIS_PATH, dis, false) if test "x$DIS_PATH" = "xfalse"; then AC_MSG_FAILURE([Object code disassembler (`dis') not found.]) fi +# The illumos source is (or was) here +# https://github.com/illumos/illumos-gate/blob/master/usr/src/lib/libscf/common/lowlevel.c#L1148 +# specifically the line +# +# request.rdr_version = REPOSITORY_DOOR_VERSION; +# +# rdr_version is a 32bit unsigned int +# The macro REPOSITORY_DOOR_VERSION contains the ascii letters "Rep" in the top 3 +# bytes and the door version in the lowest byte. Hence we look for Rep which is 526570 +# in hex and then extrace the following byte. AC_CHECK_LIB(scf, scf_handle_bind, [], [ AC_MSG_WARN([Function `scf_handle_bind' was not found in `libscf'.]) AC_MSG_ERROR([Cannot determine version of the repository cache protocol.]) |
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From: John R. <jr...@bi...> - 2023-08-17 22:21:51
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> -hex=$( $DIS_PATH -F scf_handle_bind $libscf | perl -pe '($_) = /0x(?:4d01)?526570(\d{2}),/' )
> +hex=$( $DIS_PATH -F scf_handle_bind $libscf | grep 526570 | sed 's/.*526570//;s/,.*//' )
Surely the string "526570" deserves a code comment about its origin,
maintenance, etc.
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From: Paul F. <pa...@so...> - 2023-08-17 20:10:00
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=991bf3789a828e60c24776a1cd2f8271255596bc commit 991bf3789a828e60c24776a1cd2f8271255596bc Author: Paul Floyd <pj...@wa...> Date: Thu Aug 17 22:05:47 2023 +0200 Bug 472963 - Broken regular expression in configure.ac Was extracting the last two decimal digits from a hex humber. I switched to using grep and sed because the proposed solution didn't work on Solaris 11.3. Diff: --- NEWS | 1 + configure.ac | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index 055dc41945..56f4701e00 100644 --- a/NEWS +++ b/NEWS @@ -47,6 +47,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 470978 s390x: Valgrind cannot start qemu-kvm when "sysctl vm.allocate_pgste=0" 471807 Add support for lazy reading and downloading of DWARF debuginfo 472219 Syscall param ppoll(ufds.events) points to uninitialised byte(s) +472963 Broken regular expression in configure.ac To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/configure.ac b/configure.ac index b4e9c11428..913e8e8c5d 100755 --- a/configure.ac +++ b/configure.ac @@ -4552,7 +4552,7 @@ if ! $DIS_PATH -F scf_handle_bind $libscf | grep -q -E '0x(4d01)?526570'; then AC_MSG_WARN([Function `scf_handle_bind' does not contain repository cache protocol version.]) AC_MSG_ERROR([Cannot determine version of the repository cache protocol.]) fi -hex=$( $DIS_PATH -F scf_handle_bind $libscf | perl -pe '($_) = /0x(?:4d01)?526570(\d{2}),/' ) +hex=$( $DIS_PATH -F scf_handle_bind $libscf | grep 526570 | sed 's/.*526570//;s/,.*//' ) if test -z "$hex"; then AC_MSG_WARN([Version of the repository cache protocol is empty?!]) AC_MSG_ERROR([Cannot determine version of the repository cache protocol.]) |
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From: Mark W. <ma...@so...> - 2023-08-16 12:17:13
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=60f7e89ba32b54d73b9e36d49e28d0f559ade0b9 commit 60f7e89ba32b54d73b9e36d49e28d0f559ade0b9 Author: Aaron Merey <am...@re...> Date: Fri Jun 30 18:31:42 2023 -0400 Support lazy reading and downloading of DWARF debuginfo Currently valgrind attempts to read DWARF .debug_* sections as well as separate debuginfo files for ELF binaries as soon as a shared library is loaded. This might also result in the downloading of separate debuginfo files via debuginfod. This is inefficient when some of this debuginfo never ends up being used by valgrind while running the client process. This patch adds support for lazy reading and downloading of DWARF debuginfo. When an ELF shared library is loaded, the reading of .debug_* sections as well as separate or alternate debuginfo is deferred until valgrind handles an instruction pointer corresponding to a text segment of the shared library. At this point the deferred sections and separate debug files are loaded. This feature is only supported on ELF platforms. https://bugs.kde.org/show_bug.cgi?id=471807 ChangeLog * debuginfo.c (di_notify_ACHIEVE_ACCEPT_STATE): Replace read_elf_debug_info with read_elf_object. (addr_load_di): New function. Attempts to load deferred debuginfo associated with a given address. (load_di): New function. Attempts to load a given deferred debuginfo associated with a given address. (describe_IP): Add calls to load_di and addr_load_di. (find_DiCfSI): Add call to load_di. * priv_readelf.h (read_elf_object): New declaration. (read_elf_debug): Ditto. * priv_storage.h (struct _DebugInfo): New field 'bool deferred'. * readelf.c (read_elf_debug_info): Split into read_elf_object and read_elf_debug. (read_elf_object): Read non .debug_* section from an ELF binary. (read_elf_debug): Read .debug_* sections from an ELF binary as as well any separate/alternate debuginfo files. * storage.c (canonicaliseSymtab): Remove assert in order to support canonicalization of deferred _DebugInfo. (finish_CFSI_arrays): Add early return if _DebugInfo is deferred in order to avoid freeing memory that will be needed when reading debuginfo at a later time. (canonicaliseTables): Ditto. * pub_core_debuginfo.h (addr_load_di): New declaration. (load_di): New declaration. Diff: --- NEWS | 1 + coregrind/m_debuginfo/debuginfo.c | 57 ++++- coregrind/m_debuginfo/priv_readelf.h | 24 +- coregrind/m_debuginfo/priv_storage.h | 7 + coregrind/m_debuginfo/readelf.c | 437 +++++++++++++++++++++++------------ coregrind/m_debuginfo/storage.c | 13 +- coregrind/pub_core_debuginfo.h | 4 + 7 files changed, 379 insertions(+), 164 deletions(-) diff --git a/NEWS b/NEWS index 867d2f0f43..055dc41945 100644 --- a/NEWS +++ b/NEWS @@ -45,6 +45,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. Assertion 'resolved' failed 470830 Don't print actions vgdb me ... continue for vgdb --multi mode 470978 s390x: Valgrind cannot start qemu-kvm when "sysctl vm.allocate_pgste=0" +471807 Add support for lazy reading and downloading of DWARF debuginfo 472219 Syscall param ppoll(ufds.events) points to uninitialised byte(s) To see details of a given bug, visit diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c index 22b41def21..8d1fdc6960 100644 --- a/coregrind/m_debuginfo/debuginfo.c +++ b/coregrind/m_debuginfo/debuginfo.c @@ -959,14 +959,16 @@ static ULong di_notify_ACHIEVE_ACCEPT_STATE ( struct _DebugInfo* di ) discard_DebugInfos_which_overlap_with( di ); /* The DebugInfoMappings that now exist in the FSM may involve - overlaps. This confuses ML_(read_elf_debug_info), and may cause + overlaps. This confuses ML_(read_elf_*), and may cause it to compute wrong biases. So de-overlap them now. See http://bugzilla.mozilla.org/show_bug.cgi?id=788974 */ truncate_DebugInfoMapping_overlaps( di, di->fsm.maps ); /* And acquire new info. */ # if defined(VGO_linux) || defined(VGO_solaris) || defined(VGO_freebsd) - ok = ML_(read_elf_debug_info)( di ); + ok = ML_(read_elf_object)( di ); + if (ok) + di->deferred = True; # elif defined(VGO_darwin) ok = ML_(read_macho_debug_info)( di ); # else @@ -1443,6 +1445,50 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV, Int use_fd ) } } +/* Load DI if it has a text segment containing A and DI hasn't already + been loaded. */ + +void VG_(load_di)( DebugInfo *di, Addr a) +{ + if (!di->deferred + || !di->text_present + || di->text_size <= 0 + || di->text_avma > a + || a >= di->text_avma + di->text_size) + return; + + di->deferred = False; + ML_(read_elf_debug) (di); + ML_(canonicaliseTables)( di ); + + /* Check invariants listed in + Comment_on_IMPORTANT_REPRESENTATIONAL_INVARIANTS in + priv_storage.h. */ + check_CFSI_related_invariants(di); + ML_(finish_CFSI_arrays)(di); +} + +/* Attempt to load DebugInfo with a text segment containing A, + if such a debuginfo hasn't already been loaded. */ + +void VG_(addr_load_di)( Addr a ) +{ + DebugInfo *di; + + di = VG_(find_DebugInfo)(VG_(current_DiEpoch)(), a); + if (di != NULL) + if (di->deferred) { + di->deferred = False; + ML_(read_elf_debug) (di); + ML_(canonicaliseTables)( di ); + + /* Check invariants listed in + Comment_on_IMPORTANT_REPRESENTATIONAL_INVARIANTS in + priv_storage.h. */ + check_CFSI_related_invariants(di); + ML_(finish_CFSI_arrays)(di); + } +} /* Unmap is simpler - throw away any SegInfos intersecting [a, a+len). */ @@ -2746,6 +2792,11 @@ const HChar* VG_(describe_IP)(DiEpoch ep, Addr eip, const InlIPCursor *iipc) Bool know_objname; Bool know_srcloc; + if (iipc && iipc->di) + VG_(load_di) (iipc->di, eip); + else + VG_(addr_load_di) (eip); + if (is_bottom(iipc)) { // At the bottom (towards main), we describe the fn at eip. know_fnname = VG_(clo_sym_offsets) @@ -3090,6 +3141,8 @@ static void find_DiCfSI ( /*OUT*/DebugInfo** diP, if (!is_DI_valid_for_epoch(di, curr_epoch)) continue; + VG_(load_di)(di, ip); + /* Use the per-DebugInfo summary address ranges to skip inapplicable DebugInfos quickly. */ if (di->cfsi_used == 0) diff --git a/coregrind/m_debuginfo/priv_readelf.h b/coregrind/m_debuginfo/priv_readelf.h index 57aa0cc3f3..7e0fa17c9d 100644 --- a/coregrind/m_debuginfo/priv_readelf.h +++ b/coregrind/m_debuginfo/priv_readelf.h @@ -44,13 +44,23 @@ extern Bool ML_(is_elf_object_file)( const void* image, SizeT n_image, Bool rel_ok ); -/* The central function for reading ELF debug info. For the - object/exe specified by the SegInfo, find ELF sections, then read - the symbols, line number info, file name info, CFA (stack-unwind - info) and anything else we want, into the tables within the - supplied SegInfo. -*/ -extern Bool ML_(read_elf_debug_info) ( DebugInfo* di ); +/* Read the ELF binary specified by DI. For the object/exe specified + by the SegInfo, find ELF sections, then read the symbols, line number + info, file name info, CFA (stack-unwind info) and anything else we + want, into the tables within the supplied SegInfo. + + .debug_* sections as well as any separate debuginfo files are not + loaded by this function but instead by ML_(read_elf_debug). This + separation facilitates lazy loading of debuginfo. */ +extern Bool ML_(read_elf_object) ( DebugInfo* di ); + +/* Read .debug_* sections from the ELF binary specified by DI. Also + attempt to load any separate debuginfo files associated with the + object. + + ML_(read_elf_object) should be called on DI before calling this + function. */ +extern Bool ML_(read_elf_debug) ( DebugInfo* di ); extern Bool ML_(check_elf_and_get_rw_loads) ( Int fd, const HChar* filename, Int * rw_load_count ); diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h index a4b90d36b3..b959873ab8 100644 --- a/coregrind/m_debuginfo/priv_storage.h +++ b/coregrind/m_debuginfo/priv_storage.h @@ -678,6 +678,13 @@ struct _DebugInfo { invalid and should not be consulted. */ Bool have_dinfo; /* initially False */ + /* If true then the reading of .debug_* section has been deferred + until it this information is required (such as when printing + a stacktrace). Additionally, if true then the reading of any + separate debuginfo files associated with this object has also + been deferred. */ + Bool deferred; + /* All the rest of the fields in this structure are filled in once we have committed to reading the symbols and debug info (that is, at the point where .have_dinfo is set to True). */ diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c index ce7b7998de..f99d3dfd2c 100644 --- a/coregrind/m_debuginfo/readelf.c +++ b/coregrind/m_debuginfo/readelf.c @@ -1836,6 +1836,44 @@ static HChar* readlink_path (const HChar *path) return buf; } +#define FINDX_MIMG(_sec_name, _sec_escn, _post_fx) \ + do { \ + ElfXX_Shdr a_shdr; \ + ML_(img_get)(&a_shdr, mimg, \ + INDEX_BIS(shdr_mioff, i, shdr_ment_szB), \ + sizeof(a_shdr)); \ + if (0 == ML_(img_strcmp_c)(mimg, shdr_strtab_mioff \ + + a_shdr.sh_name, _sec_name)) { \ + Bool nobits; \ + _sec_escn.img = mimg; \ + _sec_escn.ioff = (DiOffT)a_shdr.sh_offset; \ + _sec_escn.szB = a_shdr.sh_size; \ + if (!check_compression(&a_shdr, &_sec_escn)) { \ + ML_(symerr)(di, True, " Compression type is unsupported"); \ + goto out; \ + } \ + nobits = a_shdr.sh_type == SHT_NOBITS; \ + vg_assert(_sec_escn.img != NULL); \ + vg_assert(_sec_escn.ioff != DiOffT_INVALID); \ + TRACE_SYMTAB( "%-18s: ioff %llu .. %llu\n", \ + _sec_name, (ULong)a_shdr.sh_offset, \ + ((ULong)a_shdr.sh_offset) + a_shdr.sh_size - 1); \ + /* SHT_NOBITS sections have zero size in the file. */ \ + if (!nobits && \ + a_shdr.sh_offset + \ + a_shdr.sh_size > ML_(img_real_size)(mimg)) { \ + ML_(symerr)(di, True, \ + " section beyond image end?!"); \ + goto out; \ + } \ + _post_fx; \ + } \ + } while (0); + +/* Version with no post-effects */ +#define FIND_MIMG(_sec_name, _sec_escn) \ + FINDX_MIMG(_sec_name, _sec_escn, /**/) + /* The central function for reading ELF debug info. For the object/exe specified by the DebugInfo, find ELF sections, then read the symbols, line number info, file name info, CFA (stack-unwind @@ -1843,7 +1881,7 @@ static HChar* readlink_path (const HChar *path) supplied DebugInfo. */ -Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) +Bool ML_(read_elf_object) ( struct _DebugInfo* di ) { /* This function is long and complex. That, and the presence of nested scopes, means it's not always easy to see which parts are @@ -1874,7 +1912,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) /* TOPLEVEL */ - Bool res, ok; + Bool ok; Word i, j; Bool dynbss_present = False; Bool sdynbss_present = False; @@ -1882,12 +1920,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) /* Image for the main ELF file we're working with. */ DiImage* mimg = NULL; - /* Ditto for any ELF debuginfo file that we might happen to load. */ - DiImage* dimg = NULL; - - /* Ditto for alternate ELF debuginfo file that we might happen to load. */ - DiImage* aimg = NULL; - /* ELF header offset for the main file. Should be zero since the ELF header is at start of file. */ DiOffT ehdr_mioff = 0; @@ -1970,8 +2002,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) got, plt, and toc. ---------------------------------------------------------- */ - res = False; - if (VG_(clo_verbosity) > 1 || VG_(clo_trace_redir)) VG_(message)(Vg_DebugMsg, "Reading syms from %s\n", di->fsm.filename ); @@ -2056,7 +2086,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) shdr_strtab_mioff = ehdr_mioff /* isn't this always zero? */ + a_shdr.sh_offset; - if (!ML_(img_valid)(mimg, shdr_strtab_mioff, + if (!ML_(img_valid)(mimg, shdr_strtab_mioff, 1/*bogus, but we don't know the real size*/ )) { ML_(symerr)(di, True, "Invalid ELF Section Header String Table"); goto out; @@ -2798,10 +2828,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) di->text_avma - di->text_bias, di->text_avma ); - TRACE_SYMTAB("\n"); - TRACE_SYMTAB("------ Finding image addresses " - "for debug-info sections ------\n"); - /* TOPLEVEL */ /* Find interesting sections, read the symbol table(s), read any debug information. Each section is located either in the main, @@ -2821,27 +2847,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) # if defined(VGO_solaris) DiSlice ldynsym_escn = DiSlice_INVALID; // .SUNW_ldynsym # endif - DiSlice debuglink_escn = DiSlice_INVALID; // .gnu_debuglink - DiSlice debugaltlink_escn = DiSlice_INVALID; // .gnu_debugaltlink - DiSlice debug_line_escn = DiSlice_INVALID; // .debug_line (dwarf2) - DiSlice debug_info_escn = DiSlice_INVALID; // .debug_info (dwarf2) - DiSlice debug_types_escn = DiSlice_INVALID; // .debug_types (dwarf4) - DiSlice debug_abbv_escn = DiSlice_INVALID; // .debug_abbrev (dwarf2) - DiSlice debug_str_escn = DiSlice_INVALID; // .debug_str (dwarf2) - DiSlice debug_line_str_escn = DiSlice_INVALID; // .debug_line_str(dwarf5) - DiSlice debug_ranges_escn = DiSlice_INVALID; // .debug_ranges (dwarf2) - DiSlice debug_rnglists_escn = DiSlice_INVALID; // .debug_rnglists(dwarf5) - DiSlice debug_loclists_escn = DiSlice_INVALID; // .debug_loclists(dwarf5) - DiSlice debug_addr_escn = DiSlice_INVALID; // .debug_addr (dwarf5) - DiSlice debug_str_offsets_escn = DiSlice_INVALID; // .debug_str_offsets (dwarf5) - DiSlice debug_loc_escn = DiSlice_INVALID; // .debug_loc (dwarf2) - DiSlice debug_frame_escn = DiSlice_INVALID; // .debug_frame (dwarf2) - DiSlice debug_line_alt_escn = DiSlice_INVALID; // .debug_line (alt) - DiSlice debug_info_alt_escn = DiSlice_INVALID; // .debug_info (alt) - DiSlice debug_abbv_alt_escn = DiSlice_INVALID; // .debug_abbrev (alt) - DiSlice debug_str_alt_escn = DiSlice_INVALID; // .debug_str (alt) - DiSlice dwarf1d_escn = DiSlice_INVALID; // .debug (dwarf1) - DiSlice dwarf1l_escn = DiSlice_INVALID; // .line (dwarf1) DiSlice opd_escn = DiSlice_INVALID; // .opd (dwarf2, // ppc64be-linux) DiSlice ehframe_escn[N_EHFRAME_SECTS]; // .eh_frame (dwarf2) @@ -2868,118 +2873,282 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) /* TOPLEVEL */ /* Iterate over section headers (again) */ for (i = 0; i < ehdr_m.e_shnum; i++) { + /* NAME ElfSec */ + FIND_MIMG( ".dynsym", dynsym_escn) + FIND_MIMG( ".dynstr", dynstr_escn) + FIND_MIMG( ".symtab", symtab_escn) + FIND_MIMG( ".strtab", strtab_escn) +# if defined(VGO_solaris) + FIND_MIMG( ".SUNW_ldynsym", ldynsym_escn) +# endif -# define FINDX(_sec_name, _sec_escn, _post_fx) \ - do { \ - ElfXX_Shdr a_shdr; \ - ML_(img_get)(&a_shdr, mimg, \ - INDEX_BIS(shdr_mioff, i, shdr_ment_szB), \ - sizeof(a_shdr)); \ - if (0 == ML_(img_strcmp_c)(mimg, shdr_strtab_mioff \ - + a_shdr.sh_name, _sec_name)) { \ - Bool nobits; \ - _sec_escn.img = mimg; \ - _sec_escn.ioff = (DiOffT)a_shdr.sh_offset; \ - _sec_escn.szB = a_shdr.sh_size; \ - if (!check_compression(&a_shdr, &_sec_escn)) { \ - ML_(symerr)(di, True, " Compression type is unsupported"); \ - goto out; \ - } \ - nobits = a_shdr.sh_type == SHT_NOBITS; \ - vg_assert(_sec_escn.img != NULL); \ - vg_assert(_sec_escn.ioff != DiOffT_INVALID); \ - TRACE_SYMTAB( "%-18s: ioff %llu .. %llu\n", \ - _sec_name, (ULong)a_shdr.sh_offset, \ - ((ULong)a_shdr.sh_offset) + a_shdr.sh_size - 1); \ - /* SHT_NOBITS sections have zero size in the file. */ \ - if (!nobits && \ - a_shdr.sh_offset + \ - a_shdr.sh_size > ML_(img_real_size)(mimg)) { \ - ML_(symerr)(di, True, \ - " section beyond image end?!"); \ - goto out; \ - } \ - _post_fx; \ - } \ - } while (0); + FINDX_MIMG( ".eh_frame", ehframe_escn[ehframe_mix], + do { ehframe_mix++; vg_assert(ehframe_mix <= N_EHFRAME_SECTS); + } while (0) + ) + /* Comment_on_EH_FRAME_MULTIPLE_INSTANCES: w.r.t. .eh_frame + multi-instance kludgery, how are we assured that the order + in which we fill in ehframe_escn[] is consistent with the + order in which we previously filled in di->ehframe_avma[] + and di->ehframe_size[] ? By the fact that in both cases, + these arrays were filled in by iterating over the section + headers top-to-bottom. So both loops (this one and the + previous one) encounter the .eh_frame entries in the same + order and so fill in these arrays in a consistent order. + */ + } /* Iterate over section headers (again) */ - /* Version with no post-effects */ -# define FIND(_sec_name, _sec_escn) \ - FINDX(_sec_name, _sec_escn, /**/) + /* Check some sizes */ + vg_assert((dynsym_escn.szB % sizeof(ElfXX_Sym)) == 0); + vg_assert((symtab_escn.szB % sizeof(ElfXX_Sym)) == 0); +# if defined(VGO_solaris) + vg_assert((ldynsym_escn.szB % sizeof(ElfXX_Sym)) == 0); +# endif - /* NAME ElfSec */ - FIND( ".dynsym", dynsym_escn) - FIND( ".dynstr", dynstr_escn) - FIND( ".symtab", symtab_escn) - FIND( ".strtab", strtab_escn) + /* Read symbols */ + { + void (*read_elf_symtab)(struct _DebugInfo*, const HChar*, + DiSlice*, DiSlice*, DiSlice*, Bool); +# if defined(VGP_ppc64be_linux) + read_elf_symtab = read_elf_symtab__ppc64be_linux; +# else + read_elf_symtab = read_elf_symtab__normal; +# endif + if (symtab_escn.img != NULL) + read_elf_symtab(di, "symbol table", + &symtab_escn, &strtab_escn, &opd_escn, + False); + read_elf_symtab(di, "dynamic symbol table", + &dynsym_escn, &dynstr_escn, &opd_escn, + False); # if defined(VGO_solaris) - FIND( ".SUNW_ldynsym", ldynsym_escn) + read_elf_symtab(di, "local dynamic symbol table", + &ldynsym_escn, &dynstr_escn, &opd_escn, + False); # endif + } - FIND( ".gnu_debuglink", debuglink_escn) - FIND( ".gnu_debugaltlink", debugaltlink_escn) + /* TOPLEVEL */ + /* Read .eh_frame and .debug_frame (call-frame-info) if any. Do + the .eh_frame section(s) first. */ + vg_assert(di->n_ehframe >= 0 && di->n_ehframe <= N_EHFRAME_SECTS); + for (i = 0; i < di->n_ehframe; i++) { + /* see Comment_on_EH_FRAME_MULTIPLE_INSTANCES above for why + this next assertion should hold. */ + vg_assert(ML_(sli_is_valid)(ehframe_escn[i])); + vg_assert(ehframe_escn[i].szB == di->ehframe_size[i]); + ML_(read_callframe_info_dwarf3)( di, + ehframe_escn[i], + di->ehframe_avma[i], + True/*is_ehframe*/ ); + } + } + + return True; + + out: + { + /* Last, but not least, detach from the image. */ + if (mimg) ML_(img_done)(mimg); + + if (svma_ranges) VG_(deleteXA)(svma_ranges); - FIND( ".debug_line", debug_line_escn) + return False; + } /* out: */ + + /* NOTREACHED */ +} + +Bool ML_(read_elf_debug) ( struct _DebugInfo* di ) +{ + Word i, j; + Bool res = True; + Bool ok; + + /* Image for the main ELF file we're working with. */ + DiImage* mimg = NULL; + + /* Ditto for any ELF debuginfo file that we might happen to load. */ + DiImage* dimg = NULL; + + /* Ditto for alternate ELF debuginfo file that we might happen to load. */ + DiImage* aimg = NULL; + + /* Section header image addr, # entries, entry size. Also the + associated string table. */ + DiOffT shdr_mioff = 0; + UWord shdr_mnent = 0; + UWord shdr_ment_szB = 0; + DiOffT shdr_strtab_mioff = 0; + + DiOffT ehdr_mioff = 0; + + /* Connect to the primary object image, so that we can read symbols + and line number info out of it. It will be disconnected + immediately thereafter; it is only connected transiently. */ + mimg = ML_(img_from_local_file)(di->fsm.filename); + if (mimg == NULL) { + VG_(message)(Vg_UserMsg, "warning: connection to image %s failed\n", + di->fsm.filename ); + VG_(message)(Vg_UserMsg, " no debug info loaded\n" ); + return False; + } + + /* Ok, the object image is available. Now verify that it is a + valid ELF .so or executable image. */ + ok = is_elf_object_file_by_DiImage(mimg, False); + if (!ok) { + ML_(symerr)(di, True, "Invalid ELF Header"); + goto out; + } + + /* Find where the program and section header tables are, and give + up if either is missing or outside the image (bogus). */ + ElfXX_Ehdr ehdr_m; + vg_assert(ehdr_mioff == 0); // ensured by its initialisation + ok = ML_(img_valid)(mimg, ehdr_mioff, sizeof(ehdr_m)); + vg_assert(ok); // ML_(is_elf_object_file) should ensure this + ML_(img_get)(&ehdr_m, mimg, ehdr_mioff, sizeof(ehdr_m)); + + shdr_mioff = ehdr_mioff + ehdr_m.e_shoff; + shdr_mnent = ehdr_m.e_shnum; + shdr_ment_szB = ehdr_m.e_shentsize; + + if (shdr_mnent == 0 + || !ML_(img_valid)(mimg, shdr_mioff, shdr_mnent * shdr_ment_szB)) { + ML_(symerr)(di, True, "Missing or invalid ELF Section Header Table"); + goto out; + } + + /* Also find the section header's string table, and validate. */ + /* checked previously by is_elf_object_file: */ + vg_assert(ehdr_m.e_shstrndx != SHN_UNDEF); + + // shdr_mioff is the offset of the section header table + // and we need the ehdr_m.e_shstrndx'th entry + { ElfXX_Shdr a_shdr; + ML_(img_get)(&a_shdr, mimg, + INDEX_BIS(shdr_mioff, ehdr_m.e_shstrndx, shdr_ment_szB), + sizeof(a_shdr)); + shdr_strtab_mioff + = ehdr_mioff /* isn't this always zero? */ + a_shdr.sh_offset; + + if (!ML_(img_valid)(mimg, shdr_strtab_mioff, + 1/*bogus, but we don't know the real size*/ )) { + ML_(symerr)(di, True, "Invalid ELF Section Header String Table"); + goto out; + } + } + + TRACE_SYMTAB("\n"); + TRACE_SYMTAB("------ Finding image addresses " + "for debug-info sections ------\n"); + /* TOPLEVEL */ + /* Find interesting sections, read the symbol table(s), read any + debug information. Each section is located either in the main, + debug or alt-debug files, but only in one. For each section, + |section_escn| records which of |mimg|, |dimg| or |aimg| we + found it in, along with the section's image offset and its size. + The triples (section_img, section_ioff, section_szB) are + consistent, in that they are always either (NULL, + DiOffT_INVALID, 0), or refer to the same image, and are all + assigned together. */ + + { + /* TOPLEVEL */ + DiSlice strtab_escn = DiSlice_INVALID; // .strtab + DiSlice symtab_escn = DiSlice_INVALID; // .symtab + DiSlice debuglink_escn = DiSlice_INVALID; // .gnu_debuglink + DiSlice debugaltlink_escn = DiSlice_INVALID; // .gnu_debugaltlink + DiSlice debug_line_escn = DiSlice_INVALID; // .debug_line (dwarf2) + DiSlice debug_info_escn = DiSlice_INVALID; // .debug_info (dwarf2) + DiSlice debug_types_escn = DiSlice_INVALID; // .debug_types (dwarf4) + DiSlice debug_abbv_escn = DiSlice_INVALID; // .debug_abbrev (dwarf2) + DiSlice debug_str_escn = DiSlice_INVALID; // .debug_str (dwarf2) + DiSlice debug_line_str_escn = DiSlice_INVALID; // .debug_line_str(dwarf5) + DiSlice debug_ranges_escn = DiSlice_INVALID; // .debug_ranges (dwarf2) + DiSlice debug_rnglists_escn = DiSlice_INVALID; // .debug_rnglists(dwarf5) + DiSlice debug_loclists_escn = DiSlice_INVALID; // .debug_loclists(dwarf5) + DiSlice debug_addr_escn = DiSlice_INVALID; // .debug_addr (dwarf5) + DiSlice debug_str_offsets_escn = DiSlice_INVALID; // .debug_str_offsets (dwarf5) + DiSlice debug_loc_escn = DiSlice_INVALID; // .debug_loc (dwarf2) + DiSlice debug_frame_escn = DiSlice_INVALID; // .debug_frame (dwarf2) + DiSlice debug_line_alt_escn = DiSlice_INVALID; // .debug_line (alt) + DiSlice debug_info_alt_escn = DiSlice_INVALID; // .debug_info (alt) + DiSlice debug_abbv_alt_escn = DiSlice_INVALID; // .debug_abbrev (alt) + DiSlice debug_str_alt_escn = DiSlice_INVALID; // .debug_str (alt) + DiSlice dwarf1d_escn = DiSlice_INVALID; // .debug (dwarf1) + DiSlice dwarf1l_escn = DiSlice_INVALID; // .line (dwarf1) + DiSlice opd_escn = DiSlice_INVALID; // .opd (dwarf2, + // ppc64be-linux) + + /* TOPLEVEL */ + /* Iterate over section headers (again) */ + for (i = 0; i < ehdr_m.e_shnum; i++) { + + /* NAME ElfSec */ + FIND_MIMG( ".symtab", symtab_escn) + FIND_MIMG( ".strtab", strtab_escn) + FIND_MIMG( ".gnu_debuglink", debuglink_escn) + FIND_MIMG( ".gnu_debugaltlink", debugaltlink_escn) + + FIND_MIMG( ".debug_line", debug_line_escn) if (!ML_(sli_is_valid)(debug_line_escn)) - FIND(".zdebug_line", debug_line_escn) + FIND_MIMG(".zdebug_line", debug_line_escn) - FIND( ".debug_info", debug_info_escn) + FIND_MIMG( ".debug_info", debug_info_escn) if (!ML_(sli_is_valid)(debug_info_escn)) - FIND(".zdebug_info", debug_info_escn) + FIND_MIMG(".zdebug_info", debug_info_escn) - FIND( ".debug_types", debug_types_escn) + FIND_MIMG( ".debug_types", debug_types_escn) if (!ML_(sli_is_valid)(debug_types_escn)) - FIND(".zdebug_types", debug_types_escn) + FIND_MIMG(".zdebug_types", debug_types_escn) - FIND( ".debug_abbrev", debug_abbv_escn) + FIND_MIMG( ".debug_abbrev", debug_abbv_escn) if (!ML_(sli_is_valid)(debug_abbv_escn)) - FIND(".zdebug_abbrev", debug_abbv_escn) + FIND_MIMG(".zdebug_abbrev", debug_abbv_escn) - FIND( ".debug_str", debug_str_escn) + FIND_MIMG( ".debug_str", debug_str_escn) if (!ML_(sli_is_valid)(debug_str_escn)) - FIND(".zdebug_str", debug_str_escn) + FIND_MIMG(".zdebug_str", debug_str_escn) - FIND( ".debug_line_str", debug_line_str_escn) + FIND_MIMG( ".debug_line_str", debug_line_str_escn) if (!ML_(sli_is_valid)(debug_line_str_escn)) - FIND(".zdebug_str", debug_line_str_escn) + FIND_MIMG(".zdebug_str", debug_line_str_escn) - FIND( ".debug_ranges", debug_ranges_escn) + FIND_MIMG( ".debug_ranges", debug_ranges_escn) if (!ML_(sli_is_valid)(debug_ranges_escn)) - FIND(".zdebug_ranges", debug_ranges_escn) + FIND_MIMG(".zdebug_ranges", debug_ranges_escn) - FIND( ".debug_rnglists", debug_rnglists_escn) + FIND_MIMG( ".debug_rnglists", debug_rnglists_escn) if (!ML_(sli_is_valid)(debug_rnglists_escn)) - FIND(".zdebug_rnglists", debug_rnglists_escn) + FIND_MIMG(".zdebug_rnglists", debug_rnglists_escn) - FIND( ".debug_loclists", debug_loclists_escn) + FIND_MIMG( ".debug_loclists", debug_loclists_escn) if (!ML_(sli_is_valid)(debug_loclists_escn)) - FIND(".zdebug_loclists", debug_loclists_escn) + FIND_MIMG(".zdebug_loclists", debug_loclists_escn) - FIND( ".debug_loc", debug_loc_escn) + FIND_MIMG( ".debug_loc", debug_loc_escn) if (!ML_(sli_is_valid)(debug_loc_escn)) - FIND(".zdebug_loc", debug_loc_escn) + FIND_MIMG(".zdebug_loc", debug_loc_escn) - FIND( ".debug_frame", debug_frame_escn) + FIND_MIMG( ".debug_frame", debug_frame_escn) if (!ML_(sli_is_valid)(debug_frame_escn)) - FIND(".zdebug_frame", debug_frame_escn) + FIND_MIMG(".zdebug_frame", debug_frame_escn) - FIND( ".debug_addr", debug_addr_escn) + FIND_MIMG( ".debug_addr", debug_addr_escn) if (!ML_(sli_is_valid)(debug_addr_escn)) - FIND(".zdebug_addr", debug_addr_escn) + FIND_MIMG(".zdebug_addr", debug_addr_escn) - FIND( ".debug_str_offsets", debug_str_offsets_escn) + FIND_MIMG( ".debug_str_offsets", debug_str_offsets_escn) if (!ML_(sli_is_valid)(debug_str_offsets_escn)) - FIND(".zdebug_str_offsets", debug_str_offsets_escn) + FIND_MIMG(".zdebug_str_offsets", debug_str_offsets_escn) - FIND( ".debug", dwarf1d_escn) - FIND( ".line", dwarf1l_escn) + FIND_MIMG( ".debug", dwarf1d_escn) + FIND_MIMG( ".line", dwarf1l_escn) - FIND( ".opd", opd_escn) + FIND_MIMG( ".opd", opd_escn) - FINDX( ".eh_frame", ehframe_escn[ehframe_mix], - do { ehframe_mix++; vg_assert(ehframe_mix <= N_EHFRAME_SECTS); - } while (0) - ) /* Comment_on_EH_FRAME_MULTIPLE_INSTANCES: w.r.t. .eh_frame multi-instance kludgery, how are we assured that the order in which we fill in ehframe_escn[] is consistent with the @@ -2991,8 +3160,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) order and so fill in these arrays in a consistent order. */ -# undef FINDX -# undef FIND } /* Iterate over section headers (again) */ /* TOPLEVEL */ @@ -3465,53 +3632,23 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) } /* Find all interesting sections */ } /* do we have a debug image? */ - /* TOPLEVEL */ - /* Check some sizes */ - vg_assert((dynsym_escn.szB % sizeof(ElfXX_Sym)) == 0); vg_assert((symtab_escn.szB % sizeof(ElfXX_Sym)) == 0); -# if defined(VGO_solaris) - vg_assert((ldynsym_escn.szB % sizeof(ElfXX_Sym)) == 0); -# endif /* TOPLEVEL */ /* Read symbols */ { void (*read_elf_symtab)(struct _DebugInfo*, const HChar*, DiSlice*, DiSlice*, DiSlice*, Bool); - Bool symtab_in_debug; # if defined(VGP_ppc64be_linux) read_elf_symtab = read_elf_symtab__ppc64be_linux; # else read_elf_symtab = read_elf_symtab__normal; # endif - symtab_in_debug = symtab_escn.img == dimg; - read_elf_symtab(di, "symbol table", - &symtab_escn, &strtab_escn, &opd_escn, - symtab_in_debug); - read_elf_symtab(di, "dynamic symbol table", - &dynsym_escn, &dynstr_escn, &opd_escn, - False); -# if defined(VGO_solaris) - read_elf_symtab(di, "local dynamic symbol table", - &ldynsym_escn, &dynstr_escn, &opd_escn, - False); -# endif - } - - /* TOPLEVEL */ - /* Read .eh_frame and .debug_frame (call-frame-info) if any. Do - the .eh_frame section(s) first. */ - vg_assert(di->n_ehframe >= 0 && di->n_ehframe <= N_EHFRAME_SECTS); - for (i = 0; i < di->n_ehframe; i++) { - /* see Comment_on_EH_FRAME_MULTIPLE_INSTANCES above for why - this next assertion should hold. */ - vg_assert(ML_(sli_is_valid)(ehframe_escn[i])); - vg_assert(ehframe_escn[i].szB == di->ehframe_size[i]); - ML_(read_callframe_info_dwarf3)( di, - ehframe_escn[i], - di->ehframe_avma[i], - True/*is_ehframe*/ ); + if (symtab_escn.img != NULL) + read_elf_symtab(di, "symbol table", + &symtab_escn, &strtab_escn, &opd_escn, + True); } if (ML_(sli_is_valid)(debug_frame_escn)) { ML_(read_callframe_info_dwarf3)( di, @@ -3643,8 +3780,6 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) if (dimg) ML_(img_done)(dimg); if (aimg) ML_(img_done)(aimg); - if (svma_ranges) VG_(deleteXA)(svma_ranges); - return res; } /* out: */ diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c index c3fa62e96c..3ad114607b 100644 --- a/coregrind/m_debuginfo/storage.c +++ b/coregrind/m_debuginfo/storage.c @@ -1297,8 +1297,7 @@ void ML_(addVar)( struct _DebugInfo* di, that those extra sections have the same bias as .text, but that seems a reasonable assumption to me. */ /* This is assured us by top level steering logic in debuginfo.c, - and it is re-checked at the start of - ML_(read_elf_debug_info). */ + and it is re-checked at the start of ML_(read_elf_object). */ vg_assert(di->fsm.have_rx_map && di->fsm.rw_map_count); if (level > 0 && ML_(find_rx_mapping)(di, aMin, aMax) == NULL) { if (VG_(clo_verbosity) > 1) { @@ -1725,7 +1724,6 @@ static void canonicaliseSymtab ( struct _DebugInfo* di ) for (i = 0; i < di->symtab_used; i++) { DiSym* sym = &di->symtab[i]; vg_assert(sym->pri_name); - vg_assert(!sym->sec_names); } /* Sort by address. */ @@ -2383,6 +2381,9 @@ void ML_(finish_CFSI_arrays) ( struct _DebugInfo* di ) vg_assert (f_holes == n_holes); vg_assert (pos == new_used); + if (di->deferred) + return; + di->cfsi_used = new_used; di->cfsi_size = new_used; ML_(dinfo_free) (di->cfsi_rd); @@ -2398,9 +2399,13 @@ void ML_(canonicaliseTables) ( struct _DebugInfo* di ) canonicaliseLoctab ( di ); canonicaliseInltab ( di ); ML_(canonicaliseCFI) ( di ); + canonicaliseVarInfo ( di ); + + if (di->deferred) + return; + if (di->cfsi_m_pool) VG_(freezeDedupPA) (di->cfsi_m_pool, ML_(dinfo_shrink_block)); - canonicaliseVarInfo ( di ); if (di->strpool) VG_(freezeDedupPA) (di->strpool, ML_(dinfo_shrink_block)); if (di->fndnpool) diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h index 938ed00cc1..ce72462178 100644 --- a/coregrind/pub_core_debuginfo.h +++ b/coregrind/pub_core_debuginfo.h @@ -76,6 +76,10 @@ extern void VG_(di_notify_pdb_debuginfo)( Int fd, Addr avma, extern void VG_(di_notify_vm_protect)( Addr a, SizeT len, UInt prot ); #endif +extern void VG_(addr_load_di)( Addr a ); + +extern void VG_(load_di)( DebugInfo *di, Addr a ); + extern void VG_(di_discard_ALL_debuginfo)( void ); /* Like VG_(get_fnname), but it does not do C++ demangling nor Z-demangling |
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From: Jojo R <rj...@li...> - 2023-08-04 06:04:16
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Hi, We are glad to open source RVV implementation here: https://github.com/rjiejie/valgrind-riscv64 3 kinds extra ISAs were added in this repo: RV64Zfh : Half-precision floating-point RV64Xthead [1] : T-THEAD vendor extension for RV64G RV64V0p7 [2] : Vector 0.7.1 RV64V : Vector 1.x, coming soon :) [1] https://github.com/T-head-Semi/thead-extension-spec [2] https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1 Regards --Jojo 在 2023/7/17 15:05, Jojo R 写道: > > Hi, > > Sorry for the late reply, > > i have been pushing the progress of valgrind RVV implementation 😄 > We finished the first version and tested with full RVV intrinsics spec. > > For real project and developers, we implement the first useable/ full > functionality's RVV valgrind with dirtycall method, > and we will make experiment or optimize RVV implementation on ideal > RVV design. > > Back to the RVV RFC, we are happy to share our thinking of design, see > attachment for more details :) > > Regards > > --Jojo > > 在 2023/4/21 17:25, Jojo R 写道: >> >> Hi, >> >> We consider to add RVV/Vector [1] feature in valgrind, there are some >> challenges. >> RVV like ARM's SVE [2] programming model, it's scalable/VLA, that >> means the vector length is agnostic. >> ARM's SVE is not supported in valgrind :( >> >> There are three major issues in implementing RVV instruction set in >> Valgrind as following: >> >> 1. Scalable vector register width VLENB >> 2. Runtime changing property of LMUL and SEW >> 3. Lack of proper VEX IR to represent all vector operations >> >> We propose applicable methods to solve 1 and 2. As for 3, we explore >> several possible but maybe imperfect approaches to handle different >> cases. >> >> We start from 1. As each guest register should be described in >> VEXGuestState struct, the vector registers with scalable width of >> VLENB can be added into VEXGuestState as arrays using an allowable >> maximum length like 2048/4096. >> >> The actual available access range can be determined at Valgrind >> startup time by querying the CPU for its vector capability or some >> suitable setup steps. >> >> >> To solve problem 2, we are inspired by already-proven techniques in >> QEMU, where translation blocks are broken up when certain critical >> CSRs are set. Because the guest code to IR translation relies on the >> precise value of LMUL/SEW and they may change within a basic block, >> we can break up the basic block each time encountering a vsetvl{i} >> instruction and return to the scheduler to execute the translated >> code and update LMUL/SEW. Accordingly, translation cache management >> should be refactored to detect the changing of LMUL/SEW to invalidate >> outdated code cache. Without losing the generality, the LMUL/SEW >> should be encoded into an ULong flag such that other architectures >> can leverage this flag to store their arch-dependent information. The >> TTentry struct should also take the flag into account no matter >> insertion or deletion. By doing this, the flag carries the newest >> LMUL/SEW throughout the simulation and can be passed to disassemble >> functions using the VEXArchInfo struct such that we can get the real >> and newest value of LMUL and SEW to facilitate our translation. >> >> Also, some architecture-related code should be taken care of. Like >> m_dispatch part, disp_cp_xindir function looks up code cache using >> hardcoded assembly by checking the requested guest state IP and >> translation cache entry address with no more constraints. Many other >> modules should be checked to ensure the in-time update of LMUL/SEW is >> instantly visible to essential parts in Valgrind. >> >> >> The last remaining big issue is 3, which we introduce some ad-hoc >> approaches to deal with. We summarize these approaches into three >> types as following: >> >> 1. Break down a vector instruction to scalar VEX IR ops. >> 2. Break down a vector instruction to fixed-length VEX IR ops. >> 3. Use dirty helpers to realize vector instructions. >> >> The very first method theoretically exists but is probably not >> applicable as the number of IR ops explodes when a large VLENB is >> adopted. Imaging a configuration of VLENB=512, SEW=8, LMUL=8, the VL >> is 512 * 8 / 8 = 512, meaning that a single vector instruction turns >> into 512 scalar instructions and each scalar instruction would be >> expanded to multiple IRs. To make things worse, the tool >> instrumentation will insert more IRs between adjacent scalar IR ops. >> As a result, the performance is likely to be slowed down thousand >> times during running a real-world application with lots of vector >> instructions. Therefore, the other two methods are more promising and >> we will discuss them below. >> >> 2 and 3 are not mutually exclusive as we may choose a suitable method >> from them to implement a vector instruction regarding its concrete >> behavior. To explain these methods in detail, we present some >> instances to illustrate their pros and cons. >> >> In terms of method 2, we have real values of VLENB/LMUL/SEW. The >> simple case is VLENB <= 256 and LMUL=1, where many SIMD IR ops are >> available and can be directly applied to represent vector operations. >> However, even when VLENB is restricted to 128, it still exceeds the >> maximum SIMD width of 256 supported by VEX IR if LMUL>2. Hence, here >> are two variants of method 2 to deal with long vectors: >> >> >> *2.1*Add more SIMD IR ops such as 1024/2048/4096, and translate >> vector instructions in the granularity of VLENB. Accordingly, >> VLENB=4096 with LMUL=2 is fulfilled by two 4096 SIMD VEX IR ops. >> >> * *pros*: it encourages VEX backend to generate more compact and >> efficient SIMD code (maybe). Particularly,it accommodatesmask and >> gather/scatter (indexed) instructions by delivering more >> information in IR itself. >> * *cons*: too many new IR ops need to be introduced in VEX as each >> op of different length should implement its add/sub/mul variants. >> New data types to denote long vectors are necessary too, causing >> difficulties in both VEX backend register allocation and tool >> instrumentation. >> >> *2.2*Break down long vectors to multiple repeated SIMD ops. For >> instance, a vadd.vv vector instruction with VLENB=256/LMUL=2/SEW=8 is >> composed of four operators of Iop_Add8x16 type. >> >> * *pros:*less efforts are required in register allocation and tool >> instrumentation. The VEX frontend is able to notify the backend >> to generate efficient vector instructions by existing Iops. It >> better trades off the complexity of adding many long vector IR >> ops and the benefit of generating high-efficiency host code. >> * *cons:*it is hard to describe a mask operation given that the >> mask is pretty flexible (the least significant bit of each >> segment of v0). Additionally, gather/scatter instructions may >> have similar problems in appropriately dividing index registers. >> There are various corner cases left here such as widening >> arithmetic operations (widening SIMD IR ops are currently not >> compatible) and vstart CSR register. When using fixed-length IR >> ops to comprise a vector instruction, we will inevitably tell >> each IR op which position encoded in vstart you can start to >> process the data. We can use vstart as a normal guest state >> virtual register to calculate each op's start position as a guard >> IRExpr or obtain the value of vstart like what we do in LMUL/SEW. >> Nevertheless, it is non-trivial to decompose a vector instruction >> concisely. >> >> In short, both 2.1 and 2.2 confront a dilemma in reducing engineering >> efforts of refactoring Valgrind elegantly as well as implementing the >> vector instruction set efficiently. Same obstacles exist in ARM SVE >> as they are scalable vector instructions and flexible in many ways. >> >> The final solution is the dirty helper. It is undoubtedly practical >> and requires possibly the least engineering efforts in dealing with >> so many details in Valgrind. In this design, each instruction is >> completed using an inline assembly running the same instruction on >> the host. Moreover, tool instrumentation already handles IRDirty >> except that new fields should be added in _IRDirty struct to indicate >> strided/indexed/masked memory accesses and arithmetic operations. >> >> * *pros:*it supports all instructions without bothering to build >> complicated IR expressions and statements. It executes vector >> instructions using host CPU to get acceleration to some extent. >> Besides, we do not need to add VEX backend to translate new IRs >> to vector instructions. >> * *cons:*the dirty helper always keeps its operations in a black >> box such that tools can never see what happens in a dirty helper. >> Like memcheck, the bit precision merit is missing once it meets a >> dirty helper as the V-bit propagation chain adopts a pretty >> coarse determination strategy. On the other hand, it is also not >> an elegant way to implement the entire ISA extension in dirty >> helpers. >> >> In summary, it is far to reach a truly applicable solution in adding >> vector extensions in Valgrind. We need to do detailed and >> comprehensive estimations on different vector instruction categories. >> >> Any feedback is welcome in github [3] also. >> >> >> [1] https://github.com/riscv/riscv-v-spec >> >> [2] >> https://community.arm.com/arm-research/b/articles/posts/the-arm-scalable-vector-extension-sve >> >> [3] https://github.com/petrpavlu/valgrind-riscv64/issues/17 >> >> >> Thanks. >> >> Jojo >> >> >> >> _______________________________________________ >> Valgrind-developers mailing list >> Val...@li... >> https://lists.sourceforge.net/lists/listinfo/valgrind-developers > > > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
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From: Jojo R <rj...@gm...> - 2023-08-04 05:45:19
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在 2023/7/26 03:55, Petr Pavlu 写道: > On 17. Jul 23 15:05, Jojo R wrote: >> Hi, >> >> Sorry for the late reply, >> >> i have been pushing the progress of valgrind RVV implementation 😄 >> We finished the first version and tested with full RVV intrinsics spec. >> >> For real project and developers, we implement the first useable/ full >> functionality's RVV valgrind with dirtycall method, >> and we will make experiment or optimize RVV implementation on ideal RVV >> design. >> >> Back to the RVV RFC, we are happy to share our thinking of design, see >> attachment for more details :) > This is a good summary. > > As mentioned in another part of the thread, I think that in long run it > will be indeed needed to implement the approach described as "RVV to > variable-length IR". I hope to help with making sure it can work for Arm > SVE too. > > I guess if initial experiments show that this option is hard and will > take time to implement then it could make sense in short term for the > RISC-V port to go with the "RVV to dirty helper" implementation. > > Thanks, > Petr Ok, experiments are helpfull, also we will open souce our RVV implementation soon :) Regards -- Jojo > > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
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From: Feiyang C. <chr...@gm...> - 2023-08-04 03:23:19
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Hi, I want to inquire about the status of my patch. As of now, I haven't received any feedback or response regarding its review or potential inclusion in the upcoming release. I understand that everyone in the team is busy with their respective tasks, but I am eager to know if there are any plans to consider my contribution for integration. Thanks, Feiyang |