valgrind-developers — Discussion list for developers of valgrind

[Valgrind-developers] [valgrind] s390x: Reflect ppno -> prno renaming in opcode checker

[Andreas A. <ar...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=957b7e0a7e0f987baa3482bc607e84b668ce7a00

commit 957b7e0a7e0f987baa3482bc607e84b668ce7a00
Author: Andreas Arnez <ar...@li...>
Date:   Tue Apr 1 16:25:05 2025 +0200

    s390x: Reflect ppno -> prno renaming in opcode checker
    
    After consequently renaming ppno to prno, the tool s390-check-opcodes.pl
    complains:
    
      *** opcode prno is implemented but CSV file does not say so
      *** opcode ppno is not implemented but CSV file says so
      *** opcode ppno is not handled by the decoder
    
    Fix this by renaming to "prno" in s390-opcodes.csv as well and declaring
    "ppno" instead of "prno" as an alias in s390-check-opcodes.pl.

Diff:
---
 auxprogs/s390-check-opcodes.pl  | 2 +-
 docs/internals/s390-opcodes.csv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/auxprogs/s390-check-opcodes.pl b/auxprogs/s390-check-opcodes.pl
index 474bb3a7e8..bd1abc8057 100755
--- a/auxprogs/s390-check-opcodes.pl
+++ b/auxprogs/s390-check-opcodes.pl
@@ -175,7 +175,7 @@ my @extended_mnemonics = (      # Base mnemonic(s)
     "wftci[sdx]b",
     "wfsq*[sdx]b",
     "vl(ed|de)",
-    "prno"                      # ppno
+    "ppno"                      # prno
     );
 
 # Compile excluded mnemonics into one regular expression to optimize
diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv
index e2d69fc996..931d8987cb 100644
--- a/docs/internals/s390-opcodes.csv
+++ b/docs/internals/s390-opcodes.csv
@@ -1343,7 +1343,7 @@ lochi,"load halfword immediate on condition into 32 bit gpr",implemented,z13
 verllvh,"vector element rotate left logical reg halfword",implemented,z13
 cpdt,"convert from long dfp to packed","not implemented",z13
 vrepb,"vector replicate byte","implemented",z13
-ppno,"perform pseudorandom number operation",implemented,z13
+prno,"perform random number operation",implemented,z13
 irbm,"insert reference bits multiple",N/A,"privileged instruction",arch12
 tpei,"test pending external interruption",N/A,"privileged instruction",arch12
 vfeef,"vector find element equal word","implemented",z13

[Valgrind-developers] [valgrind] Bug 498421 - s390x: Add BPP, BPRP, and NIAI insns

[Andreas A. <ar...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6b8148b82580429e6e862d9119669d36a1394446

commit 6b8148b82580429e6e862d9119669d36a1394446
Author: Andreas Arnez <ar...@li...>
Date:   Tue Apr 1 16:25:05 2025 +0200

    Bug 498421 - s390x: Add BPP, BPRP, and NIAI insns
    
    Add support for the branch prediction preload (BPP), branch prediction
    relative preload (BPRP), and next instruction access intent (NIAI)
    instructions.  These instructions just provide performance hints to the
    CPU and have no other effect on program execution.  Thus implement them as
    no-ops.

Diff:
---
 NEWS                                  |  1 +
 VEX/priv/guest_s390_toIR.c            | 78 +++++++++++++++++++++++++++++++++--
 docs/internals/s390-opcodes.csv       |  6 +--
 none/tests/s390x/disasm-test/opcode.c |  7 ++--
 4 files changed, 82 insertions(+), 10 deletions(-)

diff --git a/NEWS b/NEWS
index 7145157f21..b2036da737 100644
--- a/NEWS
+++ b/NEWS
@@ -54,6 +54,7 @@ are not entered into bugzilla tend to get forgotten about or ignored.
 498143  False positive on EVIOCGRAB ioctl
 498317  FdBadUse is not a valid CoreError type in a suppression
         even though it's generated by --gen-suppressions=yes
+498421  s390x: support BPP, BPRP and NIAI insns
 498422  s390x: Fix VLRL and VSTRL insns
 498492  none/tests/amd64/lzcnt64 crashes on FreeBSD compiled with clang
 498629  s390x: Fix S[L]HHHR and S[L]HHLR insns
diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index b870b77fe4..5b16002103 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -104,6 +104,11 @@ typedef enum {
 /*------------------------------------------------------------*/
 
 #define I_i(insn) ((insn) & 0xff)
+#define IE_i1(insn) (((insn) >> 4) & 0xf)
+#define IE_i2(insn) ((insn) & 0xf)
+#define MII_m1(insn) (((insn) >> 52) & 0xf)
+#define MII_i2(insn) (((insn) >> 40) & 0xfff)
+#define MII_i3(insn) (((insn) >> 16) & 0xffffff)
 #define RR_r1(insn) (((insn) >> 4) & 0xf)
 #define RR_r2(insn) ((insn) & 0xf)
 #define RI_r1(insn) (((insn) >> 20) & 0xf)
@@ -143,6 +148,10 @@ typedef enum {
 #define SI_i2(insn) (((insn) >> 16) & 0xff)
 #define SI_b1(insn) (((insn) >> 12) & 0xf)
 #define SI_d1(insn) ((insn) & 0xfff)
+#define SMI_m1(insn) (((insn) >> 52) & 0xf)
+#define SMI_b3(insn) (((insn) >> 44) & 0xf)
+#define SMI_d3(insn) (((insn) >> 32) & 0xfff)
+#define SMI_i2(insn) (((insn) >> 16) & 0xffff)
 #define RIE_r1(insn) (((insn) >> 52) & 0xf)
 #define RIE_r3(insn) (((insn) >> 48) & 0xf)
 #define RIE_i2(insn) (((insn) >> 32) & 0xffff)
@@ -2741,6 +2750,16 @@ s390_format_I(const HChar *(*irgen)(UChar i),
       S390_DISASM(MNM(mnm), UINT(i));
 }
 
+static void
+s390_format_IE(const HChar *(*irgen)(UChar i1, UChar i2),
+               UChar i1, UChar i2)
+{
+   const HChar *mnm = irgen(i1, i2);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(i1), UINT(i2));
+}
+
 static void
 s390_format_E(const HChar *(*irgen)(void))
 {
@@ -2750,6 +2769,19 @@ s390_format_E(const HChar *(*irgen)(void))
       S390_DISASM(MNM(mnm));
 }
 
+static void
+s390_format_MII_UPP(const HChar *(*irgen)(UChar m1, UShort i2, UShort i3),
+                    UChar m1, UShort i2, UShort i3)
+{
+   const HChar *mnm;
+
+   mnm = irgen(m1, i2, i3);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)((Short)(i2 << 4) >> 4)),
+                  PCREL((Int)(Short)i3));
+}
+
 static void
 s390_format_RI(const HChar *(*irgen)(UChar r1, UShort i2),
                UChar r1, UShort i2)
@@ -3653,6 +3685,22 @@ s390_format_SIY_IRD(const HChar *(*irgen)(UChar i2, IRTemp op1addr),
       S390_DISASM(MNM(mnm), SDXB(dh1, dl1, 0, b1), INT((Int)(Char)i2));
 }
 
+static void
+s390_format_SMI_U0RDP(const HChar *(*irgen)(UChar m1, UShort i2, IRTemp op3addr),
+                      UChar m1, UShort i2, UChar b3, UShort d3)
+{
+   const HChar *mnm;
+   IRTemp op3addr = newTemp(Ity_I64);
+
+   assign(op3addr,
+          binop(Iop_Add64, mkU64(d3), b3 != 0 ? get_gpr_dw0(b3) : mkU64(0)));
+
+   mnm = irgen(m1, i2, op3addr);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)(Short)i2), UDXB(d3, 0, b3));
+}
+
 static void
 s390_format_SS_L0RDRD(const HChar *(*irgen)(UChar, IRTemp, IRTemp),
                       UChar l, UChar b1, UShort d1, UChar b2, UShort d2)
@@ -20307,6 +20355,27 @@ s390_irgen_KDSA(UChar r1, UChar r2)
    return "kdsa";
 }
 
+static const HChar *
+s390_irgen_BPP(UChar m1, UShort i2, IRTemp op3addr)
+{
+   /* Treat as a no-op */
+   return "bpp";
+}
+
+static const HChar *
+s390_irgen_BPRP(UChar m1, UShort i2, UShort i3)
+{
+   /* Treat as a no-op */
+   return "bprp";
+}
+
+static const HChar *
+s390_irgen_NIAI(UChar i1, UChar i2)
+{
+   /* Treat as a no-op */
+   return "niai";
+}
+
 /* New insns are added here.
    If an insn is contingent on a facility being installed also
    check whether function do_extension_STFLE needs updating. */
@@ -20667,7 +20736,8 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb2ec: /* ETND */ goto unimplemented;
    case 0xb2ed: /* ECPGA */ goto unimplemented;
    case 0xb2f8: /* TEND */ goto unimplemented;
-   case 0xb2fa: /* NIAI */ goto unimplemented;
+   case 0xb2fa: s390_format_IE(s390_irgen_NIAI, IE_i1(ovl),
+                               IE_i2(ovl));  goto ok;
    case 0xb2fc: /* TABORT */ goto unimplemented;
    case 0xb2ff: /* TRAP4 */ goto unimplemented;
    case 0xb300: s390_format_RRE_FF(s390_irgen_LPEBR, RRE_r1(ovl),
@@ -23295,8 +23365,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
    }
 
    switch (((ovl >> 16) & 0xff0000000000ULL) >> 40) {
-   case 0xc5ULL: /* BPRP */ goto unimplemented;
-   case 0xc7ULL: /* BPP */ goto unimplemented;
+   case 0xc5ULL: s390_format_MII_UPP(s390_irgen_BPRP, MII_m1(ovl), MII_i2(ovl),
+                                     MII_i3(ovl));  goto ok;
+   case 0xc7ULL: s390_format_SMI_U0RDP(s390_irgen_BPP, SMI_m1(ovl), SMI_i2(ovl),
+                                       SMI_b3(ovl), SMI_d3(ovl));  goto ok;
    case 0xd0ULL: /* TRTR */ goto unimplemented;
    case 0xd1ULL: /* MVN */ goto unimplemented;
    case 0xd2ULL: s390_format_SS_L0RDRD(s390_irgen_MVC, SS_l(ovl),
diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv
index 75baaf15ad..e2d69fc996 100644
--- a/docs/internals/s390-opcodes.csv
+++ b/docs/internals/s390-opcodes.csv
@@ -963,10 +963,10 @@ tabort,"transaction abort","not implemented",zEC12,
 tbegin,"transaction begin","not implemented",zEC12,
 tbeginc,"constrained transaction begin","not implemented",zEC12,
 tend,"transaction end","not implemented",zEC12,
-bpp,"branch prediction preload","not implemented",zEC12,
-bprp,"branch prediction relative preload","not implemented",zEC12,
+bpp,"branch prediction preload",implemented,zEC12,
+bprp,"branch prediction relative preload",implemented,zEC12,
 ppa,"perform processor assist","not implemented",zEC12,
-niai,"next instruction access intent","not implemented",zEC12,
+niai,"next instruction access intent",implemented,zEC12,
 crdte,"compare and replace DAT table entry",N/A,"privileged instruction"
 lat,"load and trap 32 bit",implemented,zEC12,
 lgat,"load and trap 64 bit",implemented,zEC12,
diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c
index 8bd53dae9c..993a1fb050 100644
--- a/none/tests/s390x/disasm-test/opcode.c
+++ b/none/tests/s390x/disasm-test/opcode.c
@@ -228,9 +228,8 @@ static const char *opcodes[] = {
    "bxle   r1,r3,d12(b2)",
    "bxleg  r1,r3,d20(b2)",
 
-// FIXME TBD   "bpp    m1,ri2:s16,d12(b3)", // exhi
-// FIXME TBD   "bprp   m1,ri2:s12,ri3:s24", // exhi
-
+   "bpp    i1:u4,ri2:s16,d12(b3)",  // exhi
+   "bprp   i1:u4,ri2:s12,ri3:s24",  // exhi
    "bras   r1,ri2:s16",
    "brasl  r1,ri2:s32",
 
@@ -694,7 +693,7 @@ static const char *opcodes[] = {
    "nnrk   r1,r2,r3",           // mi3
    "nngrk  r1,r2,r3",           // mi3
 
-// FIXME TBD   niai    i1:u4{0:3},i2:u4{0:3}  // exhi   no spec. exc. for i1,i2
+   "niai   i1:u4,i2:u4",        // exhi
 
    // ntstg not implemented

Re: [Valgrind-developers] [PATCH] Linux: Inhibit tail calls in cancellable system calls

[Mark W. <ma...@kl...>]

Hi,

On Fri, Mar 28, 2025 at 07:02:28PM +0100, Mark Wielaard wrote:
> On Fri, 2025-03-21 at 14:01 +0100, Florian Weimer wrote:
> > Without this change, the system call wrapper function is not visible
> > on the stack at the time of the system call, which causes problems
> > for interception tools such as valgrind.
> > 
> > Enhances commit 89b53077d2a58f00e7debdfe58afabe953dac60d ("nptl: Fix
> > Race conditions in pthread cancellation [BZ#12683]").
> > 
> > Tested on i686-linux-gnu, powerpc64le-linux-gnu, x86_64-linux-gnu.
> > (We're still discussing if valgrind needs this, but if it does, here's a
> > patch.)
> 
> I implemented the valgrind part of skipping the syscall_cancel frames
> here: https://bugs.kde.org/show_bug.cgi?id=502126#c2
> And there is a valgrind package build for fedora rawhide:
> https://koji.fedoraproject.org/koji/buildinfo?buildID=2687393
> 
> For ppc64le, s390x and x86_64 that patch seems enough.
> 
> For i686 and aarch64 there does seem to be an issue with missing the
> glibc calling function because of a tail call.
> 
> Also on i686 there is another extra frame on top __libc_do_syscall.

I extended the patch to cover some extra sycall wrapper function
symbols on i386 and armhf and pushed it to valgrind trunk and
VALGRIND_3_24_BRANCH. There are builds for fedora rawhide and
f42. This does seem to show that only on arm64 the tail calls
obscure observing the full call stack.

Cheers,

Mark

[Valgrind-developers] [valgrind] s390x disasm-test: Remove command line flags --d12, --d20, --sint, --uint

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=19b70d658a24903a9f0b179301a0300c1b256646

commit 19b70d658a24903a9f0b179301a0300c1b256646
Author: Florian Krohm <fl...@ei...>
Date:   Sun Mar 30 21:32:37 2025 +0000

    s390x disasm-test: Remove command line flags --d12, --d20, --sint, --uint
    
    These were somewhat useful in the early days of development. Not anymore.

Diff:
---
 none/tests/s390x/disasm-test/README     |  22 ------
 none/tests/s390x/disasm-test/generate.c | 114 +++++++++++++-------------------
 none/tests/s390x/disasm-test/main.c     |  37 -----------
 none/tests/s390x/disasm-test/main.h     |   4 --
 4 files changed, 47 insertions(+), 130 deletions(-)

diff --git a/none/tests/s390x/disasm-test/README b/none/tests/s390x/disasm-test/README
index d04292374a..36485aec33 100644
--- a/none/tests/s390x/disasm-test/README
+++ b/none/tests/s390x/disasm-test/README
@@ -77,28 +77,6 @@ Debugging options
 --debug
   Additional debugging output.
 
---d12=INT
-  Use INT as the value for d12 fields. The given value is checked
-  for feasibility.
-
---d20=INT
-  Use INT as the value for d20 fields. The given value is checked
-  for feasibility.
-
---sint=INT
-  Use INT as the only value for signed integer fields. The given value
-  is NOT checked for feasibility (as the field width is not known).
-  The value is expected to fit in 32 bits (and is complained about
-  if it doesn't), as there are no opcodes with immediate operands
-  that have more than 32 bits.
-
---uint=INT
-  Use INT as the only value for unsigned integer fields. The given value
-  is NOT checked for feasibility (as the field width is not known).
-  The value is expected to fit in 32 bits (and is complained about
-  if it doesn't), as there are no opcodes with immediate operands
-  that have more than 32 bits.
-
 
 Testcase generation
 -------------------
diff --git a/none/tests/s390x/disasm-test/generate.c b/none/tests/s390x/disasm-test/generate.c
index 25bcdae26e..2dc1970425 100644
--- a/none/tests/s390x/disasm-test/generate.c
+++ b/none/tests/s390x/disasm-test/generate.c
@@ -144,14 +144,14 @@ random_sint(unsigned num_bits)
 static unsigned
 d12_value(void)
 {
-   return d12_val_specified ? d12_val : random_uint(12);
+   return random_uint(12);
 }
 
 
 static int
 d20_value(void)
 {
-   return d20_val_specified ? d20_val : random_sint(20);
+   return random_sint(20);
 }
 
 
@@ -160,7 +160,7 @@ uint_value(unsigned num_bits)
 {
    if (num_bits > 32)
       fatal("integer operand > 32 bits not supported\n");
-   return uint_val_specified ? uint_val : random_uint(num_bits);
+   return random_uint(num_bits);
 }
 
 
@@ -169,7 +169,7 @@ sint_value(unsigned num_bits)
 {
    if (num_bits > 32)
       fatal("integer operand > 32 bits not supported\n");
-   return sint_val_specified ? sint_val : random_sint(num_bits);
+   return random_sint(num_bits);
 }
 #endif
 
@@ -338,17 +338,12 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
    case OPND_D12LB:
    case OPND_D12VB:
       if (f->is_displacement) {
-         if (d12_val_specified) {
-            f->assigned_value = d12_val;
+         /* Choose these interesting values */
+         static const long long values[] = { 0, 1, 2, 0xfff };
+
+         for (int i = 0; i < sizeof values / sizeof *values; ++i) {
+            f->assigned_value = values[i];
             iterate(fp, opc, fields, ix + 1);
-         } else {
-            /* Choose these interesting values */
-            static const long long values[] = { 0, 1, 2, 0xfff };
-
-            for (int i = 0; i < sizeof values / sizeof *values; ++i) {
-               f->assigned_value = values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
          }
       } else if (f->is_length) {
          /* Choose these interesting values */
@@ -376,19 +371,14 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
    case OPND_D20B:
    case OPND_D20XB:
       if (f->is_displacement) {
-         if (d20_val_specified) {
-            f->assigned_value = d20_val;
+         /* Choose these interesting values */
+         static const long long values[] = {
+            0, 1, 2, -1, -2, 0x7ffff, -0x80000
+         };
+
+         for (int i = 0; i < sizeof values / sizeof *values; ++i) {
+            f->assigned_value = values[i];
             iterate(fp, opc, fields, ix + 1);
-         } else {
-            /* Choose these interesting values */
-            static const long long values[] = {
-               0, 1, 2, -1, -2, 0x7ffff, -0x80000
-            };
-
-            for (int i = 0; i < sizeof values / sizeof *values; ++i) {
-               f->assigned_value = values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
          }
       } else {
          /* base or index register */
@@ -401,54 +391,44 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
 
    case OPND_SINT:
    case OPND_PCREL:
-      if (sint_val_specified) {
-         f->assigned_value = sint_val;
-         iterate(fp, opc, fields, ix + 1);
+      if (operand->allowed_values == NULL) {
+         /* No constraint: Choose these interesting values */
+         const long long values[] = {
+            0, 1, 2, -1, -2, (1LL << (operand->num_bits - 1)) - 1,
+            -(1LL << (operand->num_bits - 1))
+         };
+
+         for (int i = 0; i < sizeof values / sizeof *values; ++i) {
+            f->assigned_value = values[i];
+            iterate(fp, opc, fields, ix + 1);
+         }
       } else {
-         if (operand->allowed_values == NULL) {
-            /* No constraint: Choose these interesting values */
-            const long long values[] = {
-               0, 1, 2, -1, -2, (1LL << (operand->num_bits - 1)) - 1,
-               -(1LL << (operand->num_bits - 1))
-            };
-
-            for (int i = 0; i < sizeof values / sizeof *values; ++i) {
-               f->assigned_value = values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
-         } else {
-            /* Constraint. Choose only allowed values */
-            unsigned num_val = operand->allowed_values[0];
-            for (int i = 1; i <= num_val; ++i) {
-               f->assigned_value = operand->allowed_values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
+         /* Constraint. Choose only allowed values */
+         unsigned num_val = operand->allowed_values[0];
+         for (int i = 1; i <= num_val; ++i) {
+            f->assigned_value = operand->allowed_values[i];
+            iterate(fp, opc, fields, ix + 1);
          }
       }
       break;
 
    case OPND_UINT:
-      if (uint_val_specified) {
-         f->assigned_value = uint_val;
-         iterate(fp, opc, fields, ix + 1);
+      if (operand->allowed_values == NULL) {
+         /* No constraint: Choose these interesting values */
+         const long long values[] = {
+            0, 1, 2, (1LL << operand->num_bits) - 1
+         };
+
+         for (int i = 0; i < sizeof values / sizeof *values; ++i) {
+            f->assigned_value = values[i];
+            iterate(fp, opc, fields, ix + 1);
+         }
       } else {
-         if (operand->allowed_values == NULL) {
-            /* No constraint: Choose these interesting values */
-            const long long values[] = {
-               0, 1, 2, (1LL << operand->num_bits) - 1
-            };
-
-            for (int i = 0; i < sizeof values / sizeof *values; ++i) {
-               f->assigned_value = values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
-         } else {
-            /* Constraint. Choose only allowed values */
-            unsigned num_val = operand->allowed_values[0];
-            for (int i = 1; i <= num_val; ++i) {
-               f->assigned_value = operand->allowed_values[i];
-               iterate(fp, opc, fields, ix + 1);
-            }
+         /* Constraint. Choose only allowed values */
+         unsigned num_val = operand->allowed_values[0];
+         for (int i = 1; i <= num_val; ++i) {
+            f->assigned_value = operand->allowed_values[i];
+            iterate(fp, opc, fields, ix + 1);
          }
       }
       break;
diff --git a/none/tests/s390x/disasm-test/main.c b/none/tests/s390x/disasm-test/main.c
index 46f55cf4ce..f74dc73894 100644
--- a/none/tests/s390x/disasm-test/main.c
+++ b/none/tests/s390x/disasm-test/main.c
@@ -33,10 +33,6 @@
 #include "main.h"
 
 int verbose, debug, show_spec_exc, show_miscompares;
-int d12_val, d20_val;
-long long uint_val, sint_val;
-int d12_val_specified, d20_val_specified;
-int uint_val_specified, sint_val_specified;
 
 const char *gcc = "gcc";          // path to GCC
 const char *objdump = "objdump";  // path to objdump
@@ -62,10 +58,6 @@ static const char usage[] =
    "    --gcc=/path/to/gcc\n"
    "    --gcc-flags=FLAGS\n"
    "    --objdump=/path/to/objdump\n"
-   "    --d12=INT   - Use INT as value for d12 offsets\n"
-   "    --d20=INT   - Use INT as value for d20 offsets\n"
-   "    --sint=INT  - Use INT as value for signed integer fields\n"
-   "    --uint=INT  - Use INT as value for unsigned integer fields\n"
    "    --keep-temp - Do not remove temporary files\n"
    "    --summary   - Output test generation summary (with --all)\n"
    "    --unit-test - Run unit tests\n"
@@ -73,8 +65,6 @@ static const char usage[] =
    "    --no-show-miscompares - Do not show disassembly miscompares\n"
    ;
 
-static long long get_clo_value(const char *, const char *, long long,
-                               long long);
 static void remove_temp_files(const char *);
 static int  opcode_has_errors(const opcode *);
 
@@ -137,17 +127,6 @@ main(int argc, char *argv[])
          gcc_flags = strchr(clo, '=') + 1;
       } else if (CHECK_CLO(clo, "--objdump=")) {
          objdump = strchr(clo, '=') + 1;
-      } else if (CHECK_CLO(clo, "--d12=")) {
-         d12_val = get_clo_value(clo, "d12", 0, 0xfff);
-      } else if (CHECK_CLO(clo, "--d20=")) {
-         d20_val = get_clo_value(clo, "d20", -0x80000, 0x7ffff);
-      } else if (CHECK_CLO(clo, "--sint=")) {
-         /* Integer field is restricted to 32-bit */
-         long long max = 0x7fffffff;
-         sint_val = get_clo_value(clo, "sint", -max - 1, max);
-      } else if (CHECK_CLO(clo, "--uint=")) {
-         /* Integer field is restricted to 32-bit */
-         uint_val = get_clo_value(clo, "uint", 0, 0xffffffffU);
       } else {
          if (strncmp(clo, "--", 2) == 0)
             fatal("Invalid command line option '%s'\n", clo);
@@ -341,22 +320,6 @@ strnsave(const char *s, unsigned len)
 }
 
 
-static long long
-get_clo_value(const char *clo, const char *field_name, long long min,
-              long long max)
-{
-   long long value;
-
-   const char *p = strchr(clo, '=') + 1;   // succeeds
-
-   if  (sscanf(p, "%lld", &value) != 1)
-      fatal("%s value '%s' is not an integer\n", field_name, p);
-   if (value < min || value > max)
-      fatal("%s value '%lld' is out of range\n", field_name, value);
-   return value;
-}
-
-
 /* Return 1, if the given opcode has at least one invalid operand.
    This indicates that there were parse errors earlier. */
 static int
diff --git a/none/tests/s390x/disasm-test/main.h b/none/tests/s390x/disasm-test/main.h
index f51ad0c0b7..8c51b1dc20 100644
--- a/none/tests/s390x/disasm-test/main.h
+++ b/none/tests/s390x/disasm-test/main.h
@@ -91,10 +91,6 @@ extern int verbose;
 extern int debug;
 extern int show_spec_exc;
 extern int show_miscompares;
-extern int d12_val, d20_val;
-extern long long sint_val, uint_val;
-extern int d12_val_specified, d20_val_specified;
-extern int uint_val_specified, sint_val_specified;
 extern unsigned num_opcodes;
 extern const char *gcc;
 extern const char *gcc_flags;

[Valgrind-developers] [valgrind] s390x disasm-text: Update to support all implemented opcodes

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7f7294dc0f951b4748ea08f40c5ca8a7285befec

commit 7f7294dc0f951b4748ea08f40c5ca8a7285befec
Author: Florian Krohm <fl...@ei...>
Date:   Sun Mar 30 21:20:01 2025 +0000

    s390x disasm-text: Update to support all implemented opcodes
    
    A few opcodes are commented out in opcode.c because test generation
    cannot handle the constraint.
    
    For some opcodes (e.g. fixbra) VEX runs out of memory. Work around
    that by calling vex_reset. Also add a tweak so we won't segfault
    when generating tests for EXRL.

Diff:
---
 none/tests/s390x/disasm-test/README     |   21 +-
 none/tests/s390x/disasm-test/generate.c |   46 +-
 none/tests/s390x/disasm-test/main.h     |    2 +
 none/tests/s390x/disasm-test/opcode.c   | 1310 ++++++++++++++++++++++++++++---
 none/tests/s390x/disasm-test/verify.c   |    2 -
 none/tests/s390x/disasm-test/vex.c      |    8 +-
 none/tests/s390x/disasm-test/vex.h      |    1 -
 7 files changed, 1249 insertions(+), 141 deletions(-)

diff --git a/none/tests/s390x/disasm-test/README b/none/tests/s390x/disasm-test/README
index a771c41c98..d04292374a 100644
--- a/none/tests/s390x/disasm-test/README
+++ b/none/tests/s390x/disasm-test/README
@@ -107,7 +107,7 @@ number of testcases. For example, testing CRB R1,R2,M3,D4(B4)
 exhaustively would produce 16x16x16x12x16 = 786432 testcases. Instead,
 we attempt to create "interesting" testcases. Like so:
 
-- for a VR operand pick a VR at random
+- for an AR, FPR or VR operand pick a register at random
 - for a GPR operand that is not an index or base register pick a GPR
   at random
 - for a GPR that is base or index register, pick r0 and another GPR
@@ -124,12 +124,12 @@ Why are we picking these values? Boundary cases are *always*
 interesting, as is 0. '1' is picked because it is odd and '2' is picked
 because it is even.
 
-Note: if an opcode has more than one GPR operand choose different
-registers. We do this because we want to catch bugs due to mixed up
-registers.
+Note: if an opcode has more than one GPR (without specification) choose
+different registers. We do this because we want to catch bugs due to
+mixed up registers.
 E.g. If the testcase is "brxh r1,r2,8" and s390_disasm produces
 "brxh r2,r1,8" we want to catch that. Obviously, to do so the registers
-need to be different. The same applies to VRs.
+need to be different. The same applies to ARs, FPRs and VRs.
 
 
 Adding a new opcode
@@ -166,8 +166,7 @@ Integration into regression testing
 
 Status
 ------
-Only opcodes with extended mnemonics as identified in Appendix J of the
-Principles of Operation are considered.
+All opcodes which are implemented in valgrind are considered.
 
 
 TODO
@@ -176,11 +175,9 @@ TODO
     to be improved. Several interesting cases involving the T- and Z-bit
     are not considered.
 
-(2) Due to bugs and missing functionality the following miscompares are
-    observed at this point:
-    - all vector opcodes (missing functionality)
-    - c[l][g]rt  (bug in s390_disasm)
-    - bc         (bug in objdump 2.38)
+(2) Different versions of objdump produce slightly different disassembly.
+    In 2.38 base register 0 is written as "%r0". In current binutils git
+    that register will be output as "0".
 
 (3) Generated testcases may cause specification exceptions. This
     happens iff a constraint involves more than one opcode field.
diff --git a/none/tests/s390x/disasm-test/generate.c b/none/tests/s390x/disasm-test/generate.c
index 25d1607047..25bcdae26e 100644
--- a/none/tests/s390x/disasm-test/generate.c
+++ b/none/tests/s390x/disasm-test/generate.c
@@ -52,6 +52,30 @@ gpr_operand(unsigned regno)
 }
 
 
+static const char *
+ar_operand(unsigned regno)
+{
+   static const char *ars[] = {
+      "%a0", "%a1", "%a2",  "%a3",  "%a4",  "%a5",  "%a6",  "%a7",
+      "%a8", "%a9", "%a10", "%a11", "%a12", "%a13", "%a14", "%a15"
+   };
+
+   return ars[regno];
+}
+
+
+static const char *
+fpr_operand(unsigned regno)
+{
+   static const char *fprs[] = {
+      "%f0", "%f1", "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
+      "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15"
+   };
+
+   return fprs[regno];
+}
+
+
 static const char *
 vr_operand(unsigned regno)
 {
@@ -149,7 +173,7 @@ sint_value(unsigned num_bits)
 }
 #endif
 
-/* MASK is a bitvector. For a GPR rk the k'th bit will be set. The
+/* MASK is a bitvector. For an e.g. GPR rk the k'th bit will be set. The
    function returns a register number which has not been used and
    adjusts the bitvector. */
 static unsigned
@@ -187,11 +211,11 @@ write_asm_stmt(FILE *fp, const opcode *opc, const field fields[])
 {
    fprintf(fp, "  asm volatile(\"%s ", opc->name);
 
-   unsigned gpr_mask, vr_mask, regno;
+   unsigned gpr_mask, vr_mask, ar_mask, fpr_mask, regno;
    int inc;
    int needs_comma = 0;
 
-   gpr_mask = vr_mask = 0;
+   gpr_mask = vr_mask = ar_mask = fpr_mask = 0;
    for (int i = 0; i < opc->num_fields; i += inc) {
       const opnd *operand = fields[i].operand;
 
@@ -212,6 +236,18 @@ write_asm_stmt(FILE *fp, const opcode *opc, const field fields[])
             regno = unique_reg(operand->kind, regno, &vr_mask);
          fprintf(fp, "%s", vr_operand(regno));
          break;
+      case OPND_AR:
+         regno = fields[i].assigned_value;
+         if (! operand->allowed_values)
+            regno = unique_reg(operand->kind, regno, &ar_mask);
+         fprintf(fp, "%s", ar_operand(regno));
+         break;
+      case OPND_FPR:
+         regno = fields[i].assigned_value;
+         if (! operand->allowed_values)
+            regno = unique_reg(operand->kind, regno, &fpr_mask);
+         fprintf(fp, "%s", fpr_operand(regno));
+         break;
       case OPND_D12XB:
       case OPND_D20XB: {
          long long d = fields[i].assigned_value;
@@ -291,6 +327,8 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
       }
       break;
 
+   case OPND_AR:
+   case OPND_FPR:
    case OPND_VR:
       choose_reg_and_iterate(fp, opc, operand, fields, ix);
       break;
@@ -454,6 +492,8 @@ generate(FILE *fp, const opcode *opc)
       switch (operand->kind) {
       case OPND_GPR:
       case OPND_VR:
+      case OPND_AR:
+      case OPND_FPR:
       case OPND_SINT:
       case OPND_UINT:
       case OPND_PCREL:
diff --git a/none/tests/s390x/disasm-test/main.h b/none/tests/s390x/disasm-test/main.h
index c988d8874e..f51ad0c0b7 100644
--- a/none/tests/s390x/disasm-test/main.h
+++ b/none/tests/s390x/disasm-test/main.h
@@ -29,6 +29,8 @@
 typedef enum {
    OPND_GPR,
    OPND_VR,
+   OPND_AR,
+   OPND_FPR,
    OPND_D12LB,
    OPND_D12XB,
    OPND_D12VB,
diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c
index daa4899087..8bd53dae9c 100644
--- a/none/tests/s390x/disasm-test/opcode.c
+++ b/none/tests/s390x/disasm-test/opcode.c
@@ -42,6 +42,8 @@
    - 'r[0-9]+' denotes a GPR (4-bit wide unsigned value)
    - 'b[0-9]+' denotes a GPR used as base register
    - 'x[0-9]+' denotes a GPR used as index register
+   - 'a[0-9]+' denotes an AR (4-bit wide unsigned value)
+   - 'f[0-9]+' denotes an FPR (4-bit wide unsigned value)
    - 'v[0-9]+' denotes a VR (5-bit wide unsigned value)
    - 'm[0-9]+' denotes a 4-bit mask (an unsigned value)
    - 'l'       denotes an 8-bit length (an unsigned value)
@@ -66,89 +68,1122 @@
    If you need to specify #bits, signedness and allowed values you
    need to provide those in the order: signedness, #bits, allowed
    values. E.g. i2:s8{-10..42}
+
+   If a set of allowed values is specified for an operand this
+   implies that any other value would cause a specification exception.
+   UNLESS otherwise noted.
+*/
+
+/* List of for hardware facilities.
+   The abbreviated name appears as structured comment in below opcode list to
+   indicate that the opcode is only available when the facility is installed.
+
+   dflt  --> deflate-conversion facility
+   dfp   --> decimal floating point facility
+   diop  --> distinct-operands  == lsc
+   exe   --> execute-extensions
+   eimm  --> extended-immediate facility
+   etf2  --> ETF2-enhancement facility
+   etf3  --> ETF2-enhancement facility
+   exhi  --> execution-hint
+   extr2 --> extended-translation facility 2
+   extr3 --> extended-translation facility 3
+   fgx   --> FPR-GR-transfer facility
+   fpext --> floating-point extension facility
+   fpssh --> floating-point-support-sign-handling  == fgx
+   gie   --> general-instruction-extension facility
+   hiwo  --> high-word  == lsc
+   ia1   --> interlocked-access facility 1
+   lat   --> load-and-trap facility
+   laz   --> load-and-zero-rightmost byte facility
+   lsc   --> load/store-on-condition facility 1  (bit 45)
+             As well as distinct-operands, high-word, population-count,
+             and interlocked-access facility 1
+   lsc2  --> load/store-on-condition facility 2
+   mi1   --> miscellaneous-instruction-extensions facility 1
+   mi2   --> miscellaneous-instruction-extensions facility 2
+   mi3   --> miscellaneous-instruction-extensions facility 3
+   msa4  --> message-security-assist extension 4
+   msa5  --> message-security-assist extension 5
+   msa8  --> message-security-assist extension 8
+   msa9  --> message-security-assist extension 9
+   nnpa  --> neural-network-processing-assist facility
+   pfpo  --> PFPO facility
+   popc  --> population-count facility  == lsc
+   stckf --> STCKF facility
+   stfle --> STFLE facility
+   vx    --> vector facility
+   vxe   --> vector enhancements facility 1
+   vxe2  --> vector enhancements facility 2   implies vxe and vx
+   vxd   --> vector packed decimal facility
 */
+
+/* List of all supported opcodes in the order as defined in
+   Principles of Operations. */
+
 static const char *opcodes[] = {
-   /* Unsorted list of opcodes (other than vector ops)  with
-      extended mnemonics. See also:
-      Appendix J, Principles of Operation */
-   "bic    m1,d20(x2,b2)",
+   // Chapter 7:  General Instructions
+
+   "ar      r1,r2",
+   "agr     r1,r2",
+   "agfr    r1,r2",
+   "ark     r1,r2,r3",          // diop
+   "agrk    r1,r2,r3",          // diop
+   "a       r1,d12(x2,b2)",
+   "ay      r1,d20(x2,b2)",
+   "ag      r1,d20(x2,b2)",
+   "agf     r1,d20(x2,b2)",
+
+   "afi     r1,i2:s32",         // eimm
+   "agfi    r1,i2:s32",         // eimm
+   "ahik    r1,r3,i2:s16",      // diop
+   "aghik   r1,r3,i2:s16",      // diop
+   "asi     d20(b2),i2:s8",     // gie
+   "agsi    d20(b2),i2:s8",     // gie
+
+   "ah      r1,d12(x2,b2)",
+   "ahy     r1,d20(x2,b2)",
+   "agh     r1,d20(x2,b2)",     // mi2
+
+   "ahi     r1,i2:s16",
+   "aghi    r1,i2:s16",
+
+   "ahhhr   r1,r2,r3",          // hiwo
+   "ahhlr   r1,r2,r3",          // hiwo
+
+   "aih     r1,i2:s32",         // hiwo
+
+   "alr     r1,r2",
+   "algr    r1,r2",
+   "algfr   r1,r2",
+   "alrk    r1,r2,r3",          // diop
+   "algrk   r1,r2,r3",          // diop
+   "al      r1,d12(x2,b2)",
+   "aly     r1,d20(x2,b2)",
+   "alg     r1,d20(x2,b2)",
+   "algf    r1,d20(x2,b2)",
+
+   "alfi    r1,i2:u32",         // eimm
+   "algfi   r1,i2:u32",         // eimm
+
+   "alhhhr  r1,r2,r3",          // hiwo
+   "alhhlr  r1,r2,r3",          // hiwo
+
+   "alcr    r1,r2",
+   "alcgr   r1,r2",
+   "alc     r1,d20(x2,b2)",
+   "alcg    r1,d20(x2,b2)",
+
+   "alsi    d20(b1),i2:s8",     // gie
+   "algsi   d20(b1),i2:s8",     // gie
+   "alhsik  r1,r3,i2:s16",      // diop
+   "alghsik r1,r3,i2:s16",      // diop
+
+   "alsih   r1,i2:s32",         // hiwo
+   "alsihn  r1,i2:s32",         // hiwo
+
+   "nr      r1,r2",
+   "ngr     r1,r2",
+   "nrk     r1,r2,r3",          // diop
+   "ngrk    r1,r2,r3",          // diop
+   "n       r1,d12(x2,b2)",
+   "ny      r1,d20(x2,b2)",
+   "ng      r1,d20(x2,b2)",
+   "ni      d12(b1),i2:u8",
+   "niy     d20(b1),i2:u8",
+   "nc      d12(l,b1),d12(b2)",
+
+   "nihf    r1,i2:u32",         // eimm
+   "nihh    r1,i2:u16",
+   "nihl    r1,i2:u16",
+   "nilf    r1,i2:u32",         // eimm
+   "nilh    r1,i2:u16",
+   "nill    r1,i2:u16",
+
+   "ncrk    r1,r2,r3",          // mi3
+   "ncgrk   r1,r2,r3",          // mi3
+
+   // balr   not implemented
+   // bal    not implemented
+
+   "basr   r1,r2",
+   "bas    r1,d12(x2,b2)",
+
+   // bassm  not implemented
+   // bsm    not implemented
+
+   "bic    m1,d20(x2,b2)",      // mi2
+
    "bcr    m1,r2",
    "bc     m1,d12(x2,b2)",
+
+   "bctr   r1,r2",
+   "bctgr  r1,r2",
+   "bct    r1,d12(x2,b2)",
+   "bctg   r1,d20(x2,b2)",
+
+   "bxh    r1,r3,d12(b2)",
+   "bxhg   r1,r3,d20(b2)",
+
+   "bxle   r1,r3,d12(b2)",
+   "bxleg  r1,r3,d20(b2)",
+
+// FIXME TBD   "bpp    m1,ri2:s16,d12(b3)", // exhi
+// FIXME TBD   "bprp   m1,ri2:s12,ri3:s24", // exhi
+
    "bras   r1,ri2:s16",
    "brasl  r1,ri2:s32",
+
    "brc    m1,ri2:s16",
+
    "brcl   m1,ri2:s32",
+
    "brct   r1,ri2:s16",
    "brctg  r1,ri2:s16",
-   "brcth  r1,ri2:s32",
+
+   "brcth  r1,ri2:s32",         // hiwo
+
    "brxh   r1,r3,ri2:s16",
    "brxhg  r1,r3,ri2:s16",
+
    "brxle  r1,r3,ri2:s16",
    "brxlg  r1,r3,ri2:s16",
-   "crb    r1,r2,m3,d12(b4)",
-   "cgrb   r1,r2,m3,d12(b4)",
-   "crj    r1,r2,m3,ri4:s16",
-   "cgrj   r1,r2,m3,ri4:s16",
-   "crt    r1,r2,m3",
-   "cgrt   r1,r2,m3",
-   "cib    r1,i2:s8,m3,d12(b4)",
-   "cgib   r1,i2:s8,m3,d12(b4)",
-   "cij    r1,i2:s8,m3,ri4:s16",
-   "cgij   r1,i2:s8,m3,ri4:s16",
-   "cit    r1,i2:s16,m3",
-   "cgit   r1,i2:s16,m3",
-   "clrb   r1,r2,m3,d12(b4)",
-   "clgrb  r1,r2,m3,d12(b4)",
-   "clrj   r1,r2,m3,ri4:s16",
-   "clgrj  r1,r2,m3,ri4:s16",
-   "clrt   r1,r2,m3",
-   "clgrt  r1,r2,m3",
-   "clt    r1,m3,d20(b2)",
-   "clgt   r1,m3,d20(b2)",
-   "clib   r1,i2:u8,m3,d12(b4)",
-   "clgib  r1,i2:u8,m3,d12(b4)",
-   "clij   r1,i2:u8,m3,ri4:s16",
-   "clgij  r1,i2:u8,m3,ri4:s16",
+
+   "cksm   r1,r2:{0,2,4,6,8,10,12,14}",
+
+   "km     r1:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",   // msa
+   "kmc    r1:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",   // msa
+   "kma    r1:{2,4,6,8,10,12,14},r3:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",  // also: r3 != r1 && r3 != r2  // msa8
+   "kmf    r1:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",   // msa4
+   "kmctr  r1:{2,4,6,8,10,12,14},r3:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",  // msa4
+   "kmo    r1:{2,4,6,8,10,12,14},r2:{2,4,6,8,10,12,14}",   // msa4
+
+   "cr     r1,r2",
+   "cgr    r1,r2",
+   "cgfr   r1,r2",
+   "c      r1,d12(x2,b2)",
+   "cy     r1,d20(x2,b2)",
+   "cg     r1,d20(x2,b2)",
+   "cgf    r1,d20(x2,b2)",
+
+   "cfi    r1,i2:s32",                  // eimm
+   "cgfi   r1,i2:s32",                  // eimm
+
+   "crl    r1,ri2:s32",                 // gie
+   "cgrl   r1,ri2:s32",                 // gie
+   "cgfrl  r1,ri2:s32",                 // gie
+
+   "crb    r1,r2,m3,d12(b4)",           // gie
+   "cgrb   r1,r2,m3,d12(b4)",           // gie
+
+   "crj    r1,r2,m3,ri4:s16",           // gie
+   "cgrj   r1,r2,m3,ri4:s16",           // gie
+
+   "cib    r1,i2:s8,m3,d12(b4)",        // gie
+   "cgib   r1,i2:s8,m3,d12(b4)",        // gie
+
+   "cij    r1,i2:s8,m3,ri4:s16",        // gie
+   "cgij   r1,i2:s8,m3,ri4:s16",        // gie
+
+   // cfc  not implemented
+
+   "cs     r1,r3,d12(b2)",
+   "csy    r1,r3,d20(b2)",
+   "csg    r1,r3,d20(b2)",
+
+   "cds    r1:{0,2,4,6,8,10,12,14},r3:{0,2,4,6,8,10,12,14},d12(b2)",
+   "cdsy   r1:{0,2,4,6,8,10,12,14},r3:{0,2,4,6,8,10,12,14},d20(b2)",
+   "cdsg   r1:{0,2,4,6,8,10,12,14},r3:{0,2,4,6,8,10,12,14},d20(b2)",
+
+   // csst not implemented
+
+   "crt    r1,r2,m3",                   // gie
+   "cgrt   r1,r2,m3",                   // gie
+
+   "cit    r1,i2:s16,m3",               // gie
+   "cgit   r1,i2:s16,m3",               // gie
+
+   "ch     r1,d12(x2,b2)",
+   "chy    r1,d20(x2,b2)",
+   "cgh    r1,d20(x2,b2)",              // gie
+
+   "chi    r1,i2:s16",
+   "cghi   r1,i2:s16",
+   "chhsi  d12(b1),i2:s16",             // gie
+   "chsi   d12(b1),i2:s16",             // gie
+   "cghsi  d12(b1),i2:s16",             // gie
+
+   "chrl   r1,ri2:s32",                 // gie
+   "cghrl  r1,ri2:s32",                 // gie
+
+   "chhr   r1,r2",                      // hiwo
+   "chlr   r1,r2",                      // hiwo
+   "chf    r1,d20(x2,b2)",              // hiwo
+
+   "cih    r1,i2:s32",                  // hiwo
+
+   "clr    r1,r2",
+   "clgr   r1,r2",
+   "clgfr  r1,r2",
+   "cl     r1,d12(x2,b2)",
+   "cly    r1,d20(x2,b2)",
+   "clg    r1,d20(x2,b2)",
+   "clgf   r1,d20(x2,b2)",
+   "clc    d12(l,b1),d12(b2)",
+
+   "clfi   r1,i2:u32",                  // eimm
+   "clgfi  r1,i2:u32",                  // eimm
+   "cli    d12(b1),i2:u8",
+   "cliy   d20(b1),i2:u8",
+   "clfhsi d12(b1),i2:u16",             // gie
+   "clghsi d12(b1),i2:u16",             // gie
+   "clhhsi d12(b1),i2:u16",             // gie
+
+   "clrl   r1,ri2:s32",                 // gie
+   "clgrl  r1,ri2:s32",                 // gie
+   "clgfrl r1,ri2:s32",                 // gie
+   "clhrl  r1,ri2:s32",                 // gie
+   "clghrl r1,ri2:s32",                 // gie
+
+   "clrb   r1,r2,m3,d12(b4)",           // gie
+   "clgrb  r1,r2,m3,d12(b4)",           // gie
+
+   "clrj   r1,r2,m3,ri4:s16",           // gie
+   "clgrj  r1,r2,m3,ri4:s16",           // gie
+
+   "clib   r1,i2:u8,m3,d12(b4)",        // gie
+   "clgib  r1,i2:u8,m3,d12(b4)",        // gie
+
+   "clij   r1,i2:u8,m3,ri4:s16",        // gie
+   "clgij  r1,i2:u8,m3,ri4:s16",        // gie
+
+   "clrt   r1,r2,m3",                   // gie
+   "clgrt  r1,r2,m3",                   // gie
+   "clt    r1,m3,d20(b2)",              // mi1
+   "clgt   r1,m3,d20(b2)",              // mi1
+
    "clfit  r1,i2:u16,m3",
    "clgit  r1,i2:u16,m3",
-   "iilf   r1,i2:u32",
-   "lochhi r1,i2:s16,m3",
-   "lochi  r1,i2:s16,m3",
-   "locghi r1,i2:s16,m3",
-   "locfhr r1,r2,m3",
-   "locfh  r1,d20(b2),m3",
-   "llilf  r1,i2:u32",
-   "locr   r1,r2,m3",
-   "locgr  r1,r2,m3",
-   "loc    r1,d20(b2),m3",
-   "locg   r1,d20(b2),m3",
-   "nork   r1,r2,r3",
-   "nogrk  r1,r2,r3",
-   "rnsbg  r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  un/signed  i3/4/5 ? t-bit ? z-bit?
-   "rxsbg  r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "risbg  r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "risbgn r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "risbhg r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "risblg r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "rosbg  r1,r2,i3:u8,i4:u8,i5:u8",  // FIXME  ditto
-   "selr   r1,r2,r3,m4",
-   "selgr  r1,r2,r3,m4",
-   "selfhr r1,r2,r3,m4",
-   "stocfh r1,d20(b2),m3",
-   "stoc   r1,d20(b2),m3",
-   "stocg  r1,d20(b2),m3",
-
-   /* Misc. other opcodes */
-   "cksm  r1,r2",   // make sure, it gets disassmbled (BZ 495817)
-   "clcl  r1,r2",   // make sure, it gets disassmbled (BZ 495817)
-   "mvcl  r1,r2",   // make sure, it gets disassmbled (BZ 495817)
-
-   // If a set of allowed values is specified for an operand this
-   // implies that any other value would cause a specification exception.
-   // UNLESS otherwise noted.
+
+   "clm    r1,m3,d12(b2)",
+   "clmy   r1,m3,d20(b2)",
+   "clmh   r1,m3,d20(b2)",
+
+   "clhhr  r1,r2",                      // hiwo
+   "clhlr  r1,r2",                      // hiwo
+   "clhf   r1,d20(x2,b2)",              // hiwo
+
+   "clih   r1,i2:u32",                  // hiwo
+
+   "clcl   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14}",
+
+   "clcle  r1:{0,2,4,6,8,10,12,14},r3:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   // clclu not implemented
+
+   "clst   r1,r2",
+
+   // cuse  not implemented
+   // cmpsc not implemented
+
+   "kimd   r1,r2:{2,4,6,8,10,12,14}",   // msa
+   "klmd   r1,r2:{2,4,6,8,10,12,14}",   // msa
+   "kmac   r1,r2:{2,4,6,8,10,12,14}",   // msa
+
+   "cvb    r1,d12(x2,b2)",
+   "cvby   r1,d20(x2,b2)",
+   // cvbg not implemented
+
+   "cvd    r1,d12(x2,b2)",
+   "cvdy   r1,d20(x2,b2)",
+   // cvdg not implemented
+
+   "cu24   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14},m3:{0,1}",  // extr3
+
+   "cu21   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14},m3:{0,1}",
+
+   "cu42   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14}",           // extr3
+   "cu41   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14}",           // extr3
+
+   "cu12   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14},m3:{0,1}",
+
+   "cu14   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14},m3:{0,1}",  // extr3
+
+   "cpya   a1,a2",
+
+   "dr     r1:{0,2,4,6,8,10,12,14},r2",
+   "d      r1:{0,2,4,6,8,10,12,14},d12(x2,b2)",
+
+   "dlr    r1:{0,2,4,6,8,10,12,14},r2",
+   "dlgr   r1:{0,2,4,6,8,10,12,14},r2",
+   "dl     r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+   "dlg    r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+
+   "dsgr   r1:{0,2,4,6,8,10,12,14},r2",
+   "dsgfr  r1:{0,2,4,6,8,10,12,14},r2",
+   "dsg    r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+   "dsgf   r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+
+   "xr     r1,r2",
+   "xgr    r1,r2",
+   "xrk    r1,r2,r3",           // diop
+   "xgrk   r1,r2,r3",           // diop
+   "x      r1,d12(x2,b2)",
+   "xy     r1,d20(x2,b2)",
+   "xg     r1,d20(x2,b2)",
+   "xi     d12(b1),i2:u8",
+   "xiy    d20(b1),i2:u8",
+   "xc     d12(l,b1),d12(b2)",
+
+   "xihf   r1,i2:u32",          // eimm
+   "xilf   r1,i2:u32",          // eimm
+
+   "ex     r1,d12(x2,b2)",
+
+   "exrl   r1,ri2:s32",         // exe
+
+   "ear    r1,a2",
+
+   "ecag   r1,r3,d20(b2)",      // gie
+
+   // ectg  not implemented
+   // epsw  not implemented
+   // etnd  not implemented
+
+   "flogr  r1:{0,2,4,6,8,10,12,14},r2",          // eimm
+
+   "ic     r1,d12(b2,x2)",
+   "icy    r1,d20(b2,x2)",
+
+   "icm    r1,m3,d12(b2)",
+   "icmy   r1,m3,d20(b2)",
+   "icmh   r1,m3,d20(b2)",
+
+   "iihf   r1,i2:u32",          // eimm
+   "iihh   r1,i2:u8",
+   "iihl   r1,i2:u8",
+   "iilf   r1,i2:u32",          // eimm
+   "iilh   r1,i2:u8",
+   "iill   r1,i2:u8",
+
+   "ipm    r1",
+
+   "lr     r1,r2",
+   "lgr    r1,r2",
+   "lgfr   r1,r2",
+   "l      r1,d12(x2,b2)",
+   "ly     r1,d20(x2,b2)",
+   "lg     r1,d20(x2,b2)",
+   "lgf    r1,d20(x2,b2)",
+
+   "lgfi   r1,i2:s32",          // eimm
+
+   "lrl    r1,i2:s32",          // gie
+   "lgrl   r1,i2:s32",          // gie
+   "lgfrl  r1,i2:s32",          // gie
+
+   "lam    a1,a3,d12(b2)",
+   "lamy   a1,a3,d20(b2)",
+
+   "la     r1,d12(x2,b2)",
+   "lay    r1,d20(x2,b2)",
+
+   "lae    r1,d12(x2,b2)",
+   "laey   r1,d20(x2,b2)",      // gie
+
+   "larl   r1,ri2:s32",
+
+   "laa    r1,r3,d20(b2)",      // ia1
+   "laag   r1,r3,d20(b2)",      // ia1
+
+   "laal   r1,r3,d20(b2)",      // ia1
+   "laalg  r1,r3,d20(b2)",      // ia1
+
+   "lan    r1,r3,d20(b2)",      // ia1
+   "lang   r1,r3,d20(b2)",      // ia1
+
+   "lax    r1,r3,d20(b2)",      // ia1
+   "laxg   r1,r3,d20(b2)",      // ia1
+
+   "lao    r1,r3,d20(b2)",      // ia1
+   "laog   r1,r3,d20(b2)",      // ia1
+
+   "ltr    r1,r2",
+   "ltgr   r1,r2",
+   "ltgfr  r1,r2",
+   "lt     r1,d20(x2,b2)",      // eimm
+   "ltg    r1,d20(x2,b2)",      // eimm
+   "ltgf   r1,d20(x2,b2)",      // gie
+
+   "lat    r1,d20(x2,b2)",      // lat
+   "lgat   r1,d20(x2,b2)",      // lat
+
+   "lzrf   r1,d20(x2,b2)",      // laz
+   "lzrg   r1,d20(x2,b2)",      // laz
+
+   "lbr    r1,r2",              // eimm
+   "lgbr   r1,r2",              // eimm
+   "lb     r1,d20(x2,b2)",
+   "lgb    r1,d20(x2,b2)",
+
+   "lbh    r1,d20(x2,b2)",      // hiwo
+
+   "lcr    r1,r2",
+   "lcgr   r1,r2",
+   "lcgfr  r1,r2",
+
+   "lcbb   r1,d12(x2,b2),m3:{0..6}",    // vx
+
+   // lgg    not implemented
+   // llgfsg not implemented
+   // lgsc   not implemented
+
+   "lhr    r1,r2",              // eimm
+   "lghr   r1,r2",              // eimm
+   "lh     r1,d12(x2,b2)",
+   "lhy    r1,d20(x2,b2)",
+   "lgh    r1,d20(x2,b2)",
+
+   "lhi    r1,i2:s16",
+   "lghi   r1,i2:s16",
+   "lhrl   r1,ri2:s32",         // gie
+   "lghrl  r1,ri2:s32",         // gie
+
+   "lhh    r1,d20(x2,b2)",      // hiwo
+
+   "lochi  r1,i2:s16,m3",       // lsc2
+   "locghi r1,i2:s16,m3",       // lsc2
+
+   "lochhi r1,i2:s16,m3",       // lsc2
+
+   "lfh    r1,d20(x2,b2)",      // hiwo
+
+   "lfhat  r1,d20(x2,b2)",      // lat
+
+   "llgfr  r1,r2",
+   "llgf   r1,d20(x2,b2)",
+
+   "llgfrl r1,ri2:s32",         // gie
+
+   "llgfat r1,d20(x2,b2)",
+
+   "llzrgf r1,d20(x2,b2)",      // laz
+
+   "llcr   r1,r2",              // gie
+   "llgcr  r1,r2",              // gie
+   "llc    r1,d20(x2,b2)",      // gie
+   "llgc   r1,d20(x2,b2)",
+
+   "llch   r1,d20(x2,b2)",      // hiwo
+
+   "llhr   r1,r2",              // eimm
+   "llghr  r1,r2",              // eimm
+   "llh    r1,d20(x2,b2)",      // eimm
+   "llgh   r1,d20(x2,b2)",
+
+   "llhrl  r1,ri2:s32",         // gie
+   "llghrl r1,ri2:s32",         // gie
+
+   "llhh   r1,d20(x2,b2)",      // hiwo
+
+   "llihf  r1,i2:u32",          // eimm
+   "llihh  r1,i2:u16",
+   "llihl  r1,i2:u16",
+   "llilf  r1,i2:u32",          // eimm
+   "llilh  r1,i2:u16",
+   "llill  r1,i2:u16",
+
+   "llgtr  r1,r2",
+   "llgt   r1,d20(x2,b2)",
+
+   "llgtat r1,d20(x2,b2)",      // lat
+
+   "lm     r1,r3,d12(b2)",
+   "lmy    r1,r3,d20(b2)",
+   "lmg    r1,r3,d20(b2)",
+
+   // lmd  not implemented
+
+   "lmh    r1,r3,d20(b2)",
+
+   "lnr    r1,r2",
+   "lngr   r1,r2",
+   "lngfr  r1,r2",
+
+   "locr   r1,r2,m3",           // lsc
+   "locgr  r1,r2,m3",           // lsc
+   "loc    r1,d20(b2),m3",      // lsc
+   "locg   r1,d20(b2),m3",      // lsc
+
+   "locfhr r1,r2,m3",           // lsc2
+   "locfh  r1,d20(b2),m3",      // lsc2
+
+   // lpd   not implemented
+   // lpdg  not implemented
+
+   "lpq    r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+
+   "lpr    r1,r2",
+   "lpgr   r1,r2",
+   "lpgfr  r1,r2",
+
+   "lrvr   r1,r2",
+   "lrvgr  r1,r2",
+   "lrvh   r1,d20(x2,b2)",
+   "lrv    r1,d20(x2,b2)",
+   "lrvg   r1,d20(x2,b2)",
+
+   // mc   not implemented
+
+   "mvc    d12(l,b1),d12(b2)",
+   "mvhhi  d12(b2),i2:s16",             // gie
+   "mvhi   d12(b2),i2:s16",             // gie
+   "mvghi  d12(b2),i2:s16",             // gie
+   "mvi    d12(b2),i2:u8",
+   "mviy   d20(b2),i2:u8",
+
+   "mvcin  d12(l,b1),d12(b2)",
+
+   "mvcl   r1:{0,2,4,6,8,10,12,14},r2:{0,2,4,6,8,10,12,14}",
+
+   "mvcle  r1:{0,2,4,6,8,10,12,14},r3:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   // mvclu  not implemented
+   // mvn    not implemented
+
+   "mvcrl  d12(b1),d12(b2)",            // mi3
+
+   "mvst   r1,r2",
+
+   // mvo    not implemented
+   // mvz    not implemented
+
+   "mr     r1:{0,2,4,6,8,10,12,14},r2",
+   "mgrk   r1:{0,2,4,6,8,10,12,14},r2,r3",              // mi2
+   "m      r1:{0,2,4,6,8,10,12,14},d12(x2,b2)",
+   "mfy    r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",         // gie
+   "mg     r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",         // mi2
+
+   "mh     r1,d12(x2,b2)",
+   "mhy    r1,d20(x2,b2)",              // gie
+   "mgh    r1,d20(x2,b2)",              // mi2
+
+   "mhi    r1,i2:s16",
+   "mghi   r1,i2:s16",
+
+   "mlr    r1:{0,2,4,6,8,10,12,14},r2",
+   "mlgr   r1:{0,2,4,6,8,10,12,14},r2",
+   "ml     r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+   "mlg    r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+
+   "msr    r1,r2",
+   "msrkc  r1,r2,r3",           // mi2
+   "msgr   r1,r2",
+   "msgrkc r1,r2,r3",           // mi2
+   "msgfr  r1,r2",
+   "ms     r1,d12(x2,b2)",
+   "msc    r1,d20(x2,b2)",      // mi2
+   "msy    r1,d20(x2,b2)",
+   "msg    r1,d20(x2,b2)",
+   "msgc   r1,d20(x2,b2)",      // mi2
+   "msgf   r1,d20(x2,b2)",
+
+   "msfi   r1,i2:s32",          // gie
+   "msgfi  r1,i2:s32",          // gie
+
+   "nnrk   r1,r2,r3",           // mi3
+   "nngrk  r1,r2,r3",           // mi3
+
+// FIXME TBD   niai    i1:u4{0:3},i2:u4{0:3}  // exhi   no spec. exc. for i1,i2
+
+   // ntstg not implemented
+
+   "nork   r1,r2,r3",           // mi3
+   "nogrk  r1,r2,r3",           // mi3
+
+   "nxrk   r1,r2,r3",           // mi3
+   "nxgrk  r1,r2,r3",           // mi3
+
+   "or     r1,r2",
+   "ogr    r1,r2",
+   "ork    r1,r2,r3",           // diop
+   "ogrk   r1,r2,r3",           // diop
+   "o      r1,d12(x2,b2)",
+   "oy     r1,d20(x2,b2)",
+   "og     r1,d20(x2,b2)",
+   "oi     d12(b1),i2:u8",
+   "oiy    d20(b1),i2:u8",
+   "oc     d12(l,b1),d12(b2)",
+
+   "oihf   r1,i2:u32",          // eimm
+   "oihh   r1,i2:u16",
+   "oihl   r1,i2:u16",
+   "oilf   r1,i2:u32",          // eimm
+   "oilh   r1,i2:u16",
+   "oill   r1,i2:u16",
+
+   "ocrk   r1,r2,r3",           // mi3
+   "ocgrk  r1,r2,r3",           // mi3
+
+   // pack  not implemented
+   // pka   not implemented
+   // pku   not implemented
+
+   "pcc",                       // msa4
+
+   // plo   not implemented
+   // ppa   not implemented
+
+   "ppno   r1,r2",              // msa5
+   "prno   r1,r2",              // msa5
+
+   "popcnt r1,r2,m3:{0,8}",     // popc    no spec exception for m3
+
+   "pfd    m1,d20(x2,b2)",      // gie
+   "pfdrl  m1,ri2:s32",         // gie
+
+   "rll    r1,r3,d20(b2)",
+   "rllg   r1,r3,d20(b2)",
+
+   "rnsbg  r1,r2,i3:u8,i4:u8,i5:u8",  // gie FIXME  un/signed  i3/4/5 ? t-bit ? z-bit?
+   "rxsbg  r1,r2,i3:u8,i4:u8,i5:u8",  // gie FIXME  ditto
+   "rosbg  r1,r2,i3:u8,i4:u8,i5:u8",  // gie FIXME  ditto
+
+   "risbg  r1,r2,i3:u8,i4:u8,i5:u8",  // gie FIXME  ditto
+   "risbgn r1,r2,i3:u8,i4:u8,i5:u8",  // mi1 FIXME  ditto
+
+   "risbhg r1,r2,i3:u8,i4:u8,i5:u8",  // hiwo FIXME  ditto
+   "risblg r1,r2,i3:u8,i4:u8,i5:u8",  // hiwo FIXME  ditto
+
+   "srst   r1,r2",
+
+   // srstu not implemented
+
+   "selr   r1,r2,r3,m4",               // mi3
+   "selgr  r1,r2,r3,m4",               // mi3
+
+   "selfhr r1,r2,r3,m4",               // mi3
+
+   "sar    a1,r2",
+
+   // sam24  not implemented
+   // sam31  not implemented
+   // sam64  not implemented
+   // spm    not implemented
+
+   "slda   r1:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   "sldl   r1:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   "sla    r1,d12(b2)",
+   "slak   r1,r3,d20(b2)",      // diop
+   "slag   r1,r3,d20(b2)",
+
+   "sll    r1,d12(b2)",
+   "sllk   r1,r3,d20(b2)",      // diop
+   "sllg   r1,r3,d20(b2)",
+
+   "srda   r1:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   "srdl   r1:{0,2,4,6,8,10,12,14},d12(b2)",
+
+   "sra    r1,d12(b2)",
+   "srak   r1,r3,d20(b2)",      // diop
+   "srag   r1,r3,d20(b2)",
+
+   "srl    r1,d12(b2)",
+   "srlk   r1,r3,d20(b2)",      // diop
+   "srlg   r1,r3,d20(b2)",
+
+   "st     r1,d12(x2,b2)",
+   "sty    r1,d20(x2,b2)",
+   "stg    r1,d20(x2,b2)",
+
+   "strl   r1,ri2:s32",         // gie
+   "stgrl  r1,ri2:s32",         // gie
+
+   "stam   a1,a3,d12(b2)",
+   "stamy  a1,a3,d20(b2)",
+
+   "stc    r1,d12(x2,b2)",
+   "stcy   r1,d20(x2,b2)",
+
+   "stch   r1, d20(x2,b2)",     // hiwo
+
+   "stcm   r1,m3,d12(b2)",
+   "stcmy  r1,m3,d20(b2)",
+   "stcmh  r1,m3,d20(b2)",
+
+   "stck   d12(b2)",
+   "stckf  d12(b2)",            // stckf
+   "stcke  d12(b2)",
+
+   "stfle  d12(b2)",            // stfle
+
+   // stgsc  not implemented
+
+   "sth    r1,d12(x2,b2)",
+   "sthy   r1,d20(x2,b2)",
+
+   "sthrl  r1,ri2:s32",         // gie
+
+   "sthh   r1,d20(x2,b2)",      // hiwo
+
+   "stfh   r1,d20(x2,b2)",      // hiwo
+
+   "stm    r1,r3,d12(b2)",
+   "stmy   r1,r3,d20(b2)",
+   "stmg   r1,r3,d20(b2)",
+
+   "stmh   r1,r3,d20(b2)",
+
+   "stoc   r1,d20(b2),m3",      // lsc
+   "stocg  r1,d20(b2),m3",      // lsc
+
+   "stocfh r1,d20(b2),m3",      // lsc2
+
+   "stpq   r1:{0,2,4,6,8,10,12,14},d20(x2,b2)",
+
+   "strvh  r1,d20(x2,b2)",
+   "strv   r1,d20(x2,b2)",
+   "strvg  r1,d20(x2,b2)",
+
+   "sr     r1,r2",
+   "sgr    r1,r2",
+   "sgfr   r1,r2",
+   "srk    r1,r2,r3",           // diop
+   "sgrk   r1,r2,r3",           // diop
+   "s      r1,d12(x2,b2)",
+   "sy     r1,d20(x2,b2)",
+   "sg     r1,d20(x2,b2)",
+   "sgf    r1,d20(x2,b2)",
+
+   "sh     r1,d12(x2,b2)",
+   "shy    r1,d20(x2,b2)",
+   "sgh    r1,d20(x2,b2)",      // mi2
+
+   "shhhr  r1,r2,r3",           // hiwo
+   "shhlr  r1,r2,r3",           // hiwo
+
+   "slr    r1,r2",
+   "slgr   r1,r2",
+   "slgfr  r1,r2",
+   "slrk   r1,r2,r3",           // diop
+   "slgrk  r1,r2,r3",           // diop
+   "sl     r1,d12(x2,b2)",
+   "sly    r1,d20(x2,b2)",
+   "slg    r1,d20(x2,b2)",
+   "slgf   r1,d20(x2,b2)",
+
+   "slfi   r1,i2:u32",          // eimm
+   "slgfi  r1,i2:u32",          // eimm
+
+   "slhhhr r1,r2,r3",           // hiwo
+   "slhhlr r1,r2,r3",           // hiwo
+
+   "slbr   r1,r2",
+   "slbgr  r1,r2",
+   "slb    r1,d20(x2,b2)",
+   "slbg   r1,d20(x2,b2)",
+
+   "svc    i:u8",
+
+   // tam  not implemented
+   // ts   not implemented
+
+   "tm     d12(b1),i2:u8",
+   "tmy    d20(b1),i2:u8",
+   "tmhh   r1,i2:u16",
+   "tmhl   r1,i2:u16",
+   "tmlh   r1,i2:u16",
+   "tmll   r1,i2:u16",
+
+   // tabort  not implemented
+   // tbegin  not implemented
+   // tbeginc not implemented
+   // tend    not implemented
+
+   "tr     d12(l,b1),d12(b2)",
+
+   // trt   not implemented
+   // trte  not implemented
+   // trtre not implemented
+   // trtr  not implemented
+
+   "tre    r1:{0,2,4,6,8,10,12,14},r2",
+
+   "troo   r1:{0,2,4,6,8,10,12,14},r2,m3:{0,1}",  // extr2 no spec exception on m3
+   "trot   r1:{0,2,4,6,8,10,12,14},r2,m3:{0,1}",  // extr2 no spec exception on m3
+   "trto   r1:{0,2,4,6,8,10,12,14},r2,m3:{0,1}",  // extr2 no spec exception on m3
+   "trtt   r1:{0,2,4,6,8,10,12,14},r2,m3:{0,1}",  // extr2 no spec exception on m3
+
+   // unpk  not implemented
+   // unpka not implemented
+   // unpku not implemented
+   // upt   not implemented
+
+   // Chapter 8: Decimal Instructions                      not implemented
+
+   // Chapter 9: Floating-Point Overview and Support Instructions
+
+   // thder   not implemented
+   // thdr    not implemented
+   // tbedr   not implemented
+   // tbdr    not implemented
+
+   "cpsdr  f1,f3,f3",   // fpssh
+   "efpc   r1",
+   "ler    f1,f2",
+   "ldr    f1,f2",
+   "lxr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "le     f1,d12(x2,b2)",
+   "ld     f1,d12(x2,b2)",
+   "ley    f1,d20(x2,b2)",
+   "ldy    f1,d20(x2,b2)",
+   "lcdfr  f1,f2",                 // fpssh
+   "lfpc   d12(b2)",
+   // lfas   not implemented
+   "ldgr   f1,r2",                 // fgx
+   "lgdr   r1,f2",                 // fgx
+   "lndfr  f1,f2",                 // fpssh
+   "lpdfr  f1,f2",                 // fpssh
+   "lzer   f1",
+   "lzdr   f1",
+   "lzxr   f1:{0,1,4,5,8,9,12,13}",
+   "pfpo",                         // pfpo
+   "srnm   d12(b2)",
+   "srnmb  d12(b2)",               // fpext
+   "sfpc   r1",
+   // sfasr  not implemented
+   "ste    f1,d12(x2,b2)",
+   "std    f1,d12(x2,b2)",
+   "stey   f1,d20(x2,b2)",
+   "stdy   f1,d20(x2,b2)",
+   "stfpc  d12(b2)",
+
+   // Chapter 10: Control Instructions                      not implemented
+   // Chapter 14: I/O Instructions                          not implemented
+   // Chapter 18: Hexadecimal-Floating-Point Instructions   not implemented
+
+   // Chapter 19: Binary-Floating-Point Instructions
+   // Register pairs: 0-2 1-3 4-6 5-7 8-10 9-11 12-14 13-15
+   // no BFP facility bit (unlike DFP)
+   "aebr    f1,f2",
+   "adbr    f1,f2",
+   "axbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "aeb     f1,d12(x2,b2)",
+   "adb     f1,d12(x2,b2)",
+   "cebr    f1,f2",
+   "cdbr    f1,f2",
+   "cxbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "ceb     f1,d12(x2,b2)",
+   "cdb     f1,d12(x2,b2)",
+   "kebr    f1,f2",
+   "kdbr    f1,f2",
+   "kxbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "keb     f1,d12(x2,b2)",
+   "kdb     f1,d12(x2,b2)",
+   "cefbr   f1,r2",
+   "cdfbr   f1,r2",
+   "cxfbr   f1:{0,1,4,5,8,9,12,13},r2",
+   "cegbr   f1,r2",
+   "cdgbr   f1,r2",
+   "cxgbr   f1:{0,1,4,5,8,9,12,13},r2",
+   "cefbra  f1,m3:{0,1,3..7},r2,m4",
+   "cdfbra  f1,m3:{0,1,3..7},r2,m4",
+   "cxfbra  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},r2,m4",
+   "cegbra  f1,m3:{0,1,3..7},r2,m4",
+   "cdgbra  f1,m3:{0,1,3..7},r2,m4",
+   "cxgbra  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},r2,m4",
+   "celfbr  f1,m3:{0,1,3..7},r2,m4",                            // fpext
+   "cdlfbr  f1,m3:{0,1,3..7},r2,m4",                            // fpext
+   "cxlfbr  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},r2,m4",        // fpext
+   "celgbr  f1,m3:{0,1,3..7},r2,m4",                            // fpext
+   "cdlgbr  f1,m3:{0,1,3..7},r2,m4",                            // fpext
+   "cxlgbr  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},r2,m4",        // fpext
+   "cfebr   r1,m3:{0,1,3..7},f2",
+   "cfdbr   r1,m3:{0,1,3..7},f2",
+   "cfxbr   r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13}",
+   "cgebr   r1,m3:{0,1,3..7},f2",
+   "cgdbr   r1,m3:{0,1,3..7},f2",
+   "cgxbr   r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13}",
+   "cfebra  r1,m3:{0,1,3..7},f2,m4",
+   "cfdbra  r1,m3:{0,1,3..7},f2,m4",
+   "cfxbra  r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",
+   "cgebra  r1,m3:{0,1,3..7},f2,m4",
+   "cgdbra  r1,m3:{0,1,3..7},f2,m4",
+   "cgxbra  r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",
+   "clfebr  r1,m3:{0,1,3..7},f2,m4",                            // fpext
+   "clfdbr  r1,m3:{0,1,3..7},f2,m4",                            // fpext
+   "clfxbr  r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",        // fpext
+   "clgebr  r1,m3:{0,1,3..7},f2,m4",                            // fpext
+   "clgdbr  r1,m3:{0,1,3..7},f2,m4",                            // fpext
+   "clgxbr  r1,m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",        // fpext
+   "debr    f1,f2",
+   "ddbr    f1,f2",
+   "dxbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "deb     f1,d12(x2,b2)",
+   "ddb     f1,d12(x2,b2)",
+   // diebr  not implemented
+   // didbr  not implemented
+   "ltebr   f1,f2",
+   "ltdbr   f1,f2",
+   "ltxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "lcebr   f1,f2",
+   "lcdbr   f1,f2",
+   "lcxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "fiebr   f1,m3:{0,1,3..7},f2",
+   "fidbr   f1,m3:{0,1,3..7},f2",
+   "fixbr   f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13}",
+   "fiebra  f1,m3:{0,1,3..7},f2,m4",
+   "fidbra  f1,m3:{0,1,3..7},f2,m4",
+   "fixbra  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",
+   "ldebr   f1,f2",
+   "lxdbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "lxebr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "ldeb    f1,d12(x2,b2)",
+   "lxdb    f1:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+   "lxeb    f1:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+   "lnebr   f1,f2",
+   "lndbr   f1,f2",
+   "lnxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "lpebr   f1,f2",
+   "lpdbr   f1,f2",
+   "lpxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "ledbr   f1,f2",
+   "ldxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "lexbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "ledbra  f1,m3:{0,1,3..7},f2,m4",
+   "ldxbra  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",
+   "lexbra  f1:{0,1,4,5,8,9,12,13},m3:{0,1,3..7},f2:{0,1,4,5,8,9,12,13},m4",
+   "meebr   f1,f2",
+   "mdbr    f1,f2",
+   "mxbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   // mdebr  not implemented
+   // mxdbr  not implemented
+   "meeb    f1,d12(x2,b2)",
+   "mdb     f1,d12(x2,b2)",
+   // mdeb  not implemented
+   // mxdb  not implemented
+   "maebr   f1,f3,f2",
+   "madbr   f1,f3,f2",
+   "maeb    f1,f3,d12(x2,b2)",
+   "madb    f1,f3,d12(x2,b2)",
+   "msebr   f1,f3,f2",
+   "msdbr   f1,f3,f2",
+   "mseb    f1,f3,d12(x2,b2)",
+   "msdb    f1,f3,d12(x2,b2)",
+   "sqebr   f1,f2",
+   "sqdbr   f1,f2",
+   "sqxbr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "sqeb    f1,d12(x2,b2)",
+   "sqdb    f1,d12(x2,b2)",
+   "sebr    f1,f2",
+   "sdbr    f1,f2",
+   "sxbr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "seb     f1,d12(x2,b2)",
+   "sdb     f1,d12(x2,b2)",
+   "tceb    f1,d12(x2,b2)",
+   "tcdb    f1,d12(x2,b2)",
+   "tcxb    f1:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+
+   // Chapter 20: Decimal-Floating-Point Instructions
+   // Register pairs: 0-2 1-3 4-6 5-7 8-10 9-11 12-14 13-15
+
+   // All opcodes require the dfp facility
+
+   "adtr    f1,f2,f3",
+   "axtr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13}",
+   "adtra   f1,f2,f3,m4",
+   "axtra   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4",
+   "cdtr    f1,f2",
+   "cxtr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   // kdtr  not implemented
+   // kxtr  not implemented
+   "cedtr   f1,f2",
+   "cextr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "cdgtr   f1,r2",
+   "cxgtr   f1:{0,1,4,5,8,9,12,13},r2",
+   "cdgtra  f1,m3,r2,m4",
+   "cxgtra  f1:{0,1,4,5,8,9,12,13},m3,r2,m4",
+   "cdftr   f1,m3,r2,m4",
+   "cxftr   f1:{0,1,4,5,8,9,12,13},m3,r2,m4",
+   "cdlgtr  f1,m3,r2,m4",                               // fpext
+   "cxlgtr  f1:{0,1,4,5,8,9,12,13},m3,r2,m4",           // fpext
+   "cdlftr  f1,m3,r2,m4",                               // fpext
+   "cxlftr  f1:{0,1,4,5,8,9,12,13},m3,r2,m4",           // fpext
+   // cdpt  not implemented
+   // cxpt  not implemented
+   // cdstr not implemented
+   // cxstr not implemented
+   // cdutr not implemented
+   // cxutr not implemented
+   // cdzt  not implemented
+   // cxzt  not implemented
+   "cgdtr   r1,m3,f2",
+   "cgxtr   r1,m3,f2:{0,1,4,5,8,9,12,13}",
+   "cgdtra  r1,m3,f2,m4",
+   "cgxtra  r1,m3,f2:{0,1,4,5,8,9,12,13},m4",
+   "cfdtr   r1,m3,f2,m4",
+   "cfxtr   r1,m3,f2:{0,1,4,5,8,9,12,13},m4",
+   "clgdtr  r1,m3,f2,m4",                               // fpext
+   "clgxtr  r1,m3,f2:{0,1,4,5,8,9,12,13},m4",           // fpext
+   "clfdtr  r1,m3,f2,m4",                               // fpext
+   "clfxtr  r1,m3,f2:{0,1,4,5,8,9,12,13},m4",           // fpext
+   // cpdt  not implemented
+   // cpxt  not implemented
+   // csdtr not implemented
+   // csxtr not implemented
+   // cudtr not implemented
+   // cuxtr not implemented
+   // czdt  not implemented
+   // czxt  not implemented
+   "ddtr    f1,f2,f3",
+   "dxtr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13}",
+   "ddtra   f1,f2,f3,m4",
+   "dxtra   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4",
+   "eedtr   f1,f2",
+   "eextr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "esdtr   f1,f2",
+   "esxtr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "iedtr   f1,f3,f2",
+   "iextr   f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   "ltdtr   f1,f2",
+   "ltxtr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13}",
+   // fidtr  not implemented
+   // fixtr  not implemented
+   "ldetr   f1,f2,m4",
+   "lxdtr   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},m4",
+   "ledtr   f1,m3,f2,m4",
+   "ldxtr   f1:{0,1,4,5,8,9,12,13},m3,f2:{0,1,4,5,8,9,12,13},m4",
+   "mdtr    f1,f2,f3",
+   "mxtr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13}",
+   "mdtra   f1,f2,f3,m4",
+   "mxtra   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4",
+   "qadtr   f1,f3,f2,m4",
+   "qaxtr   f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},m4",
+   "rrdtr   f1,f3,f2,m4",
+   "rrxtr   f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},m4",
+   "sldt    f1,f3,d12(x2,b2)",
+   "slxt    f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+   "srdt    f1,f3,d12(x2,b2)",
+   "srxt    f1:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+   "sdtr    f1,f2,f3",
+   "sxtr    f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13}",
+   "sdtra   f1,f2,f3,m4",
+   "sxtra   f1:{0,1,4,5,8,9,12,13},f2:{0,1,4,5,8,9,12,13},f3:{0,1,4,5,8,9,12,13},m4",
+   "tdcet   f1,d12(x2,b2)",
+   "tdcdt   f1,d12(x2,b2)",
+   "tdcxt   f1:{0,1,4,5,8,9,12,13},d12(x2,b2)",
+   "tdget   f1,d12(x2,b2)",
+   "tdgdt   f1,d12(x2,b2)",
+   "tdgxt   f1:{0,1,4,5,8,9,12,13},d12(x2,b2)",
 
    // Chapter 21: Vector Overview and Support Instructions
-   "vbperm  v1,v2,v3",
+
+   // all opcodes require VX facility
+
+   "vbperm  v1,v2,v3",                          // vxe
    "vgef    v1,d12(v2,b2),m3:{0,1,2,3}",
    "vgeg    v1,d12(v2,b2),m3:{0,1}",
    "vgbm    v1,i2:u16",
@@ -156,12 +1191,12 @@ static const char *opcodes[] = {
    "vl      v1,d12(x2,b2),m3:{0,3,4}",    // no spec. exc
    "vlr     v1,v2",
    "vlrep   v1,d12(x2,b2),m3:{0..3}",
-   "vlebrh  v1,d12(x2,b2),m3:{0..7}",
-   "vlebrf  v1,d12(x2,b2),m3:{0..3}",
-   "vlebrg  v1,d12(x2,b2),m3:{0,1}",
-   "vlbrrep v1,d12(x2,b2),m3:{1..3}",
-   "vllebrz v1,d12(x2,b2),m3:{1..3,6}",
-   "vlbr    v1,d12(x2,b2),m3:{1..4}",
+   "vlebrh  v1,d12(x2,b2),m3:{0..7}",           // vxe2
+   "vlebrf  v1,d12(x2,b2),m3:{0..3}",           // vxe2
+   "vlebrg  v1,d12(x2,b2),m3:{0,1}",            // vxe2
+   "vlbrrep v1,d12(x2,b2),m3:{1..3}",           // vxe2
+   "vllebrz v1,d12(x2,b2),m3:{1..3,6}",         // vxe2
+   "vlbr    v1,d12(x2,b2),m3:{1..4}",           // vxe2
    "vleb    v1,d12(x2,b2),m3",
    "vleh    v1,d12(x2,b2),m3:{0..7}",
    "vlef    v1,d12(x2,b2),m3:{0..3}",
@@ -170,12 +1205,12 @@ static const char *opcodes[] = {
    "vleih   v1,i2:s16,m3:{0..7}",
    "vleif   v1,i2:s16,m3:{0..3}",
    "vleig   v1,i2:s16,m3:{0,1}",
-   "vler    v1,d12(x2,b2),m3:{0..3}",
+   "vler    v1,d12(x2,b2),m3:{1..3}",           // vxe2
    "vlgv    r1,v3,d12(b2),m4:{0..3}",
    "vllez   v1,d12(x2,b2),m3:{0..3,6}",
    //   "vlm     v1,v3,d12(b2),m4",  // cannot express constraint
-   "vlrlr   v1,r3,d12(b2)",
-   "vlrl    v1,d12(b2),i3:u8{0..15}",
+   "vlrlr   v1,r3,d12(b2)",                     // vxd
+   "vlrl    v1,d12(b2),i3:u8{0..15}",           // vxd
    "vlbb    v1,d12(x2,b2),m3:{0..6}",
    "vlvg    v1,r3,d12(b2),m4:{0..3}",
    "vlvgp   v1,r2,r3",
@@ -187,25 +1222,25 @@ static const char *opcodes[] = {
    "vpkls   v1,v2,v3,m4:{1..3},m5:{0,1}", // no spec. exception for m5
    "vperm   v1,v2,v3,v4",
    "vpdi    v1,v2,v3,m4",
-   "vrep    v1,v3,i2:u16,m4:{0..3}",
+//   "vrep    v1,v3,i2:u16,m4:{0..3}",
    "vrepi   v1,i2:s16,m3:{0..3}",
    "vscef   v1,d12(v2,b2),m3:{0..3}",
    "vsceg   v1,d12(v2,b2),m3:{0,1}",
    "vsel    v1,v2,v3,v4",
    "vseg    v1,v2,m3:{0..2}",
    "vst     v1,d12(x2,b2),m3",
-   "vstebrh v1,d12(x2,b2),m3:{0..7}",
-   "vstebrf v1,d12(x2,b2),m3:{0..3}",
-   "vstebrg v1,d12(x2,b2),m3:{0,1}",
-   "vstbr   v1,d12(x2,b2),m3:{1..4}",
+   "vstebrh v1,d12(x2,b2),m3:{0..7}",            // vxe2
+   "vstebrf v1,d12(x2,b2),m3:{0..3}",            // vxe2
+   "vstebrg v1,d12(x2,b2),m3:{0,1}",             // vxe2
+   "vstbr   v1,d12(x2,b2),m3:{1..4}",            // vxe2
    "vsteb   v1,d12(x2,b2),m3",
    "vsteh   v1,d12(x2,b2),m3:{0..7}",
    "vstef   v1,d12(x2,b2),m3:{0..3}",
    "vsteg   v1,d12(x2,b2),m3:{0,1}",
-   "vster   v1,d12(x2,b2),m3:{1..3}",
+   "vster   v1,d12(x2,b2),m3:{1..3}",            // vxe2
    //   "vstm    v1,v3,d12(b2),m4",  // cannot express constraint
-   "vstrlr  v1,r3,d12(b2)",
-   "vstrl   v1,d12(b2),i3:u8{0..15}",
+   "vstrlr  v1,r3,d12(b2)",                      // vxd
+   "vstrl   v1,d12(b2),i3:u8{0..15}",            // vxd
    "vstl    v1,r3,d12(b2)",
    "vuph    v1,v2,m3:{0..2}",
    "vuplh   v1,v2,m3:{0..2}",
@@ -252,12 +1287,12 @@ static const char *opcodes[] = {
    "vmle    v1,v2,v3,m4:{0..2}",
    "vmo     v1,v2,v3,m4:{0..2}",
    "vmlo    v1,v2,v3,m4:{0..2}",
-   "vmsl    v1,v2,v3,v4,m5:{3},m6:{0,4,8,12}",   // no spec. exception for m6
-   "vnn     v1,v2,v3",
+   "vmsl    v1,v2,v3,v4,m5:{3},m6:{0,4,8,12}",   // vxe  no spec. exception for m6
+   "vnn     v1,v2,v3",                           // vxe
    "vno     v1,v2,v3",
-   "vnx     v1,v2,v3",
+   "vnx     v1,v2,v3",                           // vxe
    "vo      v1,v2,v3",
-   "voc     v1,v2,v3",
+   "voc     v1,v2,v3",                           // vxe
    "vpopct  v1,v2,m3:{0..3}",
    "verllv  v1,v2,v3,m4:{0..3}",
    "verll   v1,v3,d12(b2),m4:{0..3}",
@@ -270,11 +1305,11 @@ static const char *opcodes[] = {
    "vesrl   v1,v3,d12(b2),m4:{0..3}",
    "vsl     v1,v2,v3",
    "vslb    v1,v2,v3",
-   "vsld    v1,v2,v3,i4:u8{0..7}",   // spec exc.
-   "vsldb   v1,v2,v3,i4:u8{0..15}",  // otherwise unpredictable
+   "vsld    v1,v2,v3,i4:u8{0..7}",   // vxe2  spec exc.
+   "vsldb   v1,v2,v3,i4:u8{0..15}",  // no spec. exception - otherwise unpredictable
    "vsra    v1,v2,v3",
    "vsrab   v1,v2,v3",
-   "vsrd    v1,v2,v3,i4:u8{0..7}",
+   "vsrd    v1,v2,v3,i4:u8{0..7}",   // vxe2
    "vsrl    v1,v2,v3",
    "vsrlb   v1,v2,v3",
    "vs      v1,v2,v3,m4:{0..4}",
@@ -292,7 +1327,7 @@ static const char *opcodes[] = {
    "vfene   v1,v2,v3,m4:{0..2},m5:{0..3}",
    "vistr   v1,v2,m3:{0..2},m5:{0,1}",
    "vstrc   v1,v2,v3,v4,m5:{0..2},m6",
-   "vstrs   v1,v2,v3,v4,m5:{0..2},m6:{0,2}",
+   "vstrs   v1,v2,v3,v4,m5:{0..2},m6:{0,2}",    // vxe2
 
    // Chapter 24: Vector Floating-Point Instructions
    "vfa    v1,v2,v3,m4:{2,3,4},m5:{0,8}",
@@ -301,45 +1336,44 @@ static const char *opcodes[] = {
    "vfce   v1,v2,v3,m4:{2,3,4},m5:{0,4,8,12},m6:{0,1}",
    "vfch   v1,v2,v3,m4:{2,3,4},m5:{0,4,8,12},m6:{0,1}",
    "vfche  v1,v2,v3,m4:{2,3,4},m5:{0,4,8,12},m6:{0,1}",
-   "vcfps  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcdg
+   "vcfps  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcdg   // vxe2
    "vcdg   v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcfps
-   "vcfpl  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcdlg
+   "vcfpl  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcdlg  // vxe2
    "vcdlg  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcfpl
    "vcsfp  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcgd
    "vcgd   v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vcsfp
-   "vclfp  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vclgd
+   "vclfp  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vclgd  // vxe2
    "vclgd  v1,v2,m3:{2,3},m4:{0,4,8,12},m5:{0,1,3..7}", // aka vclfp
    "vfd    v1,v2,v3,m4:{2,3,4},m5:{0,8}",
    "vfi    v1,v2,m3:{2,3,4},m4:{0,4,8,12},m5:{0,1,3..7}",
    "vfll   v1,v2,m3:{2,3},m4:{0,8}",
    "vflr   v1,v2,m3:{3,4},m4:{0,4,8,12},m5:{0,1,3..7}",
-   "vfmax  v1,v2,v3,m4:{2,3,4},m5:{0,8},m6:{0..4,8..12}",
-   "vfmin  v1,v2,v3,m4:{2,3,4},m5:{0,8},m6:{0..4,8..12}",
+   "vfmax  v1,v2,v3,m4:{2,3,4},m5:{0,8},m6:{0..4,8..12}",             // vxe
+   "vfmin  v1,v2,v3,m4:{2,3,4},m5:{0,8},m6:{0..4,8..12}",             // vxe
    "vfm    v1,v2,v3,m4:{2,3,4},m5:{0,8}",
    "vfma   v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",
    "vfms   v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",
-   "vfnma  v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",
-   "vfnms  v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",
+   "vfnma  v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",                          // vxe
+   "vfnms  v1,v2,v3,v4,m5:{0,8},m6:{2,3,4}",                          // vxe
    "vfpso  v1,v2,m3:{2,3,4},m4:{0,8},m5:{0..2}",
    "vfsq   v1,v2,m3:{2,3,4},m4:{0,8}",
    "vfs    v1,v2,v3,m4:{2,3,4},m5:{0,8}",
    "vftci  v1,v2,i3:u12,m4:{2,3,4},m5:{0,8}",
 
-   // Chapter 25: Vector Decimal Instructions
-
-   //  not implemented
+   // Chapter 25: Vector Decimal Instructions          not implemented
 
    // Chapter 26: Specialized-Function-Assist Instructions
 
-   //   "kdsa   r1,r2",    // cannot express constraint
-   //   "dfltcc r1,r2,r3", // cannot express constraint
-   //   "nnpa",            // cannot express constraint
-   //   "sortl  r1,r2",    // not implemented
-   "vclfnh  v1,v2,m3,m4",      // FIXME: m3:{2}  m4:{0}  no spec but IEEE exc.
-   "vclfnl  v1,v2,m3,m4",      // FIXME: m3:{2}  m4:{0}  no spec but IEEE exc.
-   "vcrnf   v1,v2,v3,m4,m5",   // FIXME: m4:{0}  m5:{2}  no spec but IEEE exc.
-   "vcfn    v1,v2,m3,m4",      // FIXME: m3:{0}  m4:{1}  no spec but IEEE exc.
-   "vcnf    v1,v2,m3,m4",      // FIXME: m3:{0}  m4:{1}  no spec but IEEE exc.
+   //   "kdsa   r1,r2",    // cannot express constraint   // msa9
+   //   "dfltcc r1,r2,r3", // cannot express constraint   // dflt
+   //   "nnpa",            // cannot express constraint   // nnpa
+
+   // sortl   not implemented
+   "vclfnh  v1,v2,m3:{3},m4:{0}",    // nnpa  no spec exc. for m3, m4 but IEEE exc.
+   "vclfnl  v1,v2,m3:{3},m4:{0}",    // nnpa  no spec exc. for m3, m4 but IEEE exc.
+   "vcrnf   v1,v2,v3,m4:{0},m5:{2}", // nnpa  no spec exc. for m4, m5 but IEEE exc.
+   "vcfn    v1,v2,m3:{1},m4:{0}",    // nnpa  no spec exc. for m3, m4 but IEEE exc.
+   "vcnf    v1,v2,m3:{0},m4:{1}",    // nnpa  no spec exc. for m3, m4 but IEEE exc.
 };
 
 unsigned num_opcodes = sizeof opcodes / sizeof *opcodes;
@@ -502,35 +1536,61 @@ invalid_opnd(char *name)
 }
 
 
-/* GPRs and VRs are understood. Specification not allowed. */
+/* GPRs, VRs, ARs and FPRs are understood. */
 static opnd
 register_operand(const char *opnd_string)
 {
-   char *name = strsave(opnd_string);
+   opnd_t kind = OPND_GPR;
+   unsigned num_bits = 4;
+
+   if (opnd_string[0] == 'v') {
+      kind = OPND_VR;
+      num_bits = 5;
+   } else if (opnd_string[0] == 'f') {
+      kind = OPND_FPR;
+   } else if (opnd_string[0] == 'a') {
+      kind = OPND_AR;
+   }
+
    const char *p = skip_digits(opnd_string + 1);
 
    if (p == opnd_string + 1) {   // no digits found
       error("%s: invalid register name\n", opnd_string);
-      return invalid_opnd(name);
+      return invalid_opnd(strsave(opnd_string));
    }
+
+   char *name = strnsave(opnd_string, (unsigned)(p - opnd_string));
+   long long *allowed_values = NULL;
+
    if (*p == ':') {
-      error("%s: specification is invalid for registers\n", opnd_string);
-      return invalid_opnd(name);
+      ++p;
+      if (p[0] == 's' || p[0] == 'u') {
+         error("%s: specification of signedness is invalid for registers\n", name);
+         return invalid_opnd(name);
+      }
+
+      if (p[0] != '{') {
+         error("%s: expected '{'\n", name);
+         return invalid_opnd(name);
+      }
+
+      allowed_values = consume_set(p, num_bits, 1);
+      if (allowed_values == NULL)
+         return invalid_opnd(name);
+      p = strchr(p + 1, '}');
+      if (p == NULL) {
+         error("%s: expected '}' not found\n", name);
+         return invalid_opnd(name);
+      }
+      ++p;
    }
    if (*p != '\0') {
       error("'%s' is not understood\n", opnd_string);
       return invalid_opnd(strsave(opnd_string));
    }
 
-   opnd_t kind = OPND_GPR;
-   unsigned num_bits = 4;
-
-   if (opnd_string[0] == 'v') {
-      kind = OPND_VR;
-      num_bits = 5;
-   }
    return (opnd){ .name = name, .kind = kind, .num_bits = num_bits,
-                  .is_unsigned = 1, .allowed_values = 0 };
+                  .is_unsigned = 1, .allowed_values = allowed_values };
 }
 
 
@@ -704,6 +1764,8 @@ get_operand(const char *opnd_string)
    case 'b':    // GPR
    case 'x':    // GPR
    case 'v':    // VR
+   case 'a':    // AR
+   case 'f':    // FPR
       return register_operand(opnd_string);
 
       /* Masks without specification are understood:
@@ -736,6 +1798,8 @@ opnd_kind_as_string(int kind)
    switch (kind) {
    case OPND_GPR:     return "gpr";
    case OPND_VR:      return "vr";
+   case OPND_AR:      return "ar";
+   case OPND_FPR:     return "fpr";
    case OPND_D12XB:   return "d12xb";
    case OPND_D20XB:   return "d20xb";
    case OPND_D12B:    return "d12b";
@@ -851,6 +1915,8 @@ parse_opcode(const char *spec)
       switch (opnds[i].kind) {
       case OPND_GPR:
       case OPND_VR:
+      case OPND_AR:
+      case OPND_FPR:
       case OPND_SINT:
       case OPND_UINT:
       case OPND_MASK:
diff --git a/none/tests/s390x/disasm-test/verify.c b/none/tests/s390x/disasm-test/verify.c
index c219607d9f..2d6fe48c05 100644
--- a/none/tests/s390x/disasm-test/verify.c
+++ b/none/tests/s390x/disasm-test/verify.c
@@ -38,8 +38,6 @@ verify_disassembly(const char *file)
 {
    verify_stats stats = { 0, 0, 0 };  // return value
 
-   vex_reset();
-
    objdump_file *ofile = read_objdump(file);
    if (ofile == NULL)
       return stats;
diff --git a/none/tests/s390x/disasm-test/vex.c b/none/tests/s390x/disasm-test/vex.c
index a1847b42b5..39d940371c 100644
--- a/none/tests/s390x/disasm-test/vex.c
+++ b/none/tests/s390x/disasm-test/vex.c
@@ -111,13 +111,16 @@ vex_init(void)
 
 /* Reset the VEX memory allocator. Otherwise, we'll run out of memory
    with a suggestion to recompile valgrind. Yuck. */
-void
+static void
 vex_reset(void)
 {
    if (vex_initdone) {
       vexSetAllocModeTEMP_and_clear();
       dis_irsb = emptyIRSB();
    }
+
+   /* Otherwise we won't make it through s390_irgen_EXRL. */
+   last_execute_target = 42;
 }
 
 
@@ -130,6 +133,9 @@ vex_disasm(const unsigned char *codebuf, int *spec_exc)
 {
    DisResult res;
 
+   /* Work around VEX running out of memory. */
+   vex_reset();
+
    res = disInstr_S390(dis_irsb, codebuf, /* delta */0, /* guest_IA */0,
                        VexArchS390X, NULL, NULL, VexEndnessBE, 0);
 
diff --git a/none/tests/s390x/disasm-test/vex.h b/none/tests/s390x/disasm-test/vex.h
index c96acea8bd..0a9510b519 100644
--- a/none/tests/s390x/disasm-test/vex.h
+++ b/none/tests/s390x/disasm-test/vex.h
@@ -26,7 +26,6 @@
 #define VEX_H
 
 void  vex_init(void);
-void  vex_reset(void);
 const char *vex_disasm(const unsigned char *, int *);
 
 #endif // VEX_H

[Valgrind-developers] [valgrind] s390x: Fix disassembly for various DFP and BFP opcodes (BZ 495817)

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=72de8eaf53d77b0aa51266864f5a339b787ca24c

commit 72de8eaf53d77b0aa51266864f5a339b787ca24c
Author: Florian Krohm <fl...@ei...>
Date:   Sun Mar 30 20:51:33 2025 +0000

    s390x: Fix disassembly for various DFP and BFP opcodes  (BZ 495817)
    
    Specifically:
    - DFP: add, subtract, divide, multiply
    - BFP: load FP integer, load rounded
    
    Change function names from e.g. s390_irgen/emit_LDXBR to
    s390_irgen/emit_LDXBRA because LDXBR does not have m3 and m4 operands.
    Adjust the returned mnemonic accordingly.
    
    New function s390_format_RRF_UUFF2 for FI[DEX]BRA.
    
    Add adtra_like_disasm to disassemble opcodes for DFP arithmetic.
    
    Part of fixing https://bugs.kde.org/show_bug.cgi?id=495817

Diff:
---
 VEX/priv/guest_s390_toIR.c |  59 +++++++++++++----------
 VEX/priv/host_s390_defs.c  | 116 ++++++++++++---------------------------------
 VEX/priv/s390_disasm.c     |  18 +++++++
 VEX/priv/s390_disasm.h     |   1 +
 4 files changed, 84 insertions(+), 110 deletions(-)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 7b029623d6..b870b77fe4 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -3094,7 +3094,18 @@ s390_format_RRF_UUFF(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1,
    const HChar *mnm = irgen(m3, m4, r1, r2);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM(mnm, fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
+}
+
+static void
+s390_format_RRF_UUFF2(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1,
+                                           UChar r2),
+                     UChar m3, UChar m4, UChar r1, UChar r2)
+{
+   const HChar *mnm = irgen(m3, m4, r1, r2);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(XMNM(mnm, fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 }
 
 static void
@@ -3191,7 +3202,7 @@ s390_format_RRF_FUFF2(const HChar *(*irgen)(UChar, UChar, UChar, UChar),
    const HChar *mnm = irgen(r3, m4, r1, r2);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
+      S390_DISASM(XMNM(mnm, adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 }
 
 static void
@@ -11807,8 +11818,8 @@ s390_irgen_LDEB(UChar r1, IRTemp op2addr)
 }
 
 static const HChar *
-s390_irgen_LEDBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_LEDBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -11820,7 +11831,7 @@ s390_irgen_LEDBR(UChar m3, UChar m4 __attribute__((unused)),
    put_fpr_w0(r1, binop(Iop_F64toF32, mkexpr(encode_bfp_rounding_mode(m3)),
                         mkexpr(op)));
 
-   return "ledbr";
+   return "ledbra";
 }
 
 static const HChar *
@@ -11988,7 +11999,7 @@ s390_irgen_ADTRA(UChar r3, UChar m4, UChar r1, UChar r2)
       s390_cc_thunk_putF(S390_CC_OP_DFP_RESULT_64, result);
       put_dpr_dw0(r1, mkexpr(result));
    }
-   return (m4 == 0) ? "adtr" : "adtra";
+   return "adtra";
 }
 
 static const HChar *
@@ -14970,8 +14981,8 @@ s390_irgen_LPXBR(UChar r1, UChar r2)
 }
 
 static const HChar *
-s390_irgen_LDXBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_LDXBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -14983,12 +14994,12 @@ s390_irgen_LDXBR(UChar m3, UChar m4 __attribute__((unused)),
                         get_fpr_pair(r2)));
    put_fpr_dw0(r1, mkexpr(result));
 
-   return "ldxbr";
+   return "ldxbra";
 }
 
 static const HChar *
-s390_irgen_LEXBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_LEXBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -15000,7 +15011,7 @@ s390_irgen_LEXBR(UChar m3, UChar m4 __attribute__((unused)),
                         get_fpr_pair(r2)));
    put_fpr_w0(r1, mkexpr(result));
 
-   return "lexbr";
+   return "lexbra";
 }
 
 static const HChar *
@@ -20745,18 +20756,18 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
                                    RRE_r2(ovl));  goto ok;
    case 0xb343: s390_format_RRE_FF(s390_irgen_LCXBR, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
-   case 0xb344: s390_format_RRF_UUFF(s390_irgen_LEDBR, RRF2_m3(ovl),
-                                     RRF2_m4(ovl), RRF2_r1(ovl),
-                                     RRF2_r2(ovl));  goto ok;
-   case 0xb345: s390_format_RRF_UUFF(s390_irgen_LDXBR, RRF2_m3(ovl),
+   case 0xb344: s390_format_RRF_UUFF(s390_irgen_LEDBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb346: s390_format_RRF_UUFF(s390_irgen_LEXBR, RRF2_m3(ovl),
+   case 0xb345: s390_format_RRF_UUFF(s390_irgen_LDXBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb347: s390_format_RRF_UUFF(s390_irgen_FIXBRA, RRF2_m3(ovl),
+   case 0xb346: s390_format_RRF_UUFF(s390_irgen_LEXBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
+   case 0xb347: s390_format_RRF_UUFF2(s390_irgen_FIXBRA, RRF2_m3(ovl),
+                                      RRF2_m4(ovl), RRF2_r1(ovl),
+                                      RRF2_r2(ovl));  goto ok;
    case 0xb348: s390_format_RRE_FF(s390_irgen_KXBR, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
    case 0xb349: s390_format_RRE_FF(s390_irgen_CXBR, RRE_r1(ovl),
@@ -20772,15 +20783,15 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb350: /* TBEDR */ goto unimplemented;
    case 0xb351: /* TBDR */ goto unimplemented;
    case 0xb353: /* DIEBR */ goto unimplemented;
-   case 0xb357: s390_format_RRF_UUFF(s390_irgen_FIEBRA, RRF2_m3(ovl),
-                                     RRF2_m4(ovl), RRF2_r1(ovl),
-                                     RRF2_r2(ovl));  goto ok;
+   case 0xb357: s390_format_RRF_UUFF2(s390_irgen_FIEBRA, RRF2_m3(ovl),
+                                      RRF2_m4(ovl), RRF2_r1(ovl),
+                                      RRF2_r2(ovl));  goto ok;
    case 0xb358: /* THDER */ goto unimplemented;
    case 0xb359: /* THDR */ goto unimplemented;
    case 0xb35b: /* DIDBR */ goto unimplemented;
-   case 0xb35f: s390_format_RRF_UUFF(s390_irgen_FIDBRA, RRF2_m3(ovl),
-                                     RRF2_m4(ovl), RRF2_r1(ovl),
-                                     RRF2_r2(ovl));  goto ok;
+   case 0xb35f: s390_format_RRF_UUFF2(s390_irgen_FIDBRA, RRF2_m3(ovl),
+                                      RRF2_m4(ovl), RRF2_r1(ovl),
+                                      RRF2_r2(ovl));  goto ok;
    case 0xb360: /* LPXR */ goto unimplemented;
    case 0xb361: /* LNXR */ goto unimplemented;
    case 0xb362: /* LTXR */ goto unimplemented;
diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index 684d173588..c503d6ddeb 100644
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -4383,12 +4383,8 @@ s390_emit_LEDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("ledbr"), FPR(r1), FPR(r2));
-      else
-         S390_DISASM(MNM("ledbra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("ledbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3440000, m3, m4, r1, r2);
 }
@@ -4400,12 +4396,8 @@ s390_emit_LDXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("ldxbr"), FPR(r1), FPR(r2));
-      else
-         S390_DISASM(MNM("ldxbra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("ldxbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3450000, m3, m4, r1, r2);
 }
@@ -4417,12 +4409,8 @@ s390_emit_LEXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("lexbr"), FPR(r1), FPR(r2));
-      else
-         S390_DISASM(MNM("lexbra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("lexbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3460000, m3, m4, r1, r2);
 }
@@ -4433,12 +4421,8 @@ s390_emit_FIEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("fiebr"), FPR(r1), UINT(m3), FPR(r2));
-      else
-         S390_DISASM(MNM("fiebra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("fiebra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3570000, m3, m4, r1, r2);
 }
@@ -4449,12 +4433,8 @@ s390_emit_FIDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("fidbr"), FPR(r1), UINT(m3), FPR(r2));
-      else
-         S390_DISASM(MNM("fidbra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("fidbra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb35f0000, m3, m4, r1, r2);
 }
@@ -4465,12 +4445,8 @@ s390_emit_FIXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("fixbr"), FPR(r1), UINT(m3), FPR(r2));
-      else
-         S390_DISASM(MNM("fixbra"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("fixbra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3470000, m3, m4, r1, r2);
 }
@@ -4611,12 +4587,8 @@ s390_emit_ADTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("adtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("adtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("adtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d20000, r3, m4, r1, r2);
 }
@@ -4627,12 +4599,8 @@ s390_emit_AXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("axtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("axtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("axtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3da0000, r3, m4, r1, r2);
 }
@@ -4911,12 +4879,8 @@ s390_emit_DDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("ddtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("ddtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("ddtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d10000, r3, m4, r1, r2);
 }
@@ -4927,12 +4891,8 @@ s390_emit_DXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("dxtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("dxtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("dxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d90000, r3, m4, r1, r2);
 }
@@ -5028,7 +4988,7 @@ s390_emit_LEDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext || m3 < 1 || m3 > 7);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("ledtr"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("ledtr", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3d50000, m3, m4, r1, r2);
 }
@@ -5042,7 +5002,7 @@ s390_emit_LDXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext || m3 < 1 || m3 > 7);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("ldxtr"), FPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("ldxtr", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3dd0000, m3, m4, r1, r2);
 }
@@ -5053,12 +5013,8 @@ s390_emit_MDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("mdtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("mdtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("mdtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d00000, r3, m4, r1, r2);
 }
@@ -5069,12 +5025,8 @@ s390_emit_MXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("mxtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("mxtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("mxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d80000, r3, m4, r1, r2);
 }
@@ -5150,12 +5102,8 @@ s390_emit_SDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("sdtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("sdtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("sdtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3d30000, r3, m4, r1, r2);
 }
@@ -5166,12 +5114,8 @@ s390_emit_SXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0 || s390_host_has_fpext);
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m4 == 0)
-         S390_DISASM(MNM("sxtr"), FPR(r1), FPR(r2), FPR(r3));
-      else
-         S390_DISASM(MNM("sxtra"), FPR(r1), FPR(r2), FPR(r3), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("sxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4));
 
    return emit_RRF4(p, 0xb3db0000, r3, m4, r1, r2);
 }
diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c
index 9649f9f0e1..139e141990 100644
--- a/VEX/priv/s390_disasm.c
+++ b/VEX/priv/s390_disasm.c
@@ -1066,6 +1066,24 @@ fp_convt_disasm(const s390_opnd *opnds, HChar *p)
 }
 
 
+HChar *
+adtra_like_disasm(const s390_opnd *opnds, HChar *p)
+{
+   const HChar *base = opnds[0].xmnm.base;
+   UInt m4 = opnds[get_mask_index(opnds, 1)].mask;
+   UInt len = vex_strlen(base);
+
+   HChar xmnm[len + 1];
+
+   vex_sprintf(xmnm, "%s", base);
+
+   if (xmnm[len - 1] == 'a' && m4 == 0) {
+      xmnm[len - 1] = '\0';
+   }
+   return s390_disasm_aux(opnds, xmnm, p, mask0_mh);
+}
+
+
 /* Write out OPNDS. MH is a mask handler. It decides whether or not a
    MASK operand is written and if so, massages the mask value as needed. */
 static HChar *
diff --git a/VEX/priv/s390_disasm.h b/VEX/priv/s390_disasm.h
index b28af8f659..f84f5061f6 100644
--- a/VEX/priv/s390_disasm.h
+++ b/VEX/priv/s390_disasm.h
@@ -137,6 +137,7 @@ HChar *vfce_like_disasm(const s390_opnd *, HChar *);
 HChar *vfmix_like_disasm(const s390_opnd *, HChar *);
 HChar *fp_convf_disasm(const s390_opnd *, HChar *);
 HChar *fp_convt_disasm(const s390_opnd *, HChar *);
+HChar *adtra_like_disasm(const s390_opnd *, HChar *);
 
 /*---------------------------------------------------------------*/
 /*--- end                                       s390_disasm.h ---*/

[Valgrind-developers] [valgrind/VALGRIND_3_24_BRANCH] Handle top __syscall_cancel frames when getting stack traces

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f18977fe271fc7dbfbf5d1657366cf69ec1361b8

commit f18977fe271fc7dbfbf5d1657366cf69ec1361b8
Author: Mark Wielaard <ma...@kl...>
Date:   Sun Mar 30 17:38:21 2025 +0200

    Handle top __syscall_cancel frames when getting stack traces
    
    Since glibc 2.41 there are extra frames inserted before doing a
    syscall to support proper thread cancellation.  This breaks various
    suppressions and regtests involving checking syscall arguments.
    
    Solve this by removing those extra frames from the top of the call
    stack when we are processing a linux system call.
    
    https://bugs.kde.org/show_bug.cgi?id=502126
    (cherry picked from commit 41441379baa63b5471385361d08c8df317705b69)

Diff:
---
 NEWS                     |  1 +
 coregrind/m_stacktrace.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/NEWS b/NEWS
index 23cf88c505..8b43361eb2 100644
--- a/NEWS
+++ b/NEWS
@@ -13,6 +13,7 @@ The following bugs have been fixed or resolved on this branch.
 498143  False positive on EVIOCGRAB ioctl
 501348  glibc built with -march=x86-64-v3 does not work due to ld.so memcmp
 501893  Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?
+502126  glibc 2.41 extra syscall_cancel frames
 
 To see details of a given bug, visit
   https://bugs.kde.org/show_bug.cgi?id=XXXXXX
diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c
index 630b5b8752..0ddd3639cd 100644
--- a/coregrind/m_stacktrace.c
+++ b/coregrind/m_stacktrace.c
@@ -9,6 +9,8 @@
 
    Copyright (C) 2000-2017 Julian Seward 
       js...@ac...
+   Copyright (C) 2025 Mark J. Wielaard
+      ma...@kl...
 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
@@ -1598,10 +1600,59 @@ UInt VG_(get_StackTrace_with_deltas)(
                   tid, stack_highest_byte,
                   startRegs.r_pc, startRegs.r_sp);
 
-   return VG_(get_StackTrace_wrk)(tid, ips, n_ips, 
+   Int found = VG_(get_StackTrace_wrk)(tid, ips, n_ips,
                                        sps, fps,
                                        &startRegs,
                                        stack_highest_byte);
+
+#if defined(VGO_linux)
+   /* glibc might insert some extra frames before doing a syscall to support
+      thread cancellation.  This breaks various suppressions and regtests
+      involving checking syscall arguments. So when processing a syscall just
+      remove those extra frames from the top of the call stack.  */
+   if (VG_(is_in_syscall)(tid)) {
+      Int i;
+      Int start = 0;
+      DiEpoch ep = VG_(current_DiEpoch)();
+      for (i = 0; i < found; i++) {
+         /* This could be made a little more efficient by doing the lookups
+            for the symbols at glibc load time and check the address falls
+            inside the function symbol address range here. But given this
+            is only called during syscall processing, this is probably fine
+            for now.  */
+         const HChar *buf;
+         if (VG_(get_fnname_raw)(ep, ips[i], &buf)) { // raw, don't demangle
+            if (VG_STREQ("__syscall_cancel_arch", buf) ||
+                VG_STREQ("__internal_syscall_cancel", buf) ||
+#if defined(VGP_x86_linux) || defined(VGP_arm_linux)
+                VG_STREQ("__libc_do_syscall", buf) ||
+#endif
+#if defined(VGP_x86_linux)
+                VG_STREQ("_dl_sysinfo_int80", buf) ||
+#endif
+                VG_STREQ("__syscall_cancel", buf)) {
+               start++;
+               continue; // Maybe the next one is special too?
+            } else {
+               break; // Not special, only skip top stack names.
+            }
+         } else {
+            break; // No name, not special, don't skip.
+         }
+      }
+
+      if (start > 0) {
+         for (i = 0; i < (found - start); i++) {
+            ips[i] = ips[i + start];
+            if (sps) sps[i] = sps[i + start];
+            if (fps) fps[i] = fps[i + start];
+         }
+         return found - start;
+      }
+   }
+#endif
+
+   return found;
 }
 
 UInt VG_(get_StackTrace) ( ThreadId tid,

[Valgrind-developers] [valgrind] Handle top __syscall_cancel frames when getting stack traces

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=41441379baa63b5471385361d08c8df317705b69

commit 41441379baa63b5471385361d08c8df317705b69
Author: Mark Wielaard <ma...@kl...>
Date:   Sun Mar 30 17:38:21 2025 +0200

    Handle top __syscall_cancel frames when getting stack traces
    
    Since glibc 2.41 there are extra frames inserted before doing a
    syscall to support proper thread cancellation.  This breaks various
    suppressions and regtests involving checking syscall arguments.
    
    Solve this by removing those extra frames from the top of the call
    stack when we are processing a linux system call.
    
    https://bugs.kde.org/show_bug.cgi?id=502126

Diff:
---
 NEWS                     |  1 +
 coregrind/m_stacktrace.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/NEWS b/NEWS
index 40b9539596..7145157f21 100644
--- a/NEWS
+++ b/NEWS
@@ -70,6 +70,7 @@ are not entered into bugzilla tend to get forgotten about or ignored.
 501846  Add x86 Linux shm wrappers
 501850  FreeBSD syscall arguments 7 and 8 incorrect.
 501893  Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?
+502126  glibc 2.41 extra syscall_cancel frames
 
 To see details of a given bug, visit
   https://bugs.kde.org/show_bug.cgi?id=XXXXXX
diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c
index cbeaab9db1..21c0f47942 100644
--- a/coregrind/m_stacktrace.c
+++ b/coregrind/m_stacktrace.c
@@ -9,6 +9,8 @@
 
    Copyright (C) 2000-2017 Julian Seward 
       js...@ac...
+   Copyright (C) 2025 Mark J. Wielaard
+      ma...@kl...
 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
@@ -1693,10 +1695,59 @@ UInt VG_(get_StackTrace_with_deltas)(
                   tid, stack_highest_byte,
                   startRegs.r_pc, startRegs.r_sp);
 
-   return VG_(get_StackTrace_wrk)(tid, ips, n_ips, 
+   Int found = VG_(get_StackTrace_wrk)(tid, ips, n_ips,
                                        sps, fps,
                                        &startRegs,
                                        stack_highest_byte);
+
+#if defined(VGO_linux)
+   /* glibc might insert some extra frames before doing a syscall to support
+      thread cancellation.  This breaks various suppressions and regtests
+      involving checking syscall arguments. So when processing a syscall just
+      remove those extra frames from the top of the call stack.  */
+   if (VG_(is_in_syscall)(tid)) {
+      Int i;
+      Int start = 0;
+      DiEpoch ep = VG_(current_DiEpoch)();
+      for (i = 0; i < found; i++) {
+         /* This could be made a little more efficient by doing the lookups
+            for the symbols at glibc load time and check the address falls
+            inside the function symbol address range here. But given this
+            is only called during syscall processing, this is probably fine
+            for now.  */
+         const HChar *buf;
+         if (VG_(get_fnname_raw)(ep, ips[i], &buf)) { // raw, don't demangle
+            if (VG_STREQ("__syscall_cancel_arch", buf) ||
+                VG_STREQ("__internal_syscall_cancel", buf) ||
+#if defined(VGP_x86_linux) || defined(VGP_arm_linux)
+                VG_STREQ("__libc_do_syscall", buf) ||
+#endif
+#if defined(VGP_x86_linux)
+                VG_STREQ("_dl_sysinfo_int80", buf) ||
+#endif
+                VG_STREQ("__syscall_cancel", buf)) {
+               start++;
+               continue; // Maybe the next one is special too?
+            } else {
+               break; // Not special, only skip top stack names.
+            }
+         } else {
+            break; // No name, not special, don't skip.
+         }
+      }
+
+      if (start > 0) {
+         for (i = 0; i < (found - start); i++) {
+            ips[i] = ips[i + start];
+            if (sps) sps[i] = sps[i + start];
+            if (fps) fps[i] = fps[i + start];
+         }
+         return found - start;
+      }
+   }
+#endif
+
+   return found;
 }
 
 UInt VG_(get_StackTrace) ( ThreadId tid,

[Valgrind-developers] [valgrind/VALGRIND_3_24_BRANCH] filter_gdb.in: filter out __libc_do_syscall

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e4d9cc414d13fa0685da8f1c7ac6bf027cadd730

commit e4d9cc414d13fa0685da8f1c7ac6bf027cadd730
Author: Mark Wielaard <ma...@kl...>
Date:   Sun Mar 30 13:08:55 2025 +0200

    filter_gdb.in: filter out __libc_do_syscall
    
    On i386 and armhf __libc_do_syscall might be used to invoke a syscall.
    Replace __libc_do_syscall with "in syscall ..." and filter out
    possible extra (assembly) source file lines containing
    libc-do-syscall.S from the gdb output.
    
    https://bugs.kde.org/show_bug.cgi?id=502126
    
    (cherry picked from commit ddcb3aa3ed3188cd28c193225245a76e928b850b)

Diff:
---
 gdbserver_tests/filter_gdb.in | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in
index e2b329a604..d7b1bb11c6 100755
--- a/gdbserver_tests/filter_gdb.in
+++ b/gdbserver_tests/filter_gdb.in
@@ -137,6 +137,12 @@ s/in _dl_sysinfo_int80 () from \/lib\/ld-linux.so.*/in syscall .../
 #      in __syscall_cancel_arch is just in a syscall
 s/in __syscall_cancel_arch .*/in syscall .../
 
+#	do_syscall is in syscall
+s/__libc_do_syscall ().*/0x........ in syscall .../
+
+#       extra source code line
+/libc-do-syscall.S/d
+
 #       anonymise kill syscall.
 s/in kill ().*$/in syscall .../

[Valgrind-developers] [valgrind] filter_gdb.in: filter out __libc_do_syscall

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ddcb3aa3ed3188cd28c193225245a76e928b850b

commit ddcb3aa3ed3188cd28c193225245a76e928b850b
Author: Mark Wielaard <ma...@kl...>
Date:   Sun Mar 30 13:08:55 2025 +0200

    filter_gdb.in: filter out __libc_do_syscall
    
    On i386 and armhf __libc_do_syscall might be used to invoke a syscall.
    Replace __libc_do_syscall with "in syscall ..." and filter out
    possible extra (assembly) source file lines containing
    libc-do-syscall.S from the gdb output.
    
    https://bugs.kde.org/show_bug.cgi?id=502126

Diff:
---
 gdbserver_tests/filter_gdb.in | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in
index e2b329a604..d7b1bb11c6 100755
--- a/gdbserver_tests/filter_gdb.in
+++ b/gdbserver_tests/filter_gdb.in
@@ -137,6 +137,12 @@ s/in _dl_sysinfo_int80 () from \/lib\/ld-linux.so.*/in syscall .../
 #      in __syscall_cancel_arch is just in a syscall
 s/in __syscall_cancel_arch .*/in syscall .../
 
+#	do_syscall is in syscall
+s/__libc_do_syscall ().*/0x........ in syscall .../
+
+#       extra source code line
+/libc-do-syscall.S/d
+
 #       anonymise kill syscall.
 s/in kill ().*$/in syscall .../

[Valgrind-developers] [valgrind] Linux PPC: add a suppression for an invalid read in libaio io_getevents

[Paul F. <pa...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ec3e8e7f6e5effc92923ce4058f07430ba2d065a

commit ec3e8e7f6e5effc92923ce4058f07430ba2d065a
Author: Paul Floyd <pj...@wa...>
Date:   Sun Mar 30 09:00:34 2025 +0200

    Linux PPC: add a suppression for an invalid read in libaio io_getevents
    
    The testcase memcheck/tests/linux/bug420682_1 should be a straightforward
    clean test. On old PPC systems it produces one error.

Diff:
---
 glibc-2.X.supp.in | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/glibc-2.X.supp.in b/glibc-2.X.supp.in
index fc346d8037..f606dd5df1 100644
--- a/glibc-2.X.supp.in
+++ b/glibc-2.X.supp.in
@@ -213,6 +213,12 @@
    obj:/*libc-@GLIBC_VERSION@*.so
 }
 
+{
+   libaio-CentOS-7.9-(PPC)
+   Memcheck:Addr4
+   fun:io_getevents
+}
+
 ##----------------------------------------------------------------------##
 # MontaVista Linux 4.0.1 on ppc32
 {

[Valgrind-developers] [valgrind] s390x: Fix disassembly for BFP/DFP conversion opcodes (BZ 495817)

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b720115d2f7c6aebb56c1635b81637df25a4e2d9

commit b720115d2f7c6aebb56c1635b81637df25a4e2d9
Author: Florian Krohm <fl...@ei...>
Date:   Sat Mar 29 22:54:53 2025 +0000

    s390x: Fix disassembly for BFP/DFP conversion opcodes  (BZ 495817)
    
    Specifically:
    - BFP convert from/to fixed
    - BFP convert from/to logical
    - DFP convert from/to fixed
    - DFP convert from/to logical
    
    Change function names from e.g. s390_irgen/emit_CEFBR to
    s390_irgen/emit_CEFBRA because CFEBR does not have m3 and m4 operands.
    Adjust the returned mnemonic accordingly.
    
    New functions fp_convf_disasm and fp_convt_disasm.
    
    Part of fixing https://bugs.kde.org/show_bug.cgi?id=495817

Diff:
---
 VEX/priv/guest_s390_toIR.c | 128 ++++++++++++++++++------------------
 VEX/priv/host_s390_defs.c  | 158 +++++++++++++++++++--------------------------
 VEX/priv/s390_disasm.c     |  88 +++++++++++++++++++++++++
 VEX/priv/s390_disasm.h     |   2 +
 4 files changed, 219 insertions(+), 157 deletions(-)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 1ed10acbbb..7b029623d6 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -3115,7 +3115,7 @@ s390_format_RRF_UUFR(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1,
    const HChar *mnm = irgen(m3, m4, r1, r2);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM(mnm, fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 }
 
 static void
@@ -3126,7 +3126,7 @@ s390_format_RRF_UURF(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1,
    const HChar *mnm = irgen(m3, m4, r1, r2);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM(mnm, fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 }
 
 
@@ -11394,8 +11394,8 @@ s390_irgen_ADB(UChar r1, IRTemp op2addr)
 }
 
 static const HChar *
-s390_irgen_CEFBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CEFBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -11407,24 +11407,24 @@ s390_irgen_CEFBR(UChar m3, UChar m4 __attribute__((unused)),
    put_fpr_w0(r1, binop(Iop_I32StoF32, mkexpr(encode_bfp_rounding_mode(m3)),
                         mkexpr(op2)));
 
-   return "cefbr";
+   return "cefbra";
 }
 
 static const HChar *
-s390_irgen_CDFBR(UChar m3 __attribute__((unused)),
-                 UChar m4 __attribute__((unused)), UChar r1, UChar r2)
+s390_irgen_CDFBRA(UChar m3 __attribute__((unused)),
+                  UChar m4 __attribute__((unused)), UChar r1, UChar r2)
 {
    IRTemp op2 = newTemp(Ity_I32);
 
    assign(op2, get_gpr_w1(r2));
    put_fpr_dw0(r1, unop(Iop_I32StoF64, mkexpr(op2)));
 
-   return "cdfbr";
+   return "cdfbra";
 }
 
 static const HChar *
-s390_irgen_CEGBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CEGBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -11436,12 +11436,12 @@ s390_irgen_CEGBR(UChar m3, UChar m4 __attribute__((unused)),
    put_fpr_w0(r1, binop(Iop_I64StoF32, mkexpr(encode_bfp_rounding_mode(m3)),
                         mkexpr(op2)));
 
-   return "cegbr";
+   return "cegbra";
 }
 
 static const HChar *
-s390_irgen_CDGBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CDGBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_fpext && m3 != S390_BFP_ROUND_PER_FPC) {
       emulation_warning(EmWarn_S390X_fpext_rounding);
@@ -11453,7 +11453,7 @@ s390_irgen_CDGBR(UChar m3, UChar m4 __attribute__((unused)),
    put_fpr_dw0(r1, binop(Iop_I64StoF64, mkexpr(encode_bfp_rounding_mode(m3)),
                          mkexpr(op2)));
 
-   return "cdgbr";
+   return "cdgbra";
 }
 
 static const HChar *
@@ -11601,8 +11601,8 @@ s390_irgen_CLGDBR(UChar m3, UChar m4 __attribute__((unused)),
 }
 
 static const HChar *
-s390_irgen_CFEBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CFEBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F32);
    IRTemp result = newTemp(Ity_I32);
@@ -11614,12 +11614,12 @@ s390_irgen_CFEBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_w1(r1, mkexpr(result));
    s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_INT_32, op, rounding_mode);
 
-   return "cfebr";
+   return "cfebra";
 }
 
 static const HChar *
-s390_irgen_CFDBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CFDBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F64);
    IRTemp result = newTemp(Ity_I32);
@@ -11631,12 +11631,12 @@ s390_irgen_CFDBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_w1(r1, mkexpr(result));
    s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_INT_32, op, rounding_mode);
 
-   return "cfdbr";
+   return "cfdbra";
 }
 
 static const HChar *
-s390_irgen_CGEBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CGEBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F32);
    IRTemp result = newTemp(Ity_I64);
@@ -11648,12 +11648,12 @@ s390_irgen_CGEBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_dw0(r1, mkexpr(result));
    s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_INT_64, op, rounding_mode);
 
-   return "cgebr";
+   return "cgebra";
 }
 
 static const HChar *
-s390_irgen_CGDBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CGDBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F64);
    IRTemp result = newTemp(Ity_I64);
@@ -11665,7 +11665,7 @@ s390_irgen_CGDBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_dw0(r1, mkexpr(result));
    s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_INT_64, op, rounding_mode);
 
-   return "cgdbr";
+   return "cgdbra";
 }
 
 static const HChar *
@@ -12111,12 +12111,12 @@ s390_irgen_CDGTRA(UChar m3, UChar m4 __attribute__((unused)),
       put_dpr_dw0(r1, binop(Iop_I64StoD64, mkexpr(encode_dfp_rounding_mode(m3)),
                             mkexpr(op2)));
    }
-   return (m3 == 0) ? "cdgtr" : "cdgtra";
+   return "cdgtra";
 }
 
 static const HChar *
-s390_irgen_CXGTR(UChar m3 __attribute__((unused)),
-                 UChar m4 __attribute__((unused)), UChar r1, UChar r2)
+s390_irgen_CXGTRA(UChar m3 __attribute__((unused)),
+                  UChar m4 __attribute__((unused)), UChar r1, UChar r2)
 {
    if (! s390_host_has_dfp) {
       emulation_failure(EmFail_S390X_DFP_insn);
@@ -12129,7 +12129,7 @@ s390_irgen_CXGTR(UChar m3 __attribute__((unused)),
       assign(op2, get_gpr_dw0(r2));
       put_dpr_pair(r1, unop(Iop_I64StoD128, mkexpr(op2)));
    }
-   return "cxgtr";
+   return "cxgtra";
 }
 
 static const HChar *
@@ -12236,7 +12236,7 @@ s390_irgen_CFDTR(UChar m3, UChar m4 __attribute__((unused)),
 
 static const HChar *
 s390_irgen_CFXTR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_dfp) {
       emulation_failure(EmFail_S390X_DFP_insn);
@@ -12260,8 +12260,8 @@ s390_irgen_CFXTR(UChar m3, UChar m4 __attribute__((unused)),
 }
 
 static const HChar *
-s390_irgen_CGDTR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CGDTRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_dfp) {
       emulation_failure(EmFail_S390X_DFP_insn);
@@ -12280,12 +12280,12 @@ s390_irgen_CGDTR(UChar m3, UChar m4 __attribute__((unused)),
       put_gpr_dw0(r1, binop(Iop_D64toI64S, mkexpr(rounding_mode), mkexpr(op)));
       s390_cc_thunk_putFZ(S390_CC_OP_DFP_64_TO_INT_64, op, rounding_mode);
    }
-   return "cgdtr";
+   return "cgdtra";
 }
 
 static const HChar *
-s390_irgen_CGXTR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CGXTRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    if (! s390_host_has_dfp) {
       emulation_failure(EmFail_S390X_DFP_insn);
@@ -12303,7 +12303,7 @@ s390_irgen_CGXTR(UChar m3, UChar m4 __attribute__((unused)),
       put_gpr_dw0(r1, binop(Iop_D128toI64S, mkexpr(rounding_mode), mkexpr(op)));
       s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_128_TO_INT_64, op, rounding_mode);
    }
-   return "cgxtr";
+   return "cgxtra";
 }
 
 static const HChar *
@@ -14643,15 +14643,15 @@ s390_irgen_KDB(UChar r1, IRTemp op2addr)
 }
 
 static const HChar *
-s390_irgen_CXFBR(UChar m3 __attribute__((unused)),
-                 UChar m4 __attribute__((unused)), UChar r1, UChar r2)
+s390_irgen_CXFBRA(UChar m3 __attribute__((unused)),
+                  UChar m4 __attribute__((unused)), UChar r1, UChar r2)
 {
    IRTemp op2 = newTemp(Ity_I32);
 
    assign(op2, get_gpr_w1(r2));
    put_fpr_pair(r1, unop(Iop_I32StoF128, mkexpr(op2)));
 
-   return "cxfbr";
+   return "cxfbra";
 }
 
 static const HChar *
@@ -14671,15 +14671,15 @@ s390_irgen_CXLFBR(UChar m3 __attribute__((unused)),
 
 
 static const HChar *
-s390_irgen_CXGBR(UChar m3 __attribute__((unused)),
-                 UChar m4 __attribute__((unused)), UChar r1, UChar r2)
+s390_irgen_CXGBRA(UChar m3 __attribute__((unused)),
+                  UChar m4 __attribute__((unused)), UChar r1, UChar r2)
 {
    IRTemp op2 = newTemp(Ity_I64);
 
    assign(op2, get_gpr_dw0(r2));
    put_fpr_pair(r1, unop(Iop_I64StoF128, mkexpr(op2)));
 
-   return "cxgbr";
+   return "cxgbra";
 }
 
 static const HChar *
@@ -14698,8 +14698,8 @@ s390_irgen_CXLGBR(UChar m3 __attribute__((unused)),
 }
 
 static const HChar *
-s390_irgen_CFXBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CFXBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F128);
    IRTemp result = newTemp(Ity_I32);
@@ -14711,7 +14711,7 @@ s390_irgen_CFXBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_w1(r1, mkexpr(result));
    s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_INT_32, op, rounding_mode);
 
-   return "cfxbr";
+   return "cfxbra";
 }
 
 static const HChar *
@@ -14736,8 +14736,8 @@ s390_irgen_CLFXBR(UChar m3, UChar m4 __attribute__((unused)),
 
 
 static const HChar *
-s390_irgen_CGXBR(UChar m3, UChar m4 __attribute__((unused)),
-                 UChar r1, UChar r2)
+s390_irgen_CGXBRA(UChar m3, UChar m4 __attribute__((unused)),
+                  UChar r1, UChar r2)
 {
    IRTemp op = newTemp(Ity_F128);
    IRTemp result = newTemp(Ity_I64);
@@ -14749,7 +14749,7 @@ s390_irgen_CGXBR(UChar m3, UChar m4 __attribute__((unused)),
    put_gpr_dw0(r1, mkexpr(result));
    s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_INT_64, op, rounding_mode);
 
-   return "cgxbr";
+   return "cgxbra";
 }
 
 static const HChar *
@@ -20816,22 +20816,22 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb392: s390_format_RRF_UUFR(s390_irgen_CXLFBR, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb394: s390_format_RRF_UUFR(s390_irgen_CEFBR, RRF2_m3(ovl),
+   case 0xb394: s390_format_RRF_UUFR(s390_irgen_CEFBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb395: s390_format_RRF_UUFR(s390_irgen_CDFBR, RRF2_m3(ovl),
+   case 0xb395: s390_format_RRF_UUFR(s390_irgen_CDFBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb396: s390_format_RRF_UUFR(s390_irgen_CXFBR, RRF2_m3(ovl),
+   case 0xb396: s390_format_RRF_UUFR(s390_irgen_CXFBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb398: s390_format_RRF_UURF(s390_irgen_CFEBR, RRF2_m3(ovl),
+   case 0xb398: s390_format_RRF_UURF(s390_irgen_CFEBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb399: s390_format_RRF_UURF(s390_irgen_CFDBR, RRF2_m3(ovl),
+   case 0xb399: s390_format_RRF_UURF(s390_irgen_CFDBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb39a: s390_format_RRF_UURF(s390_irgen_CFXBR, RRF2_m3(ovl),
+   case 0xb39a: s390_format_RRF_UURF(s390_irgen_CFXBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
    case 0xb39c: s390_format_RRF_UURF(s390_irgen_CLFEBR, RRF2_m3(ovl),
@@ -20852,22 +20852,22 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb3a2: s390_format_RRF_UUFR(s390_irgen_CXLGBR, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3a4: s390_format_RRF_UUFR(s390_irgen_CEGBR, RRF2_m3(ovl),
+   case 0xb3a4: s390_format_RRF_UUFR(s390_irgen_CEGBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3a5: s390_format_RRF_UUFR(s390_irgen_CDGBR, RRF2_m3(ovl),
+   case 0xb3a5: s390_format_RRF_UUFR(s390_irgen_CDGBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3a6: s390_format_RRF_UUFR(s390_irgen_CXGBR, RRF2_m3(ovl),
+   case 0xb3a6: s390_format_RRF_UUFR(s390_irgen_CXGBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3a8: s390_format_RRF_UURF(s390_irgen_CGEBR, RRF2_m3(ovl),
+   case 0xb3a8: s390_format_RRF_UURF(s390_irgen_CGEBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3a9: s390_format_RRF_UURF(s390_irgen_CGDBR, RRF2_m3(ovl),
+   case 0xb3a9: s390_format_RRF_UURF(s390_irgen_CGDBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
-   case 0xb3aa: s390_format_RRF_UURF(s390_irgen_CGXBR, RRF2_m3(ovl),
+   case 0xb3aa: s390_format_RRF_UURF(s390_irgen_CGXBRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
    case 0xb3ac: s390_format_RRF_UURF(s390_irgen_CLGEBR, RRF2_m3(ovl),
@@ -20936,7 +20936,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
                                    RRE_r2(ovl));  goto ok;
    case 0xb3df: /* FIXTR */ goto unimplemented;
    case 0xb3e0: /* KDTR */ goto unimplemented;
-   case 0xb3e1: s390_format_RRF_UURF(s390_irgen_CGDTR, RRF2_m3(ovl),
+   case 0xb3e1: s390_format_RRF_UURF(s390_irgen_CGDTRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
    case 0xb3e2: /* CUDTR */ goto unimplemented;
@@ -20948,7 +20948,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb3e7: s390_format_RRE_RF(s390_irgen_ESDTR, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
    case 0xb3e8: /* KXTR */ goto unimplemented;
-   case 0xb3e9: s390_format_RRF_UURF(s390_irgen_CGXTR, RRF2_m3(ovl),
+   case 0xb3e9: s390_format_RRF_UURF(s390_irgen_CGXTRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
    case 0xb3ea: /* CUXTR */ goto unimplemented;
@@ -20974,7 +20974,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb3f7: s390_format_RRF_FFRU(s390_irgen_RRDTR, RRF4_r3(ovl),
                                      RRF4_m4(ovl), RRF4_r1(ovl),
                                      RRF4_r2(ovl)); goto ok;
-   case 0xb3f9: s390_format_RRF_UUFR(s390_irgen_CXGTR, RRF2_m3(ovl),
+   case 0xb3f9: s390_format_RRF_UUFR(s390_irgen_CXGTRA, RRF2_m3(ovl),
                                      RRF2_m4(ovl), RRF2_r1(ovl),
                                      RRF2_r2(ovl));  goto ok;
    case 0xb3fa: /* CXUTR */ goto unimplemented;
diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index 37b4b5baa3..684d173588 100644
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -3939,12 +3939,8 @@ s390_emit_CEFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cefbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cefbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cefbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3940000, m3, m4, r1, r2);
 }
@@ -3956,12 +3952,8 @@ s390_emit_CDFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cdfbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cdfbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cdfbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3950000, m3, m4, r1, r2);
 }
@@ -3973,12 +3965,8 @@ s390_emit_CXFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cxfbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cxfbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cxfbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3960000, m3, m4, r1, r2);
 }
@@ -3990,12 +3978,8 @@ s390_emit_CEGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cegbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cegbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cegbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a40000, m3, m4, r1, r2);
 }
@@ -4007,12 +3991,8 @@ s390_emit_CDGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cdgbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cdgbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cdgbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a50000, m3, m4, r1, r2);
 }
@@ -4024,12 +4004,8 @@ s390_emit_CXGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cxgbr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cxgbra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cxgbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a60000, m3, m4, r1, r2);
 }
@@ -4042,7 +4018,7 @@ s390_emit_CELFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("celfbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("celfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3900000, m3, m4, r1, r2);
 }
@@ -4055,7 +4031,7 @@ s390_emit_CDLFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cdlfbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cdlfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3910000, m3, m4, r1, r2);
 }
@@ -4068,7 +4044,7 @@ s390_emit_CXLFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxlfbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cxlfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3920000, m3, m4, r1, r2);
 }
@@ -4081,7 +4057,7 @@ s390_emit_CELGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("celgbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("celgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a00000, m3, m4, r1, r2);
 }
@@ -4094,7 +4070,7 @@ s390_emit_CDLGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cdlgbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cdlgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a10000, m3, m4, r1, r2);
 }
@@ -4107,7 +4083,7 @@ s390_emit_CXLGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxlgbr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cxlgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3a20000, m3, m4, r1, r2);
 }
@@ -4120,7 +4096,7 @@ s390_emit_CLFEBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clfebr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clfebr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb39c0000, m3, m4, r1, r2);
 }
@@ -4133,7 +4109,7 @@ s390_emit_CLFDBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clfdbr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clfdbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb39d0000, m3, m4, r1, r2);
 }
@@ -4146,7 +4122,7 @@ s390_emit_CLFXBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clfxbr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clfxbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb39e0000, m3, m4, r1, r2);
 }
@@ -4159,7 +4135,7 @@ s390_emit_CLGEBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clgebr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clgebr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3ac0000, m3, m4, r1, r2);
 }
@@ -4172,7 +4148,7 @@ s390_emit_CLGDBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clgdbr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clgdbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3ad0000, m3, m4, r1, r2);
 }
@@ -4185,67 +4161,67 @@ s390_emit_CLGXBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clgxbr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clgxbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3ae0000, m3, m4, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CFEBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CFEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cfebr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cfebra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb3980000, m3, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CFDBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CFDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cfdbr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cfdbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb3990000, m3, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CFXBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CFXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cfxbr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cfxbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb39a0000, m3, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CGEBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CGEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cgebr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cgebra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb3a80000, m3, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CGDBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CGDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cgdbr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cgdbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb3a90000, m3, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CGXBR(UChar *p, UChar m3, UChar r1, UChar r2)
+s390_emit_CGXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cgxbr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cgxbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF3(p, 0xb3aa0000, m3, r1, r2);
 }
@@ -4691,19 +4667,15 @@ s390_emit_CDGTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m4 == 0);
    vassert(m3 == 0 || s390_host_has_fpext);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
-      if (m3 == 0)
-         S390_DISASM(MNM("cdgtr"), FPR(r1), GPR(r2));
-      else
-         S390_DISASM(MNM("cdgtra"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
-   }
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+      S390_DISASM(XMNM("cdgtra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3f10000, m3, m4, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CXGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
+s390_emit_CXGTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0);
@@ -4712,7 +4684,7 @@ s390_emit_CXGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(m3 == 0);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxgtr"), FPR(r1), GPR(r2));
+      S390_DISASM(XMNM("cxgtra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3f90000, m3, m4, r1, r2);
 }
@@ -4726,7 +4698,7 @@ s390_emit_CDFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cdftr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cdftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9510000, m3, m4, r1, r2);
 }
@@ -4740,7 +4712,7 @@ s390_emit_CXFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxftr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cxftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9590000, m3, m4, r1, r2);
 }
@@ -4754,7 +4726,7 @@ s390_emit_CDLFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cdlftr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cdlftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9530000, m3, m4, r1, r2);
 }
@@ -4768,7 +4740,7 @@ s390_emit_CXLFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxlftr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cxlftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb95b0000, m3, m4, r1, r2);
 }
@@ -4782,7 +4754,7 @@ s390_emit_CDLGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cdlgtr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cdlgtr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9520000, m3, m4, r1, r2);
 }
@@ -4796,7 +4768,7 @@ s390_emit_CXLGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cxlgtr"), FPR(r1), UINT(m3), GPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cxlgtr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb95a0000, m3, m4, r1, r2);
 }
@@ -4830,7 +4802,7 @@ s390_emit_CFDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cfdtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cfdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9410000, m3, m4, r1, r2);
 }
@@ -4844,35 +4816,35 @@ s390_emit_CFXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cfxtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("cfxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9490000, m3, m4, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CGDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
+s390_emit_CGDTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0);
    vassert(s390_host_has_fpext || m3 < 1 || m3 > 7);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cgdtr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cgdtra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3e10000, m3, m4, r1, r2);
 }
 
 
 static UChar *
-s390_emit_CGXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
+s390_emit_CGXTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
 {
    vassert(s390_host_has_dfp);
    vassert(m4 == 0);
    vassert(s390_host_has_fpext || m3 < 1 || m3 > 7);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("cgxtr"), GPR(r1), UINT(m3), FPR(r2));
+      S390_DISASM(XMNM("cgxtra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb3e90000, m3, m4, r1, r2);
 }
@@ -4886,7 +4858,7 @@ s390_emit_CLFDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clfdtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clfdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9430000, m3, m4, r1, r2);
 }
@@ -4900,7 +4872,7 @@ s390_emit_CLFXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clfxtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clfxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb94b0000, m3, m4, r1, r2);
 }
@@ -4914,7 +4886,7 @@ s390_emit_CLGDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clgdtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clgdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb9420000, m3, m4, r1, r2);
 }
@@ -4928,7 +4900,7 @@ s390_emit_CLGXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2)
    vassert(s390_host_has_fpext);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
-      S390_DISASM(MNM("clgxtr"), GPR(r1), UINT(m3), FPR(r2), UINT(m4));
+      S390_DISASM(XMNM("clgxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4));
 
    return emit_RRF2(p, 0xb94a0000, m3, m4, r1, r2);
 }
@@ -10645,12 +10617,12 @@ s390_insn_bfp_convert_emit(UChar *buf, const s390_insn *insn)
 
    switch (insn->variant.bfp_convert.tag) {
       /* Convert to fixed */
-   case S390_BFP_F32_TO_I32:  return s390_emit_CFEBR(buf, m3, r1, r2);
-   case S390_BFP_F64_TO_I32:  return s390_emit_CFDBR(buf, m3, r1, r2);
-   case S390_BFP_F128_TO_I32: return s390_emit_CFXBR(buf, m3, r1, r2);
-   case S390_BFP_F32_TO_I64:  return s390_emit_CGEBR(buf, m3, r1, r2);
-   case S390_BFP_F64_TO_I64:  return s390_emit_CGDBR(buf, m3, r1, r2);
-   case S390_BFP_F128_TO_I64: return s390_emit_CGXBR(buf, m3, r1, r2);
+   case S390_BFP_F32_TO_I32:  return s390_emit_CFEBRA(buf, m3, m4, r1, r2);
+   case S390_BFP_F64_TO_I32:  return s390_emit_CFDBRA(buf, m3, m4, r1, r2);
+   case S390_BFP_F128_TO_I32: return s390_emit_CFXBRA(buf, m3, m4, r1, r2);
+   case S390_BFP_F32_TO_I64:  return s390_emit_CGEBRA(buf, m3, m4, r1, r2);
+   case S390_BFP_F64_TO_I64:  return s390_emit_CGDBRA(buf, m3, m4, r1, r2);
+   case S390_BFP_F128_TO_I64: return s390_emit_CGXBRA(buf, m3, m4, r1, r2);
 
       /* Convert to logical */
    case S390_BFP_F32_TO_U32:  return s390_emit_CLFEBR(buf, m3, m4, r1, r2);
@@ -10884,8 +10856,8 @@ s390_insn_dfp_convert_emit(UChar *buf, const s390_insn *insn)
       /* Convert to fixed */
    case S390_DFP_D64_TO_I32:  return s390_emit_CFDTR(buf, m3, m4, r1, r2);
    case S390_DFP_D128_TO_I32: return s390_emit_CFXTR(buf, m3, m4, r1, r2);
-   case S390_DFP_D64_TO_I64:  return s390_emit_CGDTR(buf, m3, m4, r1, r2);
-   case S390_DFP_D128_TO_I64: return s390_emit_CGXTR(buf, m3, m4, r1, r2);
+   case S390_DFP_D64_TO_I64:  return s390_emit_CGDTRA(buf, m3, m4, r1, r2);
+   case S390_DFP_D128_TO_I64: return s390_emit_CGXTRA(buf, m3, m4, r1, r2);
 
       /* Convert to logical */
    case S390_DFP_D64_TO_U32:  return s390_emit_CLFDTR(buf, m3, m4, r1, r2);
@@ -10897,7 +10869,7 @@ s390_insn_dfp_convert_emit(UChar *buf, const s390_insn *insn)
    case S390_DFP_I32_TO_D64:  return s390_emit_CDFTR(buf, 0, m4, r1, r2);
    case S390_DFP_I32_TO_D128: return s390_emit_CXFTR(buf, 0, m4, r1, r2);
    case S390_DFP_I64_TO_D64:  return s390_emit_CDGTRA(buf, m3, m4, r1, r2);
-   case S390_DFP_I64_TO_D128: return s390_emit_CXGTR(buf, 0, m4, r1, r2);
+   case S390_DFP_I64_TO_D128: return s390_emit_CXGTRA(buf, 0, m4, r1, r2);
 
       /* Convert from logical */
    case S390_DFP_U32_TO_D64:  return s390_emit_CDLFTR(buf, m3, m4, r1, r2);
diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c
index 3812de0e9a..9649f9f0e1 100644
--- a/VEX/priv/s390_disasm.c
+++ b/VEX/priv/s390_disasm.c
@@ -524,6 +524,15 @@ always_mh(UInt ix __attribute__((unused)),
 }
 
 
+static Int
+never_mh(UInt ix __attribute__((unused)),
+         UInt mask, UInt *value)
+{
+   *value = mask;
+   return 0;
+}
+
+
 HChar *
 vfce_like_disasm(const s390_opnd *opnds, HChar *p)
 {
@@ -978,6 +987,85 @@ vcgld_disasm(const s390_opnd *opnds, HChar *p)
 }
 
 
+/* Used by BFP / DFP convert from fixed / logical opcodes
+
+   1) Mnemonics ending in 'A', e.g. CEFBRA
+      a) m3 == m4 == 0  --> CEFBR and no mask values written
+      b) otherwise      --> CEFBRA and both mask values written
+
+   2) Mnemonics for "logical" opcodes, e.g. CELFBR
+      These do not end in 'A'
+      --> mnemonic unchanged, both mask values written
+
+   3) Neither #1 nor #2, e.g. CDFTR
+      --> mnemonic unchanged, both mask values written
+*/
+HChar *
+fp_convf_disasm(const s390_opnd *opnds, HChar *p)
+{
+   vassert(mask_count(opnds) == 2);
+
+   const HChar *base = opnds[0].xmnm.base;
+   UInt m3 = opnds[get_mask_index(opnds, 1)].mask;
+   UInt m4 = opnds[get_mask_index(opnds, 2)].mask;
+   UInt len = vex_strlen(base);
+
+   HChar xmnm[len + 1];
+
+   vex_sprintf(xmnm, "%s", base);
+
+   if (xmnm[len - 1] == 'a' && m3 + m4 == 0) {
+      xmnm[len - 1] = '\0';
+      return s390_disasm_aux(opnds, xmnm, p, never_mh);
+   }
+   return s390_disasm_aux(opnds, xmnm, p, always_mh);
+}
+
+
+/* Return 1, if mask should be printed. In *VALUE return the mask value
+   that should be printed.  */
+static Int
+fp_convt_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value)
+{
+   *value = mask;
+   return (ix == 2 || mask != 0) ? 1 : 0;
+}
+
+
+/* Used by BFP / DFP convert to fixed / logical opcodes
+
+   1) Mnemonics ending in 'A', e.g. CFEBRA
+      a) m4 == 0     --> CFEBR and no mask values written
+      b) otherwise   --> CFEBRA and both mask values written
+
+   2) Mnemonics for "logical" opcodes, e.g. CLFEBR
+      These do not end in 'A'
+      --> mnemonic unchanged, both mask values written
+
+   3) Neither #1 nor #2, e.g. CFDTR
+      --> mnemonic unchanged, both mask values written
+*/
+HChar *
+fp_convt_disasm(const s390_opnd *opnds, HChar *p)
+{
+   vassert(mask_count(opnds) == 2);
+
+   const HChar *base = opnds[0].xmnm.base;
+   UInt m4 = opnds[get_mask_index(opnds, 2)].mask;
+   UInt len = vex_strlen(base);
+
+   HChar xmnm[len + 1];
+
+   vex_sprintf(xmnm, "%s", base);
+
+   if (xmnm[len - 1] == 'a' && m4 == 0) {
+      xmnm[len - 1] = '\0';
+      return s390_disasm_aux(opnds, xmnm, p, fp_convt_mh);
+   }
+   return s390_disasm_aux(opnds, xmnm, p, always_mh);
+}
+
+
 /* Write out OPNDS. MH is a mask handler. It decides whether or not a
    MASK operand is written and if so, massages the mask value as needed. */
 static HChar *
diff --git a/VEX/priv/s390_disasm.h b/VEX/priv/s390_disasm.h
index 89fc9e8de6..b28af8f659 100644
--- a/VEX/priv/s390_disasm.h
+++ b/VEX/priv/s390_disasm.h
@@ -135,6 +135,8 @@ HChar *wfc_like_disasm(const s390_opnd *, HChar *);
 HChar *vfae_like_disasm(const s390_opnd *, HChar *);
 HChar *vfce_like_disasm(const s390_opnd *, HChar *);
 HChar *vfmix_like_disasm(const s390_opnd *, HChar *);
+HChar *fp_convf_disasm(const s390_opnd *, HChar *);
+HChar *fp_convt_disasm(const s390_opnd *, HChar *);
 
 /*---------------------------------------------------------------*/
 /*--- end                                       s390_disasm.h ---*/

[Valgrind-developers] [valgrind] arm/v6intThumb: Disable tests for instructions modifying pc (ldr pc, add pc)

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ae32e44d1e891dd2adbb056b0bb127b21efc1b67

commit ae32e44d1e891dd2adbb056b0bb127b21efc1b67
Author: Mark Wielaard <ma...@kl...>
Date:   Sat Mar 29 21:21:45 2025 +0100

    arm/v6intThumb: Disable tests for instructions modifying pc (ldr pc, add pc)
    
    The test doesn't compile.
    
    /usr/bin/ld: v6intThumb-v6intThumb.o(.text+0xf2): unresolvable
    R_ARM_THM_CALL relocation against symbol `printf@@GLIBC_2.4'
    
    Changing the movw and movt into a ldr as suggested in
    https://bugs.kde.org/show_bug.cgi?id=339862#c1
    Causes a different compile error.
    
    /tmp/ccveFwf0.s:140: Error: offset out of range
    
    So disable it for now.

Diff:
---
 none/tests/arm/v6intThumb.c          | 5 +++--
 none/tests/arm/v6intThumb.stdout.exp | 2 --
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/none/tests/arm/v6intThumb.c b/none/tests/arm/v6intThumb.c
index e05b900855..7b769cedd7 100644
--- a/none/tests/arm/v6intThumb.c
+++ b/none/tests/arm/v6intThumb.c
@@ -344,7 +344,7 @@ static int gen_cvin(int cvin)
 ////////////////////////////////////////////////////////////
 ///////////////////////////////////////////////////////////
 ///////////////////////////////////////////////////////////
-
+/*
 __attribute__((noinline))
 void test_ldr_pc(void) {
     // special case of ldr PC, [rN, +imm?]
@@ -395,6 +395,7 @@ void test_ldr_pc(void) {
 
     }    
 }
+*/
 
 static int old_main(void)
 {
@@ -649,7 +650,7 @@ static int old_main(void)
 
     TESTCARRYEND
 
-    test_ldr_pc();
+    // test_ldr_pc();
 #if 0
 	printf("ROR\n");
 	TESTCARRY
diff --git a/none/tests/arm/v6intThumb.stdout.exp b/none/tests/arm/v6intThumb.stdout.exp
index 9169f8865f..52404cf762 100644
--- a/none/tests/arm/v6intThumb.stdout.exp
+++ b/none/tests/arm/v6intThumb.stdout.exp
@@ -17316,8 +17316,6 @@ ldrh r1, label_magic_ldrh :: rd 0x0000881b, cpsr 0xc0000000 NZ
 ldrsb r1, label_magic_ldrsb :: rd 0x0000001b, cpsr 0xc0000000 NZ  
 ldrsh r1, label_magic_ldrsh :: rd 0xffff881b, cpsr 0xc0000000 NZ  
 vldr d0, label_magic_vldr :: s0 0x8191881b s1 0x18fe9c93, cpsr 0xc0000000 NZ  
-tests for instructions modifying pc (ldr pc, add pc)
-ldr.w pc, [r9, +#432] :: r1 0x0000002a c:v-in 0, cpsr 0xc0000000 NZ  
 MUL
 mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
 mul  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ

[Valgrind-developers] [valgrind] Bug 420682 - io_pgetevents is not supported

[Paul F. <pa...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=19c00de89e0fa21c62a5c0c0d1b1cc081f4ce00a

commit 19c00de89e0fa21c62a5c0c0d1b1cc081f4ce00a
Author: Paul Floyd <pj...@wa...>
Date:   Fri Mar 28 21:45:15 2025 +0100

    Bug 420682 - io_pgetevents is not supported

Diff:
---
 .gitignore                                  |  2 +
 NEWS                                        |  1 +
 configure.ac                                | 34 +++++++++++
 coregrind/m_syswrap/priv_syswrap-linux.h    |  1 +
 coregrind/m_syswrap/syswrap-amd64-linux.c   |  2 +
 coregrind/m_syswrap/syswrap-arm64-linux.c   |  2 +
 coregrind/m_syswrap/syswrap-linux.c         | 93 ++++++++++++++++++++---------
 coregrind/m_syswrap/syswrap-mips32-linux.c  |  1 +
 coregrind/m_syswrap/syswrap-mips64-linux.c  |  1 +
 coregrind/m_syswrap/syswrap-riscv64-linux.c |  1 +
 coregrind/m_syswrap/syswrap-s390x-linux.c   |  1 +
 coregrind/m_syswrap/syswrap-x86-linux.c     |  1 +
 include/vki/vki-linux.h                     |  5 ++
 include/vki/vki-scnums-arm64-linux.h        |  2 +-
 include/vki/vki-scnums-riscv64-linux.h      |  1 +
 memcheck/tests/linux/Makefile.am            | 17 ++++++
 memcheck/tests/linux/bug420682_1.c          | 37 ++++++++++++
 memcheck/tests/linux/bug420682_1.stderr.exp |  0
 memcheck/tests/linux/bug420682_1.vgtest     |  4 ++
 memcheck/tests/linux/bug420682_2.c          | 32 ++++++++++
 memcheck/tests/linux/bug420682_2.stderr.exp | 54 +++++++++++++++++
 memcheck/tests/linux/bug420682_2.vgtest     |  4 ++
 22 files changed, 267 insertions(+), 29 deletions(-)

diff --git a/.gitignore b/.gitignore
index d64b9fab74..f9e50b1357 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1181,6 +1181,8 @@
 /memcheck/tests/linux/.deps
 /memcheck/tests/linux/aligned_alloc
 /memcheck/tests/linux/brk
+/memcheck/tests/linux/bug420682_1
+/memcheck/tests/linux/bug420682_2
 /memcheck/tests/linux/bug480706
 /memcheck/tests/linux/capget
 /memcheck/tests/linux/check_preadv2_pwritev2
diff --git a/NEWS b/NEWS
index e4e6769ba8..40b9539596 100644
--- a/NEWS
+++ b/NEWS
@@ -33,6 +33,7 @@ than mailing the developers (or mailing lists) directly -- bugs that
 are not entered into bugzilla tend to get forgotten about or ignored.
 
 396415  Valgrind is not looking up $ORIGIN rpath of shebang programs
+420682  io_pgetevents is not supported
 469782  Valgrind does not support zstd-compressed debug sections
 487296  --track-fds=yes and --track-fds=all report erroneous information
         when fds 0, 1, or 2 are used as non-std
diff --git a/configure.ac b/configure.ac
index 5d3c6d02d4..dca5661fc6 100755
--- a/configure.ac
+++ b/configure.ac
@@ -2111,6 +2111,40 @@ AC_MSG_RESULT([no])
 
 AM_CONDITIONAL(HAVE_NR_MEMBARRIER, [test x$ac_have_nr_membarrier = xyes])
 
+AC_MSG_CHECKING([for __NR_io_pgetevents])
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
+#include <linux/unistd.h>
+]], [[
+return __NR_io_pgetevents
+]])], [
+ac_have_nr_io_pgetevents=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_nr_io_pgetevents=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(HAVE_NR_IO_PGETEVENTS, [test x$ac_have_nr_io_pgetevents = xyes])
+
+safe_LIBS="$LIBS"
+LIBS="-laio"
+AC_MSG_CHECKING([for libaio])
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
+#include <libaio.h>
+]], [[
+io_context_t ctx;
+io_submit(ctx, 1, NULL);
+]])], [
+ac_have_libaio=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_libaio=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(HAVE_LIBAIO, [test x$ac_have_libaio = xyes])
+LIBS=$safe_LIBS
+
 #----------------------------------------------------------------------------
 # Checking for supported compiler flags.
 #----------------------------------------------------------------------------
diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h
index 21bd966dcb..4dad82dfbb 100644
--- a/coregrind/m_syswrap/priv_syswrap-linux.h
+++ b/coregrind/m_syswrap/priv_syswrap-linux.h
@@ -49,6 +49,7 @@ DECL_TEMPLATE(linux, sys_preadv);
 DECL_TEMPLATE(linux, sys_preadv2);
 DECL_TEMPLATE(linux, sys_pwritev);
 DECL_TEMPLATE(linux, sys_pwritev2);
+DECL_TEMPLATE(linux, sys_io_pgetevents);
 DECL_TEMPLATE(linux, sys_sendmmsg);
 DECL_TEMPLATE(linux, sys_recvmmsg);
 DECL_TEMPLATE(linux, sys_dup3);
diff --git a/coregrind/m_syswrap/syswrap-amd64-linux.c b/coregrind/m_syswrap/syswrap-amd64-linux.c
index 4189241109..646a832408 100644
--- a/coregrind/m_syswrap/syswrap-amd64-linux.c
+++ b/coregrind/m_syswrap/syswrap-amd64-linux.c
@@ -875,6 +875,8 @@ static SyscallTableEntry syscall_table[] = {
    LINX_(__NR_pkey_alloc,        sys_pkey_alloc),        // 330
    LINX_(__NR_pkey_free,         sys_pkey_free),         // 331
 
+   LINX_(__NR_io_pgetevents,     sys_io_pgetevents),     // 333
+
    LINXY(__NR_io_uring_setup,    sys_io_uring_setup),    // 425
    LINXY(__NR_io_uring_enter,    sys_io_uring_enter),    // 426
    LINXY(__NR_io_uring_register, sys_io_uring_register), // 427
diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
index 28d36764b5..c8bb486c4b 100644
--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
@@ -824,6 +824,8 @@ static SyscallTableEntry syscall_main_table[] = {
    //   (__NR_pkey_alloc,        sys_ni_syscall),        // 289
    //   (__NR_pkey_free,         sys_ni_syscall),        // 290
    LINXY(__NR_statx,             sys_statx),             // 291
+   LINX_(__NR_io_pgetevents,     sys_io_pgetevents),     // 292
+
 
    GENX_(__NR_rseq,              sys_ni_syscall),        // 293
 
diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c
index 8c166844cc..92771577bd 100644
--- a/coregrind/m_syswrap/syswrap-linux.c
+++ b/coregrind/m_syswrap/syswrap-linux.c
@@ -2569,32 +2569,49 @@ PRE(sys_io_destroy)
    }  
 }  
 
-PRE(sys_io_getevents)
+static
+void common_pre_io_getevents(ThreadId tid, UWord a1, UWord a2, UWord a3, UWord a4, UWord a5, UWord a6, UWord* flags, const HChar* funtion_name)
 {
+   HChar buf[25];
    *flags |= SfMayBlock;
-   PRINT("sys_io_getevents ( %llu, %lld, %lld, %#" FMT_REGWORD "x, %#"
-         FMT_REGWORD "x )",
-         (ULong)ARG1,(Long)ARG2,(Long)ARG3,ARG4,ARG5);
+   PRINT("sys_%s ( %llu, %lld, %lld, %#" FMT_REGWORD "x, %#"
+         FMT_REGWORD "x )", funtion_name,
+         (ULong)a1,(Long)a2,(Long)a3,a4,a5);
+   if (a3 > 0) {
+      VG_(snprintf)(buf, 25, "%s(events)", funtion_name);
+      PRE_MEM_WRITE( buf, a4, sizeof(struct vki_io_event)*a3 );
+   }
+   if (a5 != 0) {
+      VG_(snprintf)(buf, 25, "%s(timeout)", funtion_name);
+      PRE_MEM_READ( buf, a5, sizeof(struct vki_timespec));
+   }
+
+   if (a6 != 0) {
+      // only for io_pgetevents
+      PRE_MEM_READ("io_pgetevents(usig)",
+                   a6, sizeof(struct vki__aio_sigset));
+   }
+}
+
+PRE(sys_io_getevents)
+{
    PRE_REG_READ5(long, "io_getevents",
                  vki_aio_context_t, ctx_id, long, min_nr, long, nr,
                  struct io_event *, events,
                  struct timespec *, timeout);
-   if (ARG3 > 0)
-      PRE_MEM_WRITE( "io_getevents(events)",
-                     ARG4, sizeof(struct vki_io_event)*ARG3 );
-   if (ARG5 != 0)
-      PRE_MEM_READ( "io_getevents(timeout)",
-                    ARG5, sizeof(struct vki_timespec));
+   common_pre_io_getevents(tid, ARG1, ARG2, ARG3, ARG4, ARG5, 0U, flags, "io_getevents");
 }
-POST(sys_io_getevents)
+
+static
+void common_post_sys_io_events(ThreadId tid, UWord a4, SyscallStatus* status, const HChar* funtion_name)
 {
    Int i;
    vg_assert(SUCCESS);
    if (RES > 0) {
-      POST_MEM_WRITE( ARG4, sizeof(struct vki_io_event)*RES );
+      POST_MEM_WRITE( a4, sizeof(struct vki_io_event)*RES );
       for (i = 0; i < RES; i++) {
          const struct vki_io_event *vev =
-            ((struct vki_io_event *)(Addr)ARG4) + i;
+            ((struct vki_io_event *)(Addr)a4) + i;
          const struct vki_iocb *cb = (struct vki_iocb *)(Addr)vev->obj;
 
          switch (cb->aio_lio_opcode) {
@@ -2613,27 +2630,28 @@ POST(sys_io_getevents)
             break;
 
          case VKI_IOCB_CMD_PREADV:
-	     if (vev->result > 0) {
-                  struct vki_iovec * vec = (struct vki_iovec *)(Addr)cb->aio_buf;
-                  Int remains = vev->result;
-                  Int j;
-
-                  for (j = 0; j < cb->aio_nbytes; j++) {
-                       Int nReadThisBuf = vec[j].iov_len;
-                       if (nReadThisBuf > remains) nReadThisBuf = remains;
-                       POST_MEM_WRITE( (Addr)vec[j].iov_base, nReadThisBuf );
-                       remains -= nReadThisBuf;
-                       if (remains < 0) VG_(core_panic)("io_getevents(PREADV): remains < 0");
-                  }
-	     }
-             break;
+            if (vev->result > 0) {
+               struct vki_iovec * vec = (struct vki_iovec *)(Addr)cb->aio_buf;
+               Int remains = vev->result;
+                Int j;
+
+               for (j = 0; j < cb->aio_nbytes; j++) {
+                   Int nReadThisBuf = vec[j].iov_len;
+                  if (nReadThisBuf > remains) nReadThisBuf = remains;
+                  POST_MEM_WRITE( (Addr)vec[j].iov_base, nReadThisBuf );
+                  remains -= nReadThisBuf;
+                  if (remains < 0) VG_(core_panic)("io_getevents(PREADV): remains < 0");
+               }
+            }
+            break;
 
          case VKI_IOCB_CMD_PWRITEV:
              break;
 
          default:
             VG_(message)(Vg_DebugMsg,
-                        "Warning: unhandled io_getevents opcode: %u\n",
+                        "Warning: unhandled %s opcode: %u\n",
+                        funtion_name,
                         cb->aio_lio_opcode);
             break;
          }
@@ -2641,6 +2659,11 @@ POST(sys_io_getevents)
    }
 }
 
+POST(sys_io_getevents)
+{
+   common_post_sys_io_events(tid, ARG4, status, "io_getevents");
+}
+
 PRE(sys_io_submit)
 {
    Int i, j;
@@ -13462,6 +13485,20 @@ PRE(sys_pkey_free)
   SET_STATUS_Failure( VKI_EINVAL );
 }
 
+PRE(sys_io_pgetevents)
+{
+   PRE_REG_READ5(long, "io_pgetevents",
+                 vki_aio_context_t, ctx_id, long, min_nr, long, nr,
+                 struct io_event *, events,
+                 struct timespec *, timeout);
+   common_pre_io_getevents(tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, flags, "io_pgetevents");
+}
+
+POST(sys_io_pgetevents)
+{
+   common_post_sys_io_events(tid, ARG4, status, "io_pgetevents");
+}
+
 PRE(sys_pkey_mprotect)
 {
    PRINT("sys_pkey_mprotect ( %#" FMT_REGWORD "x, %" FMT_REGWORD "u, %"
diff --git a/coregrind/m_syswrap/syswrap-mips32-linux.c b/coregrind/m_syswrap/syswrap-mips32-linux.c
index f6f1f556ee..3644a088e5 100644
--- a/coregrind/m_syswrap/syswrap-mips32-linux.c
+++ b/coregrind/m_syswrap/syswrap-mips32-linux.c
@@ -1124,6 +1124,7 @@ static SyscallTableEntry syscall_main_table[] = {
    //..
    LINXY(__NR_statx,                   sys_statx),                   // 366
    GENX_(__NR_rseq,                    sys_ni_syscall),              // 367
+   LINX_(__NR_io_pgetevents,           sys_io_pgetevents),           // 368
 
    LINX_(__NR_semget,                  sys_semget),                  // 393
    LINXY(__NR_semctl,                  sys_semctl),                  // 394
diff --git a/coregrind/m_syswrap/syswrap-mips64-linux.c b/coregrind/m_syswrap/syswrap-mips64-linux.c
index 5736291c21..ba73b68d8f 100644
--- a/coregrind/m_syswrap/syswrap-mips64-linux.c
+++ b/coregrind/m_syswrap/syswrap-mips64-linux.c
@@ -814,6 +814,7 @@ static SyscallTableEntry syscall_main_table[] = {
    LINX_ (__NR_syncfs, sys_syncfs),
    LINXY (__NR_statx, sys_statx),
    GENX_ (__NR_rseq, sys_ni_syscall),
+   LINX_ (__NR_io_pgetevents, sys_io_pgetevents),
    LINX_ (__NR_setns, sys_setns),
    LINXY (__NR_io_uring_setup, sys_io_uring_setup),
    LINXY (__NR_io_uring_enter, sys_io_uring_enter),
diff --git a/coregrind/m_syswrap/syswrap-riscv64-linux.c b/coregrind/m_syswrap/syswrap-riscv64-linux.c
index f5e2f30dea..e0146f2b0d 100644
--- a/coregrind/m_syswrap/syswrap-riscv64-linux.c
+++ b/coregrind/m_syswrap/syswrap-riscv64-linux.c
@@ -574,6 +574,7 @@ static SyscallTableEntry syscall_main_table[] = {
    LINXY(__NR_preadv2, sys_preadv2),                               /* 286 */
    LINX_(__NR_pwritev2, sys_pwritev2),                             /* 287 */
    LINXY(__NR_statx, sys_statx),                                   /* 291 */
+   LINX_(__NR_io_pgetevents, sys_io_pgetevents),                   /* 292 */
    GENX_(__NR_rseq, sys_ni_syscall),                               /* 293 */
    LINXY(__NR_io_uring_setup, sys_io_uring_setup),                 /* 425 */
    LINXY(__NR_io_uring_enter, sys_io_uring_enter),                 /* 426 */
diff --git a/coregrind/m_syswrap/syswrap-s390x-linux.c b/coregrind/m_syswrap/syswrap-s390x-linux.c
index a3d74aef9b..9191c2093d 100644
--- a/coregrind/m_syswrap/syswrap-s390x-linux.c
+++ b/coregrind/m_syswrap/syswrap-s390x-linux.c
@@ -862,6 +862,7 @@ static SyscallTableEntry syscall_table[] = {
    LINXY(__NR_statx, sys_statx),                                      // 379
 
    GENX_(__NR_rseq, sys_ni_syscall),                                  // 381
+   LINX_(__NR_io_pgetevents, sys_io_pgetevents),                      // 382
 
    LINXY(__NR_io_uring_setup, sys_io_uring_setup),                    // 425
    LINXY(__NR_io_uring_enter, sys_io_uring_enter),                    // 426
diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c
index c4b00bd3f4..d7f173cd91 100644
--- a/coregrind/m_syswrap/syswrap-x86-linux.c
+++ b/coregrind/m_syswrap/syswrap-x86-linux.c
@@ -1620,6 +1620,7 @@ static SyscallTableEntry syscall_table[] = {
    /* Explicitly not supported on i386 yet. */
    GENX_(__NR_arch_prctl,        sys_ni_syscall),       // 384
 
+   LINX_(__NR_io_pgetevents,     sys_io_pgetevents),    // 385
    GENX_(__NR_rseq,              sys_ni_syscall),       // 386
 
    LINX_(__NR_shmget,            sys_shmget),           // 395
diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h
index 0df1b4c4b4..29e62ce863 100644
--- a/include/vki/vki-linux.h
+++ b/include/vki/vki-linux.h
@@ -5484,6 +5484,11 @@ struct vki_open_how {
 
 #define VKI_BTRFS_SUPER_MAGIC    0x9123683E
 
+struct vki__aio_sigset {
+   const vki_sigset_t __user	*sigmask;
+   vki_size_t		sigsetsize;
+};
+
 /*--------------------------------------------------------------------*/
 /*--- end                                                          ---*/
 /*--------------------------------------------------------------------*/
diff --git a/include/vki/vki-scnums-arm64-linux.h b/include/vki/vki-scnums-arm64-linux.h
index acdfb39c68..08d5690045 100644
--- a/include/vki/vki-scnums-arm64-linux.h
+++ b/include/vki/vki-scnums-arm64-linux.h
@@ -323,7 +323,7 @@
 #define __NR_pkey_alloc 289
 #define __NR_pkey_free 290
 #define __NR_statx 291
-#define __NR_io_pgetevents 291
+#define __NR_io_pgetevents 292
 #define __NR_rseq 293
 
 #undef __NR_syscalls
diff --git a/include/vki/vki-scnums-riscv64-linux.h b/include/vki/vki-scnums-riscv64-linux.h
index 15ba9308d3..e4cc04a608 100644
--- a/include/vki/vki-scnums-riscv64-linux.h
+++ b/include/vki/vki-scnums-riscv64-linux.h
@@ -299,6 +299,7 @@
 #define __NR_pwritev2 287
 #define __NR_pkey_free 290
 #define __NR_statx 291
+#define __NR_io_pgetevents 292
 #define __NR_rseq 293
 #define __NR_io_uring_setup 425
 #define __NR_io_uring_enter 426
diff --git a/memcheck/tests/linux/Makefile.am b/memcheck/tests/linux/Makefile.am
index 3d06d483cd..13d6a05af0 100644
--- a/memcheck/tests/linux/Makefile.am
+++ b/memcheck/tests/linux/Makefile.am
@@ -9,6 +9,8 @@ EXTRA_DIST = \
 		aligned_alloc.stderr.exp-glibc238 \
 	brk.stderr.exp brk.vgtest \
 	bug480706.stderr.exp bug480706.vgtest \
+	bug420682_1.stderr.exp bug420682_1.vgtest \
+	bug420682_2.stderr.exp bug420682_2.vgtest \
 	capget.vgtest capget.stderr.exp capget.stderr.exp2 capget.stderr.exp3 \
 	capget.stderr.exp4 \
 	debuginfod-check.stderr.exp debuginfod-check.vgtest.in \
@@ -100,6 +102,13 @@ if HAVE_STRLCAT
         check_PROGRAMS += strlcat_strlcpy
 endif
 
+if HAVE_LIBAIO
+        check_PROGRAMS += bug420682_1
+if HAVE_NR_IO_PGETEVENTS
+        check_PROGRAMS += bug420682_2
+endif
+endif
+
 AM_CFLAGS   += $(AM_FLAG_M3264_PRI)
 AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
 
@@ -110,6 +119,14 @@ if HAVE_OPENSSL
 bug480706_LDADD             = -lcrypto
 endif
 
+if HAVE_LIBAIO
+bug420682_1_LDADD               = -laio
+endif
+
+if HAVE_NR_IO_PGETEVENTS
+bug420682_2_CFLAGS              = ${AM_CFLAGS} @FLAG_W_NO_UNINITIALIZED@
+endif
+
 # Build shared object for dlclose_leak
 dlclose_leak_so_so_SOURCES    = dlclose_leak_so.c
 dlclose_leak_so_so_CFLAGS     = $(AM_CFLAGS) -fpic -g -O0
diff --git a/memcheck/tests/linux/bug420682_1.c b/memcheck/tests/linux/bug420682_1.c
new file mode 100644
index 0000000000..e33087382f
--- /dev/null
+++ b/memcheck/tests/linux/bug420682_1.c
@@ -0,0 +1,37 @@
+/*
+ * See https://bugs.kde.org/show_bug.cgi?id=420682
+ *
+ */
+#include <assert.h>
+#include <fcntl.h>
+#include <libaio.h>
+#include <unistd.h>
+
+int main(void)
+{
+    const char *msg = "hello world\n";
+    struct iocb iocb = {};
+    struct io_event event;
+    io_context_t ctx = 0;
+    struct iocb *iocbp;
+    int rc, fd;
+
+    rc = io_setup(1, &ctx);
+    assert(rc == 0);
+
+    fd = open("test.txt", O_CREAT | O_RDWR, 0666);
+    assert(fd >= 0);
+
+    io_prep_pwrite(&iocb, fd, (void *)msg, 12, 0);
+    iocbp = &iocb;
+
+    rc = io_submit(ctx, 1, &iocbp);
+    assert(rc == 1);
+
+    rc = io_getevents(ctx, 1, 1, &event, NULL);
+    assert(rc == 1);
+
+    close(fd);
+
+    io_destroy(ctx);
+}
diff --git a/memcheck/tests/linux/bug420682_1.stderr.exp b/memcheck/tests/linux/bug420682_1.stderr.exp
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/memcheck/tests/linux/bug420682_1.vgtest b/memcheck/tests/linux/bug420682_1.vgtest
new file mode 100644
index 0000000000..8531e4a090
--- /dev/null
+++ b/memcheck/tests/linux/bug420682_1.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e bug420682_1
+prog: bug420682_1
+vgopts: -q
+post: rm -f test.txt
diff --git a/memcheck/tests/linux/bug420682_2.c b/memcheck/tests/linux/bug420682_2.c
new file mode 100644
index 0000000000..de97069c19
--- /dev/null
+++ b/memcheck/tests/linux/bug420682_2.c
@@ -0,0 +1,32 @@
+/*
+ * See https://bugs.kde.org/show_bug.cgi?id=420682
+ *
+ * Some scalar-style errors.
+ */
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/syscall.h>
+#include <libaio.h>
+#include "../../../memcheck/memcheck.h"
+
+int main(void)
+{
+    long* px  = malloc(sizeof(long));
+    long  x0  = px[0];
+    syscall(__NR_io_pgetevents, x0-1, x0, x0, x0+1, x0+1, x0+1);
+
+    struct timespec ts;
+    struct aio_sigset {
+        const sigset_t* sigmask;
+        size_t sigsetsize;
+    } as;
+    struct io_event event;
+
+    VALGRIND_MAKE_MEM_UNDEFINED(&event, sizeof(event));
+    VALGRIND_MAKE_MEM_UNDEFINED(&ts, sizeof(ts));
+    VALGRIND_MAKE_MEM_UNDEFINED(&as, sizeof(as));
+
+    syscall(__NR_io_pgetevents, x0-1, x0, x0, &event, &ts, &as);
+
+    free(px);
+}
diff --git a/memcheck/tests/linux/bug420682_2.stderr.exp b/memcheck/tests/linux/bug420682_2.stderr.exp
new file mode 100644
index 0000000000..f9c8ad0be9
--- /dev/null
+++ b/memcheck/tests/linux/bug420682_2.stderr.exp
@@ -0,0 +1,54 @@
+Syscall param io_pgetevents(ctx_id) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+
+Syscall param io_pgetevents(min_nr) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+
+Syscall param io_pgetevents(nr) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+
+Syscall param io_pgetevents(events) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+
+Syscall param io_pgetevents(timeout) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+
+Syscall param io_pgetevents(timeout) points to unaddressable byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param io_pgetevents(usig) points to unaddressable byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:16)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param io_pgetevents(ctx_id) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:29)
+
+Syscall param io_pgetevents(min_nr) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:29)
+
+Syscall param io_pgetevents(nr) contains uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:29)
+
+Syscall param io_pgetevents(timeout) points to uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:29)
+ Address 0x........ is on thread 1's stack
+ in frame #1, created by main (bug420682_2.c:13)
+
+Syscall param io_pgetevents(usig) points to uninitialised byte(s)
+   ...
+   by 0x........: main (bug420682_2.c:29)
+ Address 0x........ is on thread 1's stack
+ in frame #1, created by main (bug420682_2.c:13)
+
diff --git a/memcheck/tests/linux/bug420682_2.vgtest b/memcheck/tests/linux/bug420682_2.vgtest
new file mode 100644
index 0000000000..5f9c8455de
--- /dev/null
+++ b/memcheck/tests/linux/bug420682_2.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e bug420682_2
+prog: bug420682_2
+vgopts: -q
+

[Valgrind-developers] [valgrind/VALGRIND_3_24_BRANCH] Bug 501893 - Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f206268ad56899f935d420770088076671a6b014

commit f206268ad56899f935d420770088076671a6b014
Author: Paul Floyd <pj...@wa...>
Date:   Sun Mar 23 10:21:29 2025 +0100

    Bug 501893 - Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?
    
    (cherry picked from commit f87c58e89c4a0e85c59f39a7ae01027686bfff73)

Diff:
---
 .gitignore                        |  1 +
 NEWS                              |  1 +
 memcheck/tests/Makefile.am        |  2 ++
 memcheck/tests/wcpncpy.stderr.exp |  8 ++++----
 memcheck/tests/wcscat.c           | 20 ++++++++++++++++++++
 memcheck/tests/wcscat.stderr.exp  |  0
 memcheck/tests/wcscat.stdout.exp  |  1 +
 memcheck/tests/wcscat.vgtest      |  2 ++
 shared/vg_replace_strmem.c        | 29 +++++++++++++++++++++++++++++
 9 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/.gitignore b/.gitignore
index 0682516621..65330fa089 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1043,6 +1043,7 @@
 /memcheck/tests/vcpu_fnfns
 /memcheck/tests/vgtest_ume
 /memcheck/tests/wcs
+/memcheck/tests/wcscat
 /memcheck/tests/weirdioctl
 /memcheck/tests/with space
 /memcheck/tests/wcpncpy
diff --git a/NEWS b/NEWS
index fe225c666c..23cf88c505 100644
--- a/NEWS
+++ b/NEWS
@@ -12,6 +12,7 @@ The following bugs have been fixed or resolved on this branch.
         even though it's generated by --gen-suppressions=yes
 498143  False positive on EVIOCGRAB ioctl
 501348  glibc built with -march=x86-64-v3 does not work due to ld.so memcmp
+501893  Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?
 
 To see details of a given bug, visit
   https://bugs.kde.org/show_bug.cgi?id=XXXXXX
diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
index c3b5fdbe94..2bcffbf5ce 100644
--- a/memcheck/tests/Makefile.am
+++ b/memcheck/tests/Makefile.am
@@ -445,6 +445,7 @@ EXTRA_DIST = \
 	vcpu_fnfns.stderr.exp vcpu_fnfns.vgtest \
 	wcpncpy.stderr.exp wcpncpy.vgtest \
 	wcs.vgtest wcs.stderr.exp wcs.stdout.exp \
+	wcscat.vgtest wcscat.stderr.exp wcscat.stdout.exp \
 	wcsncpy.vgtest wcsncpy.stderr.exp \
 	wmemcmp.vgtest wmemcmp.stderr.exp \
 	wrap1.vgtest wrap1.stdout.exp wrap1.stderr.exp \
@@ -551,6 +552,7 @@ check_PROGRAMS = \
 	varinforestrict \
 	vcpu_fbench vcpu_fnfns \
 	wcs \
+	wcscat \
 	xml1 \
 	wmemcmp \
 	wrap1 wrap2 wrap3 wrap4 wrap5 wrap6 wrap7 wrap7so.so wrap8 \
diff --git a/memcheck/tests/wcpncpy.stderr.exp b/memcheck/tests/wcpncpy.stderr.exp
index abe23b7730..0ff9e5c741 100644
--- a/memcheck/tests/wcpncpy.stderr.exp
+++ b/memcheck/tests/wcpncpy.stderr.exp
@@ -1,19 +1,19 @@
 Conditional jump or move depends on uninitialised value(s)
-   at 0x........: wcpncpy (vg_replace_strmem.c:2426)
+   at 0x........: wcpncpy (vg_replace_strmem.c:2427)
    by 0x........: main (wcpncpy.c:14)
 
 Invalid write of size 4
-   at 0x........: wcpncpy (vg_replace_strmem.c:2426)
+   at 0x........: wcpncpy (vg_replace_strmem.c:2427)
    by 0x........: main (wcpncpy.c:27)
  Address 0x........ is 20 bytes inside a block of size 22 alloc'd
    at 0x........: malloc (vg_replace_malloc.c:...)
    by 0x........: main (wcpncpy.c:10)
 
 Source and destination overlap in wcpncpy(0x........, 0x........)
-   at 0x........: wcpncpy (vg_replace_strmem.c:2426)
+   at 0x........: wcpncpy (vg_replace_strmem.c:2427)
    by 0x........: main (wcpncpy.c:35)
 
 Source and destination overlap in wcpncpy(0x........, 0x........)
-   at 0x........: wcpncpy (vg_replace_strmem.c:2426)
+   at 0x........: wcpncpy (vg_replace_strmem.c:2427)
    by 0x........: main (wcpncpy.c:43)
 
diff --git a/memcheck/tests/wcscat.c b/memcheck/tests/wcscat.c
new file mode 100644
index 0000000000..bf3ec70c6d
--- /dev/null
+++ b/memcheck/tests/wcscat.c
@@ -0,0 +1,20 @@
+// See https://bugs.kde.org/show_bug.cgi?id=501893
+#include <wchar.h>
+#include <stdio.h>
+#include <locale.h>
+#include <stdlib.h>
+
+int main(void)
+{
+    wchar_t* str = malloc(sizeof(L"/usr/lib/python310.zip:/usr/lib/python3.10:"));
+    wchar_t* add1 = wcsdup(L"/usr/lib/python310.zip:/usr/lib/python3.10");
+    wchar_t* add2 = wcsdup(L":");
+    str[0] = 0;
+    wcscat(str, add1);
+    wcscat(str, add2);
+    setlocale(LC_ALL, "en_US.utf8");
+    printf("%ls\n", str);
+    free(str);
+    free(add1);
+    free(add2);
+}
diff --git a/memcheck/tests/wcscat.stderr.exp b/memcheck/tests/wcscat.stderr.exp
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/memcheck/tests/wcscat.stdout.exp b/memcheck/tests/wcscat.stdout.exp
new file mode 100644
index 0000000000..b5b8c09e53
--- /dev/null
+++ b/memcheck/tests/wcscat.stdout.exp
@@ -0,0 +1 @@
+/usr/lib/python310.zip:/usr/lib/python3.10:
diff --git a/memcheck/tests/wcscat.vgtest b/memcheck/tests/wcscat.vgtest
new file mode 100644
index 0000000000..30b25d0efc
--- /dev/null
+++ b/memcheck/tests/wcscat.vgtest
@@ -0,0 +1,2 @@
+prog: wcscat
+vgopts: -q
diff --git a/shared/vg_replace_strmem.c b/shared/vg_replace_strmem.c
index ae13a2a5f8..71f15c85fb 100644
--- a/shared/vg_replace_strmem.c
+++ b/shared/vg_replace_strmem.c
@@ -108,6 +108,7 @@
    20480 WCSNCPY
    20490 MEMCCPY
    20500 WCPNCPY
+   20510 WCSCAT
 */
 
 #if defined(VGO_solaris)
@@ -2426,6 +2427,34 @@ static inline void my_exit ( int x )
  WCPNCPY(VG_Z_LIBC_SONAME, wcpncpy)
 #endif
 
+/*----------------------- wcscat ----------------------*/
+
+#define WCSCAT(soname, fnname) \
+ Int* VG_REPLACE_FUNCTION_EZU(20510,soname,fnname) \
+    ( Int *restrict dest, const Int *restrict src ); \
+    Int* VG_REPLACE_FUNCTION_EZU(20510,soname,fnname) \
+    ( Int *restrict dest, const Int *restrict src ) \
+ { \
+    const Int* src_orig = src; \
+    Int* dest_orig = dest; \
+    while (*dest) dest++; \
+    while (*src) *dest++ = *src++; \
+    *dest = 0; \
+      \
+    /* This is a bit redundant, I think;  any overlap and the wcscat will */ \
+    /* go forever... or until a seg fault occurs. */ \
+    if (is_overlap(dest_orig,  \
+                   src_orig,  \
+                  (Addr)dest-(Addr)dest_orig+1,  \
+                  (Addr)src-(Addr)src_orig+1)) \
+    RECORD_OVERLAP_ERROR("wcscat", dest_orig, src_orig, 0); \
+      \
+    return dest_orig; \
+ }
+
+#if defined(VGO_linux)
+ WCSCAT(VG_Z_LIBC_SONAME, __wcscat_avx2)
+#endif
 
 /*------------------------------------------------------------*/
 /*--- Improve definedness checking of process environment  ---*/

[Valgrind-developers] [valgrind/VALGRIND_3_24_BRANCH] filter_gdb.in: __syscall_cancel_arch is just in a syscall

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=275b98d60cee65acee7dd5793210aea7a0921bd2

commit 275b98d60cee65acee7dd5793210aea7a0921bd2
Author: Mark Wielaard <ma...@kl...>
Date:   Fri Mar 28 13:44:35 2025 +0100

    filter_gdb.in: __syscall_cancel_arch is just in a syscall
    
    Since glibc 2.41 some extra syscall_cancel frames are inserted before
    that actual syscall is made. Just filter out __syscall_cancel_arch
    from the gdb output and replace it with "in syscall ..." to make the
    regtest .exp match.
    
    https://bugs.kde.org/show_bug.cgi?id=502126
    
    (cherry picked from commit f3f30becff5851b0d0b2caa7e96e661c7889f7d1)

Diff:
---
 gdbserver_tests/filter_gdb.in | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in
index 2bef9f3ee5..e2b329a604 100755
--- a/gdbserver_tests/filter_gdb.in
+++ b/gdbserver_tests/filter_gdb.in
@@ -134,6 +134,9 @@ s/^>[> ]*//
 #       anonymise a 'general' system calls stack trace part
 s/in _dl_sysinfo_int80 () from \/lib\/ld-linux.so.*/in syscall .../
 
+#      in __syscall_cancel_arch is just in a syscall
+s/in __syscall_cancel_arch .*/in syscall .../
+
 #       anonymise kill syscall.
 s/in kill ().*$/in syscall .../

[Valgrind-developers] [valgrind] filter_gdb.in: __syscall_cancel_arch is just in a syscall

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f3f30becff5851b0d0b2caa7e96e661c7889f7d1

commit f3f30becff5851b0d0b2caa7e96e661c7889f7d1
Author: Mark Wielaard <ma...@kl...>
Date:   Fri Mar 28 13:44:35 2025 +0100

    filter_gdb.in: __syscall_cancel_arch is just in a syscall
    
    Since glibc 2.41 some extra syscall_cancel frames are inserted before
    that actual syscall is made. Just filter out __syscall_cancel_arch
    from the gdb output and replace it with "in syscall ..." to make the
    regtest .exp match.
    
    https://bugs.kde.org/show_bug.cgi?id=502126

Diff:
---
 gdbserver_tests/filter_gdb.in | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in
index 2bef9f3ee5..e2b329a604 100755
--- a/gdbserver_tests/filter_gdb.in
+++ b/gdbserver_tests/filter_gdb.in
@@ -134,6 +134,9 @@ s/^>[> ]*//
 #       anonymise a 'general' system calls stack trace part
 s/in _dl_sysinfo_int80 () from \/lib\/ld-linux.so.*/in syscall .../
 
+#      in __syscall_cancel_arch is just in a syscall
+s/in __syscall_cancel_arch .*/in syscall .../
+
 #       anonymise kill syscall.
 s/in kill ().*$/in syscall .../

Re: [Valgrind-developers] Sourceware Survey 2025

[Mark W. <ma...@kl...>]

On Fri, Mar 14, 2025 at 01:30:47AM +0100, Mark Wielaard wrote:
> The Sourceware Project Leadership Committee would like to know who our
> users are, which hosted projects they feel part of, what services they
> rely on and what the priorities should be for new initiatives.
> 
> https://nextcloud.sfconservancy.org/apps/forms/s/xmGgmJFzSb2FZNd58cXMtAZp

Just 4 more days till the Sourceware Survey 2025 ends (Monday 31
March). We already received 85 replies. Thanks! Please do fill out the
survey if you haven't yet and have some time this weekend:
https://sourceware.org/survey-2025

> The survey will run till the end of March and contains 20 quick
> questions (none of the questions are mandatory, please feel free to
> skip any you find not relevant, but any answer you give is helpful.)
> 
> The overview page (where we will also publish the summary/results) is
> here https://sourceware.org/survey-2025 the direct link to the form is
> https://nextcloud.sfconservancy.org/apps/forms/s/xmGgmJFzSb2FZNd58cXMtAZp
> 
> Also if you like to discuss this survey or give feedback another way
> there is the Sourceware Open Office this Friday 14 March at 16:00 UTC
> in #overseers on irc.libera.chat. To get the right time in your local
> timezone: $ date -d "Fri Mar 14 16:00 UTC 2025"
> 
> Thanks,
> 
>  Frank Ch. Eigler, Christopher Faylor, Ian Kelling, Ian Lance Taylor,
>  Tom Tromey, Jon Turney, Mark J. Wielaard, Elena Zannoni

[Valgrind-developers] [valgrind] s390x: PRNO tidy

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6f373a5f779c9e35b1fe1235298357db73aee088

commit 6f373a5f779c9e35b1fe1235298357db73aee088
Author: Florian Krohm <fl...@ei...>
Date:   Thu Mar 27 16:30:03 2025 +0000

    s390x: PRNO tidy
    
    The mnemonics PRNO and PPNO denote the same opcode. Both names were used
    in the code. Not anymore. From now on: consistent naming PRNO / prno
    
    While I was at it:
    - Remove left-overs from the early days when PRNO was implemented by means
      of dirty helpers.
    - Fix disassembly to use "prno".
    - Fix a bug in s390_irgen_DFLTCC which was using "ppno" as mnemonic.

Diff:
---
 VEX/priv/guest_s390_defs.h    |  4 +--
 VEX/priv/guest_s390_helpers.c | 69 -------------------------------------------
 VEX/priv/guest_s390_toIR.c    | 15 +++++-----
 VEX/priv/main_main.c          |  4 +--
 VEX/priv/s390_defs.h          | 21 -------------
 VEX/pub/libvex_emnote.h       |  4 +--
 6 files changed, 12 insertions(+), 105 deletions(-)

diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h
index 607773ad14..0039f5e784 100644
--- a/VEX/priv/guest_s390_defs.h
+++ b/VEX/priv/guest_s390_defs.h
@@ -90,9 +90,7 @@ UInt  s390_do_cvb(ULong decimal);
 ULong s390_do_cvd(ULong binary);
 ULong s390_do_ecag(ULong op2addr);
 UInt  s390_do_pfpo(UInt gpr0);
-void  s390x_dirtyhelper_PPNO_query(VexGuestS390XState *guest_state, ULong r1, ULong r2);
-ULong  s390x_dirtyhelper_PPNO_sha512(VexGuestS390XState *guest_state, ULong r1, ULong r2);
-void  s390x_dirtyhelper_PPNO_sha512_load_param_block( void );
+
 /* The various ways to compute the condition code. */
 enum {
    S390_CC_OP_BITWISE = 0,
diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c
index 94d0a242db..bbba22b478 100644
--- a/VEX/priv/guest_s390_helpers.c
+++ b/VEX/priv/guest_s390_helpers.c
@@ -2659,75 +2659,6 @@ s390x_dirtyhelper_vec_op(VexGuestS390XState *guest_state,
 
 #endif
 
-/*-----------------------------------------------------------------*/
-/*--- Dirty helper for Perform Pseudorandom number instruction  ---*/
-/*-----------------------------------------------------------------*/
-
-/* Dummy helper that is needed to indicate load of parameter block.
-   We have to use it because dirty helper cannot have two memory side
-   effects.
- */
-void s390x_dirtyhelper_PPNO_sha512_load_param_block( void )
-{
-}
-
-#if defined(VGA_s390x)
-
-/* IMPORTANT!
-   We return here bit mask where only supported functions are set to one.
-   If you implement new functions don't forget the supported array.
- */
-void
-s390x_dirtyhelper_PPNO_query(VexGuestS390XState *guest_state, ULong r1, ULong r2)
-{
-   ULong supported[2] = {0x9000000000000000ULL, 0x0000000000000000ULL};
-   ULong *result = (ULong*) guest_state->guest_r1;
-
-   result[0] = supported[0];
-   result[1] = supported[1];
-}
-
-ULong
-s390x_dirtyhelper_PPNO_sha512(VexGuestS390XState *guest_state, ULong r1, ULong r2)
-{
-   ULong* op1 = (ULong*) (((ULong)(&guest_state->guest_r0)) + r1 * sizeof(ULong));
-   ULong* op2 = (ULong*) (((ULong)(&guest_state->guest_r0)) + r2 * sizeof(ULong));
-
-   register ULong reg0 asm("0") = guest_state->guest_r0;
-   register ULong reg1 asm("1") = guest_state->guest_r1;
-   register ULong reg2 asm("2") = op1[0];
-   register ULong reg3 asm("3") = op1[1];
-   register ULong reg4 asm("4") = op2[0];
-   register ULong reg5 asm("5") = op2[1];
-
-   ULong cc = 0;
-   asm volatile(".insn rre, 0xb93c0000, %%r2, %%r4\n"
-                "ipm %[cc]\n"
-                "srl %[cc], 28\n"
-                : "+d"(reg0), "+d"(reg1),
-                  "+d"(reg2), "+d"(reg3),
-                  "+d"(reg4), "+d"(reg5),
-                  [cc] "=d"(cc)
-                :
-                : "cc", "memory");
-
-   return cc;
-}
-
-#else
-
-void
-s390x_dirtyhelper_PPNO_query(VexGuestS390XState *guest_state, ULong r1, ULong r2)
-{
-}
-
-ULong
-s390x_dirtyhelper_PPNO_sha512(VexGuestS390XState *guest_state, ULong r1, ULong r2)
-{
-   return 0;
-}
-
-#endif /* VGA_s390x */
 /*---------------------------------------------------------------*/
 /*--- end                                guest_s390_helpers.c ---*/
 /*---------------------------------------------------------------*/
diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index f8caf53164..1ed10acbbb 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -17357,20 +17357,19 @@ s390_irgen_LCBB(UChar r1, IRTemp op2addr, UChar m3)
    return "lcbb";
 }
 
-/* Also known as "PRNO" */
 static const HChar *
-s390_irgen_PPNO(UChar r1, UChar r2)
+s390_irgen_PRNO(UChar r1, UChar r2)
 {
    if (!s390_host_has_msa5) {
-      emulation_failure(EmFail_S390X_ppno);
-      return "ppno";
+      emulation_failure(EmFail_S390X_prno);
+      return "prno";
    }
 
    /* Check for obvious specification exceptions */
-   s390_insn_assert("ppno", r1 % 2 == 0 && r2 % 2 == 0 && r1 != 0 && r2 != 0);
+   s390_insn_assert("prno", r1 % 2 == 0 && r2 % 2 == 0 && r1 != 0 && r2 != 0);
 
    extension(S390_EXT_PRNO, r1 | (r2 << 4));
-   return "ppno";
+   return "prno";
 }
 
 static const HChar *
@@ -17378,7 +17377,7 @@ s390_irgen_DFLTCC(UChar r3, UChar r1, UChar r2)
 {
    if (!s390_host_has_dflt) {
       emulation_failure(EmFail_S390X_dflt);
-      return "ppno";
+      return "dfltcc";
    }
 
    /* Check for obvious specification exceptions */
@@ -21083,7 +21082,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb93a: s390_format_RRE_RR(s390_irgen_KDSA, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
    case 0xb93b: s390_format_E(s390_irgen_NNPA);  goto ok;
-   case 0xb93c: s390_format_RRE_RR(s390_irgen_PPNO, RRE_r1(ovl),
+   case 0xb93c: s390_format_RRE_RR(s390_irgen_PRNO, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
    case 0xb93e: s390_format_RRE_RR(s390_irgen_KIMD, RRE_r1(ovl),
                                    RRE_r2(ovl));  goto ok;
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index 80f6d6a6d6..fe3cf9e573 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1561,8 +1561,8 @@ const HChar* LibVEX_EmNote_string ( VexEmNote ew )
      case EmFail_S390X_vx:
         return "Encountered an instruction that requires the vector facility.\n"
                "  That facility is not available on this host";
-     case EmFail_S390X_ppno:
-        return "Instruction ppno is not supported on this host.";
+     case EmFail_S390X_prno:
+        return "Instruction prno is not supported on this host.";
      case EmFail_S390X_vxe:
         return "Encountered an instruction that requires the vector-extensions"
                " facility 1.\n"
diff --git a/VEX/priv/s390_defs.h b/VEX/priv/s390_defs.h
index da5113f7de..482dc4f0e9 100644
--- a/VEX/priv/s390_defs.h
+++ b/VEX/priv/s390_defs.h
@@ -144,27 +144,6 @@ typedef enum {
    S390_PFPO_D128_TO_F128 = 0x01070A
 } s390_pfpo_function_t;
 
-/* PPNO function code as it is encoded in bits [57:63] of GR0
-   when PPNO insn is executed. */
-typedef enum
-{
-   S390_PPNO_QUERY       = 0x00,
-   S390_PPNO_SHA512_GEN  = 0x03,
-   S390_PPNO_SHA512_SEED = 0x83
-} s390_ppno_function_t;
-
-/* Size of parameter block for PPNO functions.
-   All values are in bytes.
- */
-#define S390_PPNO_PARAM_BLOCK_SIZE_QUERY  16
-#define S390_PPNO_PARAM_BLOCK_SIZE_SHA512 240
-
-/* Maximum length of modified memory for PPNO functions.
-   All values are in bytes.
-*/
-#define S390_PPNO_MAX_SIZE_SHA512_SEED 512
-#define S390_PPNO_MAX_SIZE_SHA512_GEN  64
-
 
 /* The length of the longest mnemonic: locfhrnhe */
 #define S390_MAX_MNEMONIC_LEN  9
diff --git a/VEX/pub/libvex_emnote.h b/VEX/pub/libvex_emnote.h
index c3ebcf4203..27b95880cb 100644
--- a/VEX/pub/libvex_emnote.h
+++ b/VEX/pub/libvex_emnote.h
@@ -121,8 +121,8 @@ typedef
       /* some insn needs vector facility which is not available on this host */
       EmFail_S390X_vx,
 
-      /* ppno insn is not supported on this host */
-      EmFail_S390X_ppno,
+      /* prno insn is not supported on this host */
+      EmFail_S390X_prno,
 
       /* insn needs vector-enhancements facility 1 which is not available on
          this host */

[Valgrind-developers] [valgrind] s390x: Fix disassembly for various insns (BZ 495817)

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d17844ca7c98188b0ce7a6cfff99f55da7d82805

commit d17844ca7c98188b0ce7a6cfff99f55da7d82805
Author: Florian Krohm <fl...@ei...>
Date:   Wed Mar 26 18:32:12 2025 +0000

    s390x: Fix disassembly for various insns  (BZ 495817)
    
    Specifically: KMA, KMCTR, CU12, CU14, CU21, CU24, LCBB, TRE,
    TROO, TROT, TRTO, TRTT
    
    Part of fixing https://bugs.kde.org/show_bug.cgi?id=495817

Diff:
---
 VEX/priv/guest_s390_toIR.c | 16 +++++++++++-----
 VEX/priv/s390_disasm.c     |  5 +++++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 835d81dd76..f8caf53164 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -58,6 +58,8 @@ static const HChar *s390_irgen_VCGD(UChar, UChar, UChar, UChar, UChar);
 static const HChar *s390_irgen_VCDG(UChar, UChar, UChar, UChar, UChar);
 static const HChar *s390_irgen_VCDLG(UChar, UChar, UChar, UChar, UChar);
 static const HChar *s390_irgen_VCLGD(UChar, UChar, UChar, UChar, UChar);
+static const HChar *s390_irgen_KMA(UChar, UChar, UChar);
+static const HChar *s390_irgen_KMCTR(UChar, UChar, UChar);
 
 /*------------------------------------------------------------*/
 /*--- Globals                                              ---*/
@@ -3061,7 +3063,7 @@ s390_format_RRF_M0RERE(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2),
    const HChar *mnm = irgen(m3, r1, r2);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), GPR(r1), GPR(r2), UINT(m3));
+      S390_DISASM(XMNM(mnm, mask0_disasm), GPR(r1), GPR(r2), MASK(m3));
 }
 
 static void
@@ -3208,8 +3210,12 @@ s390_format_RRF_R0RR2(const HChar *(*irgen)(UChar r3, UChar r1, UChar r2),
 {
    const HChar *mnm = irgen(r3, r1, r2);
 
-   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), GPR(r1), GPR(r2), GPR(r3));
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) {
+      if (irgen == s390_irgen_KMA || irgen == s390_irgen_KMCTR)
+         S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), GPR(r2));
+      else
+         S390_DISASM(MNM(mnm), GPR(r1), GPR(r2), GPR(r3));
+   }
 }
 
 static void
@@ -3475,7 +3481,7 @@ s390_format_RXE_RRRDR(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar m3),
    mnm = irgen(r1, op2addr, m3);
 
    if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
-      S390_DISASM(MNM(mnm), GPR(r1), UDXB(d2, x2, b2));
+      S390_DISASM(MNM(mnm), GPR(r1), UDXB(d2, x2, b2), UINT(m3));
 }
 
 static void
@@ -20627,7 +20633,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
                                  goto ok;
    case 0xb29d: s390_format_S_RD(s390_irgen_LFPC, S_b2(ovl), S_d2(ovl));
                                  goto ok;
-   case 0xb2a5: s390_format_RRE_FF(s390_irgen_TRE, RRE_r1(ovl), RRE_r2(ovl));  goto ok;
+   case 0xb2a5: s390_format_RRE_RR(s390_irgen_TRE, RRE_r1(ovl), RRE_r2(ovl));  goto ok;
    case 0xb2a6: s390_format_RRF_M0RERE(s390_irgen_CU21, RRF3_r3(ovl),
                                        RRF3_r1(ovl), RRF3_r2(ovl));
       goto ok;
diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c
index d55ca5b791..3812de0e9a 100644
--- a/VEX/priv/s390_disasm.c
+++ b/VEX/priv/s390_disasm.c
@@ -457,6 +457,11 @@ mask0_disasm(const s390_opnd *opnds, HChar *p)
 
    const HChar *mnm = opnds[0].xmnm.base;
 
+   if (vex_streq(mnm, "cu12") && opnds[unique_mask_index(opnds)].mask == 0)
+      mnm = "cutfu";
+   if (vex_streq(mnm, "cu21") && opnds[unique_mask_index(opnds)].mask == 0)
+      mnm = "cuutf";
+
    return s390_disasm_aux(opnds, mnm, p, mask0_mh);
 }

[Valgrind-developers] [valgrind] Fix library dependency for vbit-test and disasm-test.

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3802fd8751536f57af0725a4c04afe5a57f41fb1

commit 3802fd8751536f57af0725a4c04afe5a57f41fb1
Author: Florian Krohm <fl...@ei...>
Date:   Wed Mar 26 15:11:29 2025 +0000

    Fix library dependency for vbit-test and disasm-test.
    
    The executables were not relinked when the library was updated.

Diff:
---
 memcheck/tests/vbit-test/Makefile.am     | 5 +++--
 none/tests/s390x/disasm-test/Makefile.am | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/memcheck/tests/vbit-test/Makefile.am b/memcheck/tests/vbit-test/Makefile.am
index d3bc4c51ff..ded4ab1747 100644
--- a/memcheck/tests/vbit-test/Makefile.am
+++ b/memcheck/tests/vbit-test/Makefile.am
@@ -49,7 +49,7 @@ vbit_test_CPPFLAGS     = $(AM_CPPFLAGS_PRI) \
                          -I$(top_srcdir)/memcheck \
                          -I$(top_srcdir)/VEX/pub
 vbit_test_CFLAGS       = $(AM_CFLAGS_PRI)
-vbit_test_DEPENDENCIES = 
+vbit_test_DEPENDENCIES = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
 vbit_test_LDADD        = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
 vbit_test_LDFLAGS      = $(AM_CFLAGS_PRI) @LIB_UBSAN@
 # If there is no secondary platform, and the platforms include x86-darwin,
@@ -69,7 +69,8 @@ vbit_test_sec_CPPFLAGS     = $(AM_CPPFLAGS_SEC) \
                              -I$(top_srcdir)/VEX/pub
 vbit_test_sec_CFLAGS       = $(AM_CFLAGS_SEC) \
                              $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
-vbit_test_sec_DEPENDENCIES = 
+vbit_test_sec_DEPENDENCIES = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+                             $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 vbit_test_sec_LDADD        = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
                               $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 vbit_test_sec_LDFLAGS      = $(AM_CFLAGS_SEC) @LIB_UBSAN@ \
diff --git a/none/tests/s390x/disasm-test/Makefile.am b/none/tests/s390x/disasm-test/Makefile.am
index 7758489219..ce662cb860 100644
--- a/none/tests/s390x/disasm-test/Makefile.am
+++ b/none/tests/s390x/disasm-test/Makefile.am
@@ -30,6 +30,6 @@ disasm_test_CPPFLAGS     = $(AM_CPPFLAGS_PRI) \
                            -I$(top_srcdir)/VEX/pub \
                            -I$(top_srcdir)/VEX/priv
 disasm_test_CFLAGS       = $(AM_CFLAGS_PRI)
-disasm_test_DEPENDENCIES =
+disasm_test_DEPENDENCIES = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
 disasm_test_LDADD        = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
 disasm_test_LDFLAGS      = $(AM_CFLAGS_PRI) @LIB_UBSAN@

Re: [Valgrind-developers] Makefile.am change (needs review)

[Paul F. <pj...@wa...>]

On 25/03/2025 14:25, Florian Krohm wrote:
>
>  disasm_test_CFLAGS       = $(AM_CFLAGS_PRI)
> -disasm_test_DEPENDENCIES =
> +disasm_test_DEPENDENCIES = 
> $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
>  disasm_test_LDADD        = 
> $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
>  disasm_test_LDFLAGS      = $(AM_CFLAGS_PRI) @LIB_UBSAN@
>
> does the trick. Is this the proper way?
>
Hi Florian

I'm not great at autotools either but that looks right to me.

A+

Paul

[Valgrind-developers] Makefile.am change (needs review)

[Florian K. <fl...@ei...>]

In none/tests/s390x/disasm-test there is the executable disasm-test which needs 
VEX/libvex-s390x-linux.a.
Building works fine. However, if I change a C file in VEX/priv and rebuild then 
only libvex-s390x-linux.a is being rebuilt - but not the executable.
I'm not an autotools wiz. With some guessing I found that this change

diff --git a/none/tests/s390x/disasm-test/Makefile.am 
b/none/tests/s390x/disasm-test/Makefile.am
index 775848921..ce662cb86 100644
--- a/none/tests/s390x/disasm-test/Makefile.am
+++ b/none/tests/s390x/disasm-test/Makefile.am
@@ -30,6 +30,6 @@ disasm_test_CPPFLAGS     = $(AM_CPPFLAGS_PRI) \
                             -I$(top_srcdir)/VEX/pub \
                             -I$(top_srcdir)/VEX/priv
  disasm_test_CFLAGS       = $(AM_CFLAGS_PRI)
-disasm_test_DEPENDENCIES =
+disasm_test_DEPENDENCIES = 
$(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
  disasm_test_LDADD        = 
$(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
  disasm_test_LDFLAGS      = $(AM_CFLAGS_PRI) @LIB_UBSAN@

does the trick. Is this the proper way?

BTW: memcheck/tests/vbit-test has the same issue

Thanks,
    Florian

[Valgrind-developers] [valgrind] s390x: disasm-test: prepare for AR and FPR register support

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3c8631d826bcd485034b721a450523a1557ec449

commit 3c8631d826bcd485034b721a450523a1557ec449
Author: Florian Krohm <fl...@ei...>
Date:   Mon Mar 24 21:53:11 2025 +0000

    s390x: disasm-test: prepare for AR and FPR register support
    
    - New function random_reg to replace random_gpr, random_vr.
    - New function unique_reg to replace unique_gpr, unique_vr.
    - New function choose_reg_and_iterate to handle register operands whose
      values are constrained, e.g. only even registers.
    - Do not call unique_reg for a register operand whose values are constrained.

Diff:
---
 none/tests/s390x/disasm-test/generate.c | 88 +++++++++++++++++----------------
 1 file changed, 46 insertions(+), 42 deletions(-)

diff --git a/none/tests/s390x/disasm-test/generate.c b/none/tests/s390x/disasm-test/generate.c
index 7e69085e38..25d1607047 100644
--- a/none/tests/s390x/disasm-test/generate.c
+++ b/none/tests/s390x/disasm-test/generate.c
@@ -67,15 +67,16 @@ vr_operand(unsigned regno)
 
 
 static unsigned
-random_gpr(int allow_r0)
+random_reg(opnd_t reg_kind, int r0_allowed)
 {
+   unsigned num_regs = reg_kind == OPND_VR ? 32 : 16;
    unsigned regno;
 
-   if (allow_r0) {
-      regno = rand() % 16;
+   if (r0_allowed) {
+      regno = rand() % num_regs;
    } else {
       do {
-         regno = rand() % 16;
+         regno = rand() % num_regs;
       } while (regno == 0);
    }
 
@@ -83,13 +84,6 @@ random_gpr(int allow_r0)
 }
 
 
-static unsigned
-random_vr(void)
-{
-   return rand() % 32;
-}
-
-
 #if 0
 /* These functions are currently unused. But may become useful in
    alternate test generation strategies that use random values instead
@@ -159,31 +153,15 @@ sint_value(unsigned num_bits)
    function returns a register number which has not been used and
    adjusts the bitvector. */
 static unsigned
-unique_gpr(unsigned regno, unsigned *mask)
-{
-   assert(regno < 16);
-   assert(*mask != ~0U);   // Paranoia: avoid infinite loop
-
-   unsigned bit = 1 << regno;
-   while (*mask & bit) {
-      regno = random_gpr(/* allow_r0 */1);
-      bit = 1 << regno;
-   }
-   *mask |= bit;
-   return regno;
-}
-
-
-/* Like unique_gpr */
-static unsigned
-unique_vr(unsigned regno, unsigned *mask)
+unique_reg(opnd_t reg_kind, unsigned regno, unsigned *mask)
 {
-   assert(regno < 32);
+   unsigned num_regs = reg_kind == OPND_VR ? 32 : 16;
+   assert(regno < num_regs);
    assert(*mask != ~0U);   // Paranoia: avoid infinite loop
 
    unsigned bit = 1 << regno;
    while (*mask & bit) {
-      regno = random_vr();
+      regno = random_reg(reg_kind, /* r0_allowed */1);
       bit = 1 << regno;
    }
    *mask |= bit;
@@ -200,6 +178,8 @@ typedef struct {
    long long assigned_value;
 } field;
 
+static void choose_reg_and_iterate(FILE *, const opcode *, const opnd *,
+                                   field [], unsigned);
 
 /* Write out a single ASM statement for OPC. */
 static void
@@ -221,11 +201,15 @@ write_asm_stmt(FILE *fp, const opcode *opc, const field fields[])
          fputc(',', fp);
       switch (operand->kind) {
       case OPND_GPR:
-         regno = unique_gpr(fields[i].assigned_value, &gpr_mask);
+         regno = fields[i].assigned_value;
+         if (! operand->allowed_values)
+            regno = unique_reg(operand->kind, regno, &gpr_mask);
          fprintf(fp, "%s", gpr_operand(regno));
          break;
       case OPND_VR:
-         regno = unique_vr(fields[i].assigned_value, &vr_mask);
+         regno = fields[i].assigned_value;
+         if (! operand->allowed_values)
+            regno = unique_reg(operand->kind, regno, &vr_mask);
          fprintf(fp, "%s", vr_operand(regno));
          break;
       case OPND_D12XB:
@@ -300,18 +284,15 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
          f->assigned_value = 0;
          iterate(fp, opc, fields, ix + 1);
          /* Choose any GPR other than r0 */
-         f->assigned_value = random_gpr(/* r0_allowed */ 0);
+         f->assigned_value = random_reg(operand->kind, /* r0_allowed */ 0);
          iterate(fp, opc, fields, ix + 1);
       } else {
-         /* Choose any GPR */
-         f->assigned_value = random_gpr(/* r0_allowed */ 1);
-         iterate(fp, opc, fields, ix + 1);
+         choose_reg_and_iterate(fp, opc, operand, fields, ix);
       }
       break;
 
    case OPND_VR:
-      f->assigned_value = random_vr();   // Choose any VR
-      iterate(fp, opc, fields, ix + 1);
+      choose_reg_and_iterate(fp, opc, operand, fields, ix);
       break;
 
    case OPND_D12B:
@@ -341,13 +322,15 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
          }
       } else if (f->is_vr) {
          /* v0 is not special AFAICT */
-         f->assigned_value = random_vr();
+         f->assigned_value = random_reg(OPND_VR, /* r0_allowed */ 11);
          iterate(fp, opc, fields, ix + 1);
       } else {
          /* Base or index register */
+         /* Choose r0 */
          f->assigned_value = 0;
          iterate(fp, opc, fields, ix + 1);
-         f->assigned_value = random_gpr(/* r0_allowed */ 0);
+         /* Choose any GPR other than r0 */
+         f->assigned_value = random_reg(OPND_GPR, /* r0_allowed */ 0);
          iterate(fp, opc, fields, ix + 1);
       }
       break;
@@ -373,7 +356,7 @@ iterate(FILE *fp, const opcode *opc, field fields[], unsigned ix)
          /* base or index register */
          f->assigned_value = 0;
          iterate(fp, opc, fields, ix + 1);
-         f->assigned_value = random_gpr(/* r0_allowed */ 0);
+         f->assigned_value = random_reg(OPND_GPR, /* r0_allowed */ 0);
          iterate(fp, opc, fields, ix + 1);
       }
       break;
@@ -572,6 +555,27 @@ generate_tests(const opcode *opc)
 }
 
 
+static void
+choose_reg_and_iterate(FILE *fp, const opcode *opc, const opnd *operand,
+                       field fields[], unsigned ix)
+{
+   field *f = fields + ix;
+
+   if (operand->allowed_values == NULL) {
+      /* No constraint. Pick register at random. */
+      f->assigned_value = random_reg(operand->kind, /* r0_allowed */ 1);
+      iterate(fp, opc, fields, ix + 1);
+   } else {
+      /* Constraint. Choose only allowed values */
+      unsigned num_val = operand->allowed_values[0];
+      for (int i = 1; i <= num_val; ++i) {
+         f->assigned_value = operand->allowed_values[i];
+         iterate(fp, opc, fields, ix + 1);
+      }
+   }
+}
+
+
 static void
 run_cmd(const char *fmt, ...)
 {

[Valgrind-developers] [valgrind] s390x: disasm-test tweaks

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fdca943103761e494f9e59a589d7e15100fe5e7b

commit fdca943103761e494f9e59a589d7e15100fe5e7b
Author: Florian Krohm <fl...@ei...>
Date:   Mon Mar 24 14:44:07 2025 +0000

    s390x: disasm-test tweaks
    
    - Give error messages a prefix.
    - Do not segfault when the .dump file is empty. This happens when the
      generated testcase has compiler errors.
    - Avoid a file leak when reading the .dump file causes an I/O error.

Diff:
---
 none/tests/s390x/disasm-test/main.c    |  1 +
 none/tests/s390x/disasm-test/objdump.c | 21 +++++++++++++++++----
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/none/tests/s390x/disasm-test/main.c b/none/tests/s390x/disasm-test/main.c
index 75d007b933..46f55cf4ce 100644
--- a/none/tests/s390x/disasm-test/main.c
+++ b/none/tests/s390x/disasm-test/main.c
@@ -296,6 +296,7 @@ error(const char *fmt, ...)
 {
    va_list args;
    va_start(args, fmt);
+   fprintf(stderr, "error: ");
    vfprintf(stderr, fmt, args);
    va_end(args);
 }
diff --git a/none/tests/s390x/disasm-test/objdump.c b/none/tests/s390x/disasm-test/objdump.c
index 62d8346540..7100e47420 100644
--- a/none/tests/s390x/disasm-test/objdump.c
+++ b/none/tests/s390x/disasm-test/objdump.c
@@ -32,6 +32,7 @@
 
 static int get_nibble(const char *);
 static int get_byte(const char *);
+static void io_error(FILE *, const char *, const char *);
 
 
 objdump_file *
@@ -43,20 +44,24 @@ read_objdump(const char *file)
    /* Slurp file into memory */
    FILE *fp = fopen(file, "rb");
    if (fp == NULL) {
-      error("%s: fopen failed\n", file);
+      io_error(fp, file, "fopen failed\n");
       return NULL;
    }
 
    /* Determine file size */
    int rc = fseek(fp, 0, SEEK_END);
    if (rc < 0) {
-      error("%s: fseek failed\n", file);
+      io_error(fp, file, "fseek failed\n");
       return NULL;
    }
 
    long size = ftell(fp);
    if (size < 0) {
-      error("%s: ftell failed\n", file);
+      io_error(fp, file, "ftell failed\n");
+      return NULL;
+   }
+   if (size == 0) {
+      io_error(fp, file, "file is empty\n");
       return NULL;
    }
    rewind(fp);
@@ -64,7 +69,7 @@ read_objdump(const char *file)
    char *const buf = mallock(size + 1);
    size_t num_read = fread(buf, 1, size, fp);
    if (num_read != size) {
-      error("%s: fread failed\n", file);
+      io_error(fp, file, "fread failed\n");
       free(buf);
       return NULL;
    }
@@ -235,3 +240,11 @@ get_byte(const char *p)
 
    return (n1 << 4) + n2;
 }
+
+static void
+io_error(FILE *fp, const char *file, const char *msg)
+{
+   if (fp)
+      fclose(fp);
+   error("%s: %s", file, msg);
+}