valgrind-developers — Discussion list for developers of valgrind

Re: [Valgrind-developers] Next version numbering

[Philippe W. <phi...@sk...>]

On Thu, 2025-05-01 at 09:40 +0200, Paul Floyd via Valgrind-developers wrote:
> Hi all
> 
> I've been wondering whether we should switch to a year based numbering 
> scheme rather than our current semantic versioning. I'm not sure if 
> there will ever be a version 4. Making Valgrind multithreaded would 
> warrant such a change but I can't see that happening.

I did an experimental multithreaded trial some years ago, the prototype could run
the none tool multi-threaded, so valgrind was able to do nothing faster :).
But this stopped when I found no solution for memcheck.

I still believe a multi-threaded valgrind is relevant for some tools such as callgrind
that do not depend (too much) on a "central data structure accessed on a permanent basis".

And maybe new things/instructions such as rseq might maybe provide a solution for memcheck
(avoiding the performance killer to protect the memcheck V bits infrastructure for any
access done by the guest).

But I agree with you that it is unlikely to appear very soon. On my side, I am not
expecting to have time to work on that prototype before I am retired
(but this time gets closer every day :).

> 
> What I'm thinking of is 2025.04, 2025.10 etc.
> 
> Thoughts?

On this aspect, I do not have strong preference but the "year" based approach makes
more clear when someone complains that they are using a (very) old release.

> 
> A+
> 
> Paul
> 
> 
> 
> 
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers

[Valgrind-developers] Next version numbering

[Paul F. <pj...@wa...>]

Hi all

I've been wondering whether we should switch to a year based numbering 
scheme rather than our current semantic versioning. I'm not sure if 
there will ever be a version 4. Making Valgrind multithreaded would 
warrant such a change but I can't see that happening.

What I'm thinking of is 2025.04, 2025.10 etc.

Thoughts?

A+

Paul

Re: [Valgrind-developers] [PATCH] Linux: Inhibit tail calls in cancellable system calls

[Mark W. <ma...@kl...>]

Hi all,

On Fri, Apr 18, 2025 at 05:46:54PM +0200, Mark Wielaard wrote:
> On Mon, 2025-04-14 at 14:06 +0200, Mark Wielaard wrote:
> > On Sun, Apr 06, 2025 at 03:23:54PM +0200, Mark Wielaard wrote:
> > > On Mon, Mar 31, 2025 at 11:29:41AM +0200, Mark Wielaard wrote:
> > > > On Fri, Mar 28, 2025 at 07:02:28PM +0100, Mark Wielaard wrote:
> > > > > On Fri, 2025-03-21 at 14:01 +0100, Florian Weimer wrote:
> > > > > > Without this change, the system call wrapper function is not visible
> > > > > > on the stack at the time of the system call, which causes problems
> > > > > > for interception tools such as valgrind.
> > > > > > 
> > > > > > Enhances commit 89b53077d2a58f00e7debdfe58afabe953dac60d ("nptl: Fix
> > > > > > Race conditions in pthread cancellation [BZ#12683]").
> > > > > > 
> > > > > > Tested on i686-linux-gnu, powerpc64le-linux-gnu, x86_64-linux-gnu.
> > > > > > (We're still discussing if valgrind needs this, but if it does, here's a
> > > > > > patch.)
> > > > > 
> > > > > I implemented the valgrind part of skipping the syscall_cancel frames
> > > > > here: https://bugs.kde.org/show_bug.cgi?id=502126#c2
> > > > > And there is a valgrind package build for fedora rawhide:
> > > > > https://koji.fedoraproject.org/koji/buildinfo?buildID=2687393
> > > > > 
> > > > > For ppc64le, s390x and x86_64 that patch seems enough.
> > > > > 
> > > > > For i686 and aarch64 there does seem to be an issue with missing the
> > > > > glibc calling function because of a tail call.
> > > > > 
> > > > > Also on i686 there is another extra frame on top __libc_do_syscall.
> > > > 
> > > > I extended the patch to cover some extra sycall wrapper function
> > > > symbols on i386 and armhf and pushed it to valgrind trunk and
> > > > VALGRIND_3_24_BRANCH. There are builds for fedora rawhide and
> > > > f42. This does seem to show that only on arm64 the tail calls
> > > > obscure observing the full call stack.
> > > 
> > > This has now landed in fedora rawhide and f42. Test results look good,
> > > except for some if the arm64 tests where the tail calls obscure
> > > observing the full call stack. Please let me know if you need any more
> > > input from us to get this fix in glibc.
> > 
> > Please let me know. Valgrind test results for syscall backtraces on
> > anything except arm64 look good. We are working on valgrind 3.25.0
> > now, to be released around April 24.
> 
> valgrind 3.25.0-RC1 has been released and test results look good on
> most arches. arm64 does show the issue described above where the tail
> calls obscure observing the full call stack when doing system calls.

valgrind 3.25.0 have been released and is now in Fedora rawhide and
Fedora 42 with the new glibc syscall_cancel frames. The tail calls on
aarch64 still seem to be a problem for observability of the syscall
call stack.

> Let me know what would be needed to get the above patch reviewed.

Thanks,

Mark

Re: [Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing

[P J. <Jee...@ib...>]

Hi Everyone,
valgrind-3.25.0.RC2 also looks good on Power and that there are no issues requiring fixes before releasing .

The PowerPC testsults for Both LE & BE are as follows

Powerpc64LE Results:

Power8:
There are no new failures compared to valgrind-3.25.0.RC1.

== 768 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 3 post failures ==
memcheck/tests/leak_cpp_interior         (stderr)
memcheck/tests/linux/rfcomm              (stderr)
memcheck/tests/linux/sys-execveat        (stderr)
massif/tests/bug469146                   (post)
massif/tests/new-cpp                     (post)
massif/tests/overloaded-new              (post)


Power9:
There are no new failures compared to valgrind-3.25.0.RC1.

== 775 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/linux/rfcomm              (stderr)


Power10:
There are no new failures compared to valgrind-3.25.0.RC1.

== 781 tests, 7 stderr failures, 2 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/execve1                   (stderr)
memcheck/tests/execve2                   (stderr)
memcheck/tests/linux/rfcomm              (stderr)
memcheck/tests/thread_alloca             (stderr)
helgrind/tests/getaddrinfo               (stderr)
drd/tests/getaddrinfo                    (stderr)
none/tests/allexec32                     (stdout)
none/tests/allexec64                     (stdout)
none/tests/scripts/shell                 (stderr)


PowerpcBE Results:

Power8:
There are no new failures compared to valgrind-3.25.0.RC1.

== 785 tests, 333 stderr failures, 70 stdout failures, 3 stderrB failures, 3 stdoutB failures, 6 post failures ==

Power9:
There are no new failures compared to valgrind-3.25.0.RC1

== 819 tests, 52 stderr failures, 45 stdout failures, 1 stderrB failure, 2 stdoutB failures, 2 post failures ==

Thanks,
Jeevitha


From: Mark Wielaard <ma...@kl...>
Date: Thursday, 24 April 2025 at 7:31 AM
To: val...@li... <val...@li...>, val...@li... <val...@li...>
Subject: [EXTERNAL] [Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing
An RC2 tarball for 3.25.0 is now available at
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC2.tar.bz2 
(md5sum = 4e53a0a1a8d1404e77e6c45015eeb472)
(sha1sum = ba482eeeb89dd271006f59b09f01048be6530a53)
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC2.tar.bz2.asc 

Please give it a try in configurations that are important for you and
report any problems you have, either on this mailing list, or
(preferably) via our bug tracker at
https://bugs.kde.org/enter_bug.cgi?product=valgrind 

Changes from RC1:

Florian Krohm (2):
  s390x: Fix a comment
  s390x only: Clean up unused Ijk_... values

Mark Wielaard (4):
  auxprogs/Makefile.am (EXTRA_DIST): Add ltpchecks helper files
  Update NEWS for RISCV64/Linux and --modify-fds=[no|high] option
  none/tests/riscv64/testinst.h: Use lla instead of la in JMP_RANGE
  Set version to 3.25.0-RC2

Paul Floyd (8):
  Bug 502871 - Make Helgrind "pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread" optional
  Add 3.25 highlights to NEWS for FreeBSD.
  Doc: add description of cond signal without mutex lock.
  Helgrind regtest: use --check-cond-signal-mutex=yes in tc20_verifywrap
  FreeBSD regtest: add auxv_script to dist_noinst_SCRIPTS
  Illumos suppression and regtest
  Illumos regtest: add an expected for none/tests/fdleak_socketpair_xml.stderr
  Regtest: clean up warning and compilation of bug290061.c

Petr Pavlu (4):
  riscv64: Fix tests compilation with newer GNU as
  riscv64: Merge decoding of csrrw and csrrs
  riscv64: Add support for csrrc
  riscv64: Drop the not-needed type for FpCSEL

zhaomingxin (1):
  riscv64: Add missing floating-point ITE/CSEL support in VEX backend

Unless a showstopper bug pops up 3.25.0 final will be released on
Fri Apr 27.


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[Valgrind-developers] Valgrind-3.25.0 is available

[Mark W. <ma...@kl...>]

We are pleased to announce a new release of Valgrind, version 3.25.0,
available from https://valgrind.org/downloads/current.html.

This release adds initial support for RISCV64/Linux, the GDB remote
packet 'x', zstd compressed debug sections, Linux Test Project
testsuite integration, numerous fixes for Illumos, FreeBSD atexit
filters and getrlimitusage syscall support, Linux syscall support for
landlock*, io_pgetevents, open_tree, move_mount, fsopen, fsconfig,
fsmount, fspick, userfaultfd, s390x BPP, BPRP, PPA and NIAI instruction
support, --track-fds=yes improvements and a new --modify-fds=high
option, and an helgrind --check-cond-signal-mutex=yes|no option.

See the release notes below for details of the changes.

Our thanks to all those who contribute to Valgrind's development.  This
release represents a great deal of time, energy and effort on the part
of many people.

Happy and productive debugging and profiling,

-- The Valgrind Developers

~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Release 3.25.0 (25 Apr 2025)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,
MIPS64/Linux, RISCV64/Linux, ARM/Android, ARM64/Android, MIPS32/Android,
X86/Android, X86/Solaris, AMD64/Solaris, AMD64/MacOSX 10.12, X86/FreeBSD,
AMD64/FreeBSD and ARM64/FreeBSD There is also preliminary support for
X86/macOS 10.13, AMD64/macOS 10.13 and nanoMIPS/Linux.

* ==================== CORE CHANGES ===================

* The valgrind gdbserver now supports the GDB remote protocol packet
  'x addr,len' (available in GDB release >= 16).
  The x packet can reduce the time taken by GDB to read memory from valgrind.

* Valgrind now supports zstd compressed debug sections.

* The Linux Test Project (ltp) is integrated in the testsuite try
  'make ltpchecks' (this will take a while and will point out various
  missing syscalls and valgrind crashes!)

* ================== PLATFORM CHANGES =================

* Added RISCV64 support for Linux. Specifically for the RV64GC
  instruction set.

* Numerous bug fixes for Illumos, in particular fixed a Valgrind crash
  whenever a signal handler was called.

* On FreeBSD, a change to the libc code that runs atexit handlers was
  causing Helgrind to produce an extra error about exiting threads
  still holding locks for. This applied to every multithreaded application.
  The extra error is now filtered out. A syscall wrapper had been added
  for getrlimitusage.

* On Linux various new syscalls are supported (landlock*, io_pgetevents,
  open_tree, move_mount, fsopen, fsconfig, fsmount, fspick, userfaultfd).

* s390x has support for various new instructions (BPP, BPRP, PPA and NIAI).

* ==================== TOOL CHANGES ===================

* The --track-fds=yes and --track-fds=all options now treat all
  inherited file descriptors the same as 0, 1, 2 (stdin/out/err).
  And when the stdin/out/err descriptors are reassigned they are
  now treated as normal (non-inherited) file descriptors.

* A new option --modify-fds=high can be used together with
  --track-fds=yes to create new file descriptors with the highest
  possible number (and then decreasing) instead of always using the
  lowest possible number (which is required by POSIX). This will help
  catch issues where a file descriptor number might normally be reused
  between a close and another open call.

* Helgrind:
  There is a change to warnings about calls to pthread_cond_signal and
  pthread_cond_broadcast when the associated mutex is unlocked. Previously
  Helgrind would always warn about this. Now this error is controlled by
  a command line option, --check-cond-signal-mutex=yes|no. The default is
  no. This change has been made because some C and C++ standard libraries
  use pthread_cond_signal/pthread_cond_broadcast in this way. Users are
  obliged to use suppressions if they wish to avoid this noise.

* ==================== FIXED BUGS ====================

The following bugs have been fixed or resolved.  Note that "n-i-bz"
stands for "not in bugzilla" -- that is, a bug that was reported to us
but never got a bugzilla entry.  We encourage you to file bugs in
bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather
than mailing the developers (or mailing lists) directly -- bugs that
are not entered into bugzilla tend to get forgotten about or ignored.

290061  pie elf always loaded at 0x108000
396415  Valgrind is not looking up $ORIGIN rpath of shebang programs
420682  io_pgetevents is not supported
468575  Add support for RISC-V
469782  Valgrind does not support zstd-compressed debug sections
487296  --track-fds=yes and --track-fds=all report erroneous information
        when fds 0, 1, or 2 are used as non-std
489913  WARNING: unhandled amd64-linux syscall: 444 (landlock_create_ruleset)
493433  Add --modify-fds=[no|high] option
494246  syscall fsopen not wrapped
494327  Crash when running Helgrind built with #define TRACE_PTH_FNS 1
494337  All threaded applications cause still holding lock errors
495488  Add FreeBSD getrlimitusage syscall wrapper
495816  s390x: Fix disassembler segfault for C[G]RT and CL[G]RT
495817  s390x: Disassembly to match objdump -d output
496370  Illumos: signal handling is broken
496571  False positive for null key passed to bpf_map_get_next_key syscall.
496950  s390x: Fix hardware capabilities and EmFail codes
497130  Recognize new DWARF5 DW_LANG constants
497455  Update drd/scripts/download-and-build-gcc
497723  Enabling Ada demangling breaks callgrind differentiation between
        overloaded functions and procedures
498037  s390x: Add disassembly checker
498143  False positive on EVIOCGRAB ioctl
498317  FdBadUse is not a valid CoreError type in a suppression
        even though it's generated by --gen-suppressions=yes
498421  s390x: support BPP, BPRP and NIAI insns
498422  s390x: Fix VLRL and VSTRL insns
498492  none/tests/amd64/lzcnt64 crashes on FreeBSD compiled with clang
498629  s390x: Fix S[L]HHHR and S[L]HHLR insns
498632  s390x: Fix LNGFR insn
498942  s390x: Rework s390_disasm interface
499183  FreeBSD: differences in avx-vmovq output
499212  mmap() with MAP_ALIGNED() returns unaligned pointer
501119  memcheck/tests/pointer-trace fails when run on NFS filesystem
501194  Fix ML_(check_macho_and_get_rw_loads) so that it is correct for
        any number of segment commands
501348  glibc built with -march=x86-64-v3 does not work due to ld.so memcmp
501479  Illumos DRD pthread_mutex_init wrapper errors
501365  syscall userfaultfd not wrapped
501846  Add x86 Linux shm wrappers
501850  FreeBSD syscall arguments 7 and 8 incorrect.
501893  Missing suppression for __wcscat_avx2 (strcat-strlen-avx2.h.S:68)?
502126  glibc 2.41 extra syscall_cancel frames
502288  s390x: Memcheck false positives with NNPA last tensor dimension
502324  s390x: Memcheck false positives with TMxx and TM/TMY
502679  Use LTP for testing valgrind
502871  Make Helgrind "pthread_cond_{signal,broadcast}: dubious: associated
        lock is not held by any thread" optional

To see details of a given bug, visit
  https://bugs.kde.org/show_bug.cgi?id=XXXXXX
where XXXXXX is the bug number as listed above.

(3.25.0.RC1: 18 Apr 2025)
(3.25.0.RC2: 23 Apr 2025)

Re: [Valgrind-developers] Valgrind-3.25.0.RC1 is available for testing

[P J. <Jee...@ib...>]

Hi Everyone,
valgrind-3.25.0.RC1 looks good on Power and that there are no issues requiring fixes before releasing  Valgrind 3.25

The PowerPC testsults for Both LE & BE are as follows

Powerpc64LE Results:

Power8:
There are no new failures compared to Valgrind 3.24.0.

== 768 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 3 post failures ==
memcheck/tests/leak_cpp_interior         (stderr)
memcheck/tests/linux/rfcomm              (stderr)
memcheck/tests/linux/sys-execveat        (stderr)
massif/tests/bug469146                   (post)
massif/tests/new-cpp                     (post)
massif/tests/overloaded-new              (post)


Power9:
There are no new failures compared to Valgrind 3.24.0.

== 775 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/linux/rfcomm              (stderr)


Power10:
There are no new failures compared to Valgrind 3.24.0.

== 781 tests, 7 stderr failures, 2 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/execve1                   (stderr)
memcheck/tests/execve2                   (stderr)
memcheck/tests/linux/rfcomm              (stderr)
memcheck/tests/thread_alloca             (stderr)
helgrind/tests/getaddrinfo               (stderr)
drd/tests/getaddrinfo                    (stderr)
none/tests/allexec32                     (stdout)
none/tests/allexec64                     (stdout)
none/tests/scripts/shell                 (stderr)




PowerpcBE Results:

Power8:
There are 2 new stderr failures and 1 new stdout failure compared to Valgrind 3.24.0, as these are newly added tests.  However these can be safely ignored as they were not reproduced on Power9.

Apart from previous expected failures from baseline , below are the additional failures.

== 785 tests, 333 stderr failures, 70 stdout failures, 3 stderrB failures, 3 stdoutB failures, 6 post failures ==

memcheck/tests/cdebug_zstd               (stderr)
memcheck/tests/wcscat                    (stdout)
memcheck/tests/wcscat                    (stderr)


Note: These test cases are failing due to missing symbols from certain packages. However, the issue is not reproducible on Power9.

Power9:
There are no new failures compared to Valgrind 3.24.0.

== 819 tests, 52 stderr failures, 45 stdout failures, 1 stderrB failure, 2 stdoutB failures, 2 post failures ==

Thanks,
Jeevitha


------------------------------------------------------------------------------------------------------------------
Subject:         [Valgrind-developers] Valgrind-3.25.0.RC1 is available for
testing
Date:    Fri, 18 Apr 2025 15:53:59 +0200
From:    Mark Wielaard <ma...@kl...>
To:      val...@li...,
val...@li...



Slightly later than originally planned, but the RC1 is finally out!

An RC1 tarball for 3.25.0 is now available at
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC1.tar.bz2
(md5sum = 2f02fe951278ebde62bba65c3a311a40)
(sha1sum = 3679ddc3237455f07de0ae30f21e947868c2218e)
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC1.tar.bz2.asc

Please give it a try in configurations that are important for you and
report any problems you have, either on this mailing list, or
(preferably) via our bug tracker at
https://bugs.kde.org/enter_bug.cgi?product=valgrind

The NEWS file isn't complete up to date yet, but some highlights:

- Initial RISCV64/Linux support.
- Valgrind gdbserver supports 'x' packets.
- Numerous bug fixes for Illumos.
- --track-fds=yes now treats all inherited file descriptors like
stdin/out/err (0,1,2) and there is a --modify-fds=high option.
- s390x support for various new instructions (BPP, BPRP and NIAI)
- Various new linux syscalls are supported (landlock*, open_tree,
move_mount, fsopen, fsconfig, fsmount, fspick, userfaultfd)
- The Linux Test Project (ltp) is integrated in the testsuite
try 'make ltpchecks' (this will take a while and will point out
various missing syscalls and valgrind crashes!)

Since this RC1 is slightly later than planned and it is a long Easter
weekend for those that celebrate, lets do the RC2 on Wed Apr 25, with
the 3.25.0 final on Fri Apr 27.


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Re: [Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing

[Mark W. <ma...@kl...>]

Hi Jeevitha,

On Fri, 2025-04-25 at 13:15 +0000, P Jeevitha wrote:
> Hi Everyone,
> valgrind-3.25.0.RC2 also looks good on Power and that there are no issues requiring fixes before releasing .

Thanks again. I have just tagged the final 3.25.0 release in git. Will
update the website and then announce the release officially.

Cheers,

Mark

> The PowerPC testsults for Both LE & BE are as follows
> 
> Powerpc64LE Results:
> 
> Power8:
> There are no new failures compared to valgrind-3.25.0.RC1. 
>  
> == 768 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 3 post failures ==
> memcheck/tests/leak_cpp_interior         (stderr)
> memcheck/tests/linux/rfcomm              (stderr)
> memcheck/tests/linux/sys-execveat        (stderr)
> massif/tests/bug469146                   (post)
> massif/tests/new-cpp                     (post)
> massif/tests/overloaded-new              (post)
>  
>  
> Power9:
> There are no new failures compared to valgrind-3.25.0.RC1.
>  
> == 775 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
> memcheck/tests/linux/rfcomm              (stderr)
>  
>  
> Power10:
> There are no new failures compared to valgrind-3.25.0.RC1.
>  
> == 781 tests, 7 stderr failures, 2 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
> memcheck/tests/execve1                   (stderr)
> memcheck/tests/execve2                   (stderr)
> memcheck/tests/linux/rfcomm              (stderr)
> memcheck/tests/thread_alloca             (stderr)
> helgrind/tests/getaddrinfo               (stderr)
> drd/tests/getaddrinfo                    (stderr)
> none/tests/allexec32                     (stdout)
> none/tests/allexec64                     (stdout)
> none/tests/scripts/shell                 (stderr)
>  
>  
> PowerpcBE Results:
>  
> Power8:
> There are no new failures compared to valgrind-3.25.0.RC1.
>  
> == 785 tests, 333 stderr failures, 70 stdout failures, 3 stderrB failures, 3 stdoutB failures, 6 post failures ==
>  
> Power9:
> There are no new failures compared to valgrind-3.25.0.RC1
>  
> == 819 tests, 52 stderr failures, 45 stdout failures, 1 stderrB failure, 2 stdoutB failures, 2 post failures ==
>  
> Thanks,
> Jeevitha           
>  
>  
> 
> 
> 
> 
> 
> 
> 
> 
> From:Mark Wielaard <ma...@kl...>
> Date: Thursday, 24 April 2025 at 7:31 AM
> To: val...@li... <val...@li...>, val...@li... <val...@li...>
> Subject: [EXTERNAL] [Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing
> 
> 
> An RC2 tarball for 3.25.0 is now available at
> https://urldefense.proofpoint.com/v2/url?u=https-3A__sourceware.org_pub_valgrind_valgrind-2D3.25.0.RC2.tar.bz2&d=DwICAg&c=BSDicqBQBDjDI9RkVyTcHQ&r=1GmuiRN2MNmsR6U1MCgzJDTJN341hwlj76xKBOp0NuQ&m=85bKzMP6w6T9IXjGhZvfahYOFbOzyF5743I9agGtperF27vw7g4Z4IMrGsRTwT00&s=_zaWTSpIMqnpXXiToInHiY_Kj1oYB8-M_2r5bfwdxIc&e=
> 
> (md5sum = 4e53a0a1a8d1404e77e6c45015eeb472)
> (sha1sum = ba482eeeb89dd271006f59b09f01048be6530a53)
> https://urldefense.proofpoint.com/v2/url?u=https-3A__sourceware.org_pub_valgrind_valgrind-2D3.25.0.RC2.tar.bz2.asc&d=DwICAg&c=BSDicqBQBDjDI9RkVyTcHQ&r=1GmuiRN2MNmsR6U1MCgzJDTJN341hwlj76xKBOp0NuQ&m=85bKzMP6w6T9IXjGhZvfahYOFbOzyF5743I9agGtperF27vw7g4Z4IMrGsRTwT00&s=icWh0hJCWXeHglX3_TMvNDSHAHhLrk33SZCpK6IGtT8&e=
> 
> 
> Please give it a try in configurations that are important for you and
> report any problems you have, either on this mailing list, or
> (preferably) via our bug tracker at
> https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.kde.org_enter-5Fbug.cgi-3Fproduct-3Dvalgrind&d=DwICAg&c=BSDicqBQBDjDI9RkVyTcHQ&r=1GmuiRN2MNmsR6U1MCgzJDTJN341hwlj76xKBOp0NuQ&m=85bKzMP6w6T9IXjGhZvfahYOFbOzyF5743I9agGtperF27vw7g4Z4IMrGsRTwT00&s=MhvwPxwO5oPkG89lLuOAA7ioFG7rG3VGQ5XMuPKRfL8&e=
> 
> 
> Changes from RC1:
> 
> Florian Krohm (2):
>   s390x: Fix a comment
>   s390x only: Clean up unused Ijk_... values
> 
> Mark Wielaard (4):
>   auxprogs/Makefile.am (EXTRA_DIST): Add ltpchecks helper files
>   Update NEWS for RISCV64/Linux and --modify-fds=[no|high] option
>   none/tests/riscv64/testinst.h: Use lla instead of la in JMP_RANGE
>   Set version to 3.25.0-RC2
> 
> Paul Floyd (8):
>   Bug 502871 - Make Helgrind "pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread" optional
>   Add 3.25 highlights to NEWS for FreeBSD.
>   Doc: add description of cond signal without mutex lock.
>   Helgrind regtest: use --check-cond-signal-mutex=yes in tc20_verifywrap
>   FreeBSD regtest: add auxv_script to dist_noinst_SCRIPTS
>   Illumos suppression and regtest
>   Illumos regtest: add an expected for none/tests/fdleak_socketpair_xml.stderr
>   Regtest: clean up warning and compilation of bug290061.c
> 
> Petr Pavlu (4):
>   riscv64: Fix tests compilation with newer GNU as
>   riscv64: Merge decoding of csrrw and csrrs
>   riscv64: Add support for csrrc
>   riscv64: Drop the not-needed type for FpCSEL
> 
> zhaomingxin (1):
>   riscv64: Add missing floating-point ITE/CSEL support in VEX backend
> 
> Unless a showstopper bug pops up 3.25.0 final will be released on
> Fri Apr 27.
> 
> 
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.sourceforge.net_lists_listinfo_valgrind-2Ddevelopers&d=DwICAg&c=BSDicqBQBDjDI9RkVyTcHQ&r=1GmuiRN2MNmsR6U1MCgzJDTJN341hwlj76xKBOp0NuQ&m=85bKzMP6w6T9IXjGhZvfahYOFbOzyF5743I9agGtperF27vw7g4Z4IMrGsRTwT00&s=b7F7UfNVIc0UuSe0A8ffN7yQj0axX8xNn1R2SSgEE3I&e=

[Valgrind-developers] [valgrind] Created tag 'VALGRIND_3_25_0'

[Mark W. <ma...@so...>]

The signed tag 'VALGRIND_3_25_0' was created pointing to:

 0b55712730... -> 3.25.0 final

Tagger: Mark Wielaard <ma...@kl...>
Date: Fri Apr 25 14:45:28 2025 +0200

    valgrind 3.25.0 release

[Valgrind-developers] [valgrind] -> 3.25.0 final

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0b557127300197e0c779369d2e173eb85121fd66

commit 0b557127300197e0c779369d2e173eb85121fd66
Author: Mark Wielaard <ma...@kl...>
Date:   Fri Apr 25 14:38:05 2025 +0200

    -> 3.25.0 final

Diff:
---
 NEWS         | 13 ++++++++++++-
 configure.ac |  4 ++--
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/NEWS b/NEWS
index 3cc13344a5..cd4670aca6 100644
--- a/NEWS
+++ b/NEWS
@@ -1,4 +1,4 @@
-Release 3.25.0.RC2 (23 Apr 2025)
+Release 3.25.0 (25 Apr 2025)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
@@ -14,6 +14,12 @@ X86/macOS 10.13, AMD64/macOS 10.13 and nanoMIPS/Linux.
   'x addr,len' (available in GDB release >= 16).
   The x packet can reduce the time taken by GDB to read memory from valgrind.
 
+* Valgrind now supports zstd compressed debug sections.
+
+* The Linux Test Project (ltp) is integrated in the testsuite try
+  'make ltpchecks' (this will take a while and will point out various
+  missing syscalls and valgrind crashes!)
+
 * ================== PLATFORM CHANGES =================
 
 * Added RISCV64 support for Linux. Specifically for the RV64GC
@@ -28,6 +34,11 @@ X86/macOS 10.13, AMD64/macOS 10.13 and nanoMIPS/Linux.
   The extra error is now filtered out. A syscall wrapper had been added
   for getrlimitusage.
 
+* On Linux various new syscalls are supported (landlock*, io_pgetevents,
+  open_tree, move_mount, fsopen, fsconfig, fsmount, fspick, userfaultfd).
+
+* s390x has support for various new instructions (BPP, BPRP, PPA and NIAI).
+
 * ==================== TOOL CHANGES ===================
 
 * The --track-fds=yes and --track-fds=all options now treat all
diff --git a/configure.ac b/configure.ac
index 6a7c32993d..2dfbd1c1af 100755
--- a/configure.ac
+++ b/configure.ac
@@ -18,8 +18,8 @@ AC_PREREQ(2.69)
 m4_define([v_major_ver], [3])
 m4_define([v_minor_ver], [25])
 m4_define([v_micro_ver], [0])
-m4_define([v_suffix_ver], [RC2])
-m4_define([v_rel_date], ["23 Apr 2025"])
+m4_define([v_suffix_ver], [])
+m4_define([v_rel_date], ["25 Apr 2025"])
 m4_define([v_version],
 	  m4_if(v_suffix_ver, [],
 		[v_major_ver.v_minor_ver.v_micro_ver],

Re: [Valgrind-developers] Valgrind-3.25.0.RC1 is available for testing

[Mark W. <ma...@kl...>]

Hi Jeevitha,

On Fri, 2025-04-25 at 11:52 +0000, P Jeevitha wrote:
> Hi Everyone,
> 
> valgrind-3.25.0.RC1 looks good on Power and that there are no issues requiring fixes before releasing  Valgrind 3.25

Thanks so much for testing. The results do indeed look good. I am going
to prepare the 3.25.0 final release now.

I didn't see your message on the list, I am not sure why not. Maybe
because you are not subscribed, or because the message used HTML?

So I'll quote it in full below just to make sure others are aware of
your testing efforts.

Thanks,

Mark

> The PowerPC testsults for Both LE & BE are as follows
> 
> Powerpc64LE Results:
> 
> Power8:
> 
> There are no new failures compared to Valgrind 3.24.0.
> 
>  
> 
> == 768 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 3 post failures ==
> 
> memcheck/tests/leak_cpp_interior         (stderr)
> 
> memcheck/tests/linux/rfcomm              (stderr)
> 
> memcheck/tests/linux/sys-execveat        (stderr)
> 
> massif/tests/bug469146                   (post)
> 
> massif/tests/new-cpp                     (post)
> 
> massif/tests/overloaded-new              (post)
> 
>  
> 
>  
> 
> Power9:
> 
> There are no new failures compared to Valgrind 3.24.0.
> 
>  
> 
> == 775 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
> 
> memcheck/tests/linux/rfcomm              (stderr)
> 
>  
> 
>  
> 
> Power10:
> 
> There are no new failures compared to Valgrind 3.24.0.
> 
>  
> 
> == 781 tests, 7 stderr failures, 2 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
> 
> memcheck/tests/execve1                   (stderr)
> 
> memcheck/tests/execve2                   (stderr)
> 
> memcheck/tests/linux/rfcomm              (stderr)
> 
> memcheck/tests/thread_alloca             (stderr)
> 
> helgrind/tests/getaddrinfo               (stderr)
> 
> drd/tests/getaddrinfo                    (stderr)
> 
> none/tests/allexec32                     (stdout)
> 
> none/tests/allexec64                     (stdout)
> 
> none/tests/scripts/shell                 (stderr)
> 
>  
> 
>  
> 
>  
> 
>  
> 
> PowerpcBE Results:
> 
>  
> 
> Power8:
> 
> There are 2 new stderr failures and 1 new stdout failure compared to Valgrind 3.24.0, as these are newly added tests.  However these can be safely ignored as they were not reproduced on Power9.
> 
> Apart from previous expected failures from baseline , below are the additional failures.
> 
>  
> 
> == 785 tests, 333 stderr failures, 70 stdout failures, 3 stderrB failures, 3 stdoutB failures, 6 post failures ==
> 
>  
> 
> memcheck/tests/cdebug_zstd               (stderr)
> 
> memcheck/tests/wcscat                    (stdout)
> 
> memcheck/tests/wcscat                    (stderr)
> 
>  
> 
>  
> 
> Note: These test cases are failing due to missing symbols from certain packages. However, the issue is not reproducible on Power9.
> 
>  
> 
> Power9:
> 
> There are no new failures compared to Valgrind 3.24.0.
> 
>  
> 
> == 819 tests, 52 stderr failures, 45 stdout failures, 1 stderrB failure, 2 stdoutB failures, 2 post failures ==
> 
>  
> 
> Thanks,
> 
> Jeevitha           
> 
>  
>  
> 
> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------------------------------------------
> Subject:         [Valgrind-developers] Valgrind-3.25.0.RC1 is available for 
> testing
> Date:    Fri, 18 Apr 2025 15:53:59 +0200
> From:    Mark Wielaard <ma...@kl...>
> To:      val...@li..., 
> val...@li...
> 
> 
> 
> Slightly later than originally planned, but the RC1 is finally out!
> 
> An RC1 tarball for 3.25.0 is now available at
> https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC1.tar.bz2
> (md5sum = 2f02fe951278ebde62bba65c3a311a40)
> (sha1sum = 3679ddc3237455f07de0ae30f21e947868c2218e)
> https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC1.tar.bz2.asc
> 
> Please give it a try in configurations that are important for you and
> report any problems you have, either on this mailing list, or
> (preferably) via our bug tracker at
> https://bugs.kde.org/enter_bug.cgi?product=valgrind
> 
> The NEWS file isn't complete up to date yet, but some highlights:
> 
> - Initial RISCV64/Linux support.
> - Valgrind gdbserver supports 'x' packets.
> - Numerous bug fixes for Illumos.
> - --track-fds=yes now treats all inherited file descriptors like
> stdin/out/err (0,1,2) and there is a --modify-fds=high option.
> - s390x support for various new instructions (BPP, BPRP and NIAI)
> - Various new linux syscalls are supported (landlock*, open_tree,
> move_mount, fsopen, fsconfig, fsmount, fspick, userfaultfd)
> - The Linux Test Project (ltp) is integrated in the testsuite
> try 'make ltpchecks' (this will take a while and will point out
> various missing syscalls and valgrind crashes!)
> 
> Since this RC1 is slightly later than planned and it is a long Easter
> weekend for those that celebrate, lets do the RC2 on Wed Apr 25, with
> the 3.25.0 final on Fri Apr 27.
> 
> 
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers

Re: [Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing

[Mark W. <ma...@kl...>]

Hi,

On Thu, Apr 24, 2025 at 03:59:21AM +0200, Mark Wielaard wrote:
> Please give it a try in configurations that are important for you and
> report any problems you have, either on this mailing list, or
> (preferably) via our bug tracker at
> https://bugs.kde.org/enter_bug.cgi?product=valgrind

Some results from the buildbot, most look fairly good, except for the
armhf one, which has lots of regtest failures.

Debian GNU/Linux 12 (bookworm) Linux 6.1.0-32-686-pae #1 SMP
PREEMPT_DYNAMIC Debian 6.1.129-1 (2025-03-06) GNU C Library (Debian
GLIBC 2.36-9+deb12u10) stable release version 2.36. g++ 12.2.0 GNU
objdump (GNU Binutils for Debian) 2.40

== 828 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
helgrind/tests/tc24_nonzero_sem          (stderr)

Fedora release 40 (Forty) Linux 6.8.11-300.fc40.ppc64le #1 SMP Mon May
27 14:48:15 UTC 2024 GNU C Library (GNU libc) stable release version
2.39. g++ 14.1.1 binutils 2.41

== 773 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
helgrind/tests/getaddrinfo               (stderr)

Fedora release 40 (Forty) Linux 6.1.15-legacy-k1 #9 SMP PREEMPT Mon
Aug 12 15:06:24 UTC 2024 GNU C Library (GNU libc) stable release
version 2.39. g++ 14.1.1 binutils 2.42

== 750 tests, 0 stderr failures, 0 stdout failures, 0 stderrB failures, 1 stdoutB failure, 0 post failures ==
gdbserver_tests/hgtls                   

Fedora release 40 (Forty) Linux 6.12.13-100.fc40.s390x #1 SMP Sat Feb
8 16:54:58 UTC 2025 GNU C Library (GNU libc) stable release version
2.39. g++ 14.2.1 binutils 2.41

== 888 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
drd/tests/getaddrinfo                    (stderr)

Fedora release 40 (Forty) Linux 6.13.9-100.fc40.aarch64 gcc (GCC)
14.2.1 20240912 (Red Hat 14.2.1-3) GNU objcopy version 2.41-38.fc40
iconv (GNU libc) 2.39

== 760 tests, 8 stderr failures, 0 stdout failures, 0 stderrB failures, 1 stdoutB failure, 0 post failures ==
gdbserver_tests/hgtls                    (stdoutB)
memcheck/tests/dw4                       (stderr)
memcheck/tests/varinfo2                  (stderr)
memcheck/tests/varinfo4                  (stderr)
memcheck/tests/varinfo5                  (stderr)
memcheck/tests/varinfo6                  (stderr)
memcheck/tests/varinforestrict           (stderr)
helgrind/tests/hg05_race2                (stderr)
helgrind/tests/tc20_verifywrap           (stderr)

fedora-latest gcc (GCC) 14.2.1 20250110 (Red Hat 14.2.1-7) GNU objcopy
version 2.43.1-5.fc41 iconv (GNU libc) 2.40

== 841 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
drd/tests/fork-parallel                  (stderr)
drd/tests/fork-serial                    (stderr)
drd/tests/threaded-fork-vcs              (stderr)
drd/tests/threaded-fork                  (stderr)

Ubuntu 24.04.1 LTS Linux 6.8.0-52-generic #53.1-Ubuntu SMP
PREEMPT_DYNAMIC Sun Jan 26 04:38:25 UTC 2025 riscv64 GNU C Library
(Ubuntu GLIBC 2.39-0ubuntu8.3) stable release version 2.39. g++ 14.2.0
GNU objdump (GNU Binutils) 2.43.1

== 752 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 1 stdoutB failure, 0 post failures ==
gdbserver_tests/hgtls                    (stdoutB)
memcheck/tests/linux/timerfd-syscall     (stderr)

Armbian 25.2.3 bookworm Linux 6.12.20-current-rockchip GNU C Library
(Debian GLIBC 2.36-9+deb12u10) stable release version 2.36. g++ 12.2.0
GNU objdump (GNU Binutils for Debian) 2.40

== 757 tests, 46 stderr failures, 6 stdout failures, 0 stderrB failures, 0 stdoutB failures, 5 post failures ==
memcheck/tests/dw4                       (stderr)
memcheck/tests/leak_cpp_interior         (stderr)
memcheck/tests/linux/stack_changes       (stderr)
memcheck/tests/varinfo2                  (stderr)
memcheck/tests/varinfo4                  (stderr)
memcheck/tests/varinfo5                  (stderr)
memcheck/tests/varinfo6                  (stderr)
memcheck/tests/varinforestrict           (stderr)
memcheck/tests/vbit-test/vbit-test       (stderr)
helgrind/tests/annotate_rwlock           (stderr)
helgrind/tests/bar_bad                   (stderr)
helgrind/tests/bug392331                 (stderr)
helgrind/tests/free_is_write             (stderr)
helgrind/tests/hg02_deadlock             (stderr)
helgrind/tests/hg03_inherit              (stderr)
helgrind/tests/hg04_race                 (stderr)
helgrind/tests/hg04_race_h9              (stderr)
helgrind/tests/hg05_race2                (stderr)
helgrind/tests/locked_vs_unlocked1_fwd   (stderr)
helgrind/tests/locked_vs_unlocked1_rev   (stderr)
helgrind/tests/locked_vs_unlocked2       (stderr)
helgrind/tests/locked_vs_unlocked3       (stderr)
helgrind/tests/pth_barrier1              (stderr)
helgrind/tests/pth_barrier2              (stderr)
helgrind/tests/pth_barrier3              (stderr)
helgrind/tests/pth_destroy_cond          (stderr)
helgrind/tests/rwlock_race               (stderr)
helgrind/tests/tc01_simple_race          (stderr)
helgrind/tests/tc05_simple_race          (stderr)
helgrind/tests/tc06_two_races            (stderr)
helgrind/tests/tc06_two_races_xml        (stderr)
helgrind/tests/tc09_bad_unlock           (stderr)
helgrind/tests/tc14_laog_dinphils        (stderr)
helgrind/tests/tc16_byterace             (stderr)
helgrind/tests/tc19_shadowmem            (stderr)
helgrind/tests/tc20_verifywrap           (stderr)
helgrind/tests/tc21_pthonce              (stderr)
helgrind/tests/tc22_exit_w_lock          (stderr)
massif/tests/bug469146                   (post)
massif/tests/new-cpp                     (post)
massif/tests/overloaded-new              (post)
none/tests/arm/v8crypto_a                (stdout)
none/tests/arm/v8crypto_a                (stderr)
none/tests/arm/v8crypto_t                (stdout)
none/tests/arm/v8crypto_t                (stderr)
none/tests/arm/v8fpsimd_a                (stdout)
none/tests/arm/v8fpsimd_a                (stderr)
none/tests/arm/v8fpsimd_t                (stdout)
none/tests/arm/v8fpsimd_t                (stderr)
none/tests/arm/v8memory_a                (stdout)
none/tests/arm/v8memory_a                (stderr)
none/tests/arm/v8memory_t                (stdout)
none/tests/arm/v8memory_t                (stderr)
exp-bbv/tests/arm-linux/ll               (stderr)
exp-bbv/tests/arm-linux/ll               (post)
exp-bbv/tests/arm-linux/million          (stderr)
exp-bbv/tests/arm-linux/million          (post)

[Valgrind-developers] [valgrind] Regtest: fix an arm64 Linux warning

[Paul F. <pa...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=944e98234d05c8a565a9b7eaad875a0f219ecf05

commit 944e98234d05c8a565a9b7eaad875a0f219ecf05
Author: Paul Floyd <pj...@wa...>
Date:   Thu Apr 24 12:52:52 2025 +0200

    Regtest: fix an arm64 Linux warning
    
    Just a gcc warning for the deliberate use of an uninitialised
    variable in arm64-linux/scalar.

Diff:
---
 memcheck/tests/arm64-linux/Makefile.am | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/memcheck/tests/arm64-linux/Makefile.am b/memcheck/tests/arm64-linux/Makefile.am
index 284d83f801..a694fee889 100644
--- a/memcheck/tests/arm64-linux/Makefile.am
+++ b/memcheck/tests/arm64-linux/Makefile.am
@@ -17,3 +17,5 @@ AM_CFLAGS    += @FLAG_M64@
 AM_CXXFLAGS  += @FLAG_M64@
 AM_CCASFLAGS += @FLAG_M64@
 
+scalar_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+

[Valgrind-developers] Valgrind-3.25.0.RC2 is available for testing

[Mark W. <ma...@kl...>]

An RC2 tarball for 3.25.0 is now available at
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC2.tar.bz2
(md5sum = 4e53a0a1a8d1404e77e6c45015eeb472)
(sha1sum = ba482eeeb89dd271006f59b09f01048be6530a53)
https://sourceware.org/pub/valgrind/valgrind-3.25.0.RC2.tar.bz2.asc

Please give it a try in configurations that are important for you and
report any problems you have, either on this mailing list, or
(preferably) via our bug tracker at
https://bugs.kde.org/enter_bug.cgi?product=valgrind

Changes from RC1:

Florian Krohm (2):
  s390x: Fix a comment
  s390x only: Clean up unused Ijk_... values

Mark Wielaard (4):
  auxprogs/Makefile.am (EXTRA_DIST): Add ltpchecks helper files
  Update NEWS for RISCV64/Linux and --modify-fds=[no|high] option
  none/tests/riscv64/testinst.h: Use lla instead of la in JMP_RANGE
  Set version to 3.25.0-RC2

Paul Floyd (8):
  Bug 502871 - Make Helgrind "pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread" optional
  Add 3.25 highlights to NEWS for FreeBSD.
  Doc: add description of cond signal without mutex lock.
  Helgrind regtest: use --check-cond-signal-mutex=yes in tc20_verifywrap
  FreeBSD regtest: add auxv_script to dist_noinst_SCRIPTS
  Illumos suppression and regtest
  Illumos regtest: add an expected for none/tests/fdleak_socketpair_xml.stderr
  Regtest: clean up warning and compilation of bug290061.c

Petr Pavlu (4):
  riscv64: Fix tests compilation with newer GNU as
  riscv64: Merge decoding of csrrw and csrrs
  riscv64: Add support for csrrc
  riscv64: Drop the not-needed type for FpCSEL

zhaomingxin (1):
  riscv64: Add missing floating-point ITE/CSEL support in VEX backend

Unless a showstopper bug pops up 3.25.0 final will be released on
Fri Apr 27.

[Valgrind-developers] [valgrind] Set version to 3.25.0-RC2

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=600881928b7f4470bb22bc5850ecb152f9c2fb50

commit 600881928b7f4470bb22bc5850ecb152f9c2fb50
Author: Mark Wielaard <ma...@kl...>
Date:   Thu Apr 24 03:30:58 2025 +0200

    Set version to 3.25.0-RC2

Diff:
---
 NEWS         | 3 ++-
 configure.ac | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/NEWS b/NEWS
index ad666f15cb..3cc13344a5 100644
--- a/NEWS
+++ b/NEWS
@@ -1,4 +1,4 @@
-Release 3.25.0.RC1 (18 Apr 2025)
+Release 3.25.0.RC2 (23 Apr 2025)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
@@ -115,6 +115,7 @@ To see details of a given bug, visit
 where XXXXXX is the bug number as listed above.
 
 (3.25.0.RC1: 18 Apr 2025)
+(3.25.0.RC2: 23 Apr 2025)
 
 Release 3.24.0 (31 Oct 2024)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/configure.ac b/configure.ac
index 873d065dc4..6a7c32993d 100755
--- a/configure.ac
+++ b/configure.ac
@@ -18,8 +18,8 @@ AC_PREREQ(2.69)
 m4_define([v_major_ver], [3])
 m4_define([v_minor_ver], [25])
 m4_define([v_micro_ver], [0])
-m4_define([v_suffix_ver], [RC1])
-m4_define([v_rel_date], ["18 Apr 2025"])
+m4_define([v_suffix_ver], [RC2])
+m4_define([v_rel_date], ["23 Apr 2025"])
 m4_define([v_version],
 	  m4_if(v_suffix_ver, [],
 		[v_major_ver.v_minor_ver.v_micro_ver],

[Valgrind-developers] [valgrind] none/tests/riscv64/testinst.h: Use lla instead of la in JMP_RANGE

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4091830aa547ac07c50fffa80de2436a82ac017f

commit 4091830aa547ac07c50fffa80de2436a82ac017f
Author: Mark Wielaard <ma...@kl...>
Date:   Thu Apr 24 03:11:26 2025 +0200

    none/tests/riscv64/testinst.h: Use lla instead of la in JMP_RANGE
    
    la was fine when using binutils ld >= 2.43. But older (2.41 and 2.42)
    binutils ld produced:
    
    none/tests/riscv64/integer.c:81:(.text+0x22cd8): dangerous relocation:
    The addend isn't allowed for R_RISCV_GOT_HI20
    
    Using lla makes integer and compressed link with all binutils ld
    versions.

Diff:
---
 none/tests/riscv64/testinst.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/none/tests/riscv64/testinst.h b/none/tests/riscv64/testinst.h
index 2f087d8b71..7f577edc35 100644
--- a/none/tests/riscv64/testinst.h
+++ b/none/tests/riscv64/testinst.h
@@ -403,7 +403,7 @@ static void show_block_diff(unsigned char* block1,
          ".endif;"                                                             \
          ".if \"" #rs1 "\" != \"unused\";"                                     \
          "sd " #rs1 ", 48(%[w]);"      /* Spill rs1. */                        \
-         "la " #rs1 ", " rs1_val ";"   /* Load the first input. */             \
+         "lla " #rs1 ", " rs1_val ";"   /* Load the first input. */            \
          ".endif;"                                                             \
          ".if \"" #rs2 "\" != \"unused\";"                                     \
          "sd " #rs2 ", 56(%[w]);"      /* Spill rs2. */                        \

[Valgrind-developers] [valgrind] riscv64: Drop the not-needed type for FpCSEL

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c19c7979df6dce4362f60b9e359f23d05d86c2f7

commit c19c7979df6dce4362f60b9e359f23d05d86c2f7
Author: Petr Pavlu <pet...@da...>
Date:   Tue Jul 2 21:55:57 2024 +0000

    riscv64: Drop the not-needed type for FpCSEL

Diff:
---
 VEX/priv/host_riscv64_defs.c | 23 +++++++++--------------
 VEX/priv/host_riscv64_defs.h | 11 +++++------
 VEX/priv/host_riscv64_isel.c | 12 +++++-------
 3 files changed, 19 insertions(+), 27 deletions(-)

diff --git a/VEX/priv/host_riscv64_defs.c b/VEX/priv/host_riscv64_defs.c
index 12c6cb9bdf..149483cd36 100644
--- a/VEX/priv/host_riscv64_defs.c
+++ b/VEX/priv/host_riscv64_defs.c
@@ -564,11 +564,10 @@ RISCV64Instr_FpLdSt(RISCV64FpLdStOp op, HReg reg, HReg base, Int soff12)
 }
 
 RISCV64Instr*
-RISCV64Instr_FpCSEL(IRType ty, HReg dst, HReg iftrue, HReg iffalse, HReg cond)
+RISCV64Instr_FpCSEL(HReg dst, HReg iftrue, HReg iffalse, HReg cond)
 {
    RISCV64Instr* i             = LibVEX_Alloc_inline(sizeof(RISCV64Instr));
    i->tag                      = RISCV64in_FpCSEL;
-   i->RISCV64in.FpCSEL.ty      = ty;
    i->RISCV64in.FpCSEL.dst     = dst;
    i->RISCV64in.FpCSEL.iftrue  = iftrue;
    i->RISCV64in.FpCSEL.iffalse = iffalse;
@@ -797,14 +796,13 @@ void ppRISCV64Instr(const RISCV64Instr* i, Bool mode64)
       vex_printf(")");
       return;
    case RISCV64in_FpCSEL: {
-      UChar suffix = i->RISCV64in.FpCSEL.ty == Ity_F32 ? 's' : 'd';
       vex_printf("(FpCSEL) beq ");
       ppHRegRISCV64(i->RISCV64in.FpCSEL.cond);
-      vex_printf(", zero, 1f; fmv.%c ", suffix);
+      vex_printf(", zero, 1f; fmv.d ");
       ppHRegRISCV64(i->RISCV64in.FpCSEL.dst);
       vex_printf(", ");
       ppHRegRISCV64(i->RISCV64in.FpCSEL.iftrue);
-      vex_printf("; c.j 2f; 1: fmv.%c ", suffix);
+      vex_printf("; c.j 2f; 1: fmv.d ");
       ppHRegRISCV64(i->RISCV64in.FpCSEL.dst);
       vex_printf(", ");
       ppHRegRISCV64(i->RISCV64in.FpCSEL.iffalse);
@@ -2268,23 +2266,20 @@ Int emit_RISCV64Instr(/*MB_MOD*/ Bool*    is_profInc,
       break;
    }
    case RISCV64in_FpCSEL: {
-      /* ty = RISCV64in.FpCSEL.ty == Ity_F32 ? s : d
-
-            beq cond, zero, 1f
-            fmv.{ty} dst, iftrue
+      /*    beq cond, zero, 1f
+            fmv.d dst, iftrue
             c.j 2f
-         1: fmv.{ty} dst, iffalse
+         1: fmv.d dst, iffalse
          2:
-      */
+       */
       UInt dst     = fregEnc(i->RISCV64in.FpCSEL.dst);
       UInt iftrue  = fregEnc(i->RISCV64in.FpCSEL.iftrue);
       UInt iffalse = fregEnc(i->RISCV64in.FpCSEL.iffalse);
       UInt cond    = iregEnc(i->RISCV64in.FpCSEL.cond);
-      UInt fmt     = i->RISCV64in.FpCSEL.ty == Ity_F32 ? 0b0010000 : 0b0010001;
       p = emit_B(p, 0b1100011, (10 >> 1) & 0xfff, 0b000, cond, 0 /*x0/zero*/);
-      p = emit_R(p, 0b1010011, dst, 0b000, iftrue, iftrue, fmt);
+      p = emit_R(p, 0b1010011, dst, 0b000, iftrue, iftrue, 0b0010001);
       p = emit_CJ(p, 0b01, (6 >> 1) & 0x7ff, 0b101);
-      p = emit_R(p, 0b1010011, dst, 0b000, iffalse, iffalse, fmt);
+      p = emit_R(p, 0b1010011, dst, 0b000, iffalse, iffalse, 0b0010001);
       goto done;
    }
    case RISCV64in_CAS: {
diff --git a/VEX/priv/host_riscv64_defs.h b/VEX/priv/host_riscv64_defs.h
index 59e556ca30..16c524cab3 100644
--- a/VEX/priv/host_riscv64_defs.h
+++ b/VEX/priv/host_riscv64_defs.h
@@ -458,11 +458,10 @@ typedef struct {
       } FpLdSt;
       /* Floating-point conditional-select pseudoinstruction. */
       struct {
-         IRType ty;
-         HReg   dst;
-         HReg   iftrue;
-         HReg   iffalse;
-         HReg   cond;
+         HReg dst;
+         HReg iftrue;
+         HReg iffalse;
+         HReg cond;
       } FpCSEL;
       /* Compare-and-swap pseudoinstruction. */
       struct {
@@ -562,7 +561,7 @@ RISCV64Instr_FpCompare(RISCV64FpCompareOp op, HReg dst, HReg src1, HReg src2);
 RISCV64Instr*
 RISCV64Instr_FpLdSt(RISCV64FpLdStOp op, HReg reg, HReg base, Int soff12);
 RISCV64Instr*
-RISCV64Instr_FpCSEL(IRType ty, HReg dst, HReg iftrue, HReg iffalse, HReg cond);
+RISCV64Instr_FpCSEL(HReg dst, HReg iftrue, HReg iffalse, HReg cond);
 RISCV64Instr*
 RISCV64Instr_CAS(RISCV64CASOp op, HReg old, HReg addr, HReg expd, HReg data);
 RISCV64Instr* RISCV64Instr_FENCE(void);
diff --git a/VEX/priv/host_riscv64_isel.c b/VEX/priv/host_riscv64_isel.c
index 747d415540..fd63cfc77d 100644
--- a/VEX/priv/host_riscv64_isel.c
+++ b/VEX/priv/host_riscv64_isel.c
@@ -1558,13 +1558,11 @@ static HReg iselFltExpr_wrk(ISelEnv* env, IRExpr* e)
    /* ---------------------- MULTIPLEX ---------------------- */
    case Iex_ITE: {
       /* ITE(ccexpr, iftrue, iffalse) */
-      HReg   cond    = iselIntExpr_R(env, e->Iex.ITE.cond);
-      HReg   iftrue  = iselFltExpr(env, e->Iex.ITE.iftrue);
-      HReg   iffalse = iselFltExpr(env, e->Iex.ITE.iffalse);
-      HReg   dst     = newVRegF(env);
-      IRType csel_ty = typeOfIRExpr(env->type_env, e->Iex.ITE.iftrue);
-      vassert(csel_ty == Ity_F64 || csel_ty == Ity_F32);
-      addInstr(env, RISCV64Instr_FpCSEL(csel_ty, dst, iftrue, iffalse, cond));
+      HReg cond    = iselIntExpr_R(env, e->Iex.ITE.cond);
+      HReg iftrue  = iselFltExpr(env, e->Iex.ITE.iftrue);
+      HReg iffalse = iselFltExpr(env, e->Iex.ITE.iffalse);
+      HReg dst     = newVRegF(env);
+      addInstr(env, RISCV64Instr_FpCSEL(dst, iftrue, iffalse, cond));
       return dst;
    }

[Valgrind-developers] [valgrind] riscv64: Add missing floating-point ITE/CSEL support in VEX backend

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=18c771ada2d21ec256bcece29ed5442ec20b4ced

commit 18c771ada2d21ec256bcece29ed5442ec20b4ced
Author: zhaomingxin <zha...@al...>
Date:   Thu Apr 13 15:11:46 2023 +0800

    riscv64: Add missing floating-point ITE/CSEL support in VEX backend

Diff:
---
 VEX/priv/host_riscv64_defs.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
 VEX/priv/host_riscv64_defs.h | 11 ++++++++
 VEX/priv/host_riscv64_isel.c | 13 ++++++++++
 3 files changed, 84 insertions(+)

diff --git a/VEX/priv/host_riscv64_defs.c b/VEX/priv/host_riscv64_defs.c
index 7e6b95380a..12c6cb9bdf 100644
--- a/VEX/priv/host_riscv64_defs.c
+++ b/VEX/priv/host_riscv64_defs.c
@@ -563,6 +563,19 @@ RISCV64Instr_FpLdSt(RISCV64FpLdStOp op, HReg reg, HReg base, Int soff12)
    return i;
 }
 
+RISCV64Instr*
+RISCV64Instr_FpCSEL(IRType ty, HReg dst, HReg iftrue, HReg iffalse, HReg cond)
+{
+   RISCV64Instr* i             = LibVEX_Alloc_inline(sizeof(RISCV64Instr));
+   i->tag                      = RISCV64in_FpCSEL;
+   i->RISCV64in.FpCSEL.ty      = ty;
+   i->RISCV64in.FpCSEL.dst     = dst;
+   i->RISCV64in.FpCSEL.iftrue  = iftrue;
+   i->RISCV64in.FpCSEL.iffalse = iffalse;
+   i->RISCV64in.FpCSEL.cond    = cond;
+   return i;
+}
+
 RISCV64Instr*
 RISCV64Instr_CAS(RISCV64CASOp op, HReg old, HReg addr, HReg expd, HReg data)
 {
@@ -783,6 +796,21 @@ void ppRISCV64Instr(const RISCV64Instr* i, Bool mode64)
       ppHRegRISCV64(i->RISCV64in.FpLdSt.base);
       vex_printf(")");
       return;
+   case RISCV64in_FpCSEL: {
+      UChar suffix = i->RISCV64in.FpCSEL.ty == Ity_F32 ? 's' : 'd';
+      vex_printf("(FpCSEL) beq ");
+      ppHRegRISCV64(i->RISCV64in.FpCSEL.cond);
+      vex_printf(", zero, 1f; fmv.%c ", suffix);
+      ppHRegRISCV64(i->RISCV64in.FpCSEL.dst);
+      vex_printf(", ");
+      ppHRegRISCV64(i->RISCV64in.FpCSEL.iftrue);
+      vex_printf("; c.j 2f; 1: fmv.%c ", suffix);
+      ppHRegRISCV64(i->RISCV64in.FpCSEL.dst);
+      vex_printf(", ");
+      ppHRegRISCV64(i->RISCV64in.FpCSEL.iffalse);
+      vex_printf("; 2:");
+      return;
+   }
    case RISCV64in_CAS: {
       vassert(i->RISCV64in.CAS.op == RISCV64op_CAS_D ||
               i->RISCV64in.CAS.op == RISCV64op_CAS_W);
@@ -1055,6 +1083,12 @@ void getRegUsage_RISCV64Instr(HRegUsage* u, const RISCV64Instr* i, Bool mode64)
       }
       addHRegUse(u, HRmRead, i->RISCV64in.FpLdSt.base);
       return;
+   case RISCV64in_FpCSEL:
+      addHRegUse(u, HRmWrite, i->RISCV64in.FpCSEL.dst);
+      addHRegUse(u, HRmRead, i->RISCV64in.FpCSEL.iftrue);
+      addHRegUse(u, HRmRead, i->RISCV64in.FpCSEL.iffalse);
+      addHRegUse(u, HRmRead, i->RISCV64in.FpCSEL.cond);
+      return;
    case RISCV64in_CAS:
       addHRegUse(u, HRmWrite, i->RISCV64in.CAS.old);
       addHRegUse(u, HRmRead, i->RISCV64in.CAS.addr);
@@ -1267,6 +1301,12 @@ void mapRegs_RISCV64Instr(HRegRemap* m, RISCV64Instr* i, Bool mode64)
       mapReg(m, &i->RISCV64in.FpLdSt.reg);
       mapReg(m, &i->RISCV64in.FpLdSt.base);
       return;
+   case RISCV64in_FpCSEL:
+      mapReg(m, &i->RISCV64in.FpCSEL.dst);
+      mapReg(m, &i->RISCV64in.FpCSEL.iftrue);
+      mapReg(m, &i->RISCV64in.FpCSEL.iffalse);
+      mapReg(m, &i->RISCV64in.FpCSEL.cond);
+      return;
    case RISCV64in_CAS:
       mapReg(m, &i->RISCV64in.CAS.old);
       mapReg(m, &i->RISCV64in.CAS.addr);
@@ -2227,6 +2267,26 @@ Int emit_RISCV64Instr(/*MB_MOD*/ Bool*    is_profInc,
       }
       break;
    }
+   case RISCV64in_FpCSEL: {
+      /* ty = RISCV64in.FpCSEL.ty == Ity_F32 ? s : d
+
+            beq cond, zero, 1f
+            fmv.{ty} dst, iftrue
+            c.j 2f
+         1: fmv.{ty} dst, iffalse
+         2:
+      */
+      UInt dst     = fregEnc(i->RISCV64in.FpCSEL.dst);
+      UInt iftrue  = fregEnc(i->RISCV64in.FpCSEL.iftrue);
+      UInt iffalse = fregEnc(i->RISCV64in.FpCSEL.iffalse);
+      UInt cond    = iregEnc(i->RISCV64in.FpCSEL.cond);
+      UInt fmt     = i->RISCV64in.FpCSEL.ty == Ity_F32 ? 0b0010000 : 0b0010001;
+      p = emit_B(p, 0b1100011, (10 >> 1) & 0xfff, 0b000, cond, 0 /*x0/zero*/);
+      p = emit_R(p, 0b1010011, dst, 0b000, iftrue, iftrue, fmt);
+      p = emit_CJ(p, 0b01, (6 >> 1) & 0x7ff, 0b101);
+      p = emit_R(p, 0b1010011, dst, 0b000, iffalse, iffalse, fmt);
+      goto done;
+   }
    case RISCV64in_CAS: {
       /* 1: lr.<size> old, (addr)
             bne old, expd, 2f
diff --git a/VEX/priv/host_riscv64_defs.h b/VEX/priv/host_riscv64_defs.h
index 1990fe3f51..59e556ca30 100644
--- a/VEX/priv/host_riscv64_defs.h
+++ b/VEX/priv/host_riscv64_defs.h
@@ -336,6 +336,7 @@ typedef enum {
    RISCV64in_FpConvert,       /* Floating-point convert instruction. */
    RISCV64in_FpCompare,       /* Floating-point compare instruction. */
    RISCV64in_FpLdSt,          /* Floating-point load/store instruction. */
+   RISCV64in_FpCSEL,          /* Floating-point conditional-select pseudoinstruction.*/
    RISCV64in_CAS,             /* Compare-and-swap pseudoinstruction. */
    RISCV64in_FENCE,           /* Device I/O and memory fence. */
    RISCV64in_CSEL,            /* Conditional-select pseudoinstruction. */
@@ -455,6 +456,14 @@ typedef struct {
          HReg            base;
          Int             soff12; /* -2048 .. +2047 */
       } FpLdSt;
+      /* Floating-point conditional-select pseudoinstruction. */
+      struct {
+         IRType ty;
+         HReg   dst;
+         HReg   iftrue;
+         HReg   iffalse;
+         HReg   cond;
+      } FpCSEL;
       /* Compare-and-swap pseudoinstruction. */
       struct {
          RISCV64CASOp op;
@@ -553,6 +562,8 @@ RISCV64Instr_FpCompare(RISCV64FpCompareOp op, HReg dst, HReg src1, HReg src2);
 RISCV64Instr*
 RISCV64Instr_FpLdSt(RISCV64FpLdStOp op, HReg reg, HReg base, Int soff12);
 RISCV64Instr*
+RISCV64Instr_FpCSEL(IRType ty, HReg dst, HReg iftrue, HReg iffalse, HReg cond);
+RISCV64Instr*
 RISCV64Instr_CAS(RISCV64CASOp op, HReg old, HReg addr, HReg expd, HReg data);
 RISCV64Instr* RISCV64Instr_FENCE(void);
 RISCV64Instr* RISCV64Instr_CSEL(HReg dst, HReg iftrue, HReg iffalse, HReg cond);
diff --git a/VEX/priv/host_riscv64_isel.c b/VEX/priv/host_riscv64_isel.c
index c476d133c7..747d415540 100644
--- a/VEX/priv/host_riscv64_isel.c
+++ b/VEX/priv/host_riscv64_isel.c
@@ -1555,6 +1555,19 @@ static HReg iselFltExpr_wrk(ISelEnv* env, IRExpr* e)
       return dst;
    }
 
+   /* ---------------------- MULTIPLEX ---------------------- */
+   case Iex_ITE: {
+      /* ITE(ccexpr, iftrue, iffalse) */
+      HReg   cond    = iselIntExpr_R(env, e->Iex.ITE.cond);
+      HReg   iftrue  = iselFltExpr(env, e->Iex.ITE.iftrue);
+      HReg   iffalse = iselFltExpr(env, e->Iex.ITE.iffalse);
+      HReg   dst     = newVRegF(env);
+      IRType csel_ty = typeOfIRExpr(env->type_env, e->Iex.ITE.iftrue);
+      vassert(csel_ty == Ity_F64 || csel_ty == Ity_F32);
+      addInstr(env, RISCV64Instr_FpCSEL(csel_ty, dst, iftrue, iffalse, cond));
+      return dst;
+   }
+
    default:
       break;
    }

[Valgrind-developers] [valgrind] riscv64: Add support for csrrc

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c5a916b6551b982f3ae098b38709abcdd4ca978f

commit c5a916b6551b982f3ae098b38709abcdd4ca978f
Author: Petr Pavlu <pet...@da...>
Date:   Tue Jul 2 21:12:22 2024 +0000

    riscv64: Add support for csrrc

Diff:
---
 README.riscv64                    |  4 +--
 VEX/priv/guest_riscv64_toIR.c     | 27 +++++++++++++--
 none/tests/riscv64/csr.c          | 33 +++++++++++++++++-
 none/tests/riscv64/csr.stdout.exp | 72 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 130 insertions(+), 6 deletions(-)

diff --git a/README.riscv64 b/README.riscv64
index 04f2bc9572..6ce2a082f0 100644
--- a/README.riscv64
+++ b/README.riscv64
@@ -14,7 +14,7 @@ The following ISA base and extensions are currently supported:
 | RV64A        | Atomic                            |   22/22 | (2)      |
 | RV64F        | Single-precision floating-point   |   30/30 | (3)      |
 | RV64D        | Double-precision floating-point   |   32/32 |          |
-| RV64Zicsr    | Control & status register         |     2/6 | (4), (5) |
+| RV64Zicsr    | Control & status register         |     3/6 | (4), (5) |
 | RV64Zifencei | Instruction-fetch fence           |     0/1 | (6)      |
 | RV64C        | Compressed                        |   37/37 |          |
 
@@ -22,7 +22,7 @@ Notes:
 (1) MULHSU is not recognized.
 (2) LR and SC use the VEX "fallback" method which suffers from the ABA problem.
 (3) Operations do not check if the input operands are correctly NaN-boxed.
-(4) CSRRC, CSRRWI, CSRRSI and CSRRCI are not recognized.
+(4) CSRRWI, CSRRSI and CSRRCI are not recognized.
 (5) Only registers fflags, frm and fcsr are accepted.
 (6) FENCE.I is not recognized.
 
diff --git a/VEX/priv/guest_riscv64_toIR.c b/VEX/priv/guest_riscv64_toIR.c
index 1c8a845e82..5d9b903c9b 100644
--- a/VEX/priv/guest_riscv64_toIR.c
+++ b/VEX/priv/guest_riscv64_toIR.c
@@ -3170,15 +3170,15 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
 {
    /* ------------ RV64Zicsr standard extension ------------- */
 
-   /* --------------- csrr{w,s} rd, csr, rs1 ---------------- */
+   /* -------------- csrr{w,s,c} rd, csr, rs1 --------------- */
    if (INSN(6, 0) == 0b1110011) {
       UInt rd     = INSN(11, 7);
       UInt funct3 = INSN(14, 12);
       UInt rs1    = INSN(19, 15);
       UInt csr    = INSN(31, 20);
-      if ((funct3 != 0b001 && funct3 != 0b010) ||
+      if ((funct3 != 0b001 && funct3 != 0b010 && funct3 != 0b011) ||
           (csr != 0x001 && csr != 0x002 && csr != 0x003)) {
-         /* Invalid CSRR{W,S}, fall through. */
+         /* Invalid CSRR{W,S,C}, fall through. */
       } else {
          switch (csr) {
          case 0x001: {
@@ -3201,6 +3201,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                expr = binop(Iop_Or32, mkexpr(fcsr),
                             binop(Iop_And32, getIReg32(rs1), mkU32(0x1f)));
                break;
+            case 0b011:
+               expr = binop(Iop_And32, mkexpr(fcsr),
+                            unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
+                                                  mkU32(0x1f))));
+               break;
             default:
                vassert(0);
             }
@@ -3232,6 +3237,14 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                                   binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
                                   mkU8(5)));
                break;
+            case 0b011:
+               expr =
+                  binop(Iop_And32, mkexpr(fcsr),
+                        unop(Iop_Not32,
+                             binop(Iop_Shl32,
+                                   binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
+                                   mkU8(5))));
+               break;
             default:
                vassert(0);
             }
@@ -3254,6 +3267,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                expr = binop(Iop_Or32, mkexpr(fcsr),
                             binop(Iop_And32, getIReg32(rs1), mkU32(0xff)));
                break;
+            case 0b011:
+               expr = binop(Iop_And32, mkexpr(fcsr),
+                            unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
+                                                  mkU32(0xff))));
+               break;
             default:
                vassert(0);
             }
@@ -3272,6 +3290,9 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
          case 0b010:
             name = "csrrs";
             break;
+         case 0b011:
+            name = "csrrc";
+            break;
          default:
             vassert(0);
          }
diff --git a/none/tests/riscv64/csr.c b/none/tests/riscv64/csr.c
index 48c9482aaf..41360be6de 100644
--- a/none/tests/riscv64/csr.c
+++ b/none/tests/riscv64/csr.c
@@ -77,7 +77,38 @@ static void test_csr64_shared(void)
    TESTINST_1_1_CSR(4, "csrrs a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
 
    /* ----------------- csrrc rd, csr, rs1 ------------------ */
-   /* Not currently handled. */
+   /* fflags */
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x01, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x1f, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x1e, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x00, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, fflags, t6", 0x00, 0x01, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, fflags, a1", 0xff, 0x01, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, zero", 0xff, 0x00, a0, fcsr, zero);
+
+   /* frm */
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x1, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x7, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x6, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x0, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, frm, t6", 0x00, 0x1, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, frm, a1", 0xff, 0x1, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, zero", 0xff, 0x0, a0, fcsr, zero);
+
+   /* fcsr */
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0x01, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0xfe, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0x00, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, fcsr, t6", 0x00, 0x01, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, fcsr, a1", 0xff, 0x01, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
 
    /* -------------- csrrwi rd, csr, uimm[4:0] -------------- */
    /* Not currently handled. */
diff --git a/none/tests/riscv64/csr.stdout.exp b/none/tests/riscv64/csr.stdout.exp
index 679a6b9a15..e773e205ca 100644
--- a/none/tests/riscv64/csr.stdout.exp
+++ b/none/tests/riscv64/csr.stdout.exp
@@ -143,3 +143,75 @@ csrrs zero, fcsr, a1 ::
 csrrs a0, fcsr, zero ::
   inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
   output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x000000000000001f, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x000000000000001e, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000e1
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000ff
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, fflags, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, fflags, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000fe
+csrrc a0, fflags, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000ff
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000007, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000006, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x000000000000003f
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x00000000000000ff
+csrrc a0, frm, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, frm, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, frm, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000df
+csrrc a0, frm, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x00000000000000ff
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000fe, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x0000000000000001
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, fcsr, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, fcsr, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000fe
+csrrc a0, fcsr, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x00000000000000ff

[Valgrind-developers] [valgrind] riscv64: Merge decoding of csrrw and csrrs

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d18934dce36e0cedd86ad3650b2dc651e18beb39

commit d18934dce36e0cedd86ad3650b2dc651e18beb39
Author: Petr Pavlu <pet...@da...>
Date:   Tue Jul 2 20:56:46 2024 +0000

    riscv64: Merge decoding of csrrw and csrrs

Diff:
---
 VEX/priv/guest_riscv64_toIR.c | 135 +++++++++++++++++++++---------------------
 1 file changed, 66 insertions(+), 69 deletions(-)

diff --git a/VEX/priv/guest_riscv64_toIR.c b/VEX/priv/guest_riscv64_toIR.c
index e76a602a0d..1c8a845e82 100644
--- a/VEX/priv/guest_riscv64_toIR.c
+++ b/VEX/priv/guest_riscv64_toIR.c
@@ -3170,13 +3170,15 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
 {
    /* ------------ RV64Zicsr standard extension ------------- */
 
-   /* ----------------- csrrw rd, csr, rs1 ------------------ */
-   if (INSN(6, 0) == 0b1110011 && INSN(14, 12) == 0b001) {
-      UInt rd  = INSN(11, 7);
-      UInt rs1 = INSN(19, 15);
-      UInt csr = INSN(31, 20);
-      if (csr != 0x001 && csr != 0x002 && csr != 0x003) {
-         /* Invalid CSRRW, fall through. */
+   /* --------------- csrr{w,s} rd, csr, rs1 ---------------- */
+   if (INSN(6, 0) == 0b1110011) {
+      UInt rd     = INSN(11, 7);
+      UInt funct3 = INSN(14, 12);
+      UInt rs1    = INSN(19, 15);
+      UInt csr    = INSN(31, 20);
+      if ((funct3 != 0b001 && funct3 != 0b010) ||
+          (csr != 0x001 && csr != 0x002 && csr != 0x003)) {
+         /* Invalid CSRR{W,S}, fall through. */
       } else {
          switch (csr) {
          case 0x001: {
@@ -3187,10 +3189,22 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                putIReg64(irsb, rd,
                          unop(Iop_32Uto64,
                               binop(Iop_And32, mkexpr(fcsr), mkU32(0x1f))));
-            putFCSR(irsb,
-                    binop(Iop_Or32,
-                          binop(Iop_And32, mkexpr(fcsr), mkU32(0xffffffe0)),
-                          binop(Iop_And32, getIReg32(rs1), mkU32(0x1f))));
+
+            IRExpr* expr;
+            switch (funct3) {
+            case 0b001:
+               expr = binop(Iop_Or32,
+                            binop(Iop_And32, mkexpr(fcsr), mkU32(0xffffffe0)),
+                            binop(Iop_And32, getIReg32(rs1), mkU32(0x1f)));
+               break;
+            case 0b010:
+               expr = binop(Iop_Or32, mkexpr(fcsr),
+                            binop(Iop_And32, getIReg32(rs1), mkU32(0x1f)));
+               break;
+            default:
+               vassert(0);
+            }
+            putFCSR(irsb, expr);
             break;
          }
          case 0x002: {
@@ -3203,12 +3217,25 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                   unop(Iop_32Uto64,
                        binop(Iop_And32, binop(Iop_Shr32, mkexpr(fcsr), mkU8(5)),
                              mkU32(0x7))));
-            putFCSR(irsb,
-                    binop(Iop_Or32,
-                          binop(Iop_And32, mkexpr(fcsr), mkU32(0xffffff1f)),
-                          binop(Iop_Shl32,
-                                binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
-                                mkU8(5))));
+
+            IRExpr* expr;
+            switch (funct3) {
+            case 0b001:
+               expr = binop(
+                  Iop_Or32, binop(Iop_And32, mkexpr(fcsr), mkU32(0xffffff1f)),
+                  binop(Iop_Shl32, binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
+                        mkU8(5)));
+               break;
+            case 0b010:
+               expr = binop(Iop_Or32, mkexpr(fcsr),
+                            binop(Iop_Shl32,
+                                  binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
+                                  mkU8(5)));
+               break;
+            default:
+               vassert(0);
+            }
+            putFCSR(irsb, expr);
             break;
          }
          case 0x003: {
@@ -3217,69 +3244,39 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
             assign(irsb, fcsr, getFCSR());
             if (rd != 0)
                putIReg64(irsb, rd, unop(Iop_32Uto64, mkexpr(fcsr)));
-            putFCSR(irsb, binop(Iop_And32, getIReg32(rs1), mkU32(0xff)));
+
+            IRExpr* expr;
+            switch (funct3) {
+            case 0b001:
+               expr = binop(Iop_And32, getIReg32(rs1), mkU32(0xff));
+               break;
+            case 0b010:
+               expr = binop(Iop_Or32, mkexpr(fcsr),
+                            binop(Iop_And32, getIReg32(rs1), mkU32(0xff)));
+               break;
+            default:
+               vassert(0);
+            }
+            putFCSR(irsb, expr);
             break;
          }
          default:
             vassert(0);
          }
-         DIP("csrrs %s, %s, %s\n", nameIReg(rd), nameCSR(csr), nameIReg(rs1));
-         return True;
-      }
-   }
 
-   /* ----------------- csrrs rd, csr, rs1 ------------------ */
-   if (INSN(6, 0) == 0b1110011 && INSN(14, 12) == 0b010) {
-      UInt rd  = INSN(11, 7);
-      UInt rs1 = INSN(19, 15);
-      UInt csr = INSN(31, 20);
-      if (csr != 0x001 && csr != 0x002 && csr != 0x003) {
-         /* Invalid CSRRS, fall through. */
-      } else {
-         switch (csr) {
-         case 0x001: {
-            /* fflags */
-            IRTemp fcsr = newTemp(irsb, Ity_I32);
-            assign(irsb, fcsr, getFCSR());
-            if (rd != 0)
-               putIReg64(irsb, rd,
-                         unop(Iop_32Uto64,
-                              binop(Iop_And32, mkexpr(fcsr), mkU32(0x1f))));
-            putFCSR(irsb, binop(Iop_Or32, mkexpr(fcsr),
-                                binop(Iop_And32, getIReg32(rs1), mkU32(0x1f))));
-            break;
-         }
-         case 0x002: {
-            /* frm */
-            IRTemp fcsr = newTemp(irsb, Ity_I32);
-            assign(irsb, fcsr, getFCSR());
-            if (rd != 0)
-               putIReg64(
-                  irsb, rd,
-                  unop(Iop_32Uto64,
-                       binop(Iop_And32, binop(Iop_Shr32, mkexpr(fcsr), mkU8(5)),
-                             mkU32(0x7))));
-            putFCSR(irsb,
-                    binop(Iop_Or32, mkexpr(fcsr),
-                          binop(Iop_Shl32,
-                                binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
-                                mkU8(5))));
+         const HChar* name;
+         switch (funct3) {
+         case 0b001:
+            name = "csrrw";
             break;
-         }
-         case 0x003: {
-            /* fcsr */
-            IRTemp fcsr = newTemp(irsb, Ity_I32);
-            assign(irsb, fcsr, getFCSR());
-            if (rd != 0)
-               putIReg64(irsb, rd, unop(Iop_32Uto64, mkexpr(fcsr)));
-            putFCSR(irsb, binop(Iop_Or32, mkexpr(fcsr),
-                                binop(Iop_And32, getIReg32(rs1), mkU32(0xff))));
+         case 0b010:
+            name = "csrrs";
             break;
-         }
          default:
             vassert(0);
          }
-         DIP("csrrs %s, %s, %s\n", nameIReg(rd), nameCSR(csr), nameIReg(rs1));
+         DIP("%s %s, %s, %s\n", name, nameIReg(rd), nameCSR(csr),
+             nameIReg(rs1));
          return True;
       }
    }

[Valgrind-developers] [valgrind] riscv64: Fix tests compilation with newer GNU as

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=95a3c692dc0ff48a915f152436d20e4170dd11f6

commit 95a3c692dc0ff48a915f152436d20e4170dd11f6
Author: Petr Pavlu <pet...@da...>
Date:   Wed May 15 20:55:08 2024 +0000

    riscv64: Fix tests compilation with newer GNU as
    
    Simplify the test macro JMP_COND() and avoid its use of 'la zero,0'
    which is newly rejected by GNU as.

Diff:
---
 none/tests/riscv64/testinst.h | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/none/tests/riscv64/testinst.h b/none/tests/riscv64/testinst.h
index aa4a250bc9..2f087d8b71 100644
--- a/none/tests/riscv64/testinst.h
+++ b/none/tests/riscv64/testinst.h
@@ -494,24 +494,27 @@ static void show_block_diff(unsigned char* block1,
 
 #define JMP_COND(length, instruction, rs1_val, rs2_val, rs1, rs2)              \
    {                                                                           \
-      unsigned long w[3 /*out*/ + 2 /*spill*/] = {0, 0, 0, 0, 0};              \
+      unsigned long w[3 /*out*/ + 2 /*in*/ + 2 /*spill*/] = {                  \
+         0, 0, 0, (unsigned long)rs1_val, (unsigned long)rs2_val, 0, 0};       \
       /* w[0] = flag that the branch was taken                                 \
          w[1] = flag that rs1 is valid                                         \
          w[2] = flag that rs2 is valid                                         \
-         w[3] = spill slot for rs1                                             \
-         w[4] = spill slot for rs2                                             \
+         w[3] = input rs1 value                                                \
+         w[4] = input rs2 value                                                \
+         w[5] = spill slot for rs1                                             \
+         w[6] = spill slot for rs2                                             \
        */                                                                      \
       register unsigned long* t1 asm("t1") = w;                                \
       __asm__ __volatile__(                                                    \
          "li t2, 1;"                                                           \
          "sd t2, 0(%[w]);"             /* Set result to "taken". */            \
          ".if \"" #rs1 "\" != \"unused\";"                                     \
-         "sd " #rs1 ", 24(%[w]);"      /* Spill rs1. */                        \
-         "la " #rs1 ", " rs1_val ";"   /* Load the first input. */             \
+         "sd " #rs1 ", 40(%[w]);"      /* Spill rs1. */                        \
+         "ld " #rs1 ", 24(%[w]);"      /* Load the first input. */             \
          ".endif;"                                                             \
          ".if \"" #rs2 "\" != \"unused\";"                                     \
-         "sd " #rs2 ", 32(%[w]);"      /* Spill rs2. */                        \
-         "la " #rs2 ", " rs2_val ";"   /* Load the second input. */            \
+         "sd " #rs2 ", 48(%[w]);"      /* Spill rs2. */                        \
+         "ld " #rs2 ", 32(%[w]);"      /* Load the second input. */            \
          ".endif;"                                                             \
          ASMINST_##length(instruction) ";"                                     \
          "li t2, 0;"                                                           \
@@ -526,29 +529,29 @@ static void show_block_diff(unsigned char* block1,
          "sd t2, 16(%[w]);"            /* Flag that rs2 is valid. */           \
          ".endif;"                                                             \
          ".if \"" #rs1 "\" != \"unused\";"                                     \
-         "ld " #rs1 ", 24(%[w]);"      /* Reload rs1. */                       \
+         "ld " #rs1 ", 40(%[w]);"      /* Reload rs1. */                       \
          ".endif;"                                                             \
          ".if \"" #rs2 "\" != \"unused\";"                                     \
-         "ld " #rs2 ", 32(%[w]);"      /* Reload rs2. */                       \
+         "ld " #rs2 ", 48(%[w]);"      /* Reload rs2. */                       \
          ".endif;"                                                             \
          :                                                                     \
          : [w] "r"(t1)                                                         \
          : "t2", "memory");                                                    \
       printf("%s ::\n", instruction);                                          \
       if (w[1] != 0) { /* If rs1 is valid. */                                  \
-         printf("  inputs: %s=%s", #rs1, rs1_val);                             \
+         printf("  inputs: %s=%d", #rs1, rs1_val);                             \
          if (w[2] != 0) /* If rs2 is valid. */                                 \
-            printf(", %s=%s", #rs2, rs2_val);                                  \
+            printf(", %s=%d", #rs2, rs2_val);                                  \
          printf("\n");                                                         \
       }                                                                        \
       printf("  branch: %s\n", w[0] ? "taken" : "not taken");                  \
    }
 
 #define TESTINST_0_1_BxxZ_COND(length, instruction, rs1_val, rs1)              \
-   JMP_COND(length, instruction, #rs1_val, "0", rs1, unused)
+   JMP_COND(length, instruction, rs1_val, 0, rs1, unused)
 
 #define TESTINST_0_2_Bxx_COND(length, instruction, rs1_val, rs2_val, rs1, rs2) \
-   JMP_COND(length, instruction, #rs1_val, #rs2_val, rs1, rs2)
+   JMP_COND(length, instruction, rs1_val, rs2_val, rs1, rs2)
 
 #define TYPED_X_X(length, instruction, rs1_val, fcsr_val, rd, rs1, dpre, spre) \
    {                                                                           \

[Valgrind-developers] [valgrind] Update NEWS for RISCV64/Linux and --modify-fds=[no|high] option

[Mark W. <ma...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f7331e8efd0ba2a17eb29dd67b8808c8a5941203

commit f7331e8efd0ba2a17eb29dd67b8808c8a5941203
Author: Mark Wielaard <ma...@kl...>
Date:   Wed Apr 23 19:33:26 2025 +0200

    Update NEWS for RISCV64/Linux and --modify-fds=[no|high] option
    
    As a little description plus the two bugs (468575 and 493433) to the
    bug list.

Diff:
---
 NEWS | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/NEWS b/NEWS
index e5be7f53a9..ad666f15cb 100644
--- a/NEWS
+++ b/NEWS
@@ -3,10 +3,10 @@ Release 3.25.0.RC1 (18 Apr 2025)
 
 This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
 PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,
-MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android,
-X86/Solaris, AMD64/Solaris, AMD64/MacOSX 10.12, X86/FreeBSD, AMD64/FreeBSD
-and ARM64/FreeBSD  There is also preliminary support for X86/macOS 10.13,
-AMD64/macOS 10.13 and nanoMIPS/Linux.
+MIPS64/Linux, RISCV64/Linux, ARM/Android, ARM64/Android, MIPS32/Android,
+X86/Android, X86/Solaris, AMD64/Solaris, AMD64/MacOSX 10.12, X86/FreeBSD,
+AMD64/FreeBSD and ARM64/FreeBSD There is also preliminary support for
+X86/macOS 10.13, AMD64/macOS 10.13 and nanoMIPS/Linux.
 
 * ==================== CORE CHANGES ===================
 
@@ -16,6 +16,9 @@ AMD64/macOS 10.13 and nanoMIPS/Linux.
 
 * ================== PLATFORM CHANGES =================
 
+* Added RISCV64 support for Linux. Specifically for the RV64GC
+  instruction set.
+
 * Numerous bug fixes for Illumos, in particular fixed a Valgrind crash
   whenever a signal handler was called.
 
@@ -32,6 +35,13 @@ AMD64/macOS 10.13 and nanoMIPS/Linux.
   And when the stdin/out/err descriptors are reassigned they are
   now treated as normal (non-inherited) file descriptors.
 
+* A new option --modify-fds=high can be used together with
+  --track-fds=yes to create new file descriptors with the highest
+  possible number (and then decreasing) instead of always using the
+  lowest possible number (which is required by POSIX). This will help
+  catch issues where a file descriptor number might normally be reused
+  between a close and another open call.
+
 * Helgrind:
   There is a change to warnings about calls to pthread_cond_signal and
   pthread_cond_broadcast when the associated mutex is unlocked. Previously
@@ -53,10 +63,12 @@ are not entered into bugzilla tend to get forgotten about or ignored.
 290061  pie elf always loaded at 0x108000
 396415  Valgrind is not looking up $ORIGIN rpath of shebang programs
 420682  io_pgetevents is not supported
+468575  Add support for RISC-V
 469782  Valgrind does not support zstd-compressed debug sections
 487296  --track-fds=yes and --track-fds=all report erroneous information
         when fds 0, 1, or 2 are used as non-std
 489913  WARNING: unhandled amd64-linux syscall: 444 (landlock_create_ruleset)
+493433  Add --modify-fds=[no|high] option
 494246  syscall fsopen not wrapped
 494327  Crash when running Helgrind built with #define TRACE_PTH_FNS 1
 494337  All threaded applications cause still holding lock errors

[Valgrind-developers] [valgrind] s390x only: Clean up unused Ijk_... values

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b44d61f5b63f1330cbca0ffd6294991979d370e9

commit b44d61f5b63f1330cbca0ffd6294991979d370e9
Author: Florian Krohm <fl...@ei...>
Date:   Wed Apr 23 12:49:20 2025 +0000

    s390x only: Clean up unused Ijk_... values
    
    The following jump kinds were never assigned to any variable but were
    checked for in various contexts:
    
    - Ijk_MapFail
    - Ijk_SigTRAP
    - Ijk_SigSEGV
    - Ijk_SigBUS
    
    Tighten that up.

Diff:
---
 VEX/priv/host_s390_defs.c | 7 -------
 VEX/priv/host_s390_isel.c | 2 --
 2 files changed, 9 deletions(-)

diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index 3cf1cbd3a0..e26ea09d48 100644
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -7572,13 +7572,9 @@ s390_jump_kind_as_string(IRJumpKind kind)
    case Ijk_EmWarn:      return "EmWarn";
    case Ijk_EmFail:      return "EmFail";
    case Ijk_NoDecode:    return "NoDecode";
-   case Ijk_MapFail:     return "MapFail";
    case Ijk_InvalICache: return "Invalidate";
    case Ijk_NoRedir:     return "NoRedir";
-   case Ijk_SigTRAP:     return "SigTRAP";
    case Ijk_SigFPE:      return "SigFPE";
-   case Ijk_SigSEGV:     return "SigSEGV";
-   case Ijk_SigBUS:      return "SigBUS";
    case Ijk_Sys_syscall: return "Sys_syscall";
    case Ijk_Extension:   return "Extension";
    default:
@@ -11300,13 +11296,10 @@ s390_insn_xassisted_emit(UChar *buf, const s390_insn *insn,
    case Ijk_Yield:       trcval = VEX_TRC_JMP_YIELD;       break;
    case Ijk_EmWarn:      trcval = VEX_TRC_JMP_EMWARN;      break;
    case Ijk_EmFail:      trcval = VEX_TRC_JMP_EMFAIL;      break;
-   case Ijk_MapFail:     trcval = VEX_TRC_JMP_MAPFAIL;     break;
    case Ijk_NoDecode:    trcval = VEX_TRC_JMP_NODECODE;    break;
    case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
    case Ijk_NoRedir:     trcval = VEX_TRC_JMP_NOREDIR;     break;
-   case Ijk_SigTRAP:     trcval = VEX_TRC_JMP_SIGTRAP;     break;
    case Ijk_SigFPE:      trcval = VEX_TRC_JMP_SIGFPE;      break;
-   case Ijk_SigSEGV:     trcval = VEX_TRC_JMP_SIGSEGV;     break;
    case Ijk_Boring:      trcval = VEX_TRC_JMP_BORING;      break;
       /* We don't expect to see the following being assisted. */
    case Ijk_Ret:
diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c
index 10aebf73f0..2b075c9300 100644
--- a/VEX/priv/host_s390_isel.c
+++ b/VEX/priv/host_s390_isel.c
@@ -5365,7 +5365,6 @@ no_memcpy_put:
       case Ijk_ClientReq:
       case Ijk_NoRedir:
       case Ijk_Yield:
-      case Ijk_SigTRAP:
       case Ijk_SigFPE: {
          HReg dst = s390_isel_int_expr(env, IRExpr_Const(stmt->Ist.Exit.dst));
          addInstr(env, s390_insn_xassisted(cond, dst, guest_IA,
@@ -5482,7 +5481,6 @@ iselNext(ISelEnv *env, IRExpr *next, IRJumpKind jk, Int offsIP)
    case Ijk_ClientReq:
    case Ijk_NoRedir:
    case Ijk_Yield:
-   case Ijk_SigTRAP:
    case Ijk_SigFPE: {
       HReg dst = s390_isel_int_expr(env, next);
       addInstr(env, s390_insn_xassisted(S390_CC_ALWAYS, dst, guest_IA, jk));

[Valgrind-developers] [valgrind] s390x: Fix a comment

[Florian K. <fk...@so...>]

https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3ddf7065ec36f49307ed7111eb7c5c3c766af273

commit 3ddf7065ec36f49307ed7111eb7c5c3c766af273
Author: Florian Krohm <fl...@ei...>
Date:   Wed Apr 23 11:37:40 2025 +0000

    s390x: Fix a comment

Diff:
---
 VEX/priv/host_s390_defs.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index b7b2f25207..3cf1cbd3a0 100644
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -457,7 +457,9 @@ getRRegUniverse_S390(void)
              registers 0..7 are caller saved, list them after
              FPR12 - FPR15 are also used as register pairs for 128-bit
              floating point operations
-      VRs:   registers 0..31 are available
+      VRs:   registers 16..31 are available
+             registers 0..15 are not available because they overlap
+             with FPRs 0..15
    */
    ru->allocable_start[HRcInt64] = ru->size;
    for (UInt regno = 6; regno <= 11; ++regno) {

[Valgrind-developers] Sourceware infrastructure updates for Q1 2025

[Mark W. <ma...@kl...>]

Sourceware infrastructure community updates for Q1 2025

Sourceware has provided the infrastructure for core toolchain
and developer tools projects for more than 25 years.
https://sourceware.org/sourceware-25-roadmap.html

Over the last couple of years, Sourceware has transformed from a
purely volunteer into a professional organization with an eight person
strong Project Leadership Committee, monthly open office hours,
multiple hardware services partners, expanded services, the Software
Freedom Conservancy as fiscal sponsor and a more diverse funding model
that allows us to enter into contracts with paid contractors or staff
when appropriate.

Every quarter we provide a summary of news about Sourceware, the core
toolchain and developer tools infrastructure, covering the previous 3
months.

- Sourceware Survey 2025
- Cyber Security update and secure project policy checklist
- AI/LLM scraperbots attacks and Anubis
- New RISC-V CI builders
- Q3 server moves
- Signed-commit census report
- Sourceware Organization, Contact and Open Office hours

= Sourceware Survey 2025

  The survey ran from Friday, 14 March to Monday, 31 March. In the end
  we got 103 (!) responses with a nice mix of developers, users and
  maintainers from various hosted projects.

  Full results can be found at https://sourceware.org/survey-2025

  Thanks to everybody who responded, this will help guide the PLC
  allocate resources.

= Cyber Security update and secure project policy checklist

  Thanks to all the input during some of the Sourceware Open Office
  hours earlier this year, feedback given at Fosdem and discussions
  with the Software Freedom Conservancy we have update the Sourceware
  Cyber Security FAQ (really an explainer) with updates to the current
  state of the US Improving the Nation's Cybersecurity Executive Order
  and EU Cyber Resilience Act.

  We also added a section with Recommendations for Sourceware hosted
  projects.

  https://sourceware.org/cyber-security-faq.html

  For Sourceware hosted projects that want to have a documented
  verifiable cybersecurity policy we now have a policy checklist your
  project can follow. Most are common sense things most projects
  already do.
  https://sourceware.org/cyber-security-faq.html#policy-checklist

  Also check out the Sourceware infrastructure security vision and
  sourceware security posture:
  https://sourceware.org/sourceware-security-vision.html
  https://sourceware.org/sourceware-wiki/sourceware_security_posture/

= AI/LLM scraperbots attacks and Anubis

  As some of you might have noticed Sourceware has been fighting the
  new AI/LLM scraperbots since start of the year. We are not alone in
  this.

  https://lwn.net/Articles/1008897/
  https://arstechnica.com/ai/2025/03/devs-say-ai-crawlers-dominate-traffic-forcing-blocks-on-entire-countries/

  We have tried to isolate services more and block various ip-blocks
  that were abusing the servers. But that has helped only so much.
  Unfortunately the scraper bots are using lots of ip addresses
  (probably by installing "free" VPN services that use normal user
  connections as exit point) and pretending to be common
  browsers/agents.  We seem to have to make access to some services
  depend on solving a javascript challenge.

  So when using https://patchwork.sourceware.org or Bunsen
  https://builder.sourceware.org/testruns/ you might now have to
  enable javascript.  This should not impact any scripts, just
  browsers (or bots pretending to be browsers).  If it does cause
  trouble, please let us know.  If this works out we might also
  "protect" bugzilla, gitweb, cgit, and the wikis this way.

  Thanks Xe Iaso who has helped us set this up.
  Please check out if you want to be one of their patrons as thank you.
  https://xeiaso.net/notes/2025/anubis-works/
  https://xeiaso.net/patrons/

= New RISC-V CI builders

  Thanks to RISC-V International we got 3 new buildbot CI workers.
  One HiFive Premier P550
  https://www.sifive.com/boards/hifive-premier-p550
  and two Banana Pi BPI-F3
  https://wiki.banana-pi.org/Banana_Pi_BPI-F3

  They have been used for testing the Valgrind risc-v backend that
  will be introduced with Valgrind 3.25.0 later this month.

  The P550 now runs a gdb and full testsuite build. One bpi-f3 runs
  glibc and the full testsuite. The other bpi-f3 runs a gcc bootstrap
  and full testsuite the bpi-f3 has an 8 core SpacemiT K1 supporting
  rvv 1.0.

  Unfortunately we had to shut down the Pioneer box, which was faster
  than the above machines, but just overheated too often and then
  needed manual intervention.

= Q3 server moves

  Somewhere in Q3 the Red Hat community cage, which hosts two of our
  servers, will move to another data center
  https://www.osci.io/tenants/

  We don't know the precise date yet. Please contact us ASAP if there
  is a specific date where your project really cannot tolerate any
  down time. The data centers are not too far apart and we hope any
  downtime will be no more than 24 to 48 hours.

  The PLC is currently discussing if we can take advantage of this
  move by adding more machines, which might be installed in the new
  data center before the move. Which might help make any downtime as
  short as possible. And would help with our goals to isolate more
  services on separate machines.

= Signed-commit census report

  Analyzing branch HEAD since 2025-01-01
  annobin        25 commits  25 signed 100%   1 committers 1 signers 100%
  binutils-gdb 1296 commits  40 signed   3%  64 committers 4 signers   6%
  builder        35 commits  16 signed  45%   4 committers 3 signers  75%
  bunsen        118 commits  91 signed  77%   2 committers 2 signers 100%
  cygwin-calm    12 commits  12 signed 100%   1 committers 1 signers 100%
  cygwin-setup    4 commits   4 signed 100%   1 committers 1 signers 100%
  debugedit       5 commits   0 signed   0%   1 committers 0 signers   0%
  elfutils       53 commits   3 signed   5%   3 committers 1 signers  33%
  forge           6 commits   0 signed   0%   1 committers 0 signers   0%
  gcc          3125 commits 223 signed   7% 122 committers 9 signers   7%
  gitsigur        5 commits   5 signed 100%   1 committers 1 signers 100%
  glibc         449 commits  36 signed   8%  31 committers 2 signers   6%
  insight        18 commits   0 signed   0%   1 committers 0 signers   0%
  libabigail     49 commits   0 signed   0%   1 committers 0 signers   0%
  lvm2          232 commits  21 signed   9%   5 committers 1 signers  20%
  newlib-cygwin 220 commits   9 signed   4%  10 committers 2 signers  20%
  systemtap      37 commits  31 signed  83%   2 committers 1 signers  50%
  valgrind      171 commits   0 signed   0%   5 committers 0 signers   0%

= Sourceware Organization, Contact and Open Office hours

  We can be reached through irc, email and bugzilla
  https://sourceware.org/mission.html#organization

  There is also a fediverse account for for announcements, notices
  about downtime and temporary issues with our network.
  https://fosstodon.org/@sourceware

  Every second Friday of the month is the Sourceware Overseers Open
  Office hour in #overseers on irc.libera.chat from 16:00 till 17:00
  UTC. Please feel free to drop by with any Sourceware services and
  hosting questions.

  If you aren't already and want to keep up to date on Sourceware
  infrastructure services then please also subscribe to the overseers
  mailinglist. https://sourceware.org/mailman/listinfo/overseers

  Please see https://sourceware.org/donate.html if you want to
  financially support Sourceware.

Sourceware PLC,

 Frank Ch. Eigler, Christopher Faylor, Ian Kelling, Ian Lance Taylor,
 Tom Tromey, Jon Turney, Mark J. Wielaard, Elena Zannoni

Re: [Valgrind-developers] Valgrind-3.25.0.RC1 is available for testing

[Florian K. <fl...@ei...>]

Hi Mark,

On 22.04.25 18:37, Mark Wielaard wrote:
> 
> I assume most of the failures are missing syscall wrappers? On my
> x86_64 setup I got 66 FAILs, full log here:
> https://bugsfiles.kde.org/attachment.cgi?id=180366
> 

Yep, most of the failures are due to missing syscall wrappers. Also 5 SIGSEGV 
and one assertion failure as well as unsupported clone flags, fcntl stuff.

Cheers,
    Florian