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From: Josef W. <Jos...@gm...> - 2004-06-02 14:41:26
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On Wednesday 02 June 2004 15:56, Nicholas Nethercote wrote: > I think fixing it by changing Valgrind's core (ie. modifying BB layout) > is a bad idea -- I don't want to introduce nasty special cases into the > core just so Cachegrind can handle REP prefixes slightly more cleanly. Of course. The correction scheme I proposed seems the best one here, but I don't care if the special handling is removed (and would apply it to calltree as well). As you said: there are a few other minor shortcomings. > > Yes, perhaps that's the easiest: I don't think this JIFZ special case > > makes any big differences in the result anyway. Have you done any > > experiments regarding REP prefixes and the results from real hardware > > counters for "instructions retired"? > > No. And if we meassure, this is for sure processor specific... > (I found another inaccuracy in the simulation today -- CMPS does two data > accesses but Cachegrind only treats it as one. Again, only minor...) And the common coding sequence call x x: pop ax to get the instruction pointer is attributed with 1 instruction fetch only, as it is recoded in valgrind core as a register move. Josef |