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From: Sebastian K. <Seb...@so...> - 2004-06-15 10:19:42
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ozgun erdogan wrote: > >> Only 27%!? That's really bad, especially if its L2 -- remember that >> an L2 >> miss can cost 100s of cycles (206 in the worst case on my Athlon). > > > Is there a website (paper) that summarizes the cost of cache misses? You can measure it yourself. For example this little tool (made by a bunch of benchmark guys incl. me): http://www.sf.net/projects/later will tell you memory latency in ns (translating nanoseconds to cpu cycles is easy) with about 5-10% accuracy (run it as a user who has rioght to up process the priority). > I've read a paper that says the cost of accessing the memory is around > 15 CPU cyles... It must be 15-20 years old. Today it's around 100-120 cycles min. on Athnlon 64 and about 200-300 on Pentium 4. Those are good to best cases. In bad case, when TLB miss occurs multiple those numbers by 3. -- Sebastian Kaliszewski |