[Valgrind-developers] Absolutely mystifying problem with fxrstor

[Julian S. <js...@ac...>]

Hi

I wonder if anyone can cast any light on the following.  I am
completely mystified, not to mention stuck.

I'm doing stuff to add SSE/SSE2 support.  This means changing various
fsave/frstor instructions, which move the FPU state back and forth
between the simulated and real cpus, into their SSE equivalents,
fxsave and fxrstor.  The SSE state is larger than the FPU/MMX 
state so various structures have had their size increased.
There is also a 16-byte alignment constraint on addresses in
fxsave/fxrstor, so I've ensured that too.

Now, I think I've done everything right.  Nevertheless, one
of my fxrstor's, in vg_syscalls.S, is segfaulting.  I have no
idea why.  It's this

	fxrstor	VG_(m_state_static)+64

(previously of course)

	frstor	VG_(m_state_static)+64

and the address is duly 16-byte aligned, and the memory from
that address for 512 bytes (the SSE state size) appears
suitably accessible.  A few lines earlier there is

	fxrstor	VG_(real_sse_state_saved_over_syscall)

and that works fine.

Help!  I'm stuck.  Is there some other magic constraints on
fxrstor I need to know about?  I read the fine print in the P4
documentation carefully, but I cannot see anything other than the
16-byte-alignment constraint.

J