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From: Joerg B. <jo...@we...> - 2003-07-28 09:54:12
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Vincent Penquerc'h wrote: >>OK, so an implementation to do cycle counting needs to have >>a table that lists for every instruction how many cycles it >>need for the different cache-hit/miss situations. >> >>Are these informations available (for all the processors)? > > > Yes, but there is an awful lot of possible combinations. That what are the conditions? Is it this or more? * L1 Hit, L2 hit, Cache Miss * branch prediction was true, false and this all per instruction, per processor. > would be nifty to try out a piece of time critical code on > various architectures to see how it fares, since one would > usually optimize for one's dev machine... > I thought that the assumptions "all instructions will take the same amount of time", but you tould me that this is to easy :-) Joerg |