Re: [Valgrind-developers] [RFC 00/12] RISC-V Vector support for Valgrind

[Wu, F. <fe...@in...>]

On 5/28/2023 1:11 AM, Petr Pavlu wrote:
> On 26. May 23 21:59, Fei Wu wrote:
>> I'm from Intel RISC-V team and working on a RISC-V International
>> development partner project to add RISC-V vector (RVV) support on 
>> Valgrind, the target tool is memcheck. My work bases on commit
>> 71272b252977 of Petr's riscv64-linux branch, many thanks to Petr for his
>> great work first.
>>     https://github.com/petrpavlu/valgrind-riscv64
>>
>> This RFC is a starting point of RVV support on Valgrind, It's far from
>> complete, which will take huge time, but I do think it's more effective
>> to have some real code for discussion, so this series adds the RVV
>> support to run memcpy/strcmp/strcpy/strlen/strncpy in:
>>     https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/examples
>>
>> The whole idea is splitting the vector instructions into scalar
>> instructions which have already been well supported on Petr's branch,
>> the correctness of binary translation (tool=none) is simple to ensure,
>> but the logic of tool=memcheck should not be broken, one of the keys is
>> to deal with the instructions with mask:
>>
>> [...]
>>
>> At last, if the performance is tolerable, is this the right way to go?
> 
> Have you seen the recent mail about RVV to this list from Jojo [1]? It
> has some discussion on breaking vector operations down to scalars too.
> 
Thank you for pointing it out, it's a nice writeup, now I subscribed the
mailing list in order to capture all the traffics.

> It seems you are both looking at the same topic. It would be good if you
> can cooperate on this, if that is not already the case.
> 
Agreed, I will sync up with him.

Thanks,
Fei.

> [1] https://sourceforge.net/p/valgrind/mailman/valgrind-developers/thread/84b7a55c-1868-ca14-2626-ffb88925741a%40linux.alibaba.com/
> 
> Thanks,
> Petr