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[Valgrind-developers] [RFC 06/12] riscv64: Add cpu_state to TB
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From: Fei Wu <fe...@in...> - 2023-05-26 13:57:49
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During translation to IR, the states such guest vl and vtype are
referenced directly, add them to cpu_state to differentiate the same
guest code with different cpu_state.
Signed-off-by: Fei Wu <fe...@in...>
---
VEX/pub/libvex_guest_riscv64.h | 9 +++++++++
coregrind/m_scheduler/scheduler.c | 17 +++++++++++++----
coregrind/m_translate.c | 3 +++
coregrind/m_transtab.c | 26 ++++++++++++++++++++++++--
coregrind/pub_core_transtab.h | 5 +++++
5 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/VEX/pub/libvex_guest_riscv64.h b/VEX/pub/libvex_guest_riscv64.h
index 50bec58bd..36149bbf2 100644
--- a/VEX/pub/libvex_guest_riscv64.h
+++ b/VEX/pub/libvex_guest_riscv64.h
@@ -177,6 +177,15 @@ typedef struct {
/* Initialise all guest riscv64 state. */
void LibVEX_GuestRISCV64_initialise(/*OUT*/ VexGuestRISCV64State* vex_state);
+static inline ULong get_cpu_state(VexGuestRISCV64State* guest)
+{
+#if defined(VGA_riscv64)
+ return guest->guest_vl | (guest->guest_vtype << 16);
+#else
+ return 0;
+#endif
+}
+
#endif /* ndef __LIBVEX_PUB_GUEST_RISCV64_H */
/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c
index 4e18c80fa..6d9a721c0 100644
--- a/coregrind/m_scheduler/scheduler.c
+++ b/coregrind/m_scheduler/scheduler.c
@@ -948,6 +948,8 @@ void run_thread_for_a_while ( /*OUT*/HWord* two_words,
do_pre_run_checks( tst );
/* end Paranoia */
+ ULong cpu_state = get_cpu_state(&tst->arch.vex);
+
/* Futz with the XIndir stats counters. */
vg_assert(VG_(stats__n_xIndirs_32) == 0);
vg_assert(VG_(stats__n_xIndir_hits1_32) == 0);
@@ -977,6 +979,7 @@ void run_thread_for_a_while ( /*OUT*/HWord* two_words,
to the scheduler. */
Bool found = VG_(search_transtab)(&res, NULL, NULL,
(Addr)tst->arch.vex.VG_INSTR_PTR,
+ cpu_state,
True/*upd cache*/
);
if (LIKELY(found)) {
@@ -1133,16 +1136,19 @@ static void handle_tt_miss ( ThreadId tid )
Bool found;
Addr ip = VG_(get_IP)(tid);
+ volatile ThreadState* tst = VG_(get_ThreadState)(tid);
+ ULong cpu_state = get_cpu_state(&tst->arch.vex);
+
/* Trivial event. Miss in the fast-cache. Do a full
lookup for it. */
found = VG_(search_transtab)( NULL, NULL, NULL,
- ip, True/*upd_fast_cache*/ );
+ ip, cpu_state, True/*upd_fast_cache*/ );
if (UNLIKELY(!found)) {
/* Not found; we need to request a translation. */
if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/,
bbs_done, True/*allow redirection*/ )) {
found = VG_(search_transtab)( NULL, NULL, NULL,
- ip, True );
+ ip, cpu_state, True );
vg_assert2(found, "handle_tt_miss: missing tt_fast entry");
} else {
@@ -1163,14 +1169,17 @@ void handle_chain_me ( ThreadId tid, void* place_to_chain, Bool toFastEP )
SECno to_sNo = INV_SNO;
TTEno to_tteNo = INV_TTE;
+ volatile ThreadState* tst = VG_(get_ThreadState)(tid);
+ ULong cpu_state = get_cpu_state(&tst->arch.vex);
+
found = VG_(search_transtab)( NULL, &to_sNo, &to_tteNo,
- ip, False/*dont_upd_fast_cache*/ );
+ ip, cpu_state, False/*dont_upd_fast_cache*/ );
if (!found) {
/* Not found; we need to request a translation. */
if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/,
bbs_done, True/*allow redirection*/ )) {
found = VG_(search_transtab)( NULL, &to_sNo, &to_tteNo,
- ip, False );
+ ip, cpu_state, False );
vg_assert2(found, "handle_chain_me: missing tt_fast entry");
} else {
// If VG_(translate)() fails, it's because it had to throw a
diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
index dc3c65814..cad9184b9 100644
--- a/coregrind/m_translate.c
+++ b/coregrind/m_translate.c
@@ -1510,6 +1510,7 @@ Bool VG_(translate) ( ThreadId tid,
VexTranslateArgs vta;
VexTranslateResult tres;
VgCallbackClosure closure;
+ ULong cpu_state = 0;
/* Make sure Vex is initialised right. */
@@ -1754,6 +1755,7 @@ Bool VG_(translate) ( ThreadId tid,
vex_abiinfo.guest__use_fallback_LLSC = True;
ThreadState *tst = VG_(get_ThreadState)(tid);
vex_abiinfo.riscv64_guest_state = &tst->arch.vex;
+ cpu_state = get_cpu_state(&tst->arch.vex);
# endif
/* Set up closure args. */
@@ -1868,6 +1870,7 @@ Bool VG_(translate) ( ThreadId tid,
// addr, which might have been changed by the redirection
VG_(add_to_transtab)( &vge,
nraddr,
+ cpu_state,
(Addr)(&tmpbuf[0]),
tmpbuf_used,
tres.n_sc_extents > 0,
diff --git a/coregrind/m_transtab.c b/coregrind/m_transtab.c
index 102108a35..06019efa1 100644
--- a/coregrind/m_transtab.c
+++ b/coregrind/m_transtab.c
@@ -192,6 +192,9 @@ typedef
may not be a lie, depending on whether or not we're doing
redirection. */
Addr entry;
+#ifdef VGA_riscv64
+ ULong cpu_state;
+#endif
/* Address range summary info: these are pointers back to
eclass[] entries in the containing Sector. Those entries in
@@ -1461,7 +1464,7 @@ static inline HTTno HASH_TT ( Addr key )
}
/* Invalidate the fast cache VG_(tt_fast). */
-static void invalidateFastCache ( void )
+void invalidateFastCache ( void )
{
for (UWord j = 0; j < VG_TT_FAST_SETS; j++) {
FastCacheSet* set = &VG_(tt_fast)[j];
@@ -1734,6 +1737,7 @@ static void initialiseSector ( SECno sno )
*/
void VG_(add_to_transtab)( const VexGuestExtents* vge,
Addr entry,
+ ULong cpu_state,
Addr code,
UInt code_len,
Bool is_self_checking,
@@ -1845,6 +1849,9 @@ void VG_(add_to_transtab)( const VexGuestExtents* vge,
(code_len == 0 ? 1 : (code_len / 4));
sectors[y].ttC[tteix].entry = entry;
+#ifdef VGA_riscv64
+ sectors[y].ttC[tteix].cpu_state = cpu_state;
+#endif
TTEntryH__from_VexGuestExtents( §ors[y].ttH[tteix], vge );
sectors[y].ttH[tteix].status = InUse;
@@ -1905,6 +1912,14 @@ void VG_(add_to_transtab)( const VexGuestExtents* vge,
upd_eclasses_after_add( §ors[y], tteix );
}
+static inline Bool cpu_state_match(TTEntryC* ttC, ULong cpu_state)
+{
+#ifdef VGA_riscv64
+ return ttC->cpu_state == cpu_state;
+#else
+ return True;
+#endif
+}
/* Search for the translation of the given guest address. If
requested, a successful search can also cause the fast-caches to be
@@ -1914,6 +1929,7 @@ Bool VG_(search_transtab) ( /*OUT*/Addr* res_hcode,
/*OUT*/SECno* res_sNo,
/*OUT*/TTEno* res_tteNo,
Addr guest_addr,
+ ULong cpu_state,
Bool upd_cache )
{
SECno i, sno;
@@ -1940,7 +1956,9 @@ Bool VG_(search_transtab) ( /*OUT*/Addr* res_hcode,
n_lookup_probes++;
tti = sectors[sno].htt[k];
if (tti < N_TTES_PER_SECTOR
- && sectors[sno].ttC[tti].entry == guest_addr) {
+ && sectors[sno].ttC[tti].entry == guest_addr
+ && cpu_state_match(§ors[sno].ttC[tti], cpu_state)
+ ) {
/* found it */
if (upd_cache)
setFastCacheEntry(
@@ -2553,7 +2571,11 @@ void VG_(init_tt_tc) ( void )
have a lot of TTEntryCs so let's check that too. */
if (sizeof(HWord) == 8) {
vg_assert(sizeof(TTEntryH) <= 32);
+#ifdef VGA_riscv64
+ vg_assert(sizeof(TTEntryC) <= 120);
+#else
vg_assert(sizeof(TTEntryC) <= 112);
+#endif
}
else if (sizeof(HWord) == 4) {
vg_assert(sizeof(TTEntryH) <= 20);
diff --git a/coregrind/pub_core_transtab.h b/coregrind/pub_core_transtab.h
index cc70a2944..b352891cf 100644
--- a/coregrind/pub_core_transtab.h
+++ b/coregrind/pub_core_transtab.h
@@ -171,6 +171,7 @@ extern void VG_(init_tt_tc) ( void );
extern
void VG_(add_to_transtab)( const VexGuestExtents* vge,
Addr entry,
+ ULong cpu_state,
Addr code,
UInt code_len,
Bool is_self_checking,
@@ -194,6 +195,7 @@ extern Bool VG_(search_transtab) ( /*OUT*/Addr* res_hcode,
/*OUT*/SECno* res_sNo,
/*OUT*/TTEno* res_tteNo,
Addr guest_addr,
+ ULong cpu_state,
Bool upd_cache );
extern void VG_(discard_translations) ( Addr start, ULong range,
@@ -216,6 +218,9 @@ extern
Bool VG_(search_unredir_transtab) ( /*OUT*/Addr* result,
Addr guest_addr );
+extern
+void invalidateFastCache ( void );
+
// SB profiling stuff
typedef struct _SBProfEntry {
--
2.25.1
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