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[Valgrind-developers] [RFC 01/12] riscv64: Starting Vector support, registers added
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From: Fei Wu <fe...@in...> - 2023-05-26 13:57:46
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Add v0-v31, vl and vtype
Signed-off-by: Fei Wu <fe...@in...>
---
VEX/priv/guest_riscv64_toIR.c | 135 +++++++++++++++++++++++++++++++++
VEX/pub/libvex_guest_riscv64.h | 38 +++++++++-
memcheck/mc_machine.c | 35 +++++++++
3 files changed, 207 insertions(+), 1 deletion(-)
diff --git a/VEX/priv/guest_riscv64_toIR.c b/VEX/priv/guest_riscv64_toIR.c
index 93ea5a173..423260679 100644
--- a/VEX/priv/guest_riscv64_toIR.c
+++ b/VEX/priv/guest_riscv64_toIR.c
@@ -289,6 +289,42 @@ static IRExpr* narrowFrom64(IRType dstTy, IRExpr* e)
#define OFFB_LLSC_ADDR offsetof(VexGuestRISCV64State, guest_LLSC_ADDR)
#define OFFB_LLSC_DATA offsetof(VexGuestRISCV64State, guest_LLSC_DATA)
+#define OFFB_V0 offsetof(VexGuestRISCV64State, guest_v0)
+#define OFFB_V1 offsetof(VexGuestRISCV64State, guest_v1)
+#define OFFB_V2 offsetof(VexGuestRISCV64State, guest_v2)
+#define OFFB_V3 offsetof(VexGuestRISCV64State, guest_v3)
+#define OFFB_V4 offsetof(VexGuestRISCV64State, guest_v4)
+#define OFFB_V5 offsetof(VexGuestRISCV64State, guest_v5)
+#define OFFB_V6 offsetof(VexGuestRISCV64State, guest_v6)
+#define OFFB_V7 offsetof(VexGuestRISCV64State, guest_v7)
+#define OFFB_V8 offsetof(VexGuestRISCV64State, guest_v8)
+#define OFFB_V9 offsetof(VexGuestRISCV64State, guest_v9)
+#define OFFB_V10 offsetof(VexGuestRISCV64State, guest_v10)
+#define OFFB_V11 offsetof(VexGuestRISCV64State, guest_v11)
+#define OFFB_V12 offsetof(VexGuestRISCV64State, guest_v12)
+#define OFFB_V13 offsetof(VexGuestRISCV64State, guest_v13)
+#define OFFB_V14 offsetof(VexGuestRISCV64State, guest_v14)
+#define OFFB_V15 offsetof(VexGuestRISCV64State, guest_v15)
+#define OFFB_V16 offsetof(VexGuestRISCV64State, guest_v16)
+#define OFFB_V17 offsetof(VexGuestRISCV64State, guest_v17)
+#define OFFB_V18 offsetof(VexGuestRISCV64State, guest_v18)
+#define OFFB_V19 offsetof(VexGuestRISCV64State, guest_v19)
+#define OFFB_V20 offsetof(VexGuestRISCV64State, guest_v20)
+#define OFFB_V21 offsetof(VexGuestRISCV64State, guest_v21)
+#define OFFB_V22 offsetof(VexGuestRISCV64State, guest_v22)
+#define OFFB_V23 offsetof(VexGuestRISCV64State, guest_v23)
+#define OFFB_V24 offsetof(VexGuestRISCV64State, guest_v24)
+#define OFFB_V25 offsetof(VexGuestRISCV64State, guest_v25)
+#define OFFB_V26 offsetof(VexGuestRISCV64State, guest_v26)
+#define OFFB_V27 offsetof(VexGuestRISCV64State, guest_v27)
+#define OFFB_V28 offsetof(VexGuestRISCV64State, guest_v28)
+#define OFFB_V29 offsetof(VexGuestRISCV64State, guest_v29)
+#define OFFB_V30 offsetof(VexGuestRISCV64State, guest_v30)
+#define OFFB_V31 offsetof(VexGuestRISCV64State, guest_v31)
+
+#define OFFB_VL offsetof(VexGuestRISCV64State, guest_vl)
+#define OFFB_VTYPE offsetof(VexGuestRISCV64State, guest_vtype)
+
/*------------------------------------------------------------*/
/*--- Integer registers ---*/
/*------------------------------------------------------------*/
@@ -413,6 +449,105 @@ static void putPC(/*OUT*/ IRSB* irsb, /*IN*/ IRExpr* e)
stmt(irsb, IRStmt_Put(OFFB_PC, e));
}
+/*------------------------------------------------------------*/
+/*--- Vector registers ---*/
+/*------------------------------------------------------------*/
+static Int offsetVReg(UInt vregNo)
+{
+ switch (vregNo) {
+ case 0:
+ return OFFB_V0;
+ case 1:
+ return OFFB_V1;
+ case 2:
+ return OFFB_V2;
+ case 3:
+ return OFFB_V3;
+ case 4:
+ return OFFB_V4;
+ case 5:
+ return OFFB_V5;
+ case 6:
+ return OFFB_V6;
+ case 7:
+ return OFFB_V7;
+ case 8:
+ return OFFB_V8;
+ case 9:
+ return OFFB_V9;
+ case 10:
+ return OFFB_V10;
+ case 11:
+ return OFFB_V11;
+ case 12:
+ return OFFB_V12;
+ case 13:
+ return OFFB_V13;
+ case 14:
+ return OFFB_V14;
+ case 15:
+ return OFFB_V15;
+ case 16:
+ return OFFB_V16;
+ case 17:
+ return OFFB_V17;
+ case 18:
+ return OFFB_V18;
+ case 19:
+ return OFFB_V19;
+ case 20:
+ return OFFB_V20;
+ case 21:
+ return OFFB_V21;
+ case 22:
+ return OFFB_V22;
+ case 23:
+ return OFFB_V23;
+ case 24:
+ return OFFB_V24;
+ case 25:
+ return OFFB_V25;
+ case 26:
+ return OFFB_V26;
+ case 27:
+ return OFFB_V27;
+ case 28:
+ return OFFB_V28;
+ case 29:
+ return OFFB_V29;
+ case 30:
+ return OFFB_V30;
+ case 31:
+ return OFFB_V31;
+ default:
+ vassert(0);
+ }
+}
+
+static const HChar* nameVReg(UInt iregNo)
+{
+ vassert(iregNo < 32);
+ static const HChar* names[32] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
+ return names[iregNo];
+}
+
+static IRExpr* getVReg(UInt vregNo, UInt offset, IRType ty)
+{
+ vassert(vregNo < 32);
+ return IRExpr_Get(offsetVReg(vregNo) + offset, ty);
+}
+
+static void putVReg(/*OUT*/ IRSB* irsb, UInt vregNo, UInt offset, /*IN*/ IRExpr* e)
+{
+ vassert(vregNo < 32);
+ stmt(irsb, IRStmt_Put(offsetVReg(vregNo) + offset, e));
+}
+
+
/*------------------------------------------------------------*/
/*--- Floating-point registers ---*/
/*------------------------------------------------------------*/
diff --git a/VEX/pub/libvex_guest_riscv64.h b/VEX/pub/libvex_guest_riscv64.h
index 31264b124..50bec58bd 100644
--- a/VEX/pub/libvex_guest_riscv64.h
+++ b/VEX/pub/libvex_guest_riscv64.h
@@ -128,8 +128,44 @@ typedef struct {
/* 576 */ ULong guest_LLSC_ADDR; /* Address of the transaction. */
/* 584 */ ULong guest_LLSC_DATA; /* Original value at ADDR, sign-extended. */
+#define VLEN 128
+ /* 592 */ V128 guest_v0;
+ V128 guest_v1;
+ V128 guest_v2;
+ V128 guest_v3;
+ V128 guest_v4;
+ V128 guest_v5;
+ V128 guest_v6;
+ V128 guest_v7;
+ V128 guest_v8;
+ V128 guest_v9;
+ V128 guest_v10;
+ V128 guest_v11;
+ V128 guest_v12;
+ V128 guest_v13;
+ V128 guest_v14;
+ V128 guest_v15;
+ V128 guest_v16;
+ V128 guest_v17;
+ V128 guest_v18;
+ V128 guest_v19;
+ V128 guest_v20;
+ V128 guest_v21;
+ V128 guest_v22;
+ V128 guest_v23;
+ V128 guest_v24;
+ V128 guest_v25;
+ V128 guest_v26;
+ V128 guest_v27;
+ V128 guest_v28;
+ V128 guest_v29;
+ V128 guest_v30;
+ V128 guest_v31;
+
+ /* 1104 */ ULong guest_vl;
+ /* 1112 */ ULong guest_vtype;
+
/* Padding to 16 bytes. */
- /* 592 */
} VexGuestRISCV64State;
/*------------------------------------------------------------*/
diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 34df0011a..acda0bd95 100644
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -1489,6 +1489,41 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
if (o == GOF(LLSC_ADDR) && sz == 8) return o;
if (o == GOF(LLSC_DATA) && sz == 8) return o;
+ if (o >= GOF(v0) && o+sz <= GOF(v0) +SZB(v0)) return GOF(v0);
+ if (o >= GOF(v1) && o+sz <= GOF(v1) +SZB(v1)) return GOF(v1);
+ if (o >= GOF(v2) && o+sz <= GOF(v2) +SZB(v2)) return GOF(v2);
+ if (o >= GOF(v3) && o+sz <= GOF(v3) +SZB(v3)) return GOF(v3);
+ if (o >= GOF(v4) && o+sz <= GOF(v4) +SZB(v4)) return GOF(v4);
+ if (o >= GOF(v5) && o+sz <= GOF(v5) +SZB(v5)) return GOF(v5);
+ if (o >= GOF(v6) && o+sz <= GOF(v6) +SZB(v6)) return GOF(v6);
+ if (o >= GOF(v7) && o+sz <= GOF(v7) +SZB(v7)) return GOF(v7);
+ if (o >= GOF(v8) && o+sz <= GOF(v8) +SZB(v8)) return GOF(v8);
+ if (o >= GOF(v9) && o+sz <= GOF(v9) +SZB(v9)) return GOF(v9);
+ if (o >= GOF(v10) && o+sz <= GOF(v10)+SZB(v10)) return GOF(v10);
+ if (o >= GOF(v11) && o+sz <= GOF(v11)+SZB(v11)) return GOF(v11);
+ if (o >= GOF(v12) && o+sz <= GOF(v12)+SZB(v12)) return GOF(v12);
+ if (o >= GOF(v13) && o+sz <= GOF(v13)+SZB(v13)) return GOF(v13);
+ if (o >= GOF(v14) && o+sz <= GOF(v14)+SZB(v14)) return GOF(v14);
+ if (o >= GOF(v15) && o+sz <= GOF(v15)+SZB(v15)) return GOF(v15);
+ if (o >= GOF(v16) && o+sz <= GOF(v16)+SZB(v16)) return GOF(v16);
+ if (o >= GOF(v17) && o+sz <= GOF(v17)+SZB(v17)) return GOF(v17);
+ if (o >= GOF(v18) && o+sz <= GOF(v18)+SZB(v18)) return GOF(v18);
+ if (o >= GOF(v19) && o+sz <= GOF(v19)+SZB(v19)) return GOF(v19);
+ if (o >= GOF(v20) && o+sz <= GOF(v20)+SZB(v20)) return GOF(v20);
+ if (o >= GOF(v21) && o+sz <= GOF(v21)+SZB(v21)) return GOF(v21);
+ if (o >= GOF(v22) && o+sz <= GOF(v22)+SZB(v22)) return GOF(v22);
+ if (o >= GOF(v23) && o+sz <= GOF(v23)+SZB(v23)) return GOF(v23);
+ if (o >= GOF(v24) && o+sz <= GOF(v24)+SZB(v24)) return GOF(v24);
+ if (o >= GOF(v25) && o+sz <= GOF(v25)+SZB(v25)) return GOF(v25);
+ if (o >= GOF(v26) && o+sz <= GOF(v26)+SZB(v26)) return GOF(v26);
+ if (o >= GOF(v27) && o+sz <= GOF(v27)+SZB(v27)) return GOF(v27);
+ if (o >= GOF(v28) && o+sz <= GOF(v28)+SZB(v28)) return GOF(v28);
+ if (o >= GOF(v29) && o+sz <= GOF(v29)+SZB(v29)) return GOF(v29);
+ if (o >= GOF(v30) && o+sz <= GOF(v30)+SZB(v30)) return GOF(v30);
+ if (o >= GOF(v31) && o+sz <= GOF(v31)+SZB(v31)) return GOF(v31);
+ if (o >= GOF(vl) && o+sz <= GOF(vl)+SZB(vl)) return GOF(vl);
+ if (o >= GOF(vtype) && o+sz <= GOF(vtype)+SZB(vtype)) return GOF(vtype);
+
VG_(printf)("MC_(get_otrack_shadow_offset)(riscv64)(off=%d,sz=%d)\n",
offset,szB);
tl_assert(0);
--
2.25.1
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