[Valgrind-developers] [RFC 02/12] riscv64: Pass riscv guest_state for translation

[Fei Wu <fe...@in...>]

Vector instruction needs this info in guest_riscv64_toIR.c

Signed-off-by: Fei Wu <fe...@in...>
---
 VEX/pub/libvex.h        | 4 ++++
 coregrind/m_translate.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 2c54a8d8f..7cabc36aa 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -37,6 +37,7 @@
 
 #include "libvex_basictypes.h"
 #include "libvex_ir.h"
+#include "pub_tool_guest.h"
 
 
 /*---------------------------------------------------------------*/
@@ -470,6 +471,9 @@ typedef
 
       /* MIPS32/MIPS64 GUESTS only: emulated FPU mode. */
       UInt guest_mips_fp_mode;
+
+      /* RISC-V vector needs guest state on translation */
+      VexGuestArchState* riscv64_guest_state;
    }
    VexAbiInfo;
 
diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
index 75dca062d..dc3c65814 100644
--- a/coregrind/m_translate.c
+++ b/coregrind/m_translate.c
@@ -1752,6 +1752,8 @@ Bool VG_(translate) ( ThreadId tid,
 
 #  if defined(VGP_riscv64_linux)
    vex_abiinfo.guest__use_fallback_LLSC = True;
+   ThreadState *tst = VG_(get_ThreadState)(tid);
+   vex_abiinfo.riscv64_guest_state = &tst->arch.vex;
 #  endif
 
    /* Set up closure args. */
-- 
2.25.1