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From: Julian S. <se...@so...> - 2020-10-30 16:36:02
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2471e0521da06200bd9d553b4d17750af2852bb0 commit 2471e0521da06200bd9d553b4d17750af2852bb0 Author: Julian Seward <js...@ac...> Date: Fri Oct 30 17:34:14 2020 +0100 arm64 front end: mark a couple of vector load/store insns as "verbose". Mark LD3/ST3 (multiple 3-elem structs to/from 3 regs LD4/ST4 (multiple 4-elem structs to/from 4 regs as "verbose", since they can generate so much IR that a long sequence of them causes later stages of the JIT to run out of space. Diff: --- VEX/priv/guest_arm64_toIR.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index fa4596a905..556b85a6af 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -6040,6 +6040,9 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, (tt+0) % 32, arr, (tt+nRegs-1) % 32, arr, nameIReg64orSP(nn), pxStr); + if (nRegs >= 3) { + dres->hint = Dis_HintVerbose; + } return True; } /* else fall through */ |