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From: Julian S. <se...@so...> - 2020-01-02 06:29:04
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=20e2a5bcc9beb561911b26af50ac6e2a4cc1ee7c commit 20e2a5bcc9beb561911b26af50ac6e2a4cc1ee7c Author: Julian Seward <js...@ac...> Date: Fri Nov 22 08:32:03 2019 +0100 Implement And1 and Or1 for the x86 insn selector. Diff: --- VEX/priv/host_x86_isel.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c index c8fae08..50b3235 100644 --- a/VEX/priv/host_x86_isel.c +++ b/VEX/priv/host_x86_isel.c @@ -2053,6 +2053,25 @@ static X86CondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e ) } } + /* And1(x,y), Or1(x,y) */ + /* FIXME: We could (and probably should) do a lot better here. If both args + are in temps already then we can just emit a reg-reg And/Or directly, + followed by the final Test. */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_And1 || e->Iex.Binop.op == Iop_Or1)) { + // We could probably be cleverer about this. In the meantime .. + HReg x_as_32 = newVRegI(env); + X86CondCode cc_x = iselCondCode(env, e->Iex.Binop.arg1); + addInstr(env, X86Instr_Set32(cc_x, x_as_32)); + HReg y_as_32 = newVRegI(env); + X86CondCode cc_y = iselCondCode(env, e->Iex.Binop.arg2); + addInstr(env, X86Instr_Set32(cc_y, y_as_32)); + X86AluOp aop = e->Iex.Binop.op == Iop_And1 ? Xalu_AND : Xalu_OR; + addInstr(env, X86Instr_Alu32R(aop, X86RMI_Reg(x_as_32), y_as_32)); + addInstr(env, X86Instr_Test32(1, X86RM_Reg(y_as_32))); + return Xcc_NZ; + } + ppIRExpr(e); vpanic("iselCondCode"); } |