[Valgrind-developers] [valgrind] PPC64, Add support for vlogefp, vexptefp instructions

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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3a345d9f8e8e98ee74f2c66f69ab51220cd18d47

commit 3a345d9f8e8e98ee74f2c66f69ab51220cd18d47
Author: Carl Love <ca...@us...>
Date:   Tue May 28 14:07:04 2019 -0500

    PPC64, Add support for vlogefp, vexptefp instructions
    
    Add Iop_Exp2_32Fx4 to VEX/pub/libvex_ir.h to support the 2^x instruction.
    
    Enable the existing test support for the two instructions in
    none/tests/ppc64/subnormal_test.c and none/tests/ppc64/jm-insns.c.
    
    https://bugs.kde.org/show_bug.cgi?id=407340

Diff:
---
 NEWS                             |  1 +
 VEX/priv/guest_ppc_toIR.c        | 12 ++++++++----
 VEX/priv/host_ppc_defs.c         |  4 ++++
 VEX/priv/host_ppc_defs.h         |  2 +-
 VEX/priv/host_ppc_isel.c         |  2 ++
 VEX/priv/ir_defs.c               |  4 +++-
 VEX/pub/libvex_ir.h              |  2 ++
 memcheck/mc_translate.c          |  1 +
 memcheck/tests/vbit-test/irops.c |  1 +
 9 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/NEWS b/NEWS
index 788e92f..753171f 100644
--- a/NEWS
+++ b/NEWS
@@ -212,6 +212,7 @@ where XXXXXX is the bug number as listed below.
 406360  memcheck/tests/libstdc++.supp needs more supression variants
 406422  none/tests/amd64-linux/map_32bits.vgtest fails too easily
 406465  arm64 insn selector fails on "t0 = <expr>" where <expr> has type Ity_F16
+407340  PPC64, does not support the vlogefp, vexptefp instructions.
 n-i-bz  add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64.
 n-i-bz  Fix callgrind_annotate non deterministic order for equal total
 n-i-bz  callgrind_annotate --threshold=100 does not print all functions.
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index ad79b5e..12480b3 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -27702,17 +27702,21 @@ static Bool dis_av_fp_arith ( UInt theInstr )
 
    case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173)
       DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr);
-      DIP(" => not implemented\n");
       /* NOTE, need to address dnormalized value handling when this is
          implemented.  */
-      return False;
+      putVReg( vD_addr,
+               dnorm_adj_Vector( unop( Iop_Exp2_32Fx4,
+                                       dnorm_adj_Vector( mkexpr( vB ) ) ) ) );
+      return True;
 
    case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175)
       DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr);
-      DIP(" => not implemented\n");
       /* NOTE, need to address dnormalized value handling when this is
          implemented.  */
-      return False;
+      putVReg( vD_addr,
+               dnorm_adj_Vector( unop( Iop_Log2_32Fx4,
+                                       dnorm_adj_Vector( mkexpr( vB ) ) ) ) );
+      return True;
 
    default:
       vex_printf("dis_av_fp_arith(ppc)(opc2=0x%x)\n",opc2);
diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
index 682500a..6c298fa 100644
--- a/VEX/priv/host_ppc_defs.c
+++ b/VEX/priv/host_ppc_defs.c
@@ -750,6 +750,8 @@ const HChar* showPPCAvFpOp ( PPCAvFpOp op ) {
    /* Floating Point Unary */
    case Pavfp_RCPF:      return "vrefp";
    case Pavfp_RSQRTF:    return "vrsqrtefp";
+   case Pavfp_Log2:      return "vlogefp";
+   case Pavfp_Exp2:      return "vexptefp";
    case Pavfp_CVTU2F:    return "vcfux";
    case Pavfp_CVTS2F:    return "vcfsx";
    case Pavfp_QCVTF2U:   return "vctuxs";
@@ -5733,6 +5735,8 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
       switch (i->Pin.AvUn32Fx4.op) {
       case Pavfp_RCPF:    opc2 =  266; break; // vrefp
       case Pavfp_RSQRTF:  opc2 =  330; break; // vrsqrtefp
+      case Pavfp_Log2:    opc2 =  458; break; // vlogefp
+      case Pavfp_Exp2:    opc2 =  394; break; // vexptefp
       case Pavfp_CVTU2F:  opc2 =  778; break; // vcfux
       case Pavfp_CVTS2F:  opc2 =  842; break; // vcfsx
       case Pavfp_QCVTF2U: opc2 =  906; break; // vctuxs
diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
index 0d05954..70c3b6c 100644
--- a/VEX/priv/host_ppc_defs.h
+++ b/VEX/priv/host_ppc_defs.h
@@ -489,7 +489,7 @@ typedef
       Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
 
       /* Floating point unary */
-      Pavfp_RCPF, Pavfp_RSQRTF,
+      Pavfp_RCPF, Pavfp_RSQRTF, Pavfp_Log2, Pavfp_Exp2,
       Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S,
       Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ,
    }
diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index e05145c..5e2a3b8 100644
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -5779,6 +5779,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
 
       case Iop_RecipEst32Fx4: fpop = Pavfp_RCPF;    goto do_32Fx4_unary;
       case Iop_RSqrtEst32Fx4: fpop = Pavfp_RSQRTF;  goto do_32Fx4_unary;
+      case Iop_Log2_32Fx4:    fpop = Pavfp_Log2;    goto do_32Fx4_unary;
+      case Iop_Exp2_32Fx4:    fpop = Pavfp_Exp2;    goto do_32Fx4_unary;
       case Iop_I32UtoF32x4_DEP: fpop = Pavfp_CVTU2F;  goto do_32Fx4_unary;
       case Iop_I32StoF32x4_DEP: fpop = Pavfp_CVTS2F;  goto do_32Fx4_unary;
       case Iop_QF32toI32Ux4_RZ: fpop = Pavfp_QCVTF2U; goto do_32Fx4_unary;
diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c
index f30cf0d..30e936a 100644
--- a/VEX/priv/ir_defs.c
+++ b/VEX/priv/ir_defs.c
@@ -707,7 +707,8 @@ void ppIROp ( IROp op )
       case Iop_Scale2_64Fx2: vex_printf("Scale2_64Fx2"); return;
       case Iop_Log2_32Fx4: vex_printf("Log2_32Fx4"); return;
       case Iop_Log2_64Fx2: vex_printf("Log2_64Fx2"); return;
- 
+      case Iop_Exp2_32Fx4: vex_printf("Iop_Exp2_32Fx4"); return;
+
       case Iop_Sub32Fx4:  vex_printf("Sub32Fx4"); return;
       case Iop_Sub32Fx2:  vex_printf("Sub32Fx2"); return;
       case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return;
@@ -3012,6 +3013,7 @@ void typeOfPrimop ( IROp op,
          TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128);
       case Iop_Log2_32Fx4:
       case Iop_Log2_64Fx2:
+      case Iop_Exp2_32Fx4:
          UNARY(Ity_V128, Ity_V128);
 
       case Iop_V128to64: case Iop_V128HIto64:
diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
index d797bd4..d5e7f50 100644
--- a/VEX/pub/libvex_ir.h
+++ b/VEX/pub/libvex_ir.h
@@ -1385,6 +1385,8 @@ typedef
       /* Vector floating-point base 2 logarithm */
       Iop_Log2_32Fx4,
 
+      /* Vector floating-point exponential 2^x */
+      Iop_Exp2_32Fx4,
 
       /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
          Note, that of one of the arguments is zero and another one is infiinty
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 424de15..02b93ba 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -4921,6 +4921,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_Neg32Fx4:
       case Iop_RSqrtEst32Fx4:
       case Iop_Log2_32Fx4:
+      case Iop_Exp2_32Fx4:
          return unary32Fx4(mce, vatom);
 
       case Iop_I32UtoF32x2_DEP:
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index 58d03e9..29451b4 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -631,6 +631,7 @@ static irop_t irops[] = {
   { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Scale2_32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Log2_32Fx4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Exp2_32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RecipEst32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RecipStep32Fx4, UNDEF_UNKNOWN), },


